AgWiki - User contributions [en]

Chronobox

2025-03-27T00:45:28Z

Olchansk: /* Initial hardware setup */

= Chronobox =

= Links =

* https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano
* https://bitbucket.org/expalpha/chronobox_firmware
* https://bitbucket.org/expalpha/chronobox_software
* https://edev-group.triumf.ca/hw/alphag/chrono-box/rev0
* https://bitbucket.org/expalpha/chronobox_firmware/src/master/docs/Chrono.pdf

= Chronobox connectors =

<pre>
|
| LEMO - CLK_IN - jumpers: SINE<->CLK<->NIM/TTL and NIM<->CLK<->TTL
|
| ECL P1
| 32
| |
| 1
|
| ECL P2
| 32
| |
| 1
|
| PLED - power-on LED
|
| jumper: bank A direction IN<->X<->OUT
| LEMO 0-1
| LED 0-1
| LEMO 2-3
| LED 2-3
|
| jumper: bank B direction IN<->X<->OUT
| LEMO 4-5
| LED 4-5
| LEMO 6-7
| LED 6-7
|
</pre>

= Electrical connections =

* ECL P1 and P2: LeCroy 4616 compatible
* LEMO TTL inputs: 0..5V, logic level 0: <0.8V, logic level 1: >2V
* LEMO TTL outputs: logic level 0: 0V, logic level 1: 5V to 3.3V
* clock NIM input: NIM compatible
* clock TTL input: ???
* clock sine wave input: ???

= Input channel mapping =

* 0+16 : first ECL connector
* 16+16 : second ECL connector
* 32+8 : LEMO inputs (TTL)
* 40+18 : GPIO inputs (FPGA pins)
* 58 : external clock (10 MHz nominal)
* 59 : internal clock (100 MHz)

= Functional units =

== Scalers ==

TBW

=== Firmware 0x61832695 ===

* minimum pulse width (leading edge to trailing edge): longer than 10 ns (15 ns is safe) (sampled by 100 MHz/ 10 ns clock)
* minimum time between pulses (trailing edge to next leading edge): longer than 10 ns (15 ns is safe) (ditto)

=== Firmware 0x624e22ad ===

* minimum pulse width: leading edge triggered (2 ns is safe)
* minimum time between pulses (trailing edge to next leading edge): 25 ns or more is safe

== Timestamps (TSC) ==

TBW

=== Firmware 0x61832695 ===

* minimum pulse width (leading edge to trailing edge): longer than 100 ns (105 ns is safe) (sampled by 10 MHz/100 ns clock)
* minimum time between pulses (trailing edge to next leading edge): longer than 100 ns (105 ns is safe) (ditto)

=== Firmware 0x624e22ad ===

* minimum pulse width: leading edge triggered (5 ns is safe)
* minimum time between pulses (trailing edge to next leading edge): longer than 200 ns (205 ns is safe) (sampled by 10 MHz/100 ns clock)

Each TSC input has a 256 entry FIFO. (LE is 1 entry, TE is 1 entry, so 128 hits if both LE and TE enabled).

== Output data fifo ==

TBW

=== Firmware before 0x61832695 ===

Output fifo is 4096 entries deep.

=== Firmware 0x624e22ad ===

Output fifo is 64k entries deep.

= Initial hardware setup =

* refer to DE10-NANO information here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano
* prepare hardware:
** remove chronobox from enclosure (cannot access JTAG connector when installed)
** remove DE10-Nano from chronobox baseboard
** check that SW10 jumpers are: U-D-U-U-D-U. (U=up, D=down, when "ALTERA" text on the FPGA is right side up)
** reinstall DE10-Nano on chronobox baseboard
** do NOT reinstall chronobox in enclosure
* prepare software:
** check that you have quartus 17.1 (at /opt/intelFPGA/17.1/ in this example)
** check that you installed chronobox software in /home/agdaq/online/chronobox_software
** check that you installed chronobox firmware project in /home/agdaq/online/firmware/git/chronobox_firmware
* connect serial console, for more info, go here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#Serial_console
** connect a mini-USB (*not* Micto-USB!) cable from mini-USB port on the side of the ethernet connection to a PC
** minicom -D /dev/ttyUSB0 -b 115200
* connect fpga jtag, for more info, go here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#JTAG
** connect a mini-USB (*not* Micro-USB!) cable on the side of HDMI and power connectors to a PC
** /opt/intelFPGA/17.1/quartus/bin/jtagconfig
* prepare SD flash card for booting from network: generic instructions are here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#boot_Linux_from_SD_flash
** connect new or used 8GB SD flash card to USB flash adapter to a linux computer
** login as root
** identify the flash device as /dev/sdX. Use "lsblk" or "blkid" or "dmesg". be careful to not write to the computer system disk (usually /dev/sda)
** echo -e 'o\nn\np\n1\n2048\n4095\nn\np\n2\n4096\n1681816\nn\np\n3\n\n\nt\n1\na2\nt\n2\nb\nw' | fdisk /dev/sdX
** eject /dev/sdX
** remove card, reintall card, this is to ensure we use the new partition table
** fdisk -l /dev/sdX
<pre>
root@daq01:~# fdisk -l /dev/sdg
Disk /dev/sdg: 7.38 GiB, 7910457344 bytes, 15450112 sectors
Disk model: STORAGE DEVICE
Units: sectors of 1 * 512 = 512 bytes
Sector size (logical/physical): 512 bytes / 512 bytes
I/O size (minimum/optimal): 512 bytes / 512 bytes
Disklabel type: dos
Disk identifier: 0xa033868b

Device Boot Start End Sectors Size Id Type
/dev/sdg1 2048 4095 2048 1M a2 unknown
/dev/sdg2 4096 1681816 1677721 819.2M b W95 FAT32
/dev/sdg3 1683456 15450111 13766656 6.6G 83 Linux
root@daq01:~#
</pre>
** dd if=/daq/daqstore/olchansk/daq/DE10-Nano/image-1-fpga.img of=/dev/sdX1 bs=1024k
** dd if=/daq/daqstore/olchansk/daq/DE10-Nano/image-2-uboot.img of=/dev/sdX2 bs=1024k
** eject /dev/sdX
* install prepared flash card into the chronobox DE10-Nano
* cycle power
* in the minicom window, IMMEDIATELY press the space bar to stop automatic booting (if it doesn't react, ensure flow control is disabled in minicom)
* you will have the uboot "=>" prompt
* confirm uboot version: U-Boot 2013.01.01
* setup uboot to boot linux from network, more details here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#boot_Linux_from_network
** setenv ethaddr 02:aa:bb:cc:cb:04 # for cb04, see below for explanation
** setenv bootcmd 'run bridge_enable_handoff; run netboot'
** setenv ramboot bootz \${loadaddr} - \${fdtaddr}
** setenv bootargs console=ttyS0,115200 ip=dhcp root=/dev/nfs rw nfsroot=192.168.1.1:/nfsroot/%s,vers=3,nolock,proto=tcp panic=15
** saveenv
** reset
* DE10-Nano should boot into linux:
** uboot will restart
** DHCP will run
** tftp load of linux kernel will run
** linux kernel will start
** linux kernel will get an IP address
** linux kernel will NFS-mount the root filesystem (.../nfsroot/cb04)
** systemd will start all services
** there will be a login prompt on minicom console
** ssh will work (maybe 1 minute delay before it starts)
* try a few things:
** from agdaq or agmini account, ssh root@cb04
** "df" should show /home/agdaq is mounted (and ssh agdaq@cb04 should work)
** "/home/agdaq/online/chronobox_software/test_cb.exe 0" should fail ("bus error") because FPGA is not loaded yet
* load sof file, for more info, go here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#JTAG
** /opt/intelFPGA/17.1/quartus/bin/quartus_pgm -m JTAG -o "p;/home/agdaq/online/firmware/git/chronobox_firmware/output_files/DE10_NANO_SoC_GHRD.sof@2"
* "test_cb.exe 0" should work now
* use srunner_cb.exe to load the pof file into FPGA boot flash
* use reboot_cb.exe to reboot the FPGA from flash
* "test_cb.exe 0" should report the expected FPGA firmware version number.
* success.

== assign ethernet MAC address ==

Usually ethernet MAC address is assigned by manufacturer and is stored in a tiny little flash chip. The DE10-Nano board
is too cheap and does not have it. So a fake ethernet address has to be assigned manually from
the "locally administered range" of MAC addresses that start from "02:...", see
https://en.wikipedia.org/wiki/MAC_address#Ranges_of_group_and_locally_administered_addresses

All MAC addresses must be unique on an ethernet network, but with manual assignement confusion is easy to create.

For chronobox devices, use MAC addresses that start with "l02:aa:bb:cc:xx:yy" and have last digits "cb:01", "cb:02", "cb:03", "cb04" for the first four chronoboxes.

== new board test checklist ==

to check newly built chronobox baseboard, follow this checklist.

=== test ECL inputs ===

* stop midas frontend
* ssh agdaq@alphagdaq ### or agmini@daq16
* ssh root@cb03
* /home/agdaq/online/chronobox_software/test_cb.exe 0 ### read firmware revision, confirm communication with chronobox firmware
* /home/agdaq/online/chronobox_software/test_cb.exe inputs ### output should look like this:
<pre>
inputs: ecl_p1: 0xaa55, ecl_p2: 0xaa55, lemo: 0xe0, gpio: 0x3ffff
</pre>
* connect ECL ribbon cable from LeCroy 4616 NIM-to-ECL converter to chronobox ECL_P1 input (left one)
* ecl_p1 input should read 0x0000
* connect lemo jumper from NIM logic level 1 otput (i.e. any module OUT-bar output) to first channel of LeCroy 4616, ecl_p1 should read 0x0001
* move to 2nd channel, get 0x0002
* and so forth until last channel 0x8000.
* if any channel does not give expected reading, attach label (i.e. "ECL_P1 0x0002 bad") and send for repair.
* repeat with ECL_P2 input (right one), watch printed value of ecl_p2.

=== test TTL inputs ===

* NOTE: front panel LEMO connector labels are wrong. correct numbering of LEMO connectors is as shown in [[#Chronobox connectors]]
* disconnect all LEMO inputs
* set "bank A direction" and "bank B direction" for input
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_in_a # set bank A to input
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_in_b # set bank B to input
* all 8 LEMO LEDs should be on
* /home/agdaq/online/chronobox_software/test_cb.exe inputs ### lemo inputs should read 0xFF
* connect LEMO 0 (left bottom) to TTL output of Lecroy 222 or equivalent, set "scale" to "latch", operate push buttons to turn output on and off (LED should come in and out).
* /home/agdaq/online/chronobox_software/test_cb.exe inputs
<pre>
inputs: ecl_p1: 0xaa55, ecl_p2: 0xaa55, lemo: 0xfe (~0x01), gpio: 0x3ffff
</pre>
* change TTL signal from logic level 0 to 1 and back, observe the corresponding LED to turn on and off, observe the correct bit in the "lemo" column (watch the inverted input ~0x01) change.
* repeat with LEMO input 1 (left top) through 7 (right top).

=== test TTL outputs ===

* NOTE: front panel LEMO connector labels are wrong. correct numbering of LEMO connectors is as shown in #Chronobox connectors
* set "bank A direction" and "bank B direction" for output
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_a 0
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_b 0
* all LEMO LEDs should be off
* with voltmeter measure LEMO output voltage should be 0.135 V
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_a 0xF
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_b 0xF
* all LEMO LEDs should be on
* with voltmeter measure LEMO output voltage should be 3.4 to 3.8 V
* if you measure 1.69 V, the bank direction switch is still in the "input" position
* to test individual output, instead of 0xF use 0x1, 0x2, 0x4 and 0x8.

=== test clock input ===

* we test the TTL input mode first
* disconnect CLK_IN input
* /home/agdaq/online/chronobox_software/test_cb.exe intclk ### switch to internal timestamp clock
* /home/agdaq/online/chronobox_software/test_cb.exe clocks
<pre>
clock status: ext_clk: counter 0x00000000, freq 0.0 Hz, ts_clk: counter 0x00cccccc, freq 9999999.4 Hz, PLL status 0xa0000000
</pre>
notice: ts_clk frequency is around 10 MHz (internal oscillator) and ext_clk frequency is zero (nothing connected)
* if ts_clk is not around 10 MHz, PLL is not locked correctly, reboot the FPGA and try again: /home/agdaq/online/chronobox_software/test_cb.exe reboot
* set CLK_IN jumpers to "TTL/NIM" and "TTL" position
* connect LEMO cable from LEMO output 0 (bottom left) to CLK_IN
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_clk 0 ### output timestamp clock on LEMO output 0
* /home/agdaq/online/chronobox_software/test_cb.exe clocks
<pre>
clock status: ext_clk: counter 0x00cccccc, freq 9999999.4 Hz, ts_clk: counter 0x00cccccc, freq 9999999.4 Hz, PLL status 0x80000000
</pre>
* observe ext_clk frequency is the same as ts_clk frequency
* to test NIM input mode, we need a NIM clock signal, i.e. from a VME-NIMIO32, etc. Or use a TTL-to-NIM converter to use clock on LEMO output 0.
* set CLK_IN jumpers to "TTL/NIM" and "NIM" position
* connect VME-NIMIO32 NIM output 3 (40 MHz V1190 clock) to CLK_IN
* /home/agdaq/online/chronobox_software/test_cb.exe clocks
<pre>
clock status: ext_clk: counter 0x03333c0c, freq 40001687.4 Hz, ts_clk: counter 0x00cccccc, freq 9999999.4 Hz, PLL status 0x80000000
</pre>
* observe ext_clk frequency is 40 MHz.
* to test "sine wave" input mode, TBW, do not have a sine wave signal source.

K.O.

=== test GPIO pins ===

TBW

= Install chronobox software =

<pre>
cd /home/agdaq/online
git clone https://bitbucket.org/expalpha/chronobox_software.git
cd chronobox_software
make clean
make
ls -l *.exe
-rwxr-xr-x 1 olchansk users 18808 Aug 16 15:26 reboot_cb.exe
-rwxr-xr-x 1 olchansk users 47256 Aug 16 15:26 srunner_cb.exe
-rwxr-xr-x 1 olchansk users 20732 Aug 16 15:26 test_cb.exe
</pre>

= Install chronobox quartus firmware project =

<pre>
cd /home/agdaq/online/firmware/git
git clone https://bitbucket.org/expalpha/chronobox_firmware.git
cd chronobox_firmware
git fetch ### update repository
git tag ### list available tags
git checkout 20210420_ko ### checkout a specific version
git status
cat timestamp.v ### confirm firmware version
ls -l output_files/*.{jic,sof,rpd}
</pre>

= Firmware revisions =

* 0x5aceaed2 - April 2018 - all inputs connected to counters (except ext clock), 58 inputs, 50 MHz clock
* 0x5b6de806 - August 2018 - added fpga boot flash programmer and fpga reboot
* 0x5b7c827d - August 2018 - bshaw added debounce on GPIO inputs (for flow meters), 100 MHz clock
* 0x5b873169 - August 2018 - rebuilt, no changes
* 0x5b89e4b4 - August 2018 - added external clock signal, 59 inputs, 100 MHz clock
* 0x5b8de2b0 - September 2018 - added data fifo and timestamp counters (TSCs) for the first 4 inputs
* 0x5b906c56 - September 2018 - improved overflow markers, added scalers readout into the data fifo
* 0x5da8e4c2 - October 2019 - timestamps for all inputs, inversion of inputs
* 0x5db764a7 - October 2019 - FPGA reboot works now.
* 0x607f6709 - April 2021 - working timestamp synchronization, memory mapped registers, improved sdc file, correct clock transfers
* 0x60860e61 - April 2021 - faster data FIFO readout (from ~8 Mbytes/sec to ~80 Mbytes/sec)
* 0x61832695 - Nov 2021 - increase timestamp FIFO from 4k to 64k words
* 20220406_ko_0x624e22ad - April 2022 - make inputs edge-triggered instead of sampled.
* 20220420_ko_0x62608957 - April 2022 - fix first fifo data word is zero

= Firmware update =

* use srunner_cb.exe to load firmware RPD file into EPCQ flash memory.
* if FPGA is not running compatible firmware, srunner_cb will fail
* connect JTAG and load the firmware sof file from the quartus project (use "make load_sof")
* if JTAG is connected, one can use "make load_jic" to load firmware jic file into EPCQ flash memory.

After correct firmware is loaded, access to chronobox registers may fail (srunner_cb will not work)
because FPGA bridges are not enabled. To check, run following commands. If some bridge reports "disabled", reboot linux (do not cycle the power!).
<pre>
root@cb02:~# cat /sys/class/fpga_bridge/br*/state
enabled
enabled
enabled
enabled
root@cb02:~#
</pre>

Some DE10-Nano boards have an EPCQ64 flash memory chip, some have the EPCQ128 flash memory chip.
* identify EPCQ64 and use "-64" with all srunner commands:
<pre>
cd /home/agdaq/online/chronobox_software
./srunner_cb.exe -id -64 /dev/null # identify EPCS64 flash
...
Info: Silicon ID - 0x16
Info: Serial Configuration Device - EPCS64
</pre>
* identify EPCQ128 and use "-128" with all srunner commands:
<pre>
./srunner_cb.exe -id -128 /dev/null # identify EPCQ128 flash
...
Info: Silicon ID - 0x18
Info: Serial Configuration Device - EPCS128
</pre>

Identify -64 or -128 flash memory, write RPD file to flash memory, verify and reboot the fpga:

<pre>
cd /home/agdaq/online/chronobox_software
./srunner_cb.exe -id -64 /dev/null # identify EPCS64 flash
./srunner_cb.exe -id -128 /dev/null # identify EPCQ128 flash
#./srunner_cb.exe -read -128 test.rpd # read flash contents into a file
./srunner_cb.exe -program -128 /home/agdaq/online/firmware/git/chronobox_firmware/output_files/DE10_NANO_SoC_GHRD_auto.rpd
./srunner_cb.exe -verify -128 /home/agdaq/online/firmware/git/chronobox_firmware/output_files/DE10_NANO_SoC_GHRD_auto.rpd
./reboot_cb.exe # reboot the fpga into the new firmware
</pre>

= Firmware build =

for building firmware use: /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh

<pre>
ssh daq01
cd online
git clone git@bitbucket.org:expalpha/chronobox_firmware.git
cd chronobox_firmware
/opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
make quartus
ls -l output_files/*.{sof,jic,rpd}
-rw-r--r-- 1 olchansk users 7007185 Apr 20 16:57 output_files/DE10_NANO_SoC_GHRD_auto.rpd
-rw-r--r-- 1 olchansk users 8388833 Apr 20 16:57 output_files/DE10_NANO_SoC_GHRD.jic
-rw-r--r-- 1 olchansk users 7510701 Apr 20 16:57 output_files/DE10_NANO_SoC_GHRD.sof
</pre>

other make targets:
* make quartus - build fpga programmer files: sof, jic and rpd.
* make clean - clean the quartus project
* make qsys - regenerate the qsys block
* make jic - regenerate the jic file
* make load_sof - load sof file into fpga via jtag
* make load_jic - load jic file into fpga boot flash (epcq) via jtag
* make verify_jic - verify jic checksum in fpga boot flash (epcq)

for jtag access, use /daq/quartus/13.1.3.178/quartus/bin/jtagconfig

<pre>
daq16:chronobox_firmware$ /daq/quartus/13.1.3.178/quartus/bin/jtagconfig
1) DE-SoC [2-1.4.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) Remote server daq16: Unable to connect

daq16:chronobox_firmware$
</pre>

== Errata ==

* after regenerating qsys, manually edit ./soc_system/synthesis/submodules/hps_sdram_pll.sv to comment-out line "assign pll_dr_clk = clk_out[2];"

= Firmware details =

* DDR3 clock is 400 MHz (DDR3-800)
* memcpy speed ~1500 Mbytes/sec
* FIFO access single word read: 80, 44, 44 clocks at 10 ns/clock is 2.3 MHz at 4 bytes/word is 9 Mbytes/sec
* FIFO access memcpy: burst 2, delay 32, b4, delay 36, b5, d1, b5, d1, b5, d1, b1, delay 53, repeat. this reads 16 words in 72 clocks at 10 ns/clock is 1.388 MHz at 4*16=64 bytes/burst is 88.9 Mbytes/sec.

= Chronobox firmware registers =

<pre>
reg | rw/ro | quartus name | firmware | description
0 | ro | sof_revision_in | all | firmware revision timestamp code
0 | wo | latch_scalers_out, zero_scalers_out | all | see [[#reg_0x00_write_bits]]
1 | rw | reg1_led_out | all | DE10-Nano LED output
2 | ro | switches_in | all | read DE10-Nano switches
3 | ro | buttons_in | all | read DE10-Nano buttons
4 | rw | reg4_test | all | 32-bit read-write test register
5 | rw | flash_programmer_in, reg5_flash_programmer_out | 0x5b6de806 | 0xABCD srunner flash programmer
6 | ro | ecl_in | all | read state of ECL inputs
7 | ro | reg7_test_in | all | ???
8 | rw | scaler_addr_out, reg8_scaler_data_in | all | top 16 bits of address becomes scaler bus address, 32 bit read is the corresponding scaler data
9 | ro | lemo_in | all | read state of LEMO inputs
10/0xA | ro | gpio_in | all | read state of GPIO inputs
11/0xB | rw | regB_lemo_out | all | LEMO output data
12/0xC | rw | regC_gpio_out | all | GPIO output data
13/0xD | rw | regD_out_enable_out | all | enable output tristates: [31:24] - LEMO_OUT, [17:0] - GPIO_OUT
14/0xE | rw | regE, reconfig_out | 0x5b6de806 | FPGA reboot: write inverted firmware revision (reg0) to reboot the FPGA
15/0xF | ro | regF_input_num_in | 0x5b89e4b4 | number of chronobox inputs (to read scalers, add 1 for the clock counter)
16/0x10 | ro | reg10_fifo_status | 0x5b8de2b0 | data fifo status, see below
17/0x11 | ro | reg11_fifo_data | 0x5b8de2b0 | data fifo data, see below
18/0x12 | rw | cb_invert_a | 0x5bf7557e | invert inputs 31..0
19/0x13 | rw | cb_invert_b | 0x5bf7557e | invert inputs 63..32
20/0x14 | rw | cb_enable_le_a | 0x5bf7557e | enable TSC leading edge inputs 31..0
21/0x15 | rw | cb_enable_le_b | 0x5bf7557e | enable TSC leading edge inputs 63..32
22/0x16 | rw | cb_enable_te_a | 0x5bf7557e | enable TSC trailing edge inputs 31..0
23/0x17 | rw | cb_enable_te_b | 0x5bf7557e | enable TSC trailing edge inputs 63..32
24/0x18 | ro | fc_ext_clk_100_counter | 0x5bf7557e | external clock frequency counter 100MHz reference
25/0x19 | ro | fc_ext_clk_ext_counter | 0x5bf7557e | external clock frequency counter
26/0x1A | ro | fc_ts_clk_100_counter | 0x5bf7557e | timestamp clock frequency counter 100MHz reference
27/0x1B | ro | fc_ts_clk_ts_counter | 0x5bf7557e | timestamp clock frequency counter
28/0x1C | ro | ts_clk_pll_status | 0x5bf7557e | timestamp clock PLL status
29/0x1D | rw | cb_lemo_out_mux_ctrl | 0x5bfdc798 | 8*4 bits to control 8 LEMO output multiplexers (4 bits/16 options each mux, see [[#LEMO outputs]])
30/0x1E | rw | cb_sync_mask[31:0] | 0x607f6709 | source of chronobox sync signal, low bits
31/0x1F | rw | cb_sync_mask[63:32] | 0x607f6709 | source of chronobox sync signal, high bits
32 | rw | cb_sync_reg[31:0], cb_sync_status[31:0] | 0x607f6709 | control of timestamp sync
33 | ro | tdc_fifo_status | DLTDC | TDC fifo status
34 | ro | tdc_fifo_data_lo | DLTDC | TDC fifo low 32-bits
35 | ro | tdc_fifo_data_hi | DLTDC | TDC fifo high 32-bits and fifo rdack
36 | rw | dl_input_mask | DLTDC | DL trigger input mask
37 | rw | dl_ctrl | DLTDC | DL trigger control
38 | rw | tdc_input_mask | DLTDC | TDC input mask
39 | ro | axi_fifo_status | DLTDC | AXI fifo status
</pre>

== reg 0x00 write bits ==

<pre>
bit | fw revision | quartus signal | description
0 | all | | latch scalers
1 | all | | zero scalers
2 | ... | fifo_rdreq_out | fifo_rdreq_out (not used in version 0x607f6709 and later)
3 | ... | ts_clk_pll_extswitch_out | clear ts_clk_pll_extswitch_out
4 | ... | ts_clk_pll_extswitch_out | set ts_clk_pll_extswitch_out
</pre>

== reg 16 fifo status ==

Data fifo status bits:
<pre>
31: fifo_full - data fifo is current full
30: fifo_empty - data fifo is currently empty
29: cb_fifo_ch_full - TSC per-channel fifos have overflown at some point
28: fifo_full_latch - data fifo has overflown at some point
24+4: 0
0+24: fifo_usedw
</pre>

== reg 28 ==

Timestamp clock PLL status bits:
<pre>
31 : PLL locked
30 : PLL active clock (0=internal, 1=external
29 : external clock bad
28 : internal clock bad
27 : ts_clk_pll_extswitch
0..26 : not used
</pre>

== reg 32 timestamp sync ==

Timestamp synchronization register bits:
<pre>
31 : write 1 to arm timestamp sync circuit, scalers and TSCs are placed in reset state
30 : write 1 to disarm timestamp sync circuit, reset is released
...
16 : write 1 to send a timestamp sync signal
15 : sync circuit armed
14 : sync done
13 : sync signal received (cleared by writing bits 31 or 30)
12 : 0
11 : sync circuit armed, clk_ts section
10 : sync done, clk_ts section
9 : sync signal received, clk_ts section
8 : 0
7 : unused
...
0 : unused
</pre>

nominal sequence for synchronizing timestamps:
* make sure nothing is sending the external sync signal (i.e. run is stopped, etc)
* arm the sync circuit: cb_write32(32, 0x80000000); cb_write32(32, 0);
* check that the arming was successful: cb_read32(32), only bits 0x8800 should be set
* scalers are in reset state, not incrementing
* TSCs are in reset state, no data in the TSC FIFO
* some time later, send the external sync signal
* or send the internal sync signal: cb_write32(32, 0x10000); cb_write32(32, 0);
* check that the timestamp reset happened: cb_read32(32), bits 0x6600 should be set, bits 0x8800 should be cleared
* check that the scalers are counting, check that there is TSC data in the TSC FIFO

== reg 33, 39 TDC and AXI FIFO status ==

<pre>
bit | mask | description
31 | 0x80000000 | fifo empty
30 | 0x40000000 | fifo full
15:0 | 0x0000FFFF | fifo usedw (64-bit words)
</pre>

== Timestamp clock ==

Timestamp clock is 10 MHz selectable from internal oscillator or external reference on the CLK_IN input.

CLK_IN input can be selected using 2 two-position jumpers:
* NIM input: CLK<->NIM/TTL and CLK<->NIM

To select the clock from command line, use:
* test_cb.exe intclk # select internal clock
* test_cb.exe extclk # select external clock

From software:
<pre>
Chronobox* cb = ...;
cb->cb_int_clock(); # select internal clock
cb->cb_ext_clock(); # select external clock
</pre>

To see current status, run "test_cb.exe clocks":
<pre>
# ./test_cb.exe clocks
...
Chronobox firmware revision: 0x5bf7557e
...
clock status: ext_clk: counter 0x00cccf2a, freq 10000450.9 Hz, ts_clk: counter 0x00cccf2a, freq 10000450.9 Hz, PLL status 0xc0000000
</pre>

Reported is external clock frequency, currently selected timestamp clock frequency and PLL status (register 0x1C).

Normal values for the PLL status:
* internal clock: 0x80000000
* external clock: 0xC0000000
* external clock selected, but invalid: 0x60000000
* internal clock selected, external clock invalid: 0xa0000000

Disconnected/absent/broken external clock will report ext_clk frequency zero, bit 0x20000000 in the PLL status register 0x1C.

If external clock is CDM, set chronobox clock jumpers to "CLK NIM/TTL" and "NIM", use CDM 10 MHz clock output LEMO3B.

If external clock is another chronobox (usually LEMO output 0), set clock jumpers to "CLK NIM/TTL" and "TTL".

== LEMO outputs ==

LEMO connectors can be used as TTL level outputs:

* set the "bank a" and/or "bank b" jumpers for "output"
* set the lemo output multiplexor bits in register 0x1D
* set the "lemo output enable" bit in register 0x0D, use bits 24..31 for LEMO outputs 0..7.
* observe the corresponding LED is on or off according to the LEMO output TTL logic level

The function of each LEMO output is controlled by the lemo output multiplexor. Up to 16 different
signals can be routed into each output. This is controlled by register 0x1D.

Register 0x1D multiplexor control is 32 bits organized into 8 groups of 4 bits, per each of the 8 LEMO outputs: 0x76543210,
i.e. value 0x00000001 routes signal function 1 into output 0, and signal function 0 into outputs 1..7.

For each output, there are 16 possible signal functions (4 bits):

<pre>
bit | firmware signal | firmware revision | signal description
0 | cb_lemo_out_reg[n] | 0x5bfdc798 | output is controlled by register 0xB bits 0..7 for outputs 0..7
1 | clk_ts | 0x5bfdc798 | output is the 10MHz timestamp clock
2 | cb_sync_in_clk_ts | 0x607f6709 | daisy-chained timestamp sync signal (from control register or from sync input, see registers 30 and 31. see bit 0x10000 in register 32)
3..30 | gnd | 0x5bfdc798 | not used
31 | vcc | 0x5bfdc798 | logic level 1
</pre>

== front panel LEDs ==

The front panel LEDs are numbered 0..7 per [[#Chronobox_connectors]]

Each LED can be individually lit by setting a bit in register 0x1 bits 8..15.

If LEMO outputs are active, corresponding LEDs will show LEMO output status (logic level 1 -> LED is on, logic level 0 -> LED is off).

If LEMO inputs are active ...

== Synchronization of multiple chronoboxes ==

To operate several chronoboxes as one unit, they must have two common signals, a clock and a sync signal.

Each chronobox must be configured as:
* master: this will issue the sync signal
* slave: will receive the clock and sync signals from master
* slave daisy-chain: and pass them to the next slave down the chain
* (one can use the CDM or the TRG as sync masters)

For the purpose of this example (recommended configuration), set the LEMO direction jumpers:
* bank A: set to "out": master and slave daisy-chain clock and sync output
* bank B: set to "in": slave sync input

Clock connections:
* sync master can be configured with external or internal clock (CLK_IN input)
* sync slave must be configured with external clock (CLK_IN input)
<pre>
sync master LEMO #0 -> slave CLK_IN, LEMO #0 -> next slave CLK_IN, LEMO #0 -> ...
10 MHz clock from CDM & etc -> sync master CLK_IN, LEMO #0 -> slave CLK_IN, ...
</pre>

Sync connections:
* sync signal can be generated externally by the CDM or TRG
* sync signal can be generated internally by writing 0x10000 into reg 32 of sync master
* (sync must be armed on the master and all slaves before sending the first sync signal, write 0x80000000 into reg 32)
<pre>
sync master LEMO #1 -> slave LEMO #4, LEMO #1 -> next slave LEMO #4 -> ...
external sync -> master LEMO #4, LEMO #1 -> slave LEMO #4 -> ...
</pre>

Sync configuration: (see register 32 for explanation!)
* master and slave: disarm sync: write 0x40000000 to reg 32, write 0 to reg 32, bits 0x8800 and 0x6600 should clear
* master and slave daisy chain: setup clock and sync outputs:
** register 29 lemo output mux to 0xXXXX'XX21 (2=output sync signal, 1=output clock)
** register 13 lemo output enable, set bits 0x0F00'0000 (set bank A jumper for "out")
* slave and slave daisy chain: enable external sync from LEMO #4:
** register 30, write 0
** register 31, write 0x10
* master: switch to external or internal clock, as needed
* slave: switch to external clock
* master and slave: arm sync: write 0x80000000 to reg 32, write 0 to reg 32, bits 0x8800 should turn on.
* timestamps, scalers and data fifo go into the reset state, all old data is cleared
* when sync is received, timestamp is reset to zero, reset state is cleared and there should be data into FIFO. reg 32 will read 0x6600.
* if using external sync (no master), wait for reg 32 bits to become 0x6600 (sync completed)
* master: issue sync signal, write 0x10000 to reg 32, write 0 to reg 32. master reg 32 should read 0x6600, slave reg 32 should read 0x6600.

== FIFO data format ==

* 0x8ntttttt: TSC data, 24 bits "tttttt" of timestamp, 7 bits "nn" of channel number, top bit set to 1. Low bit of "t" indicates 0=leading edge, 1=trailing edge.
* 0xffTTmmmm: (before 20220420_ko_0x62608957) timestamp wrap around marker: "TT" is the top 8 bits of the timestamp, "mmmm" is a 16 bit counter
* 0xff8mmmmm: timestamp wrap around marker: bit 24 is the top bit of the timestamp (0/8), "mmmmm" is a 23 bit counter
* 0xfe00nnnn: scaler data, following "nnnn" words are the latched scalers
* 0xfd000000: start of data after chronobox sync (cbtrg only, for now)

Time range is (before 20220420_ko_0x62608957):
* 24 bits of "tttttt"
* 15 bits of "mmmm"
* computation:
<pre>
(gdb) p (100.0*1.0*0x00007FFF*1.0*0x00FFFFFF)/(1e9)/3600.0
$22 = 15.270527886249999 ### in hours
</pre>

Time range is:
* 24 bits of "tttttt"
* 22 bits of "mmmmm"
* computation:
<pre>
(gdb) p (100.0*1.0*0x003FFFFF*1.0*0x00FFFFFF)/(1e9)/3600.0
$2 = 1954.6867557262499 ### in hours
$3 = 81.445281488593736 ### in days
</pre>

== timestamp wrap around marker ==

The timestamp data is only 24 bits, to allow timestamping
with longer time range, wrap around markers are added to the
data stream.

For input signals that arrive close to the time of timestamp wrap around,
there is ambiguity in the ordering of the data fifo: does the wrap around
marker or the signal timestamp show up first? For example for rare
signals, one can see this:
<pre>
wrap 1
wrap 2
timestamp 0x00000003
wrap 3
wrap 4
</pre>
does the hit belong with wrap marker 2 (written to the fifo just after wrap marker 2)
or with marker 3 (written to the fifo just before wrap marker 3)?

To remove this ambiguity, additional markers are written to the data stream
half way between the wrap arounds, making it obvious that the signal
arrived right after wrap marker 3 (but was written to the FIFO before the marker):
<pre>
wrap 1 0x00
wrap 1 0x80
wrap 2 0x00
wrap 2 0x80
timestamp 0x00000003
wrap 3 0x00
wrap 3 0x80
</pre>

= test_cb.exe =

test_cb.exe is the general test program for the chronobox.

* test_cb.exe 0 # read chronobox register 0
* test_cb.exe 4 0x1234 # write to chronobox register 4
* test_cb.exe fpga 0 # read FPGA LW bridge address 0
* test_cb.exe fpga 0 0x12345678 # write 0x12345678 to FPGA LW bridge address 0
* test_cb.exe reboot # reboot the FPGA (the ARM CPU keeps running)
* test_cb.exe scalers # read all scalers in a loop
* test_cb.exe fifo # read the data fifo in a loop
* test_cb.exe tsfifo # read the timestamp fifo in a loop (do not latch scalers)
* test_cb.exe intclk # select internal timestamp clock
* test_cb.exe extclk # select external timestamp clock (10MHz)
* test_cb.exe clocks # report current status of timestamp clock

= Errata =

* 0x607f6709 - after FIFO reset (timestamp sync, etc), the first word in the FIFO is always 0x00000000, not a real timestamps.
* 20220420_ko_0x62608957 - after FIFO reset (timestamp sync), the first word in the FIFO is 0xFF000000, a timestamp overflow marker, as expected. after FPGA reboot (before timestamp sync), the first word in the FIFO is also 0xFF000000 for reasons unknown.
* linux - after power up, chronobox registers are not accessible, check that the FPGA bridges are enabled, if any bridge reports "disabled", reboot linux. do NOT cycle power.
<pre>
root@cb04:~# cat /sys/class/fpga_bridge/br*/state
enabled
enabled
enabled
enabled
root@cb04:~#
</pre>

= TODO =

* FIXED 23apr2021 - use updated "bootcmd". figure out why FPGA bridges are disabled on first power up
* figure out how to load FPGA sof from Linux, probably need new kernel
* FIXED apr2022, use fw_printenv build from source - fix fw_printenv, probably requires using newer uboot
* add mmap driver for FPGA LW bridge, probably need new kernel
* figure out how to build linux kernel from git (now using kernel from GHRD demo kit)
* enable watchdog timer to auto-reboot on hang
* figure out why ssh takes 30 second to start. read this: https://daniel-lange.com/archives/152-Openssh-taking-minutes-to-become-available,-booting-takes-half-an-hour-...-because-your-server-waits-for-a-few-bytes-of-randomness.html https://lwn.net/Articles/800509/
* FIXED 20220420_ko_0x62608957 - fix problem on startup first word in the FIFO is 0x00000000.
* FIXED 20220420_ko_0x62608957 - increase number of bits in the timestamp wraparound counter: 0xFF8mmmmm -> 23 bits is possible, keep high bit 0x00800000 as is.

= ZZZ =

Chronobox

2024-07-15T21:45:27Z

Olchansk: /* reg 33, 39 TDC and AXI FIFO status */

= Chronobox =

= Links =

* https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano
* https://bitbucket.org/expalpha/chronobox_firmware
* https://bitbucket.org/expalpha/chronobox_software
* https://edev-group.triumf.ca/hw/alphag/chrono-box/rev0
* https://bitbucket.org/expalpha/chronobox_firmware/src/master/docs/Chrono.pdf

= Chronobox connectors =

<pre>
|
| LEMO - CLK_IN - jumpers: SINE<->CLK<->NIM/TTL and NIM<->CLK<->TTL
|
| ECL P1
| 32
| |
| 1
|
| ECL P2
| 32
| |
| 1
|
| PLED - power-on LED
|
| jumper: bank A direction IN<->X<->OUT
| LEMO 0-1
| LED 0-1
| LEMO 2-3
| LED 2-3
|
| jumper: bank B direction IN<->X<->OUT
| LEMO 4-5
| LED 4-5
| LEMO 6-7
| LED 6-7
|
</pre>

= Electrical connections =

* ECL P1 and P2: LeCroy 4616 compatible
* LEMO TTL inputs: 0..5V, logic level 0: <0.8V, logic level 1: >2V
* LEMO TTL outputs: logic level 0: 0V, logic level 1: 5V to 3.3V
* clock NIM input: NIM compatible
* clock TTL input: ???
* clock sine wave input: ???

= Input channel mapping =

* 0+16 : first ECL connector
* 16+16 : second ECL connector
* 32+8 : LEMO inputs (TTL)
* 40+18 : GPIO inputs (FPGA pins)
* 58 : external clock (10 MHz nominal)
* 59 : internal clock (100 MHz)

= Functional units =

== Scalers ==

TBW

=== Firmware 0x61832695 ===

* minimum pulse width (leading edge to trailing edge): longer than 10 ns (15 ns is safe) (sampled by 100 MHz/ 10 ns clock)
* minimum time between pulses (trailing edge to next leading edge): longer than 10 ns (15 ns is safe) (ditto)

=== Firmware 0x624e22ad ===

* minimum pulse width: leading edge triggered (2 ns is safe)
* minimum time between pulses (trailing edge to next leading edge): 25 ns or more is safe

== Timestamps (TSC) ==

TBW

=== Firmware 0x61832695 ===

* minimum pulse width (leading edge to trailing edge): longer than 100 ns (105 ns is safe) (sampled by 10 MHz/100 ns clock)
* minimum time between pulses (trailing edge to next leading edge): longer than 100 ns (105 ns is safe) (ditto)

=== Firmware 0x624e22ad ===

* minimum pulse width: leading edge triggered (5 ns is safe)
* minimum time between pulses (trailing edge to next leading edge): longer than 200 ns (205 ns is safe) (sampled by 10 MHz/100 ns clock)

Each TSC input has a 256 entry FIFO. (LE is 1 entry, TE is 1 entry, so 128 hits if both LE and TE enabled).

== Output data fifo ==

TBW

=== Firmware before 0x61832695 ===

Output fifo is 4096 entries deep.

=== Firmware 0x624e22ad ===

Output fifo is 64k entries deep.

= Initial hardware setup =

* refer to DE10-NANO information here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano
* prepare hardware:
** remove chronobox from enclosure (cannot access JTAG connector when installed)
** remove DE10-Nano from chronobox baseboard
** check that SW10 jumpers are: U-D-U-U-D-U. (U=up, D=down, when "ALTERA" text on the FPGA is right side up)
** reinstall DE10-Nano on chronobox baseboard
** do NOT reinstall chronobox in enclosure
* prepare software:
** check that you have quartus 17.1 (at /opt/intelFPGA/17.1/ in this example)
** check that you installed chronobox software in /home/agdaq/online/chronobox_software
** check that you installed chronobox firmware project in /home/agdaq/online/firmware/git/chronobox_firmware
* connect serial console, for more info, go here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#Serial_console
** connect a mini-USB (*not* Micto-USB!) cable from mini-USB port on the side of the ethernet connection to a PC
** minicom -D /dev/ttyUSB0 -b 115200
* connect fpga jtag, for more info, go here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#JTAG
** connect a mini-USB (*not* Micro-USB!) cable on the side of HDMI and power connectors to a PC
** /opt/intelFPGA/17.1/quartus/bin/jtagconfig
* prepare SD flash card for booting from network: generic instructions are here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#boot_Linux_from_SD_flash
** connect new or used 8GB SD flash card to USB flash adapter to a linux computer
** login as root
** identify the flash device as /dev/sdX. Use "lsblk" or "blkid" or "dmesg". be careful to not write to the computer system disk (usually /dev/sda)
** echo -e 'o\nn\np\n1\n2048\n4095\nn\np\n2\n4096\n1681816\nn\np\n3\n\n\nt\n1\na2\nt\n2\nb\nw' | fdisk /dev/sdX
** eject /dev/sdX
** remove card, reintall card, this is to ensure we use the new partition table
** fdisk -l /dev/sdX
<pre>
root@daq01:~# fdisk -l /dev/sdg
Disk /dev/sdg: 7.38 GiB, 7910457344 bytes, 15450112 sectors
Disk model: STORAGE DEVICE
Units: sectors of 1 * 512 = 512 bytes
Sector size (logical/physical): 512 bytes / 512 bytes
I/O size (minimum/optimal): 512 bytes / 512 bytes
Disklabel type: dos
Disk identifier: 0xa033868b

Device Boot Start End Sectors Size Id Type
/dev/sdg1 2048 4095 2048 1M a2 unknown
/dev/sdg2 4096 1681816 1677721 819.2M b W95 FAT32
/dev/sdg3 1683456 15450111 13766656 6.6G 83 Linux
root@daq01:~#
</pre>
** dd if=/daq/daqstore/olchansk/daq/DE10-Nano/image-1-fpga.img of=/dev/sdX1 bs=1024k
** dd if=/daq/daqstore/olchansk/daq/DE10-Nano/image-2-uboot.img of=/dev/sdX2 bs=1024k
** eject /dev/sdX
* install prepared flash card into the chronobox DE10-Nano
* cycle power
* in the minicom window, IMMEDIATELY press the space bar to stop automatic booting (if it doesn't react, ensure flow control is disabled in minicom)
* you will have the uboot "=>" prompt
* confirm uboot version: U-Boot 2013.01.01
* setup uboot to boot linux from network, more details here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#boot_Linux_from_network
** setenv ethaddr 02:aa:bb:cc:cb:04 # for cb04, see below for explanation
** setenv bootcmd 'run bridge_enable_handoff; run netboot'
** setenv ramboot bootz \${loadaddr} - \${fdtaddr}
** setenv bootargs console=ttyS0,115200 ip=dhcp root=/dev/nfs rw nfsroot=192.168.1.1:/zssd1tb/nfsroot/%s,vers=3 panic=15
** saveenv
** reset
* DE10-Nano should boot into linux:
** uboot will restart
** DHCP will run
** tftp load of linux kernel will run
** linux kernel will start
** linux kernel will get an IP address
** linux kernel will NFS-mount the root filesystem (.../nfsroot/cb04)
** systemd will start all services
** there will be a login prompt on minicom console
** ssh will work (maybe 1 minute delay before it starts)
* try a few things:
** from agdaq or agmini account, ssh root@cb04
** "df" should show /home/agdaq is mounted (and ssh agdaq@cb04 should work)
** "/home/agdaq/online/chronobox_software/test_cb.exe 0" should fail ("bus error") because FPGA is not loaded yet
* load sof file, for more info, go here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#JTAG
** /opt/intelFPGA/17.1/quartus/bin/quartus_pgm -m JTAG -o "p;/home/agdaq/online/firmware/git/chronobox_firmware/output_files/DE10_NANO_SoC_GHRD.sof@2"
* "test_cb.exe 0" should work now
* use srunner_cb.exe to load the pof file into FPGA boot flash
* use reboot_cb.exe to reboot the FPGA from flash
* "test_cb.exe 0" should report the expected FPGA firmware version number.
* success.

== assign ethernet MAC address ==

Usually ethernet MAC address is assigned by manufacturer and is stored in a tiny little flash chip. The DE10-Nano board
is too cheap and does not have it. So a fake ethernet address has to be assigned manually from
the "locally administered range" of MAC addresses that start from "02:...", see
https://en.wikipedia.org/wiki/MAC_address#Ranges_of_group_and_locally_administered_addresses

All MAC addresses must be unique on an ethernet network, but with manual assignement confusion is easy to create.

For chronobox devices, use MAC addresses that start with "l02:aa:bb:cc:xx:yy" and have last digits "cb:01", "cb:02", "cb:03", "cb04" for the first four chronoboxes.

== new board test checklist ==

to check newly built chronobox baseboard, follow this checklist.

=== test ECL inputs ===

* stop midas frontend
* ssh agdaq@alphagdaq ### or agmini@daq16
* ssh root@cb03
* /home/agdaq/online/chronobox_software/test_cb.exe 0 ### read firmware revision, confirm communication with chronobox firmware
* /home/agdaq/online/chronobox_software/test_cb.exe inputs ### output should look like this:
<pre>
inputs: ecl_p1: 0xaa55, ecl_p2: 0xaa55, lemo: 0xe0, gpio: 0x3ffff
</pre>
* connect ECL ribbon cable from LeCroy 4616 NIM-to-ECL converter to chronobox ECL_P1 input (left one)
* ecl_p1 input should read 0x0000
* connect lemo jumper from NIM logic level 1 otput (i.e. any module OUT-bar output) to first channel of LeCroy 4616, ecl_p1 should read 0x0001
* move to 2nd channel, get 0x0002
* and so forth until last channel 0x8000.
* if any channel does not give expected reading, attach label (i.e. "ECL_P1 0x0002 bad") and send for repair.
* repeat with ECL_P2 input (right one), watch printed value of ecl_p2.

=== test TTL inputs ===

* NOTE: front panel LEMO connector labels are wrong. correct numbering of LEMO connectors is as shown in [[#Chronobox connectors]]
* disconnect all LEMO inputs
* set "bank A direction" and "bank B direction" for input
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_in_a # set bank A to input
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_in_b # set bank B to input
* all 8 LEMO LEDs should be on
* /home/agdaq/online/chronobox_software/test_cb.exe inputs ### lemo inputs should read 0xFF
* connect LEMO 0 (left bottom) to TTL output of Lecroy 222 or equivalent, set "scale" to "latch", operate push buttons to turn output on and off (LED should come in and out).
* /home/agdaq/online/chronobox_software/test_cb.exe inputs
<pre>
inputs: ecl_p1: 0xaa55, ecl_p2: 0xaa55, lemo: 0xfe (~0x01), gpio: 0x3ffff
</pre>
* change TTL signal from logic level 0 to 1 and back, observe the corresponding LED to turn on and off, observe the correct bit in the "lemo" column (watch the inverted input ~0x01) change.
* repeat with LEMO input 1 (left top) through 7 (right top).

=== test TTL outputs ===

* NOTE: front panel LEMO connector labels are wrong. correct numbering of LEMO connectors is as shown in #Chronobox connectors
* set "bank A direction" and "bank B direction" for output
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_a 0
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_b 0
* all LEMO LEDs should be off
* with voltmeter measure LEMO output voltage should be 0.135 V
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_a 0xF
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_b 0xF
* all LEMO LEDs should be on
* with voltmeter measure LEMO output voltage should be 3.4 to 3.8 V
* if you measure 1.69 V, the bank direction switch is still in the "input" position
* to test individual output, instead of 0xF use 0x1, 0x2, 0x4 and 0x8.

=== test clock input ===

* we test the TTL input mode first
* disconnect CLK_IN input
* /home/agdaq/online/chronobox_software/test_cb.exe intclk ### switch to internal timestamp clock
* /home/agdaq/online/chronobox_software/test_cb.exe clocks
<pre>
clock status: ext_clk: counter 0x00000000, freq 0.0 Hz, ts_clk: counter 0x00cccccc, freq 9999999.4 Hz, PLL status 0xa0000000
</pre>
notice: ts_clk frequency is around 10 MHz (internal oscillator) and ext_clk frequency is zero (nothing connected)
* if ts_clk is not around 10 MHz, PLL is not locked correctly, reboot the FPGA and try again: /home/agdaq/online/chronobox_software/test_cb.exe reboot
* set CLK_IN jumpers to "TTL/NIM" and "TTL" position
* connect LEMO cable from LEMO output 0 (bottom left) to CLK_IN
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_clk 0 ### output timestamp clock on LEMO output 0
* /home/agdaq/online/chronobox_software/test_cb.exe clocks
<pre>
clock status: ext_clk: counter 0x00cccccc, freq 9999999.4 Hz, ts_clk: counter 0x00cccccc, freq 9999999.4 Hz, PLL status 0x80000000
</pre>
* observe ext_clk frequency is the same as ts_clk frequency
* to test NIM input mode, we need a NIM clock signal, i.e. from a VME-NIMIO32, etc. Or use a TTL-to-NIM converter to use clock on LEMO output 0.
* set CLK_IN jumpers to "TTL/NIM" and "NIM" position
* connect VME-NIMIO32 NIM output 3 (40 MHz V1190 clock) to CLK_IN
* /home/agdaq/online/chronobox_software/test_cb.exe clocks
<pre>
clock status: ext_clk: counter 0x03333c0c, freq 40001687.4 Hz, ts_clk: counter 0x00cccccc, freq 9999999.4 Hz, PLL status 0x80000000
</pre>
* observe ext_clk frequency is 40 MHz.
* to test "sine wave" input mode, TBW, do not have a sine wave signal source.

K.O.

=== test GPIO pins ===

TBW

= Install chronobox software =

<pre>
cd /home/agdaq/online
git clone https://bitbucket.org/expalpha/chronobox_software.git
cd chronobox_software
make clean
make
ls -l *.exe
-rwxr-xr-x 1 olchansk users 18808 Aug 16 15:26 reboot_cb.exe
-rwxr-xr-x 1 olchansk users 47256 Aug 16 15:26 srunner_cb.exe
-rwxr-xr-x 1 olchansk users 20732 Aug 16 15:26 test_cb.exe
</pre>

= Install chronobox quartus firmware project =

<pre>
cd /home/agdaq/online/firmware/git
git clone https://bitbucket.org/expalpha/chronobox_firmware.git
cd chronobox_firmware
git fetch ### update repository
git tag ### list available tags
git checkout 20210420_ko ### checkout a specific version
git status
cat timestamp.v ### confirm firmware version
ls -l output_files/*.{jic,sof,rpd}
</pre>

= Firmware revisions =

* 0x5aceaed2 - April 2018 - all inputs connected to counters (except ext clock), 58 inputs, 50 MHz clock
* 0x5b6de806 - August 2018 - added fpga boot flash programmer and fpga reboot
* 0x5b7c827d - August 2018 - bshaw added debounce on GPIO inputs (for flow meters), 100 MHz clock
* 0x5b873169 - August 2018 - rebuilt, no changes
* 0x5b89e4b4 - August 2018 - added external clock signal, 59 inputs, 100 MHz clock
* 0x5b8de2b0 - September 2018 - added data fifo and timestamp counters (TSCs) for the first 4 inputs
* 0x5b906c56 - September 2018 - improved overflow markers, added scalers readout into the data fifo
* 0x5da8e4c2 - October 2019 - timestamps for all inputs, inversion of inputs
* 0x5db764a7 - October 2019 - FPGA reboot works now.
* 0x607f6709 - April 2021 - working timestamp synchronization, memory mapped registers, improved sdc file, correct clock transfers
* 0x60860e61 - April 2021 - faster data FIFO readout (from ~8 Mbytes/sec to ~80 Mbytes/sec)
* 0x61832695 - Nov 2021 - increase timestamp FIFO from 4k to 64k words
* 20220406_ko_0x624e22ad - April 2022 - make inputs edge-triggered instead of sampled.
* 20220420_ko_0x62608957 - April 2022 - fix first fifo data word is zero

= Firmware update =

* use srunner_cb.exe to load firmware RPD file into EPCQ flash memory.
* if FPGA is not running compatible firmware, srunner_cb will fail
* connect JTAG and load the firmware sof file from the quartus project (use "make load_sof")
* if JTAG is connected, one can use "make load_jic" to load firmware jic file into EPCQ flash memory.

After correct firmware is loaded, access to chronobox registers may fail (srunner_cb will not work)
because FPGA bridges are not enabled. To check, run following commands. If some bridge reports "disabled", reboot linux (do not cycle the power!).
<pre>
root@cb02:~# cat /sys/class/fpga_bridge/br*/state
enabled
enabled
enabled
enabled
root@cb02:~#
</pre>

Some DE10-Nano boards have an EPCQ64 flash memory chip, some have the EPCQ128 flash memory chip.
* identify EPCQ64 and use "-64" with all srunner commands:
<pre>
cd /home/agdaq/online/chronobox_software
./srunner_cb.exe -id -64 /dev/null # identify EPCS64 flash
...
Info: Silicon ID - 0x16
Info: Serial Configuration Device - EPCS64
</pre>
* identify EPCQ128 and use "-128" with all srunner commands:
<pre>
./srunner_cb.exe -id -128 /dev/null # identify EPCQ128 flash
...
Info: Silicon ID - 0x18
Info: Serial Configuration Device - EPCS128
</pre>

Identify -64 or -128 flash memory, write RPD file to flash memory, verify and reboot the fpga:

<pre>
cd /home/agdaq/online/chronobox_software
./srunner_cb.exe -id -64 /dev/null # identify EPCS64 flash
./srunner_cb.exe -id -128 /dev/null # identify EPCQ128 flash
#./srunner_cb.exe -read -128 test.rpd # read flash contents into a file
./srunner_cb.exe -program -128 /home/agdaq/online/firmware/git/chronobox_firmware/output_files/DE10_NANO_SoC_GHRD_auto.rpd
./srunner_cb.exe -verify -128 /home/agdaq/online/firmware/git/chronobox_firmware/output_files/DE10_NANO_SoC_GHRD_auto.rpd
./reboot_cb.exe # reboot the fpga into the new firmware
</pre>

= Firmware build =

for building firmware use: /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh

<pre>
ssh daq01
cd online
git clone git@bitbucket.org:expalpha/chronobox_firmware.git
cd chronobox_firmware
/opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
make quartus
ls -l output_files/*.{sof,jic,rpd}
-rw-r--r-- 1 olchansk users 7007185 Apr 20 16:57 output_files/DE10_NANO_SoC_GHRD_auto.rpd
-rw-r--r-- 1 olchansk users 8388833 Apr 20 16:57 output_files/DE10_NANO_SoC_GHRD.jic
-rw-r--r-- 1 olchansk users 7510701 Apr 20 16:57 output_files/DE10_NANO_SoC_GHRD.sof
</pre>

other make targets:
* make quartus - build fpga programmer files: sof, jic and rpd.
* make clean - clean the quartus project
* make qsys - regenerate the qsys block
* make jic - regenerate the jic file
* make load_sof - load sof file into fpga via jtag
* make load_jic - load jic file into fpga boot flash (epcq) via jtag
* make verify_jic - verify jic checksum in fpga boot flash (epcq)

for jtag access, use /daq/quartus/13.1.3.178/quartus/bin/jtagconfig

<pre>
daq16:chronobox_firmware$ /daq/quartus/13.1.3.178/quartus/bin/jtagconfig
1) DE-SoC [2-1.4.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) Remote server daq16: Unable to connect

daq16:chronobox_firmware$
</pre>

== Errata ==

* after regenerating qsys, manually edit ./soc_system/synthesis/submodules/hps_sdram_pll.sv to comment-out line "assign pll_dr_clk = clk_out[2];"

= Firmware details =

* DDR3 clock is 400 MHz (DDR3-800)
* memcpy speed ~1500 Mbytes/sec
* FIFO access single word read: 80, 44, 44 clocks at 10 ns/clock is 2.3 MHz at 4 bytes/word is 9 Mbytes/sec
* FIFO access memcpy: burst 2, delay 32, b4, delay 36, b5, d1, b5, d1, b5, d1, b1, delay 53, repeat. this reads 16 words in 72 clocks at 10 ns/clock is 1.388 MHz at 4*16=64 bytes/burst is 88.9 Mbytes/sec.

= Chronobox firmware registers =

<pre>
reg | rw/ro | quartus name | firmware | description
0 | ro | sof_revision_in | all | firmware revision timestamp code
0 | wo | latch_scalers_out, zero_scalers_out | all | see [[#reg_0x00_write_bits]]
1 | rw | reg1_led_out | all | DE10-Nano LED output
2 | ro | switches_in | all | read DE10-Nano switches
3 | ro | buttons_in | all | read DE10-Nano buttons
4 | rw | reg4_test | all | 32-bit read-write test register
5 | rw | flash_programmer_in, reg5_flash_programmer_out | 0x5b6de806 | 0xABCD srunner flash programmer
6 | ro | ecl_in | all | read state of ECL inputs
7 | ro | reg7_test_in | all | ???
8 | rw | scaler_addr_out, reg8_scaler_data_in | all | top 16 bits of address becomes scaler bus address, 32 bit read is the corresponding scaler data
9 | ro | lemo_in | all | read state of LEMO inputs
10/0xA | ro | gpio_in | all | read state of GPIO inputs
11/0xB | rw | regB_lemo_out | all | LEMO output data
12/0xC | rw | regC_gpio_out | all | GPIO output data
13/0xD | rw | regD_out_enable_out | all | enable output tristates: [31:24] - LEMO_OUT, [17:0] - GPIO_OUT
14/0xE | rw | regE, reconfig_out | 0x5b6de806 | FPGA reboot: write inverted firmware revision (reg0) to reboot the FPGA
15/0xF | ro | regF_input_num_in | 0x5b89e4b4 | number of chronobox inputs (to read scalers, add 1 for the clock counter)
16/0x10 | ro | reg10_fifo_status | 0x5b8de2b0 | data fifo status, see below
17/0x11 | ro | reg11_fifo_data | 0x5b8de2b0 | data fifo data, see below
18/0x12 | rw | cb_invert_a | 0x5bf7557e | invert inputs 31..0
19/0x13 | rw | cb_invert_b | 0x5bf7557e | invert inputs 63..32
20/0x14 | rw | cb_enable_le_a | 0x5bf7557e | enable TSC leading edge inputs 31..0
21/0x15 | rw | cb_enable_le_b | 0x5bf7557e | enable TSC leading edge inputs 63..32
22/0x16 | rw | cb_enable_te_a | 0x5bf7557e | enable TSC trailing edge inputs 31..0
23/0x17 | rw | cb_enable_te_b | 0x5bf7557e | enable TSC trailing edge inputs 63..32
24/0x18 | ro | fc_ext_clk_100_counter | 0x5bf7557e | external clock frequency counter 100MHz reference
25/0x19 | ro | fc_ext_clk_ext_counter | 0x5bf7557e | external clock frequency counter
26/0x1A | ro | fc_ts_clk_100_counter | 0x5bf7557e | timestamp clock frequency counter 100MHz reference
27/0x1B | ro | fc_ts_clk_ts_counter | 0x5bf7557e | timestamp clock frequency counter
28/0x1C | ro | ts_clk_pll_status | 0x5bf7557e | timestamp clock PLL status
29/0x1D | rw | cb_lemo_out_mux_ctrl | 0x5bfdc798 | 8*4 bits to control 8 LEMO output multiplexers (4 bits/16 options each mux, see [[#LEMO outputs]])
30/0x1E | rw | cb_sync_mask[31:0] | 0x607f6709 | source of chronobox sync signal, low bits
31/0x1F | rw | cb_sync_mask[63:32] | 0x607f6709 | source of chronobox sync signal, high bits
32 | rw | cb_sync_reg[31:0], cb_sync_status[31:0] | 0x607f6709 | control of timestamp sync
33 | ro | tdc_fifo_status | DLTDC | TDC fifo status
34 | ro | tdc_fifo_data_lo | DLTDC | TDC fifo low 32-bits
35 | ro | tdc_fifo_data_hi | DLTDC | TDC fifo high 32-bits and fifo rdack
36 | rw | dl_input_mask | DLTDC | DL trigger input mask
37 | rw | dl_ctrl | DLTDC | DL trigger control
38 | rw | tdc_input_mask | DLTDC | TDC input mask
39 | ro | axi_fifo_status | DLTDC | AXI fifo status
</pre>

== reg 0x00 write bits ==

<pre>
bit | fw revision | quartus signal | description
0 | all | | latch scalers
1 | all | | zero scalers
2 | ... | fifo_rdreq_out | fifo_rdreq_out (not used in version 0x607f6709 and later)
3 | ... | ts_clk_pll_extswitch_out | clear ts_clk_pll_extswitch_out
4 | ... | ts_clk_pll_extswitch_out | set ts_clk_pll_extswitch_out
</pre>

== reg 16 fifo status ==

Data fifo status bits:
<pre>
31: fifo_full - data fifo is current full
30: fifo_empty - data fifo is currently empty
29: cb_fifo_ch_full - TSC per-channel fifos have overflown at some point
28: fifo_full_latch - data fifo has overflown at some point
24+4: 0
0+24: fifo_usedw
</pre>

== reg 28 ==

Timestamp clock PLL status bits:
<pre>
31 : PLL locked
30 : PLL active clock (0=internal, 1=external
29 : external clock bad
28 : internal clock bad
27 : ts_clk_pll_extswitch
0..26 : not used
</pre>

== reg 32 timestamp sync ==

Timestamp synchronization register bits:
<pre>
31 : write 1 to arm timestamp sync circuit, scalers and TSCs are placed in reset state
30 : write 1 to disarm timestamp sync circuit, reset is released
...
16 : write 1 to send a timestamp sync signal
15 : sync circuit armed
14 : sync done
13 : sync signal received (cleared by writing bits 31 or 30)
12 : 0
11 : sync circuit armed, clk_ts section
10 : sync done, clk_ts section
9 : sync signal received, clk_ts section
8 : 0
7 : unused
...
0 : unused
</pre>

nominal sequence for synchronizing timestamps:
* make sure nothing is sending the external sync signal (i.e. run is stopped, etc)
* arm the sync circuit: cb_write32(32, 0x80000000); cb_write32(32, 0);
* check that the arming was successful: cb_read32(32), only bits 0x8800 should be set
* scalers are in reset state, not incrementing
* TSCs are in reset state, no data in the TSC FIFO
* some time later, send the external sync signal
* or send the internal sync signal: cb_write32(32, 0x10000); cb_write32(32, 0);
* check that the timestamp reset happened: cb_read32(32), bits 0x6600 should be set, bits 0x8800 should be cleared
* check that the scalers are counting, check that there is TSC data in the TSC FIFO

== reg 33, 39 TDC and AXI FIFO status ==

<pre>
bit | mask | description
31 | 0x80000000 | fifo empty
30 | 0x40000000 | fifo full
15:0 | 0x0000FFFF | fifo usedw (64-bit words)
</pre>

== Timestamp clock ==

Timestamp clock is 10 MHz selectable from internal oscillator or external reference on the CLK_IN input.

CLK_IN input can be selected using 2 two-position jumpers:
* NIM input: CLK<->NIM/TTL and CLK<->NIM

To select the clock from command line, use:
* test_cb.exe intclk # select internal clock
* test_cb.exe extclk # select external clock

From software:
<pre>
Chronobox* cb = ...;
cb->cb_int_clock(); # select internal clock
cb->cb_ext_clock(); # select external clock
</pre>

To see current status, run "test_cb.exe clocks":
<pre>
# ./test_cb.exe clocks
...
Chronobox firmware revision: 0x5bf7557e
...
clock status: ext_clk: counter 0x00cccf2a, freq 10000450.9 Hz, ts_clk: counter 0x00cccf2a, freq 10000450.9 Hz, PLL status 0xc0000000
</pre>

Reported is external clock frequency, currently selected timestamp clock frequency and PLL status (register 0x1C).

Normal values for the PLL status:
* internal clock: 0x80000000
* external clock: 0xC0000000
* external clock selected, but invalid: 0x60000000
* internal clock selected, external clock invalid: 0xa0000000

Disconnected/absent/broken external clock will report ext_clk frequency zero, bit 0x20000000 in the PLL status register 0x1C.

If external clock is CDM, set chronobox clock jumpers to "CLK NIM/TTL" and "NIM", use CDM 10 MHz clock output LEMO3B.

If external clock is another chronobox (usually LEMO output 0), set clock jumpers to "CLK NIM/TTL" and "TTL".

== LEMO outputs ==

LEMO connectors can be used as TTL level outputs:

* set the "bank a" and/or "bank b" jumpers for "output"
* set the lemo output multiplexor bits in register 0x1D
* set the "lemo output enable" bit in register 0x0D, use bits 24..31 for LEMO outputs 0..7.
* observe the corresponding LED is on or off according to the LEMO output TTL logic level

The function of each LEMO output is controlled by the lemo output multiplexor. Up to 16 different
signals can be routed into each output. This is controlled by register 0x1D.

Register 0x1D multiplexor control is 32 bits organized into 8 groups of 4 bits, per each of the 8 LEMO outputs: 0x76543210,
i.e. value 0x00000001 routes signal function 1 into output 0, and signal function 0 into outputs 1..7.

For each output, there are 16 possible signal functions (4 bits):

<pre>
bit | firmware signal | firmware revision | signal description
0 | cb_lemo_out_reg[n] | 0x5bfdc798 | output is controlled by register 0xB bits 0..7 for outputs 0..7
1 | clk_ts | 0x5bfdc798 | output is the 10MHz timestamp clock
2 | cb_sync_in_clk_ts | 0x607f6709 | daisy-chained timestamp sync signal (from control register or from sync input, see registers 30 and 31. see bit 0x10000 in register 32)
3..30 | gnd | 0x5bfdc798 | not used
31 | vcc | 0x5bfdc798 | logic level 1
</pre>

== front panel LEDs ==

The front panel LEDs are numbered 0..7 per [[#Chronobox_connectors]]

Each LED can be individually lit by setting a bit in register 0x1 bits 8..15.

If LEMO outputs are active, corresponding LEDs will show LEMO output status (logic level 1 -> LED is on, logic level 0 -> LED is off).

If LEMO inputs are active ...

== Synchronization of multiple chronoboxes ==

To operate several chronoboxes as one unit, they must have two common signals, a clock and a sync signal.

Each chronobox must be configured as:
* master: this will issue the sync signal
* slave: will receive the clock and sync signals from master
* slave daisy-chain: and pass them to the next slave down the chain
* (one can use the CDM or the TRG as sync masters)

For the purpose of this example (recommended configuration), set the LEMO direction jumpers:
* bank A: set to "out": master and slave daisy-chain clock and sync output
* bank B: set to "in": slave sync input

Clock connections:
* sync master can be configured with external or internal clock (CLK_IN input)
* sync slave must be configured with external clock (CLK_IN input)
<pre>
sync master LEMO #0 -> slave CLK_IN, LEMO #0 -> next slave CLK_IN, LEMO #0 -> ...
10 MHz clock from CDM & etc -> sync master CLK_IN, LEMO #0 -> slave CLK_IN, ...
</pre>

Sync connections:
* sync signal can be generated externally by the CDM or TRG
* sync signal can be generated internally by writing 0x10000 into reg 32 of sync master
* (sync must be armed on the master and all slaves before sending the first sync signal, write 0x80000000 into reg 32)
<pre>
sync master LEMO #1 -> slave LEMO #4, LEMO #1 -> next slave LEMO #4 -> ...
external sync -> master LEMO #4, LEMO #1 -> slave LEMO #4 -> ...
</pre>

Sync configuration: (see register 32 for explanation!)
* master and slave: disarm sync: write 0x40000000 to reg 32, write 0 to reg 32, bits 0x8800 and 0x6600 should clear
* master and slave daisy chain: setup clock and sync outputs:
** register 29 lemo output mux to 0xXXXX'XX21 (2=output sync signal, 1=output clock)
** register 13 lemo output enable, set bits 0x0F00'0000 (set bank A jumper for "out")
* slave and slave daisy chain: enable external sync from LEMO #4:
** register 30, write 0
** register 31, write 0x10
* master: switch to external or internal clock, as needed
* slave: switch to external clock
* master and slave: arm sync: write 0x80000000 to reg 32, write 0 to reg 32, bits 0x8800 should turn on.
* timestamps, scalers and data fifo go into the reset state, all old data is cleared
* when sync is received, timestamp is reset to zero, reset state is cleared and there should be data into FIFO. reg 32 will read 0x6600.
* if using external sync (no master), wait for reg 32 bits to become 0x6600 (sync completed)
* master: issue sync signal, write 0x10000 to reg 32, write 0 to reg 32. master reg 32 should read 0x6600, slave reg 32 should read 0x6600.

== FIFO data format ==

* 0x8ntttttt: TSC data, 24 bits "tttttt" of timestamp, 7 bits "nn" of channel number, top bit set to 1. Low bit of "t" indicates 0=leading edge, 1=trailing edge.
* 0xffTTmmmm: (before 20220420_ko_0x62608957) timestamp wrap around marker: "TT" is the top 8 bits of the timestamp, "mmmm" is a 16 bit counter
* 0xff8mmmmm: timestamp wrap around marker: bit 24 is the top bit of the timestamp (0/8), "mmmmm" is a 23 bit counter
* 0xfe00nnnn: scaler data, following "nnnn" words are the latched scalers
* 0xfd000000: start of data after chronobox sync (cbtrg only, for now)

Time range is (before 20220420_ko_0x62608957):
* 24 bits of "tttttt"
* 15 bits of "mmmm"
* computation:
<pre>
(gdb) p (100.0*1.0*0x00007FFF*1.0*0x00FFFFFF)/(1e9)/3600.0
$22 = 15.270527886249999 ### in hours
</pre>

Time range is:
* 24 bits of "tttttt"
* 22 bits of "mmmmm"
* computation:
<pre>
(gdb) p (100.0*1.0*0x003FFFFF*1.0*0x00FFFFFF)/(1e9)/3600.0
$2 = 1954.6867557262499 ### in hours
$3 = 81.445281488593736 ### in days
</pre>

== timestamp wrap around marker ==

The timestamp data is only 24 bits, to allow timestamping
with longer time range, wrap around markers are added to the
data stream.

For input signals that arrive close to the time of timestamp wrap around,
there is ambiguity in the ordering of the data fifo: does the wrap around
marker or the signal timestamp show up first? For example for rare
signals, one can see this:
<pre>
wrap 1
wrap 2
timestamp 0x00000003
wrap 3
wrap 4
</pre>
does the hit belong with wrap marker 2 (written to the fifo just after wrap marker 2)
or with marker 3 (written to the fifo just before wrap marker 3)?

To remove this ambiguity, additional markers are written to the data stream
half way between the wrap arounds, making it obvious that the signal
arrived right after wrap marker 3 (but was written to the FIFO before the marker):
<pre>
wrap 1 0x00
wrap 1 0x80
wrap 2 0x00
wrap 2 0x80
timestamp 0x00000003
wrap 3 0x00
wrap 3 0x80
</pre>

= test_cb.exe =

test_cb.exe is the general test program for the chronobox.

* test_cb.exe 0 # read chronobox register 0
* test_cb.exe 4 0x1234 # write to chronobox register 4
* test_cb.exe fpga 0 # read FPGA LW bridge address 0
* test_cb.exe fpga 0 0x12345678 # write 0x12345678 to FPGA LW bridge address 0
* test_cb.exe reboot # reboot the FPGA (the ARM CPU keeps running)
* test_cb.exe scalers # read all scalers in a loop
* test_cb.exe fifo # read the data fifo in a loop
* test_cb.exe tsfifo # read the timestamp fifo in a loop (do not latch scalers)
* test_cb.exe intclk # select internal timestamp clock
* test_cb.exe extclk # select external timestamp clock (10MHz)
* test_cb.exe clocks # report current status of timestamp clock

= Errata =

* 0x607f6709 - after FIFO reset (timestamp sync, etc), the first word in the FIFO is always 0x00000000, not a real timestamps.
* 20220420_ko_0x62608957 - after FIFO reset (timestamp sync), the first word in the FIFO is 0xFF000000, a timestamp overflow marker, as expected. after FPGA reboot (before timestamp sync), the first word in the FIFO is also 0xFF000000 for reasons unknown.
* linux - after power up, chronobox registers are not accessible, check that the FPGA bridges are enabled, if any bridge reports "disabled", reboot linux. do NOT cycle power.
<pre>
root@cb04:~# cat /sys/class/fpga_bridge/br*/state
enabled
enabled
enabled
enabled
root@cb04:~#
</pre>

= TODO =

* FIXED 23apr2021 - use updated "bootcmd". figure out why FPGA bridges are disabled on first power up
* figure out how to load FPGA sof from Linux, probably need new kernel
* FIXED apr2022, use fw_printenv build from source - fix fw_printenv, probably requires using newer uboot
* add mmap driver for FPGA LW bridge, probably need new kernel
* figure out how to build linux kernel from git (now using kernel from GHRD demo kit)
* enable watchdog timer to auto-reboot on hang
* figure out why ssh takes 30 second to start. read this: https://daniel-lange.com/archives/152-Openssh-taking-minutes-to-become-available,-booting-takes-half-an-hour-...-because-your-server-waits-for-a-few-bytes-of-randomness.html https://lwn.net/Articles/800509/
* FIXED 20220420_ko_0x62608957 - fix problem on startup first word in the FIFO is 0x00000000.
* FIXED 20220420_ko_0x62608957 - increase number of bits in the timestamp wraparound counter: 0xFF8mmmmm -> 23 bits is possible, keep high bit 0x00800000 as is.

= ZZZ =

Chronobox

2024-07-15T21:45:16Z

Olchansk: /* reg 33, 39 TDC and AXI FIFO status */

= Chronobox =

= Links =

* https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano
* https://bitbucket.org/expalpha/chronobox_firmware
* https://bitbucket.org/expalpha/chronobox_software
* https://edev-group.triumf.ca/hw/alphag/chrono-box/rev0
* https://bitbucket.org/expalpha/chronobox_firmware/src/master/docs/Chrono.pdf

= Chronobox connectors =

<pre>
|
| LEMO - CLK_IN - jumpers: SINE<->CLK<->NIM/TTL and NIM<->CLK<->TTL
|
| ECL P1
| 32
| |
| 1
|
| ECL P2
| 32
| |
| 1
|
| PLED - power-on LED
|
| jumper: bank A direction IN<->X<->OUT
| LEMO 0-1
| LED 0-1
| LEMO 2-3
| LED 2-3
|
| jumper: bank B direction IN<->X<->OUT
| LEMO 4-5
| LED 4-5
| LEMO 6-7
| LED 6-7
|
</pre>

= Electrical connections =

* ECL P1 and P2: LeCroy 4616 compatible
* LEMO TTL inputs: 0..5V, logic level 0: <0.8V, logic level 1: >2V
* LEMO TTL outputs: logic level 0: 0V, logic level 1: 5V to 3.3V
* clock NIM input: NIM compatible
* clock TTL input: ???
* clock sine wave input: ???

= Input channel mapping =

* 0+16 : first ECL connector
* 16+16 : second ECL connector
* 32+8 : LEMO inputs (TTL)
* 40+18 : GPIO inputs (FPGA pins)
* 58 : external clock (10 MHz nominal)
* 59 : internal clock (100 MHz)

= Functional units =

== Scalers ==

TBW

=== Firmware 0x61832695 ===

* minimum pulse width (leading edge to trailing edge): longer than 10 ns (15 ns is safe) (sampled by 100 MHz/ 10 ns clock)
* minimum time between pulses (trailing edge to next leading edge): longer than 10 ns (15 ns is safe) (ditto)

=== Firmware 0x624e22ad ===

* minimum pulse width: leading edge triggered (2 ns is safe)
* minimum time between pulses (trailing edge to next leading edge): 25 ns or more is safe

== Timestamps (TSC) ==

TBW

=== Firmware 0x61832695 ===

* minimum pulse width (leading edge to trailing edge): longer than 100 ns (105 ns is safe) (sampled by 10 MHz/100 ns clock)
* minimum time between pulses (trailing edge to next leading edge): longer than 100 ns (105 ns is safe) (ditto)

=== Firmware 0x624e22ad ===

* minimum pulse width: leading edge triggered (5 ns is safe)
* minimum time between pulses (trailing edge to next leading edge): longer than 200 ns (205 ns is safe) (sampled by 10 MHz/100 ns clock)

Each TSC input has a 256 entry FIFO. (LE is 1 entry, TE is 1 entry, so 128 hits if both LE and TE enabled).

== Output data fifo ==

TBW

=== Firmware before 0x61832695 ===

Output fifo is 4096 entries deep.

=== Firmware 0x624e22ad ===

Output fifo is 64k entries deep.

= Initial hardware setup =

* refer to DE10-NANO information here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano
* prepare hardware:
** remove chronobox from enclosure (cannot access JTAG connector when installed)
** remove DE10-Nano from chronobox baseboard
** check that SW10 jumpers are: U-D-U-U-D-U. (U=up, D=down, when "ALTERA" text on the FPGA is right side up)
** reinstall DE10-Nano on chronobox baseboard
** do NOT reinstall chronobox in enclosure
* prepare software:
** check that you have quartus 17.1 (at /opt/intelFPGA/17.1/ in this example)
** check that you installed chronobox software in /home/agdaq/online/chronobox_software
** check that you installed chronobox firmware project in /home/agdaq/online/firmware/git/chronobox_firmware
* connect serial console, for more info, go here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#Serial_console
** connect a mini-USB (*not* Micto-USB!) cable from mini-USB port on the side of the ethernet connection to a PC
** minicom -D /dev/ttyUSB0 -b 115200
* connect fpga jtag, for more info, go here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#JTAG
** connect a mini-USB (*not* Micro-USB!) cable on the side of HDMI and power connectors to a PC
** /opt/intelFPGA/17.1/quartus/bin/jtagconfig
* prepare SD flash card for booting from network: generic instructions are here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#boot_Linux_from_SD_flash
** connect new or used 8GB SD flash card to USB flash adapter to a linux computer
** login as root
** identify the flash device as /dev/sdX. Use "lsblk" or "blkid" or "dmesg". be careful to not write to the computer system disk (usually /dev/sda)
** echo -e 'o\nn\np\n1\n2048\n4095\nn\np\n2\n4096\n1681816\nn\np\n3\n\n\nt\n1\na2\nt\n2\nb\nw' | fdisk /dev/sdX
** eject /dev/sdX
** remove card, reintall card, this is to ensure we use the new partition table
** fdisk -l /dev/sdX
<pre>
root@daq01:~# fdisk -l /dev/sdg
Disk /dev/sdg: 7.38 GiB, 7910457344 bytes, 15450112 sectors
Disk model: STORAGE DEVICE
Units: sectors of 1 * 512 = 512 bytes
Sector size (logical/physical): 512 bytes / 512 bytes
I/O size (minimum/optimal): 512 bytes / 512 bytes
Disklabel type: dos
Disk identifier: 0xa033868b

Device Boot Start End Sectors Size Id Type
/dev/sdg1 2048 4095 2048 1M a2 unknown
/dev/sdg2 4096 1681816 1677721 819.2M b W95 FAT32
/dev/sdg3 1683456 15450111 13766656 6.6G 83 Linux
root@daq01:~#
</pre>
** dd if=/daq/daqstore/olchansk/daq/DE10-Nano/image-1-fpga.img of=/dev/sdX1 bs=1024k
** dd if=/daq/daqstore/olchansk/daq/DE10-Nano/image-2-uboot.img of=/dev/sdX2 bs=1024k
** eject /dev/sdX
* install prepared flash card into the chronobox DE10-Nano
* cycle power
* in the minicom window, IMMEDIATELY press the space bar to stop automatic booting (if it doesn't react, ensure flow control is disabled in minicom)
* you will have the uboot "=>" prompt
* confirm uboot version: U-Boot 2013.01.01
* setup uboot to boot linux from network, more details here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#boot_Linux_from_network
** setenv ethaddr 02:aa:bb:cc:cb:04 # for cb04, see below for explanation
** setenv bootcmd 'run bridge_enable_handoff; run netboot'
** setenv ramboot bootz \${loadaddr} - \${fdtaddr}
** setenv bootargs console=ttyS0,115200 ip=dhcp root=/dev/nfs rw nfsroot=192.168.1.1:/zssd1tb/nfsroot/%s,vers=3 panic=15
** saveenv
** reset
* DE10-Nano should boot into linux:
** uboot will restart
** DHCP will run
** tftp load of linux kernel will run
** linux kernel will start
** linux kernel will get an IP address
** linux kernel will NFS-mount the root filesystem (.../nfsroot/cb04)
** systemd will start all services
** there will be a login prompt on minicom console
** ssh will work (maybe 1 minute delay before it starts)
* try a few things:
** from agdaq or agmini account, ssh root@cb04
** "df" should show /home/agdaq is mounted (and ssh agdaq@cb04 should work)
** "/home/agdaq/online/chronobox_software/test_cb.exe 0" should fail ("bus error") because FPGA is not loaded yet
* load sof file, for more info, go here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#JTAG
** /opt/intelFPGA/17.1/quartus/bin/quartus_pgm -m JTAG -o "p;/home/agdaq/online/firmware/git/chronobox_firmware/output_files/DE10_NANO_SoC_GHRD.sof@2"
* "test_cb.exe 0" should work now
* use srunner_cb.exe to load the pof file into FPGA boot flash
* use reboot_cb.exe to reboot the FPGA from flash
* "test_cb.exe 0" should report the expected FPGA firmware version number.
* success.

== assign ethernet MAC address ==

Usually ethernet MAC address is assigned by manufacturer and is stored in a tiny little flash chip. The DE10-Nano board
is too cheap and does not have it. So a fake ethernet address has to be assigned manually from
the "locally administered range" of MAC addresses that start from "02:...", see
https://en.wikipedia.org/wiki/MAC_address#Ranges_of_group_and_locally_administered_addresses

All MAC addresses must be unique on an ethernet network, but with manual assignement confusion is easy to create.

For chronobox devices, use MAC addresses that start with "l02:aa:bb:cc:xx:yy" and have last digits "cb:01", "cb:02", "cb:03", "cb04" for the first four chronoboxes.

== new board test checklist ==

to check newly built chronobox baseboard, follow this checklist.

=== test ECL inputs ===

* stop midas frontend
* ssh agdaq@alphagdaq ### or agmini@daq16
* ssh root@cb03
* /home/agdaq/online/chronobox_software/test_cb.exe 0 ### read firmware revision, confirm communication with chronobox firmware
* /home/agdaq/online/chronobox_software/test_cb.exe inputs ### output should look like this:
<pre>
inputs: ecl_p1: 0xaa55, ecl_p2: 0xaa55, lemo: 0xe0, gpio: 0x3ffff
</pre>
* connect ECL ribbon cable from LeCroy 4616 NIM-to-ECL converter to chronobox ECL_P1 input (left one)
* ecl_p1 input should read 0x0000
* connect lemo jumper from NIM logic level 1 otput (i.e. any module OUT-bar output) to first channel of LeCroy 4616, ecl_p1 should read 0x0001
* move to 2nd channel, get 0x0002
* and so forth until last channel 0x8000.
* if any channel does not give expected reading, attach label (i.e. "ECL_P1 0x0002 bad") and send for repair.
* repeat with ECL_P2 input (right one), watch printed value of ecl_p2.

=== test TTL inputs ===

* NOTE: front panel LEMO connector labels are wrong. correct numbering of LEMO connectors is as shown in [[#Chronobox connectors]]
* disconnect all LEMO inputs
* set "bank A direction" and "bank B direction" for input
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_in_a # set bank A to input
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_in_b # set bank B to input
* all 8 LEMO LEDs should be on
* /home/agdaq/online/chronobox_software/test_cb.exe inputs ### lemo inputs should read 0xFF
* connect LEMO 0 (left bottom) to TTL output of Lecroy 222 or equivalent, set "scale" to "latch", operate push buttons to turn output on and off (LED should come in and out).
* /home/agdaq/online/chronobox_software/test_cb.exe inputs
<pre>
inputs: ecl_p1: 0xaa55, ecl_p2: 0xaa55, lemo: 0xfe (~0x01), gpio: 0x3ffff
</pre>
* change TTL signal from logic level 0 to 1 and back, observe the corresponding LED to turn on and off, observe the correct bit in the "lemo" column (watch the inverted input ~0x01) change.
* repeat with LEMO input 1 (left top) through 7 (right top).

=== test TTL outputs ===

* NOTE: front panel LEMO connector labels are wrong. correct numbering of LEMO connectors is as shown in #Chronobox connectors
* set "bank A direction" and "bank B direction" for output
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_a 0
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_b 0
* all LEMO LEDs should be off
* with voltmeter measure LEMO output voltage should be 0.135 V
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_a 0xF
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_b 0xF
* all LEMO LEDs should be on
* with voltmeter measure LEMO output voltage should be 3.4 to 3.8 V
* if you measure 1.69 V, the bank direction switch is still in the "input" position
* to test individual output, instead of 0xF use 0x1, 0x2, 0x4 and 0x8.

=== test clock input ===

* we test the TTL input mode first
* disconnect CLK_IN input
* /home/agdaq/online/chronobox_software/test_cb.exe intclk ### switch to internal timestamp clock
* /home/agdaq/online/chronobox_software/test_cb.exe clocks
<pre>
clock status: ext_clk: counter 0x00000000, freq 0.0 Hz, ts_clk: counter 0x00cccccc, freq 9999999.4 Hz, PLL status 0xa0000000
</pre>
notice: ts_clk frequency is around 10 MHz (internal oscillator) and ext_clk frequency is zero (nothing connected)
* if ts_clk is not around 10 MHz, PLL is not locked correctly, reboot the FPGA and try again: /home/agdaq/online/chronobox_software/test_cb.exe reboot
* set CLK_IN jumpers to "TTL/NIM" and "TTL" position
* connect LEMO cable from LEMO output 0 (bottom left) to CLK_IN
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_clk 0 ### output timestamp clock on LEMO output 0
* /home/agdaq/online/chronobox_software/test_cb.exe clocks
<pre>
clock status: ext_clk: counter 0x00cccccc, freq 9999999.4 Hz, ts_clk: counter 0x00cccccc, freq 9999999.4 Hz, PLL status 0x80000000
</pre>
* observe ext_clk frequency is the same as ts_clk frequency
* to test NIM input mode, we need a NIM clock signal, i.e. from a VME-NIMIO32, etc. Or use a TTL-to-NIM converter to use clock on LEMO output 0.
* set CLK_IN jumpers to "TTL/NIM" and "NIM" position
* connect VME-NIMIO32 NIM output 3 (40 MHz V1190 clock) to CLK_IN
* /home/agdaq/online/chronobox_software/test_cb.exe clocks
<pre>
clock status: ext_clk: counter 0x03333c0c, freq 40001687.4 Hz, ts_clk: counter 0x00cccccc, freq 9999999.4 Hz, PLL status 0x80000000
</pre>
* observe ext_clk frequency is 40 MHz.
* to test "sine wave" input mode, TBW, do not have a sine wave signal source.

K.O.

=== test GPIO pins ===

TBW

= Install chronobox software =

<pre>
cd /home/agdaq/online
git clone https://bitbucket.org/expalpha/chronobox_software.git
cd chronobox_software
make clean
make
ls -l *.exe
-rwxr-xr-x 1 olchansk users 18808 Aug 16 15:26 reboot_cb.exe
-rwxr-xr-x 1 olchansk users 47256 Aug 16 15:26 srunner_cb.exe
-rwxr-xr-x 1 olchansk users 20732 Aug 16 15:26 test_cb.exe
</pre>

= Install chronobox quartus firmware project =

<pre>
cd /home/agdaq/online/firmware/git
git clone https://bitbucket.org/expalpha/chronobox_firmware.git
cd chronobox_firmware
git fetch ### update repository
git tag ### list available tags
git checkout 20210420_ko ### checkout a specific version
git status
cat timestamp.v ### confirm firmware version
ls -l output_files/*.{jic,sof,rpd}
</pre>

= Firmware revisions =

* 0x5aceaed2 - April 2018 - all inputs connected to counters (except ext clock), 58 inputs, 50 MHz clock
* 0x5b6de806 - August 2018 - added fpga boot flash programmer and fpga reboot
* 0x5b7c827d - August 2018 - bshaw added debounce on GPIO inputs (for flow meters), 100 MHz clock
* 0x5b873169 - August 2018 - rebuilt, no changes
* 0x5b89e4b4 - August 2018 - added external clock signal, 59 inputs, 100 MHz clock
* 0x5b8de2b0 - September 2018 - added data fifo and timestamp counters (TSCs) for the first 4 inputs
* 0x5b906c56 - September 2018 - improved overflow markers, added scalers readout into the data fifo
* 0x5da8e4c2 - October 2019 - timestamps for all inputs, inversion of inputs
* 0x5db764a7 - October 2019 - FPGA reboot works now.
* 0x607f6709 - April 2021 - working timestamp synchronization, memory mapped registers, improved sdc file, correct clock transfers
* 0x60860e61 - April 2021 - faster data FIFO readout (from ~8 Mbytes/sec to ~80 Mbytes/sec)
* 0x61832695 - Nov 2021 - increase timestamp FIFO from 4k to 64k words
* 20220406_ko_0x624e22ad - April 2022 - make inputs edge-triggered instead of sampled.
* 20220420_ko_0x62608957 - April 2022 - fix first fifo data word is zero

= Firmware update =

* use srunner_cb.exe to load firmware RPD file into EPCQ flash memory.
* if FPGA is not running compatible firmware, srunner_cb will fail
* connect JTAG and load the firmware sof file from the quartus project (use "make load_sof")
* if JTAG is connected, one can use "make load_jic" to load firmware jic file into EPCQ flash memory.

After correct firmware is loaded, access to chronobox registers may fail (srunner_cb will not work)
because FPGA bridges are not enabled. To check, run following commands. If some bridge reports "disabled", reboot linux (do not cycle the power!).
<pre>
root@cb02:~# cat /sys/class/fpga_bridge/br*/state
enabled
enabled
enabled
enabled
root@cb02:~#
</pre>

Some DE10-Nano boards have an EPCQ64 flash memory chip, some have the EPCQ128 flash memory chip.
* identify EPCQ64 and use "-64" with all srunner commands:
<pre>
cd /home/agdaq/online/chronobox_software
./srunner_cb.exe -id -64 /dev/null # identify EPCS64 flash
...
Info: Silicon ID - 0x16
Info: Serial Configuration Device - EPCS64
</pre>
* identify EPCQ128 and use "-128" with all srunner commands:
<pre>
./srunner_cb.exe -id -128 /dev/null # identify EPCQ128 flash
...
Info: Silicon ID - 0x18
Info: Serial Configuration Device - EPCS128
</pre>

Identify -64 or -128 flash memory, write RPD file to flash memory, verify and reboot the fpga:

<pre>
cd /home/agdaq/online/chronobox_software
./srunner_cb.exe -id -64 /dev/null # identify EPCS64 flash
./srunner_cb.exe -id -128 /dev/null # identify EPCQ128 flash
#./srunner_cb.exe -read -128 test.rpd # read flash contents into a file
./srunner_cb.exe -program -128 /home/agdaq/online/firmware/git/chronobox_firmware/output_files/DE10_NANO_SoC_GHRD_auto.rpd
./srunner_cb.exe -verify -128 /home/agdaq/online/firmware/git/chronobox_firmware/output_files/DE10_NANO_SoC_GHRD_auto.rpd
./reboot_cb.exe # reboot the fpga into the new firmware
</pre>

= Firmware build =

for building firmware use: /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh

<pre>
ssh daq01
cd online
git clone git@bitbucket.org:expalpha/chronobox_firmware.git
cd chronobox_firmware
/opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
make quartus
ls -l output_files/*.{sof,jic,rpd}
-rw-r--r-- 1 olchansk users 7007185 Apr 20 16:57 output_files/DE10_NANO_SoC_GHRD_auto.rpd
-rw-r--r-- 1 olchansk users 8388833 Apr 20 16:57 output_files/DE10_NANO_SoC_GHRD.jic
-rw-r--r-- 1 olchansk users 7510701 Apr 20 16:57 output_files/DE10_NANO_SoC_GHRD.sof
</pre>

other make targets:
* make quartus - build fpga programmer files: sof, jic and rpd.
* make clean - clean the quartus project
* make qsys - regenerate the qsys block
* make jic - regenerate the jic file
* make load_sof - load sof file into fpga via jtag
* make load_jic - load jic file into fpga boot flash (epcq) via jtag
* make verify_jic - verify jic checksum in fpga boot flash (epcq)

for jtag access, use /daq/quartus/13.1.3.178/quartus/bin/jtagconfig

<pre>
daq16:chronobox_firmware$ /daq/quartus/13.1.3.178/quartus/bin/jtagconfig
1) DE-SoC [2-1.4.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) Remote server daq16: Unable to connect

daq16:chronobox_firmware$
</pre>

== Errata ==

* after regenerating qsys, manually edit ./soc_system/synthesis/submodules/hps_sdram_pll.sv to comment-out line "assign pll_dr_clk = clk_out[2];"

= Firmware details =

* DDR3 clock is 400 MHz (DDR3-800)
* memcpy speed ~1500 Mbytes/sec
* FIFO access single word read: 80, 44, 44 clocks at 10 ns/clock is 2.3 MHz at 4 bytes/word is 9 Mbytes/sec
* FIFO access memcpy: burst 2, delay 32, b4, delay 36, b5, d1, b5, d1, b5, d1, b1, delay 53, repeat. this reads 16 words in 72 clocks at 10 ns/clock is 1.388 MHz at 4*16=64 bytes/burst is 88.9 Mbytes/sec.

= Chronobox firmware registers =

<pre>
reg | rw/ro | quartus name | firmware | description
0 | ro | sof_revision_in | all | firmware revision timestamp code
0 | wo | latch_scalers_out, zero_scalers_out | all | see [[#reg_0x00_write_bits]]
1 | rw | reg1_led_out | all | DE10-Nano LED output
2 | ro | switches_in | all | read DE10-Nano switches
3 | ro | buttons_in | all | read DE10-Nano buttons
4 | rw | reg4_test | all | 32-bit read-write test register
5 | rw | flash_programmer_in, reg5_flash_programmer_out | 0x5b6de806 | 0xABCD srunner flash programmer
6 | ro | ecl_in | all | read state of ECL inputs
7 | ro | reg7_test_in | all | ???
8 | rw | scaler_addr_out, reg8_scaler_data_in | all | top 16 bits of address becomes scaler bus address, 32 bit read is the corresponding scaler data
9 | ro | lemo_in | all | read state of LEMO inputs
10/0xA | ro | gpio_in | all | read state of GPIO inputs
11/0xB | rw | regB_lemo_out | all | LEMO output data
12/0xC | rw | regC_gpio_out | all | GPIO output data
13/0xD | rw | regD_out_enable_out | all | enable output tristates: [31:24] - LEMO_OUT, [17:0] - GPIO_OUT
14/0xE | rw | regE, reconfig_out | 0x5b6de806 | FPGA reboot: write inverted firmware revision (reg0) to reboot the FPGA
15/0xF | ro | regF_input_num_in | 0x5b89e4b4 | number of chronobox inputs (to read scalers, add 1 for the clock counter)
16/0x10 | ro | reg10_fifo_status | 0x5b8de2b0 | data fifo status, see below
17/0x11 | ro | reg11_fifo_data | 0x5b8de2b0 | data fifo data, see below
18/0x12 | rw | cb_invert_a | 0x5bf7557e | invert inputs 31..0
19/0x13 | rw | cb_invert_b | 0x5bf7557e | invert inputs 63..32
20/0x14 | rw | cb_enable_le_a | 0x5bf7557e | enable TSC leading edge inputs 31..0
21/0x15 | rw | cb_enable_le_b | 0x5bf7557e | enable TSC leading edge inputs 63..32
22/0x16 | rw | cb_enable_te_a | 0x5bf7557e | enable TSC trailing edge inputs 31..0
23/0x17 | rw | cb_enable_te_b | 0x5bf7557e | enable TSC trailing edge inputs 63..32
24/0x18 | ro | fc_ext_clk_100_counter | 0x5bf7557e | external clock frequency counter 100MHz reference
25/0x19 | ro | fc_ext_clk_ext_counter | 0x5bf7557e | external clock frequency counter
26/0x1A | ro | fc_ts_clk_100_counter | 0x5bf7557e | timestamp clock frequency counter 100MHz reference
27/0x1B | ro | fc_ts_clk_ts_counter | 0x5bf7557e | timestamp clock frequency counter
28/0x1C | ro | ts_clk_pll_status | 0x5bf7557e | timestamp clock PLL status
29/0x1D | rw | cb_lemo_out_mux_ctrl | 0x5bfdc798 | 8*4 bits to control 8 LEMO output multiplexers (4 bits/16 options each mux, see [[#LEMO outputs]])
30/0x1E | rw | cb_sync_mask[31:0] | 0x607f6709 | source of chronobox sync signal, low bits
31/0x1F | rw | cb_sync_mask[63:32] | 0x607f6709 | source of chronobox sync signal, high bits
32 | rw | cb_sync_reg[31:0], cb_sync_status[31:0] | 0x607f6709 | control of timestamp sync
33 | ro | tdc_fifo_status | DLTDC | TDC fifo status
34 | ro | tdc_fifo_data_lo | DLTDC | TDC fifo low 32-bits
35 | ro | tdc_fifo_data_hi | DLTDC | TDC fifo high 32-bits and fifo rdack
36 | rw | dl_input_mask | DLTDC | DL trigger input mask
37 | rw | dl_ctrl | DLTDC | DL trigger control
38 | rw | tdc_input_mask | DLTDC | TDC input mask
39 | ro | axi_fifo_status | DLTDC | AXI fifo status
</pre>

== reg 0x00 write bits ==

<pre>
bit | fw revision | quartus signal | description
0 | all | | latch scalers
1 | all | | zero scalers
2 | ... | fifo_rdreq_out | fifo_rdreq_out (not used in version 0x607f6709 and later)
3 | ... | ts_clk_pll_extswitch_out | clear ts_clk_pll_extswitch_out
4 | ... | ts_clk_pll_extswitch_out | set ts_clk_pll_extswitch_out
</pre>

== reg 16 fifo status ==

Data fifo status bits:
<pre>
31: fifo_full - data fifo is current full
30: fifo_empty - data fifo is currently empty
29: cb_fifo_ch_full - TSC per-channel fifos have overflown at some point
28: fifo_full_latch - data fifo has overflown at some point
24+4: 0
0+24: fifo_usedw
</pre>

== reg 28 ==

Timestamp clock PLL status bits:
<pre>
31 : PLL locked
30 : PLL active clock (0=internal, 1=external
29 : external clock bad
28 : internal clock bad
27 : ts_clk_pll_extswitch
0..26 : not used
</pre>

== reg 32 timestamp sync ==

Timestamp synchronization register bits:
<pre>
31 : write 1 to arm timestamp sync circuit, scalers and TSCs are placed in reset state
30 : write 1 to disarm timestamp sync circuit, reset is released
...
16 : write 1 to send a timestamp sync signal
15 : sync circuit armed
14 : sync done
13 : sync signal received (cleared by writing bits 31 or 30)
12 : 0
11 : sync circuit armed, clk_ts section
10 : sync done, clk_ts section
9 : sync signal received, clk_ts section
8 : 0
7 : unused
...
0 : unused
</pre>

nominal sequence for synchronizing timestamps:
* make sure nothing is sending the external sync signal (i.e. run is stopped, etc)
* arm the sync circuit: cb_write32(32, 0x80000000); cb_write32(32, 0);
* check that the arming was successful: cb_read32(32), only bits 0x8800 should be set
* scalers are in reset state, not incrementing
* TSCs are in reset state, no data in the TSC FIFO
* some time later, send the external sync signal
* or send the internal sync signal: cb_write32(32, 0x10000); cb_write32(32, 0);
* check that the timestamp reset happened: cb_read32(32), bits 0x6600 should be set, bits 0x8800 should be cleared
* check that the scalers are counting, check that there is TSC data in the TSC FIFO

== reg 33, 39 TDC and AXI FIFO status ==

<pre>
bit | mask | description
31 | 0x80000000 | fifo empty
30 | 0x40000000 | fifo full
15:0 | 0x000000FF | fifo usedw (64-bit words)
</pre>

== Timestamp clock ==

Timestamp clock is 10 MHz selectable from internal oscillator or external reference on the CLK_IN input.

CLK_IN input can be selected using 2 two-position jumpers:
* NIM input: CLK<->NIM/TTL and CLK<->NIM

To select the clock from command line, use:
* test_cb.exe intclk # select internal clock
* test_cb.exe extclk # select external clock

From software:
<pre>
Chronobox* cb = ...;
cb->cb_int_clock(); # select internal clock
cb->cb_ext_clock(); # select external clock
</pre>

To see current status, run "test_cb.exe clocks":
<pre>
# ./test_cb.exe clocks
...
Chronobox firmware revision: 0x5bf7557e
...
clock status: ext_clk: counter 0x00cccf2a, freq 10000450.9 Hz, ts_clk: counter 0x00cccf2a, freq 10000450.9 Hz, PLL status 0xc0000000
</pre>

Reported is external clock frequency, currently selected timestamp clock frequency and PLL status (register 0x1C).

Normal values for the PLL status:
* internal clock: 0x80000000
* external clock: 0xC0000000
* external clock selected, but invalid: 0x60000000
* internal clock selected, external clock invalid: 0xa0000000

Disconnected/absent/broken external clock will report ext_clk frequency zero, bit 0x20000000 in the PLL status register 0x1C.

If external clock is CDM, set chronobox clock jumpers to "CLK NIM/TTL" and "NIM", use CDM 10 MHz clock output LEMO3B.

If external clock is another chronobox (usually LEMO output 0), set clock jumpers to "CLK NIM/TTL" and "TTL".

== LEMO outputs ==

LEMO connectors can be used as TTL level outputs:

* set the "bank a" and/or "bank b" jumpers for "output"
* set the lemo output multiplexor bits in register 0x1D
* set the "lemo output enable" bit in register 0x0D, use bits 24..31 for LEMO outputs 0..7.
* observe the corresponding LED is on or off according to the LEMO output TTL logic level

The function of each LEMO output is controlled by the lemo output multiplexor. Up to 16 different
signals can be routed into each output. This is controlled by register 0x1D.

Register 0x1D multiplexor control is 32 bits organized into 8 groups of 4 bits, per each of the 8 LEMO outputs: 0x76543210,
i.e. value 0x00000001 routes signal function 1 into output 0, and signal function 0 into outputs 1..7.

For each output, there are 16 possible signal functions (4 bits):

<pre>
bit | firmware signal | firmware revision | signal description
0 | cb_lemo_out_reg[n] | 0x5bfdc798 | output is controlled by register 0xB bits 0..7 for outputs 0..7
1 | clk_ts | 0x5bfdc798 | output is the 10MHz timestamp clock
2 | cb_sync_in_clk_ts | 0x607f6709 | daisy-chained timestamp sync signal (from control register or from sync input, see registers 30 and 31. see bit 0x10000 in register 32)
3..30 | gnd | 0x5bfdc798 | not used
31 | vcc | 0x5bfdc798 | logic level 1
</pre>

== front panel LEDs ==

The front panel LEDs are numbered 0..7 per [[#Chronobox_connectors]]

Each LED can be individually lit by setting a bit in register 0x1 bits 8..15.

If LEMO outputs are active, corresponding LEDs will show LEMO output status (logic level 1 -> LED is on, logic level 0 -> LED is off).

If LEMO inputs are active ...

== Synchronization of multiple chronoboxes ==

To operate several chronoboxes as one unit, they must have two common signals, a clock and a sync signal.

Each chronobox must be configured as:
* master: this will issue the sync signal
* slave: will receive the clock and sync signals from master
* slave daisy-chain: and pass them to the next slave down the chain
* (one can use the CDM or the TRG as sync masters)

For the purpose of this example (recommended configuration), set the LEMO direction jumpers:
* bank A: set to "out": master and slave daisy-chain clock and sync output
* bank B: set to "in": slave sync input

Clock connections:
* sync master can be configured with external or internal clock (CLK_IN input)
* sync slave must be configured with external clock (CLK_IN input)
<pre>
sync master LEMO #0 -> slave CLK_IN, LEMO #0 -> next slave CLK_IN, LEMO #0 -> ...
10 MHz clock from CDM & etc -> sync master CLK_IN, LEMO #0 -> slave CLK_IN, ...
</pre>

Sync connections:
* sync signal can be generated externally by the CDM or TRG
* sync signal can be generated internally by writing 0x10000 into reg 32 of sync master
* (sync must be armed on the master and all slaves before sending the first sync signal, write 0x80000000 into reg 32)
<pre>
sync master LEMO #1 -> slave LEMO #4, LEMO #1 -> next slave LEMO #4 -> ...
external sync -> master LEMO #4, LEMO #1 -> slave LEMO #4 -> ...
</pre>

Sync configuration: (see register 32 for explanation!)
* master and slave: disarm sync: write 0x40000000 to reg 32, write 0 to reg 32, bits 0x8800 and 0x6600 should clear
* master and slave daisy chain: setup clock and sync outputs:
** register 29 lemo output mux to 0xXXXX'XX21 (2=output sync signal, 1=output clock)
** register 13 lemo output enable, set bits 0x0F00'0000 (set bank A jumper for "out")
* slave and slave daisy chain: enable external sync from LEMO #4:
** register 30, write 0
** register 31, write 0x10
* master: switch to external or internal clock, as needed
* slave: switch to external clock
* master and slave: arm sync: write 0x80000000 to reg 32, write 0 to reg 32, bits 0x8800 should turn on.
* timestamps, scalers and data fifo go into the reset state, all old data is cleared
* when sync is received, timestamp is reset to zero, reset state is cleared and there should be data into FIFO. reg 32 will read 0x6600.
* if using external sync (no master), wait for reg 32 bits to become 0x6600 (sync completed)
* master: issue sync signal, write 0x10000 to reg 32, write 0 to reg 32. master reg 32 should read 0x6600, slave reg 32 should read 0x6600.

== FIFO data format ==

* 0x8ntttttt: TSC data, 24 bits "tttttt" of timestamp, 7 bits "nn" of channel number, top bit set to 1. Low bit of "t" indicates 0=leading edge, 1=trailing edge.
* 0xffTTmmmm: (before 20220420_ko_0x62608957) timestamp wrap around marker: "TT" is the top 8 bits of the timestamp, "mmmm" is a 16 bit counter
* 0xff8mmmmm: timestamp wrap around marker: bit 24 is the top bit of the timestamp (0/8), "mmmmm" is a 23 bit counter
* 0xfe00nnnn: scaler data, following "nnnn" words are the latched scalers
* 0xfd000000: start of data after chronobox sync (cbtrg only, for now)

Time range is (before 20220420_ko_0x62608957):
* 24 bits of "tttttt"
* 15 bits of "mmmm"
* computation:
<pre>
(gdb) p (100.0*1.0*0x00007FFF*1.0*0x00FFFFFF)/(1e9)/3600.0
$22 = 15.270527886249999 ### in hours
</pre>

Time range is:
* 24 bits of "tttttt"
* 22 bits of "mmmmm"
* computation:
<pre>
(gdb) p (100.0*1.0*0x003FFFFF*1.0*0x00FFFFFF)/(1e9)/3600.0
$2 = 1954.6867557262499 ### in hours
$3 = 81.445281488593736 ### in days
</pre>

== timestamp wrap around marker ==

The timestamp data is only 24 bits, to allow timestamping
with longer time range, wrap around markers are added to the
data stream.

For input signals that arrive close to the time of timestamp wrap around,
there is ambiguity in the ordering of the data fifo: does the wrap around
marker or the signal timestamp show up first? For example for rare
signals, one can see this:
<pre>
wrap 1
wrap 2
timestamp 0x00000003
wrap 3
wrap 4
</pre>
does the hit belong with wrap marker 2 (written to the fifo just after wrap marker 2)
or with marker 3 (written to the fifo just before wrap marker 3)?

To remove this ambiguity, additional markers are written to the data stream
half way between the wrap arounds, making it obvious that the signal
arrived right after wrap marker 3 (but was written to the FIFO before the marker):
<pre>
wrap 1 0x00
wrap 1 0x80
wrap 2 0x00
wrap 2 0x80
timestamp 0x00000003
wrap 3 0x00
wrap 3 0x80
</pre>

= test_cb.exe =

test_cb.exe is the general test program for the chronobox.

* test_cb.exe 0 # read chronobox register 0
* test_cb.exe 4 0x1234 # write to chronobox register 4
* test_cb.exe fpga 0 # read FPGA LW bridge address 0
* test_cb.exe fpga 0 0x12345678 # write 0x12345678 to FPGA LW bridge address 0
* test_cb.exe reboot # reboot the FPGA (the ARM CPU keeps running)
* test_cb.exe scalers # read all scalers in a loop
* test_cb.exe fifo # read the data fifo in a loop
* test_cb.exe tsfifo # read the timestamp fifo in a loop (do not latch scalers)
* test_cb.exe intclk # select internal timestamp clock
* test_cb.exe extclk # select external timestamp clock (10MHz)
* test_cb.exe clocks # report current status of timestamp clock

= Errata =

* 0x607f6709 - after FIFO reset (timestamp sync, etc), the first word in the FIFO is always 0x00000000, not a real timestamps.
* 20220420_ko_0x62608957 - after FIFO reset (timestamp sync), the first word in the FIFO is 0xFF000000, a timestamp overflow marker, as expected. after FPGA reboot (before timestamp sync), the first word in the FIFO is also 0xFF000000 for reasons unknown.
* linux - after power up, chronobox registers are not accessible, check that the FPGA bridges are enabled, if any bridge reports "disabled", reboot linux. do NOT cycle power.
<pre>
root@cb04:~# cat /sys/class/fpga_bridge/br*/state
enabled
enabled
enabled
enabled
root@cb04:~#
</pre>

= TODO =

* FIXED 23apr2021 - use updated "bootcmd". figure out why FPGA bridges are disabled on first power up
* figure out how to load FPGA sof from Linux, probably need new kernel
* FIXED apr2022, use fw_printenv build from source - fix fw_printenv, probably requires using newer uboot
* add mmap driver for FPGA LW bridge, probably need new kernel
* figure out how to build linux kernel from git (now using kernel from GHRD demo kit)
* enable watchdog timer to auto-reboot on hang
* figure out why ssh takes 30 second to start. read this: https://daniel-lange.com/archives/152-Openssh-taking-minutes-to-become-available,-booting-takes-half-an-hour-...-because-your-server-waits-for-a-few-bytes-of-randomness.html https://lwn.net/Articles/800509/
* FIXED 20220420_ko_0x62608957 - fix problem on startup first word in the FIFO is 0x00000000.
* FIXED 20220420_ko_0x62608957 - increase number of bits in the timestamp wraparound counter: 0xFF8mmmmm -> 23 bits is possible, keep high bit 0x00800000 as is.

= ZZZ =

Chronobox

2024-07-15T00:16:54Z

Olchansk: /* reg 33, 39 TDC and AXI FIFO status */

= Chronobox =

= Links =

* https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano
* https://bitbucket.org/expalpha/chronobox_firmware
* https://bitbucket.org/expalpha/chronobox_software
* https://edev-group.triumf.ca/hw/alphag/chrono-box/rev0
* https://bitbucket.org/expalpha/chronobox_firmware/src/master/docs/Chrono.pdf

= Chronobox connectors =

<pre>
|
| LEMO - CLK_IN - jumpers: SINE<->CLK<->NIM/TTL and NIM<->CLK<->TTL
|
| ECL P1
| 32
| |
| 1
|
| ECL P2
| 32
| |
| 1
|
| PLED - power-on LED
|
| jumper: bank A direction IN<->X<->OUT
| LEMO 0-1
| LED 0-1
| LEMO 2-3
| LED 2-3
|
| jumper: bank B direction IN<->X<->OUT
| LEMO 4-5
| LED 4-5
| LEMO 6-7
| LED 6-7
|
</pre>

= Electrical connections =

* ECL P1 and P2: LeCroy 4616 compatible
* LEMO TTL inputs: 0..5V, logic level 0: <0.8V, logic level 1: >2V
* LEMO TTL outputs: logic level 0: 0V, logic level 1: 5V to 3.3V
* clock NIM input: NIM compatible
* clock TTL input: ???
* clock sine wave input: ???

= Input channel mapping =

* 0+16 : first ECL connector
* 16+16 : second ECL connector
* 32+8 : LEMO inputs (TTL)
* 40+18 : GPIO inputs (FPGA pins)
* 58 : external clock (10 MHz nominal)
* 59 : internal clock (100 MHz)

= Functional units =

== Scalers ==

TBW

=== Firmware 0x61832695 ===

* minimum pulse width (leading edge to trailing edge): longer than 10 ns (15 ns is safe) (sampled by 100 MHz/ 10 ns clock)
* minimum time between pulses (trailing edge to next leading edge): longer than 10 ns (15 ns is safe) (ditto)

=== Firmware 0x624e22ad ===

* minimum pulse width: leading edge triggered (2 ns is safe)
* minimum time between pulses (trailing edge to next leading edge): 25 ns or more is safe

== Timestamps (TSC) ==

TBW

=== Firmware 0x61832695 ===

* minimum pulse width (leading edge to trailing edge): longer than 100 ns (105 ns is safe) (sampled by 10 MHz/100 ns clock)
* minimum time between pulses (trailing edge to next leading edge): longer than 100 ns (105 ns is safe) (ditto)

=== Firmware 0x624e22ad ===

* minimum pulse width: leading edge triggered (5 ns is safe)
* minimum time between pulses (trailing edge to next leading edge): longer than 200 ns (205 ns is safe) (sampled by 10 MHz/100 ns clock)

Each TSC input has a 256 entry FIFO. (LE is 1 entry, TE is 1 entry, so 128 hits if both LE and TE enabled).

== Output data fifo ==

TBW

=== Firmware before 0x61832695 ===

Output fifo is 4096 entries deep.

=== Firmware 0x624e22ad ===

Output fifo is 64k entries deep.

= Initial hardware setup =

* refer to DE10-NANO information here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano
* prepare hardware:
** remove chronobox from enclosure (cannot access JTAG connector when installed)
** remove DE10-Nano from chronobox baseboard
** check that SW10 jumpers are: U-D-U-U-D-U. (U=up, D=down, when "ALTERA" text on the FPGA is right side up)
** reinstall DE10-Nano on chronobox baseboard
** do NOT reinstall chronobox in enclosure
* prepare software:
** check that you have quartus 17.1 (at /opt/intelFPGA/17.1/ in this example)
** check that you installed chronobox software in /home/agdaq/online/chronobox_software
** check that you installed chronobox firmware project in /home/agdaq/online/firmware/git/chronobox_firmware
* connect serial console, for more info, go here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#Serial_console
** connect a mini-USB (*not* Micto-USB!) cable from mini-USB port on the side of the ethernet connection to a PC
** minicom -D /dev/ttyUSB0 -b 115200
* connect fpga jtag, for more info, go here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#JTAG
** connect a mini-USB (*not* Micro-USB!) cable on the side of HDMI and power connectors to a PC
** /opt/intelFPGA/17.1/quartus/bin/jtagconfig
* prepare SD flash card for booting from network: generic instructions are here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#boot_Linux_from_SD_flash
** connect new or used 8GB SD flash card to USB flash adapter to a linux computer
** login as root
** identify the flash device as /dev/sdX. Use "lsblk" or "blkid" or "dmesg". be careful to not write to the computer system disk (usually /dev/sda)
** echo -e 'o\nn\np\n1\n2048\n4095\nn\np\n2\n4096\n1681816\nn\np\n3\n\n\nt\n1\na2\nt\n2\nb\nw' | fdisk /dev/sdX
** eject /dev/sdX
** remove card, reintall card, this is to ensure we use the new partition table
** fdisk -l /dev/sdX
<pre>
root@daq01:~# fdisk -l /dev/sdg
Disk /dev/sdg: 7.38 GiB, 7910457344 bytes, 15450112 sectors
Disk model: STORAGE DEVICE
Units: sectors of 1 * 512 = 512 bytes
Sector size (logical/physical): 512 bytes / 512 bytes
I/O size (minimum/optimal): 512 bytes / 512 bytes
Disklabel type: dos
Disk identifier: 0xa033868b

Device Boot Start End Sectors Size Id Type
/dev/sdg1 2048 4095 2048 1M a2 unknown
/dev/sdg2 4096 1681816 1677721 819.2M b W95 FAT32
/dev/sdg3 1683456 15450111 13766656 6.6G 83 Linux
root@daq01:~#
</pre>
** dd if=/daq/daqstore/olchansk/daq/DE10-Nano/image-1-fpga.img of=/dev/sdX1 bs=1024k
** dd if=/daq/daqstore/olchansk/daq/DE10-Nano/image-2-uboot.img of=/dev/sdX2 bs=1024k
** eject /dev/sdX
* install prepared flash card into the chronobox DE10-Nano
* cycle power
* in the minicom window, IMMEDIATELY press the space bar to stop automatic booting (if it doesn't react, ensure flow control is disabled in minicom)
* you will have the uboot "=>" prompt
* confirm uboot version: U-Boot 2013.01.01
* setup uboot to boot linux from network, more details here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#boot_Linux_from_network
** setenv ethaddr 02:aa:bb:cc:cb:04 # for cb04, see below for explanation
** setenv bootcmd 'run bridge_enable_handoff; run netboot'
** setenv ramboot bootz \${loadaddr} - \${fdtaddr}
** setenv bootargs console=ttyS0,115200 ip=dhcp root=/dev/nfs rw nfsroot=192.168.1.1:/zssd1tb/nfsroot/%s,vers=3 panic=15
** saveenv
** reset
* DE10-Nano should boot into linux:
** uboot will restart
** DHCP will run
** tftp load of linux kernel will run
** linux kernel will start
** linux kernel will get an IP address
** linux kernel will NFS-mount the root filesystem (.../nfsroot/cb04)
** systemd will start all services
** there will be a login prompt on minicom console
** ssh will work (maybe 1 minute delay before it starts)
* try a few things:
** from agdaq or agmini account, ssh root@cb04
** "df" should show /home/agdaq is mounted (and ssh agdaq@cb04 should work)
** "/home/agdaq/online/chronobox_software/test_cb.exe 0" should fail ("bus error") because FPGA is not loaded yet
* load sof file, for more info, go here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#JTAG
** /opt/intelFPGA/17.1/quartus/bin/quartus_pgm -m JTAG -o "p;/home/agdaq/online/firmware/git/chronobox_firmware/output_files/DE10_NANO_SoC_GHRD.sof@2"
* "test_cb.exe 0" should work now
* use srunner_cb.exe to load the pof file into FPGA boot flash
* use reboot_cb.exe to reboot the FPGA from flash
* "test_cb.exe 0" should report the expected FPGA firmware version number.
* success.

== assign ethernet MAC address ==

Usually ethernet MAC address is assigned by manufacturer and is stored in a tiny little flash chip. The DE10-Nano board
is too cheap and does not have it. So a fake ethernet address has to be assigned manually from
the "locally administered range" of MAC addresses that start from "02:...", see
https://en.wikipedia.org/wiki/MAC_address#Ranges_of_group_and_locally_administered_addresses

All MAC addresses must be unique on an ethernet network, but with manual assignement confusion is easy to create.

For chronobox devices, use MAC addresses that start with "l02:aa:bb:cc:xx:yy" and have last digits "cb:01", "cb:02", "cb:03", "cb04" for the first four chronoboxes.

== new board test checklist ==

to check newly built chronobox baseboard, follow this checklist.

=== test ECL inputs ===

* stop midas frontend
* ssh agdaq@alphagdaq ### or agmini@daq16
* ssh root@cb03
* /home/agdaq/online/chronobox_software/test_cb.exe 0 ### read firmware revision, confirm communication with chronobox firmware
* /home/agdaq/online/chronobox_software/test_cb.exe inputs ### output should look like this:
<pre>
inputs: ecl_p1: 0xaa55, ecl_p2: 0xaa55, lemo: 0xe0, gpio: 0x3ffff
</pre>
* connect ECL ribbon cable from LeCroy 4616 NIM-to-ECL converter to chronobox ECL_P1 input (left one)
* ecl_p1 input should read 0x0000
* connect lemo jumper from NIM logic level 1 otput (i.e. any module OUT-bar output) to first channel of LeCroy 4616, ecl_p1 should read 0x0001
* move to 2nd channel, get 0x0002
* and so forth until last channel 0x8000.
* if any channel does not give expected reading, attach label (i.e. "ECL_P1 0x0002 bad") and send for repair.
* repeat with ECL_P2 input (right one), watch printed value of ecl_p2.

=== test TTL inputs ===

* NOTE: front panel LEMO connector labels are wrong. correct numbering of LEMO connectors is as shown in [[#Chronobox connectors]]
* disconnect all LEMO inputs
* set "bank A direction" and "bank B direction" for input
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_in_a # set bank A to input
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_in_b # set bank B to input
* all 8 LEMO LEDs should be on
* /home/agdaq/online/chronobox_software/test_cb.exe inputs ### lemo inputs should read 0xFF
* connect LEMO 0 (left bottom) to TTL output of Lecroy 222 or equivalent, set "scale" to "latch", operate push buttons to turn output on and off (LED should come in and out).
* /home/agdaq/online/chronobox_software/test_cb.exe inputs
<pre>
inputs: ecl_p1: 0xaa55, ecl_p2: 0xaa55, lemo: 0xfe (~0x01), gpio: 0x3ffff
</pre>
* change TTL signal from logic level 0 to 1 and back, observe the corresponding LED to turn on and off, observe the correct bit in the "lemo" column (watch the inverted input ~0x01) change.
* repeat with LEMO input 1 (left top) through 7 (right top).

=== test TTL outputs ===

* NOTE: front panel LEMO connector labels are wrong. correct numbering of LEMO connectors is as shown in #Chronobox connectors
* set "bank A direction" and "bank B direction" for output
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_a 0
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_b 0
* all LEMO LEDs should be off
* with voltmeter measure LEMO output voltage should be 0.135 V
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_a 0xF
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_b 0xF
* all LEMO LEDs should be on
* with voltmeter measure LEMO output voltage should be 3.4 to 3.8 V
* if you measure 1.69 V, the bank direction switch is still in the "input" position
* to test individual output, instead of 0xF use 0x1, 0x2, 0x4 and 0x8.

=== test clock input ===

* we test the TTL input mode first
* disconnect CLK_IN input
* /home/agdaq/online/chronobox_software/test_cb.exe intclk ### switch to internal timestamp clock
* /home/agdaq/online/chronobox_software/test_cb.exe clocks
<pre>
clock status: ext_clk: counter 0x00000000, freq 0.0 Hz, ts_clk: counter 0x00cccccc, freq 9999999.4 Hz, PLL status 0xa0000000
</pre>
notice: ts_clk frequency is around 10 MHz (internal oscillator) and ext_clk frequency is zero (nothing connected)
* if ts_clk is not around 10 MHz, PLL is not locked correctly, reboot the FPGA and try again: /home/agdaq/online/chronobox_software/test_cb.exe reboot
* set CLK_IN jumpers to "TTL/NIM" and "TTL" position
* connect LEMO cable from LEMO output 0 (bottom left) to CLK_IN
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_clk 0 ### output timestamp clock on LEMO output 0
* /home/agdaq/online/chronobox_software/test_cb.exe clocks
<pre>
clock status: ext_clk: counter 0x00cccccc, freq 9999999.4 Hz, ts_clk: counter 0x00cccccc, freq 9999999.4 Hz, PLL status 0x80000000
</pre>
* observe ext_clk frequency is the same as ts_clk frequency
* to test NIM input mode, we need a NIM clock signal, i.e. from a VME-NIMIO32, etc. Or use a TTL-to-NIM converter to use clock on LEMO output 0.
* set CLK_IN jumpers to "TTL/NIM" and "NIM" position
* connect VME-NIMIO32 NIM output 3 (40 MHz V1190 clock) to CLK_IN
* /home/agdaq/online/chronobox_software/test_cb.exe clocks
<pre>
clock status: ext_clk: counter 0x03333c0c, freq 40001687.4 Hz, ts_clk: counter 0x00cccccc, freq 9999999.4 Hz, PLL status 0x80000000
</pre>
* observe ext_clk frequency is 40 MHz.
* to test "sine wave" input mode, TBW, do not have a sine wave signal source.

K.O.

=== test GPIO pins ===

TBW

= Install chronobox software =

<pre>
cd /home/agdaq/online
git clone https://bitbucket.org/expalpha/chronobox_software.git
cd chronobox_software
make clean
make
ls -l *.exe
-rwxr-xr-x 1 olchansk users 18808 Aug 16 15:26 reboot_cb.exe
-rwxr-xr-x 1 olchansk users 47256 Aug 16 15:26 srunner_cb.exe
-rwxr-xr-x 1 olchansk users 20732 Aug 16 15:26 test_cb.exe
</pre>

= Install chronobox quartus firmware project =

<pre>
cd /home/agdaq/online/firmware/git
git clone https://bitbucket.org/expalpha/chronobox_firmware.git
cd chronobox_firmware
git fetch ### update repository
git tag ### list available tags
git checkout 20210420_ko ### checkout a specific version
git status
cat timestamp.v ### confirm firmware version
ls -l output_files/*.{jic,sof,rpd}
</pre>

= Firmware revisions =

* 0x5aceaed2 - April 2018 - all inputs connected to counters (except ext clock), 58 inputs, 50 MHz clock
* 0x5b6de806 - August 2018 - added fpga boot flash programmer and fpga reboot
* 0x5b7c827d - August 2018 - bshaw added debounce on GPIO inputs (for flow meters), 100 MHz clock
* 0x5b873169 - August 2018 - rebuilt, no changes
* 0x5b89e4b4 - August 2018 - added external clock signal, 59 inputs, 100 MHz clock
* 0x5b8de2b0 - September 2018 - added data fifo and timestamp counters (TSCs) for the first 4 inputs
* 0x5b906c56 - September 2018 - improved overflow markers, added scalers readout into the data fifo
* 0x5da8e4c2 - October 2019 - timestamps for all inputs, inversion of inputs
* 0x5db764a7 - October 2019 - FPGA reboot works now.
* 0x607f6709 - April 2021 - working timestamp synchronization, memory mapped registers, improved sdc file, correct clock transfers
* 0x60860e61 - April 2021 - faster data FIFO readout (from ~8 Mbytes/sec to ~80 Mbytes/sec)
* 0x61832695 - Nov 2021 - increase timestamp FIFO from 4k to 64k words
* 20220406_ko_0x624e22ad - April 2022 - make inputs edge-triggered instead of sampled.
* 20220420_ko_0x62608957 - April 2022 - fix first fifo data word is zero

= Firmware update =

* use srunner_cb.exe to load firmware RPD file into EPCQ flash memory.
* if FPGA is not running compatible firmware, srunner_cb will fail
* connect JTAG and load the firmware sof file from the quartus project (use "make load_sof")
* if JTAG is connected, one can use "make load_jic" to load firmware jic file into EPCQ flash memory.

After correct firmware is loaded, access to chronobox registers may fail (srunner_cb will not work)
because FPGA bridges are not enabled. To check, run following commands. If some bridge reports "disabled", reboot linux (do not cycle the power!).
<pre>
root@cb02:~# cat /sys/class/fpga_bridge/br*/state
enabled
enabled
enabled
enabled
root@cb02:~#
</pre>

Some DE10-Nano boards have an EPCQ64 flash memory chip, some have the EPCQ128 flash memory chip.
* identify EPCQ64 and use "-64" with all srunner commands:
<pre>
cd /home/agdaq/online/chronobox_software
./srunner_cb.exe -id -64 /dev/null # identify EPCS64 flash
...
Info: Silicon ID - 0x16
Info: Serial Configuration Device - EPCS64
</pre>
* identify EPCQ128 and use "-128" with all srunner commands:
<pre>
./srunner_cb.exe -id -128 /dev/null # identify EPCQ128 flash
...
Info: Silicon ID - 0x18
Info: Serial Configuration Device - EPCS128
</pre>

Identify -64 or -128 flash memory, write RPD file to flash memory, verify and reboot the fpga:

<pre>
cd /home/agdaq/online/chronobox_software
./srunner_cb.exe -id -64 /dev/null # identify EPCS64 flash
./srunner_cb.exe -id -128 /dev/null # identify EPCQ128 flash
#./srunner_cb.exe -read -128 test.rpd # read flash contents into a file
./srunner_cb.exe -program -128 /home/agdaq/online/firmware/git/chronobox_firmware/output_files/DE10_NANO_SoC_GHRD_auto.rpd
./srunner_cb.exe -verify -128 /home/agdaq/online/firmware/git/chronobox_firmware/output_files/DE10_NANO_SoC_GHRD_auto.rpd
./reboot_cb.exe # reboot the fpga into the new firmware
</pre>

= Firmware build =

for building firmware use: /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh

<pre>
ssh daq01
cd online
git clone git@bitbucket.org:expalpha/chronobox_firmware.git
cd chronobox_firmware
/opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
make quartus
ls -l output_files/*.{sof,jic,rpd}
-rw-r--r-- 1 olchansk users 7007185 Apr 20 16:57 output_files/DE10_NANO_SoC_GHRD_auto.rpd
-rw-r--r-- 1 olchansk users 8388833 Apr 20 16:57 output_files/DE10_NANO_SoC_GHRD.jic
-rw-r--r-- 1 olchansk users 7510701 Apr 20 16:57 output_files/DE10_NANO_SoC_GHRD.sof
</pre>

other make targets:
* make quartus - build fpga programmer files: sof, jic and rpd.
* make clean - clean the quartus project
* make qsys - regenerate the qsys block
* make jic - regenerate the jic file
* make load_sof - load sof file into fpga via jtag
* make load_jic - load jic file into fpga boot flash (epcq) via jtag
* make verify_jic - verify jic checksum in fpga boot flash (epcq)

for jtag access, use /daq/quartus/13.1.3.178/quartus/bin/jtagconfig

<pre>
daq16:chronobox_firmware$ /daq/quartus/13.1.3.178/quartus/bin/jtagconfig
1) DE-SoC [2-1.4.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) Remote server daq16: Unable to connect

daq16:chronobox_firmware$
</pre>

== Errata ==

* after regenerating qsys, manually edit ./soc_system/synthesis/submodules/hps_sdram_pll.sv to comment-out line "assign pll_dr_clk = clk_out[2];"

= Firmware details =

* DDR3 clock is 400 MHz (DDR3-800)
* memcpy speed ~1500 Mbytes/sec
* FIFO access single word read: 80, 44, 44 clocks at 10 ns/clock is 2.3 MHz at 4 bytes/word is 9 Mbytes/sec
* FIFO access memcpy: burst 2, delay 32, b4, delay 36, b5, d1, b5, d1, b5, d1, b1, delay 53, repeat. this reads 16 words in 72 clocks at 10 ns/clock is 1.388 MHz at 4*16=64 bytes/burst is 88.9 Mbytes/sec.

= Chronobox firmware registers =

<pre>
reg | rw/ro | quartus name | firmware | description
0 | ro | sof_revision_in | all | firmware revision timestamp code
0 | wo | latch_scalers_out, zero_scalers_out | all | see [[#reg_0x00_write_bits]]
1 | rw | reg1_led_out | all | DE10-Nano LED output
2 | ro | switches_in | all | read DE10-Nano switches
3 | ro | buttons_in | all | read DE10-Nano buttons
4 | rw | reg4_test | all | 32-bit read-write test register
5 | rw | flash_programmer_in, reg5_flash_programmer_out | 0x5b6de806 | 0xABCD srunner flash programmer
6 | ro | ecl_in | all | read state of ECL inputs
7 | ro | reg7_test_in | all | ???
8 | rw | scaler_addr_out, reg8_scaler_data_in | all | top 16 bits of address becomes scaler bus address, 32 bit read is the corresponding scaler data
9 | ro | lemo_in | all | read state of LEMO inputs
10/0xA | ro | gpio_in | all | read state of GPIO inputs
11/0xB | rw | regB_lemo_out | all | LEMO output data
12/0xC | rw | regC_gpio_out | all | GPIO output data
13/0xD | rw | regD_out_enable_out | all | enable output tristates: [31:24] - LEMO_OUT, [17:0] - GPIO_OUT
14/0xE | rw | regE, reconfig_out | 0x5b6de806 | FPGA reboot: write inverted firmware revision (reg0) to reboot the FPGA
15/0xF | ro | regF_input_num_in | 0x5b89e4b4 | number of chronobox inputs (to read scalers, add 1 for the clock counter)
16/0x10 | ro | reg10_fifo_status | 0x5b8de2b0 | data fifo status, see below
17/0x11 | ro | reg11_fifo_data | 0x5b8de2b0 | data fifo data, see below
18/0x12 | rw | cb_invert_a | 0x5bf7557e | invert inputs 31..0
19/0x13 | rw | cb_invert_b | 0x5bf7557e | invert inputs 63..32
20/0x14 | rw | cb_enable_le_a | 0x5bf7557e | enable TSC leading edge inputs 31..0
21/0x15 | rw | cb_enable_le_b | 0x5bf7557e | enable TSC leading edge inputs 63..32
22/0x16 | rw | cb_enable_te_a | 0x5bf7557e | enable TSC trailing edge inputs 31..0
23/0x17 | rw | cb_enable_te_b | 0x5bf7557e | enable TSC trailing edge inputs 63..32
24/0x18 | ro | fc_ext_clk_100_counter | 0x5bf7557e | external clock frequency counter 100MHz reference
25/0x19 | ro | fc_ext_clk_ext_counter | 0x5bf7557e | external clock frequency counter
26/0x1A | ro | fc_ts_clk_100_counter | 0x5bf7557e | timestamp clock frequency counter 100MHz reference
27/0x1B | ro | fc_ts_clk_ts_counter | 0x5bf7557e | timestamp clock frequency counter
28/0x1C | ro | ts_clk_pll_status | 0x5bf7557e | timestamp clock PLL status
29/0x1D | rw | cb_lemo_out_mux_ctrl | 0x5bfdc798 | 8*4 bits to control 8 LEMO output multiplexers (4 bits/16 options each mux, see [[#LEMO outputs]])
30/0x1E | rw | cb_sync_mask[31:0] | 0x607f6709 | source of chronobox sync signal, low bits
31/0x1F | rw | cb_sync_mask[63:32] | 0x607f6709 | source of chronobox sync signal, high bits
32 | rw | cb_sync_reg[31:0], cb_sync_status[31:0] | 0x607f6709 | control of timestamp sync
33 | ro | tdc_fifo_status | DLTDC | TDC fifo status
34 | ro | tdc_fifo_data_lo | DLTDC | TDC fifo low 32-bits
35 | ro | tdc_fifo_data_hi | DLTDC | TDC fifo high 32-bits and fifo rdack
36 | rw | dl_input_mask | DLTDC | DL trigger input mask
37 | rw | dl_ctrl | DLTDC | DL trigger control
38 | rw | tdc_input_mask | DLTDC | TDC input mask
39 | ro | axi_fifo_status | DLTDC | AXI fifo status
</pre>

== reg 0x00 write bits ==

<pre>
bit | fw revision | quartus signal | description
0 | all | | latch scalers
1 | all | | zero scalers
2 | ... | fifo_rdreq_out | fifo_rdreq_out (not used in version 0x607f6709 and later)
3 | ... | ts_clk_pll_extswitch_out | clear ts_clk_pll_extswitch_out
4 | ... | ts_clk_pll_extswitch_out | set ts_clk_pll_extswitch_out
</pre>

== reg 16 fifo status ==

Data fifo status bits:
<pre>
31: fifo_full - data fifo is current full
30: fifo_empty - data fifo is currently empty
29: cb_fifo_ch_full - TSC per-channel fifos have overflown at some point
28: fifo_full_latch - data fifo has overflown at some point
24+4: 0
0+24: fifo_usedw
</pre>

== reg 28 ==

Timestamp clock PLL status bits:
<pre>
31 : PLL locked
30 : PLL active clock (0=internal, 1=external
29 : external clock bad
28 : internal clock bad
27 : ts_clk_pll_extswitch
0..26 : not used
</pre>

== reg 32 timestamp sync ==

Timestamp synchronization register bits:
<pre>
31 : write 1 to arm timestamp sync circuit, scalers and TSCs are placed in reset state
30 : write 1 to disarm timestamp sync circuit, reset is released
...
16 : write 1 to send a timestamp sync signal
15 : sync circuit armed
14 : sync done
13 : sync signal received (cleared by writing bits 31 or 30)
12 : 0
11 : sync circuit armed, clk_ts section
10 : sync done, clk_ts section
9 : sync signal received, clk_ts section
8 : 0
7 : unused
...
0 : unused
</pre>

nominal sequence for synchronizing timestamps:
* make sure nothing is sending the external sync signal (i.e. run is stopped, etc)
* arm the sync circuit: cb_write32(32, 0x80000000); cb_write32(32, 0);
* check that the arming was successful: cb_read32(32), only bits 0x8800 should be set
* scalers are in reset state, not incrementing
* TSCs are in reset state, no data in the TSC FIFO
* some time later, send the external sync signal
* or send the internal sync signal: cb_write32(32, 0x10000); cb_write32(32, 0);
* check that the timestamp reset happened: cb_read32(32), bits 0x6600 should be set, bits 0x8800 should be cleared
* check that the scalers are counting, check that there is TSC data in the TSC FIFO

== reg 33, 39 TDC and AXI FIFO status ==

<pre>
bit | mask | quartus signal | description
31 | 0x80000000 | fifo empty
8 | 0x00000100 | fifo full
7:0 | 0x000000FF | fifo usedw (64-bit words)
</pre>

== Timestamp clock ==

Timestamp clock is 10 MHz selectable from internal oscillator or external reference on the CLK_IN input.

CLK_IN input can be selected using 2 two-position jumpers:
* NIM input: CLK<->NIM/TTL and CLK<->NIM

To select the clock from command line, use:
* test_cb.exe intclk # select internal clock
* test_cb.exe extclk # select external clock

From software:
<pre>
Chronobox* cb = ...;
cb->cb_int_clock(); # select internal clock
cb->cb_ext_clock(); # select external clock
</pre>

To see current status, run "test_cb.exe clocks":
<pre>
# ./test_cb.exe clocks
...
Chronobox firmware revision: 0x5bf7557e
...
clock status: ext_clk: counter 0x00cccf2a, freq 10000450.9 Hz, ts_clk: counter 0x00cccf2a, freq 10000450.9 Hz, PLL status 0xc0000000
</pre>

Reported is external clock frequency, currently selected timestamp clock frequency and PLL status (register 0x1C).

Normal values for the PLL status:
* internal clock: 0x80000000
* external clock: 0xC0000000
* external clock selected, but invalid: 0x60000000
* internal clock selected, external clock invalid: 0xa0000000

Disconnected/absent/broken external clock will report ext_clk frequency zero, bit 0x20000000 in the PLL status register 0x1C.

If external clock is CDM, set chronobox clock jumpers to "CLK NIM/TTL" and "NIM", use CDM 10 MHz clock output LEMO3B.

If external clock is another chronobox (usually LEMO output 0), set clock jumpers to "CLK NIM/TTL" and "TTL".

== LEMO outputs ==

LEMO connectors can be used as TTL level outputs:

* set the "bank a" and/or "bank b" jumpers for "output"
* set the lemo output multiplexor bits in register 0x1D
* set the "lemo output enable" bit in register 0x0D, use bits 24..31 for LEMO outputs 0..7.
* observe the corresponding LED is on or off according to the LEMO output TTL logic level

The function of each LEMO output is controlled by the lemo output multiplexor. Up to 16 different
signals can be routed into each output. This is controlled by register 0x1D.

Register 0x1D multiplexor control is 32 bits organized into 8 groups of 4 bits, per each of the 8 LEMO outputs: 0x76543210,
i.e. value 0x00000001 routes signal function 1 into output 0, and signal function 0 into outputs 1..7.

For each output, there are 16 possible signal functions (4 bits):

<pre>
bit | firmware signal | firmware revision | signal description
0 | cb_lemo_out_reg[n] | 0x5bfdc798 | output is controlled by register 0xB bits 0..7 for outputs 0..7
1 | clk_ts | 0x5bfdc798 | output is the 10MHz timestamp clock
2 | cb_sync_in_clk_ts | 0x607f6709 | daisy-chained timestamp sync signal (from control register or from sync input, see registers 30 and 31. see bit 0x10000 in register 32)
3..30 | gnd | 0x5bfdc798 | not used
31 | vcc | 0x5bfdc798 | logic level 1
</pre>

== front panel LEDs ==

The front panel LEDs are numbered 0..7 per [[#Chronobox_connectors]]

Each LED can be individually lit by setting a bit in register 0x1 bits 8..15.

If LEMO outputs are active, corresponding LEDs will show LEMO output status (logic level 1 -> LED is on, logic level 0 -> LED is off).

If LEMO inputs are active ...

== Synchronization of multiple chronoboxes ==

To operate several chronoboxes as one unit, they must have two common signals, a clock and a sync signal.

Each chronobox must be configured as:
* master: this will issue the sync signal
* slave: will receive the clock and sync signals from master
* slave daisy-chain: and pass them to the next slave down the chain
* (one can use the CDM or the TRG as sync masters)

For the purpose of this example (recommended configuration), set the LEMO direction jumpers:
* bank A: set to "out": master and slave daisy-chain clock and sync output
* bank B: set to "in": slave sync input

Clock connections:
* sync master can be configured with external or internal clock (CLK_IN input)
* sync slave must be configured with external clock (CLK_IN input)
<pre>
sync master LEMO #0 -> slave CLK_IN, LEMO #0 -> next slave CLK_IN, LEMO #0 -> ...
10 MHz clock from CDM & etc -> sync master CLK_IN, LEMO #0 -> slave CLK_IN, ...
</pre>

Sync connections:
* sync signal can be generated externally by the CDM or TRG
* sync signal can be generated internally by writing 0x10000 into reg 32 of sync master
* (sync must be armed on the master and all slaves before sending the first sync signal, write 0x80000000 into reg 32)
<pre>
sync master LEMO #1 -> slave LEMO #4, LEMO #1 -> next slave LEMO #4 -> ...
external sync -> master LEMO #4, LEMO #1 -> slave LEMO #4 -> ...
</pre>

Sync configuration: (see register 32 for explanation!)
* master and slave: disarm sync: write 0x40000000 to reg 32, write 0 to reg 32, bits 0x8800 and 0x6600 should clear
* master and slave daisy chain: setup clock and sync outputs:
** register 29 lemo output mux to 0xXXXX'XX21 (2=output sync signal, 1=output clock)
** register 13 lemo output enable, set bits 0x0F00'0000 (set bank A jumper for "out")
* slave and slave daisy chain: enable external sync from LEMO #4:
** register 30, write 0
** register 31, write 0x10
* master: switch to external or internal clock, as needed
* slave: switch to external clock
* master and slave: arm sync: write 0x80000000 to reg 32, write 0 to reg 32, bits 0x8800 should turn on.
* timestamps, scalers and data fifo go into the reset state, all old data is cleared
* when sync is received, timestamp is reset to zero, reset state is cleared and there should be data into FIFO. reg 32 will read 0x6600.
* if using external sync (no master), wait for reg 32 bits to become 0x6600 (sync completed)
* master: issue sync signal, write 0x10000 to reg 32, write 0 to reg 32. master reg 32 should read 0x6600, slave reg 32 should read 0x6600.

== FIFO data format ==

* 0x8ntttttt: TSC data, 24 bits "tttttt" of timestamp, 7 bits "nn" of channel number, top bit set to 1. Low bit of "t" indicates 0=leading edge, 1=trailing edge.
* 0xffTTmmmm: (before 20220420_ko_0x62608957) timestamp wrap around marker: "TT" is the top 8 bits of the timestamp, "mmmm" is a 16 bit counter
* 0xff8mmmmm: timestamp wrap around marker: bit 24 is the top bit of the timestamp (0/8), "mmmmm" is a 23 bit counter
* 0xfe00nnnn: scaler data, following "nnnn" words are the latched scalers
* 0xfd000000: start of data after chronobox sync (cbtrg only, for now)

Time range is (before 20220420_ko_0x62608957):
* 24 bits of "tttttt"
* 15 bits of "mmmm"
* computation:
<pre>
(gdb) p (100.0*1.0*0x00007FFF*1.0*0x00FFFFFF)/(1e9)/3600.0
$22 = 15.270527886249999 ### in hours
</pre>

Time range is:
* 24 bits of "tttttt"
* 22 bits of "mmmmm"
* computation:
<pre>
(gdb) p (100.0*1.0*0x003FFFFF*1.0*0x00FFFFFF)/(1e9)/3600.0
$2 = 1954.6867557262499 ### in hours
$3 = 81.445281488593736 ### in days
</pre>

== timestamp wrap around marker ==

The timestamp data is only 24 bits, to allow timestamping
with longer time range, wrap around markers are added to the
data stream.

For input signals that arrive close to the time of timestamp wrap around,
there is ambiguity in the ordering of the data fifo: does the wrap around
marker or the signal timestamp show up first? For example for rare
signals, one can see this:
<pre>
wrap 1
wrap 2
timestamp 0x00000003
wrap 3
wrap 4
</pre>
does the hit belong with wrap marker 2 (written to the fifo just after wrap marker 2)
or with marker 3 (written to the fifo just before wrap marker 3)?

To remove this ambiguity, additional markers are written to the data stream
half way between the wrap arounds, making it obvious that the signal
arrived right after wrap marker 3 (but was written to the FIFO before the marker):
<pre>
wrap 1 0x00
wrap 1 0x80
wrap 2 0x00
wrap 2 0x80
timestamp 0x00000003
wrap 3 0x00
wrap 3 0x80
</pre>

= test_cb.exe =

test_cb.exe is the general test program for the chronobox.

* test_cb.exe 0 # read chronobox register 0
* test_cb.exe 4 0x1234 # write to chronobox register 4
* test_cb.exe fpga 0 # read FPGA LW bridge address 0
* test_cb.exe fpga 0 0x12345678 # write 0x12345678 to FPGA LW bridge address 0
* test_cb.exe reboot # reboot the FPGA (the ARM CPU keeps running)
* test_cb.exe scalers # read all scalers in a loop
* test_cb.exe fifo # read the data fifo in a loop
* test_cb.exe tsfifo # read the timestamp fifo in a loop (do not latch scalers)
* test_cb.exe intclk # select internal timestamp clock
* test_cb.exe extclk # select external timestamp clock (10MHz)
* test_cb.exe clocks # report current status of timestamp clock

= Errata =

* 0x607f6709 - after FIFO reset (timestamp sync, etc), the first word in the FIFO is always 0x00000000, not a real timestamps.
* 20220420_ko_0x62608957 - after FIFO reset (timestamp sync), the first word in the FIFO is 0xFF000000, a timestamp overflow marker, as expected. after FPGA reboot (before timestamp sync), the first word in the FIFO is also 0xFF000000 for reasons unknown.
* linux - after power up, chronobox registers are not accessible, check that the FPGA bridges are enabled, if any bridge reports "disabled", reboot linux. do NOT cycle power.
<pre>
root@cb04:~# cat /sys/class/fpga_bridge/br*/state
enabled
enabled
enabled
enabled
root@cb04:~#
</pre>

= TODO =

* FIXED 23apr2021 - use updated "bootcmd". figure out why FPGA bridges are disabled on first power up
* figure out how to load FPGA sof from Linux, probably need new kernel
* FIXED apr2022, use fw_printenv build from source - fix fw_printenv, probably requires using newer uboot
* add mmap driver for FPGA LW bridge, probably need new kernel
* figure out how to build linux kernel from git (now using kernel from GHRD demo kit)
* enable watchdog timer to auto-reboot on hang
* figure out why ssh takes 30 second to start. read this: https://daniel-lange.com/archives/152-Openssh-taking-minutes-to-become-available,-booting-takes-half-an-hour-...-because-your-server-waits-for-a-few-bytes-of-randomness.html https://lwn.net/Articles/800509/
* FIXED 20220420_ko_0x62608957 - fix problem on startup first word in the FIFO is 0x00000000.
* FIXED 20220420_ko_0x62608957 - increase number of bits in the timestamp wraparound counter: 0xFF8mmmmm -> 23 bits is possible, keep high bit 0x00800000 as is.

= ZZZ =

Chronobox

2024-07-15T00:16:31Z

Olchansk: /* Chronobox firmware registers */

= Chronobox =

= Links =

* https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano
* https://bitbucket.org/expalpha/chronobox_firmware
* https://bitbucket.org/expalpha/chronobox_software
* https://edev-group.triumf.ca/hw/alphag/chrono-box/rev0
* https://bitbucket.org/expalpha/chronobox_firmware/src/master/docs/Chrono.pdf

= Chronobox connectors =

<pre>
|
| LEMO - CLK_IN - jumpers: SINE<->CLK<->NIM/TTL and NIM<->CLK<->TTL
|
| ECL P1
| 32
| |
| 1
|
| ECL P2
| 32
| |
| 1
|
| PLED - power-on LED
|
| jumper: bank A direction IN<->X<->OUT
| LEMO 0-1
| LED 0-1
| LEMO 2-3
| LED 2-3
|
| jumper: bank B direction IN<->X<->OUT
| LEMO 4-5
| LED 4-5
| LEMO 6-7
| LED 6-7
|
</pre>

= Electrical connections =

* ECL P1 and P2: LeCroy 4616 compatible
* LEMO TTL inputs: 0..5V, logic level 0: <0.8V, logic level 1: >2V
* LEMO TTL outputs: logic level 0: 0V, logic level 1: 5V to 3.3V
* clock NIM input: NIM compatible
* clock TTL input: ???
* clock sine wave input: ???

= Input channel mapping =

* 0+16 : first ECL connector
* 16+16 : second ECL connector
* 32+8 : LEMO inputs (TTL)
* 40+18 : GPIO inputs (FPGA pins)
* 58 : external clock (10 MHz nominal)
* 59 : internal clock (100 MHz)

= Functional units =

== Scalers ==

TBW

=== Firmware 0x61832695 ===

* minimum pulse width (leading edge to trailing edge): longer than 10 ns (15 ns is safe) (sampled by 100 MHz/ 10 ns clock)
* minimum time between pulses (trailing edge to next leading edge): longer than 10 ns (15 ns is safe) (ditto)

=== Firmware 0x624e22ad ===

* minimum pulse width: leading edge triggered (2 ns is safe)
* minimum time between pulses (trailing edge to next leading edge): 25 ns or more is safe

== Timestamps (TSC) ==

TBW

=== Firmware 0x61832695 ===

* minimum pulse width (leading edge to trailing edge): longer than 100 ns (105 ns is safe) (sampled by 10 MHz/100 ns clock)
* minimum time between pulses (trailing edge to next leading edge): longer than 100 ns (105 ns is safe) (ditto)

=== Firmware 0x624e22ad ===

* minimum pulse width: leading edge triggered (5 ns is safe)
* minimum time between pulses (trailing edge to next leading edge): longer than 200 ns (205 ns is safe) (sampled by 10 MHz/100 ns clock)

Each TSC input has a 256 entry FIFO. (LE is 1 entry, TE is 1 entry, so 128 hits if both LE and TE enabled).

== Output data fifo ==

TBW

=== Firmware before 0x61832695 ===

Output fifo is 4096 entries deep.

=== Firmware 0x624e22ad ===

Output fifo is 64k entries deep.

= Initial hardware setup =

* refer to DE10-NANO information here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano
* prepare hardware:
** remove chronobox from enclosure (cannot access JTAG connector when installed)
** remove DE10-Nano from chronobox baseboard
** check that SW10 jumpers are: U-D-U-U-D-U. (U=up, D=down, when "ALTERA" text on the FPGA is right side up)
** reinstall DE10-Nano on chronobox baseboard
** do NOT reinstall chronobox in enclosure
* prepare software:
** check that you have quartus 17.1 (at /opt/intelFPGA/17.1/ in this example)
** check that you installed chronobox software in /home/agdaq/online/chronobox_software
** check that you installed chronobox firmware project in /home/agdaq/online/firmware/git/chronobox_firmware
* connect serial console, for more info, go here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#Serial_console
** connect a mini-USB (*not* Micto-USB!) cable from mini-USB port on the side of the ethernet connection to a PC
** minicom -D /dev/ttyUSB0 -b 115200
* connect fpga jtag, for more info, go here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#JTAG
** connect a mini-USB (*not* Micro-USB!) cable on the side of HDMI and power connectors to a PC
** /opt/intelFPGA/17.1/quartus/bin/jtagconfig
* prepare SD flash card for booting from network: generic instructions are here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#boot_Linux_from_SD_flash
** connect new or used 8GB SD flash card to USB flash adapter to a linux computer
** login as root
** identify the flash device as /dev/sdX. Use "lsblk" or "blkid" or "dmesg". be careful to not write to the computer system disk (usually /dev/sda)
** echo -e 'o\nn\np\n1\n2048\n4095\nn\np\n2\n4096\n1681816\nn\np\n3\n\n\nt\n1\na2\nt\n2\nb\nw' | fdisk /dev/sdX
** eject /dev/sdX
** remove card, reintall card, this is to ensure we use the new partition table
** fdisk -l /dev/sdX
<pre>
root@daq01:~# fdisk -l /dev/sdg
Disk /dev/sdg: 7.38 GiB, 7910457344 bytes, 15450112 sectors
Disk model: STORAGE DEVICE
Units: sectors of 1 * 512 = 512 bytes
Sector size (logical/physical): 512 bytes / 512 bytes
I/O size (minimum/optimal): 512 bytes / 512 bytes
Disklabel type: dos
Disk identifier: 0xa033868b

Device Boot Start End Sectors Size Id Type
/dev/sdg1 2048 4095 2048 1M a2 unknown
/dev/sdg2 4096 1681816 1677721 819.2M b W95 FAT32
/dev/sdg3 1683456 15450111 13766656 6.6G 83 Linux
root@daq01:~#
</pre>
** dd if=/daq/daqstore/olchansk/daq/DE10-Nano/image-1-fpga.img of=/dev/sdX1 bs=1024k
** dd if=/daq/daqstore/olchansk/daq/DE10-Nano/image-2-uboot.img of=/dev/sdX2 bs=1024k
** eject /dev/sdX
* install prepared flash card into the chronobox DE10-Nano
* cycle power
* in the minicom window, IMMEDIATELY press the space bar to stop automatic booting (if it doesn't react, ensure flow control is disabled in minicom)
* you will have the uboot "=>" prompt
* confirm uboot version: U-Boot 2013.01.01
* setup uboot to boot linux from network, more details here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#boot_Linux_from_network
** setenv ethaddr 02:aa:bb:cc:cb:04 # for cb04, see below for explanation
** setenv bootcmd 'run bridge_enable_handoff; run netboot'
** setenv ramboot bootz \${loadaddr} - \${fdtaddr}
** setenv bootargs console=ttyS0,115200 ip=dhcp root=/dev/nfs rw nfsroot=192.168.1.1:/zssd1tb/nfsroot/%s,vers=3 panic=15
** saveenv
** reset
* DE10-Nano should boot into linux:
** uboot will restart
** DHCP will run
** tftp load of linux kernel will run
** linux kernel will start
** linux kernel will get an IP address
** linux kernel will NFS-mount the root filesystem (.../nfsroot/cb04)
** systemd will start all services
** there will be a login prompt on minicom console
** ssh will work (maybe 1 minute delay before it starts)
* try a few things:
** from agdaq or agmini account, ssh root@cb04
** "df" should show /home/agdaq is mounted (and ssh agdaq@cb04 should work)
** "/home/agdaq/online/chronobox_software/test_cb.exe 0" should fail ("bus error") because FPGA is not loaded yet
* load sof file, for more info, go here: https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#JTAG
** /opt/intelFPGA/17.1/quartus/bin/quartus_pgm -m JTAG -o "p;/home/agdaq/online/firmware/git/chronobox_firmware/output_files/DE10_NANO_SoC_GHRD.sof@2"
* "test_cb.exe 0" should work now
* use srunner_cb.exe to load the pof file into FPGA boot flash
* use reboot_cb.exe to reboot the FPGA from flash
* "test_cb.exe 0" should report the expected FPGA firmware version number.
* success.

== assign ethernet MAC address ==

Usually ethernet MAC address is assigned by manufacturer and is stored in a tiny little flash chip. The DE10-Nano board
is too cheap and does not have it. So a fake ethernet address has to be assigned manually from
the "locally administered range" of MAC addresses that start from "02:...", see
https://en.wikipedia.org/wiki/MAC_address#Ranges_of_group_and_locally_administered_addresses

All MAC addresses must be unique on an ethernet network, but with manual assignement confusion is easy to create.

For chronobox devices, use MAC addresses that start with "l02:aa:bb:cc:xx:yy" and have last digits "cb:01", "cb:02", "cb:03", "cb04" for the first four chronoboxes.

== new board test checklist ==

to check newly built chronobox baseboard, follow this checklist.

=== test ECL inputs ===

* stop midas frontend
* ssh agdaq@alphagdaq ### or agmini@daq16
* ssh root@cb03
* /home/agdaq/online/chronobox_software/test_cb.exe 0 ### read firmware revision, confirm communication with chronobox firmware
* /home/agdaq/online/chronobox_software/test_cb.exe inputs ### output should look like this:
<pre>
inputs: ecl_p1: 0xaa55, ecl_p2: 0xaa55, lemo: 0xe0, gpio: 0x3ffff
</pre>
* connect ECL ribbon cable from LeCroy 4616 NIM-to-ECL converter to chronobox ECL_P1 input (left one)
* ecl_p1 input should read 0x0000
* connect lemo jumper from NIM logic level 1 otput (i.e. any module OUT-bar output) to first channel of LeCroy 4616, ecl_p1 should read 0x0001
* move to 2nd channel, get 0x0002
* and so forth until last channel 0x8000.
* if any channel does not give expected reading, attach label (i.e. "ECL_P1 0x0002 bad") and send for repair.
* repeat with ECL_P2 input (right one), watch printed value of ecl_p2.

=== test TTL inputs ===

* NOTE: front panel LEMO connector labels are wrong. correct numbering of LEMO connectors is as shown in [[#Chronobox connectors]]
* disconnect all LEMO inputs
* set "bank A direction" and "bank B direction" for input
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_in_a # set bank A to input
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_in_b # set bank B to input
* all 8 LEMO LEDs should be on
* /home/agdaq/online/chronobox_software/test_cb.exe inputs ### lemo inputs should read 0xFF
* connect LEMO 0 (left bottom) to TTL output of Lecroy 222 or equivalent, set "scale" to "latch", operate push buttons to turn output on and off (LED should come in and out).
* /home/agdaq/online/chronobox_software/test_cb.exe inputs
<pre>
inputs: ecl_p1: 0xaa55, ecl_p2: 0xaa55, lemo: 0xfe (~0x01), gpio: 0x3ffff
</pre>
* change TTL signal from logic level 0 to 1 and back, observe the corresponding LED to turn on and off, observe the correct bit in the "lemo" column (watch the inverted input ~0x01) change.
* repeat with LEMO input 1 (left top) through 7 (right top).

=== test TTL outputs ===

* NOTE: front panel LEMO connector labels are wrong. correct numbering of LEMO connectors is as shown in #Chronobox connectors
* set "bank A direction" and "bank B direction" for output
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_a 0
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_b 0
* all LEMO LEDs should be off
* with voltmeter measure LEMO output voltage should be 0.135 V
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_a 0xF
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_b 0xF
* all LEMO LEDs should be on
* with voltmeter measure LEMO output voltage should be 3.4 to 3.8 V
* if you measure 1.69 V, the bank direction switch is still in the "input" position
* to test individual output, instead of 0xF use 0x1, 0x2, 0x4 and 0x8.

=== test clock input ===

* we test the TTL input mode first
* disconnect CLK_IN input
* /home/agdaq/online/chronobox_software/test_cb.exe intclk ### switch to internal timestamp clock
* /home/agdaq/online/chronobox_software/test_cb.exe clocks
<pre>
clock status: ext_clk: counter 0x00000000, freq 0.0 Hz, ts_clk: counter 0x00cccccc, freq 9999999.4 Hz, PLL status 0xa0000000
</pre>
notice: ts_clk frequency is around 10 MHz (internal oscillator) and ext_clk frequency is zero (nothing connected)
* if ts_clk is not around 10 MHz, PLL is not locked correctly, reboot the FPGA and try again: /home/agdaq/online/chronobox_software/test_cb.exe reboot
* set CLK_IN jumpers to "TTL/NIM" and "TTL" position
* connect LEMO cable from LEMO output 0 (bottom left) to CLK_IN
* /home/agdaq/online/chronobox_software/test_cb.exe lemo_out_clk 0 ### output timestamp clock on LEMO output 0
* /home/agdaq/online/chronobox_software/test_cb.exe clocks
<pre>
clock status: ext_clk: counter 0x00cccccc, freq 9999999.4 Hz, ts_clk: counter 0x00cccccc, freq 9999999.4 Hz, PLL status 0x80000000
</pre>
* observe ext_clk frequency is the same as ts_clk frequency
* to test NIM input mode, we need a NIM clock signal, i.e. from a VME-NIMIO32, etc. Or use a TTL-to-NIM converter to use clock on LEMO output 0.
* set CLK_IN jumpers to "TTL/NIM" and "NIM" position
* connect VME-NIMIO32 NIM output 3 (40 MHz V1190 clock) to CLK_IN
* /home/agdaq/online/chronobox_software/test_cb.exe clocks
<pre>
clock status: ext_clk: counter 0x03333c0c, freq 40001687.4 Hz, ts_clk: counter 0x00cccccc, freq 9999999.4 Hz, PLL status 0x80000000
</pre>
* observe ext_clk frequency is 40 MHz.
* to test "sine wave" input mode, TBW, do not have a sine wave signal source.

K.O.

=== test GPIO pins ===

TBW

= Install chronobox software =

<pre>
cd /home/agdaq/online
git clone https://bitbucket.org/expalpha/chronobox_software.git
cd chronobox_software
make clean
make
ls -l *.exe
-rwxr-xr-x 1 olchansk users 18808 Aug 16 15:26 reboot_cb.exe
-rwxr-xr-x 1 olchansk users 47256 Aug 16 15:26 srunner_cb.exe
-rwxr-xr-x 1 olchansk users 20732 Aug 16 15:26 test_cb.exe
</pre>

= Install chronobox quartus firmware project =

<pre>
cd /home/agdaq/online/firmware/git
git clone https://bitbucket.org/expalpha/chronobox_firmware.git
cd chronobox_firmware
git fetch ### update repository
git tag ### list available tags
git checkout 20210420_ko ### checkout a specific version
git status
cat timestamp.v ### confirm firmware version
ls -l output_files/*.{jic,sof,rpd}
</pre>

= Firmware revisions =

* 0x5aceaed2 - April 2018 - all inputs connected to counters (except ext clock), 58 inputs, 50 MHz clock
* 0x5b6de806 - August 2018 - added fpga boot flash programmer and fpga reboot
* 0x5b7c827d - August 2018 - bshaw added debounce on GPIO inputs (for flow meters), 100 MHz clock
* 0x5b873169 - August 2018 - rebuilt, no changes
* 0x5b89e4b4 - August 2018 - added external clock signal, 59 inputs, 100 MHz clock
* 0x5b8de2b0 - September 2018 - added data fifo and timestamp counters (TSCs) for the first 4 inputs
* 0x5b906c56 - September 2018 - improved overflow markers, added scalers readout into the data fifo
* 0x5da8e4c2 - October 2019 - timestamps for all inputs, inversion of inputs
* 0x5db764a7 - October 2019 - FPGA reboot works now.
* 0x607f6709 - April 2021 - working timestamp synchronization, memory mapped registers, improved sdc file, correct clock transfers
* 0x60860e61 - April 2021 - faster data FIFO readout (from ~8 Mbytes/sec to ~80 Mbytes/sec)
* 0x61832695 - Nov 2021 - increase timestamp FIFO from 4k to 64k words
* 20220406_ko_0x624e22ad - April 2022 - make inputs edge-triggered instead of sampled.
* 20220420_ko_0x62608957 - April 2022 - fix first fifo data word is zero

= Firmware update =

* use srunner_cb.exe to load firmware RPD file into EPCQ flash memory.
* if FPGA is not running compatible firmware, srunner_cb will fail
* connect JTAG and load the firmware sof file from the quartus project (use "make load_sof")
* if JTAG is connected, one can use "make load_jic" to load firmware jic file into EPCQ flash memory.

After correct firmware is loaded, access to chronobox registers may fail (srunner_cb will not work)
because FPGA bridges are not enabled. To check, run following commands. If some bridge reports "disabled", reboot linux (do not cycle the power!).
<pre>
root@cb02:~# cat /sys/class/fpga_bridge/br*/state
enabled
enabled
enabled
enabled
root@cb02:~#
</pre>

Some DE10-Nano boards have an EPCQ64 flash memory chip, some have the EPCQ128 flash memory chip.
* identify EPCQ64 and use "-64" with all srunner commands:
<pre>
cd /home/agdaq/online/chronobox_software
./srunner_cb.exe -id -64 /dev/null # identify EPCS64 flash
...
Info: Silicon ID - 0x16
Info: Serial Configuration Device - EPCS64
</pre>
* identify EPCQ128 and use "-128" with all srunner commands:
<pre>
./srunner_cb.exe -id -128 /dev/null # identify EPCQ128 flash
...
Info: Silicon ID - 0x18
Info: Serial Configuration Device - EPCS128
</pre>

Identify -64 or -128 flash memory, write RPD file to flash memory, verify and reboot the fpga:

<pre>
cd /home/agdaq/online/chronobox_software
./srunner_cb.exe -id -64 /dev/null # identify EPCS64 flash
./srunner_cb.exe -id -128 /dev/null # identify EPCQ128 flash
#./srunner_cb.exe -read -128 test.rpd # read flash contents into a file
./srunner_cb.exe -program -128 /home/agdaq/online/firmware/git/chronobox_firmware/output_files/DE10_NANO_SoC_GHRD_auto.rpd
./srunner_cb.exe -verify -128 /home/agdaq/online/firmware/git/chronobox_firmware/output_files/DE10_NANO_SoC_GHRD_auto.rpd
./reboot_cb.exe # reboot the fpga into the new firmware
</pre>

= Firmware build =

for building firmware use: /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh

<pre>
ssh daq01
cd online
git clone git@bitbucket.org:expalpha/chronobox_firmware.git
cd chronobox_firmware
/opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
make quartus
ls -l output_files/*.{sof,jic,rpd}
-rw-r--r-- 1 olchansk users 7007185 Apr 20 16:57 output_files/DE10_NANO_SoC_GHRD_auto.rpd
-rw-r--r-- 1 olchansk users 8388833 Apr 20 16:57 output_files/DE10_NANO_SoC_GHRD.jic
-rw-r--r-- 1 olchansk users 7510701 Apr 20 16:57 output_files/DE10_NANO_SoC_GHRD.sof
</pre>

other make targets:
* make quartus - build fpga programmer files: sof, jic and rpd.
* make clean - clean the quartus project
* make qsys - regenerate the qsys block
* make jic - regenerate the jic file
* make load_sof - load sof file into fpga via jtag
* make load_jic - load jic file into fpga boot flash (epcq) via jtag
* make verify_jic - verify jic checksum in fpga boot flash (epcq)

for jtag access, use /daq/quartus/13.1.3.178/quartus/bin/jtagconfig

<pre>
daq16:chronobox_firmware$ /daq/quartus/13.1.3.178/quartus/bin/jtagconfig
1) DE-SoC [2-1.4.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) Remote server daq16: Unable to connect

daq16:chronobox_firmware$
</pre>

== Errata ==

* after regenerating qsys, manually edit ./soc_system/synthesis/submodules/hps_sdram_pll.sv to comment-out line "assign pll_dr_clk = clk_out[2];"

= Firmware details =

* DDR3 clock is 400 MHz (DDR3-800)
* memcpy speed ~1500 Mbytes/sec
* FIFO access single word read: 80, 44, 44 clocks at 10 ns/clock is 2.3 MHz at 4 bytes/word is 9 Mbytes/sec
* FIFO access memcpy: burst 2, delay 32, b4, delay 36, b5, d1, b5, d1, b5, d1, b1, delay 53, repeat. this reads 16 words in 72 clocks at 10 ns/clock is 1.388 MHz at 4*16=64 bytes/burst is 88.9 Mbytes/sec.

= Chronobox firmware registers =

<pre>
reg | rw/ro | quartus name | firmware | description
0 | ro | sof_revision_in | all | firmware revision timestamp code
0 | wo | latch_scalers_out, zero_scalers_out | all | see [[#reg_0x00_write_bits]]
1 | rw | reg1_led_out | all | DE10-Nano LED output
2 | ro | switches_in | all | read DE10-Nano switches
3 | ro | buttons_in | all | read DE10-Nano buttons
4 | rw | reg4_test | all | 32-bit read-write test register
5 | rw | flash_programmer_in, reg5_flash_programmer_out | 0x5b6de806 | 0xABCD srunner flash programmer
6 | ro | ecl_in | all | read state of ECL inputs
7 | ro | reg7_test_in | all | ???
8 | rw | scaler_addr_out, reg8_scaler_data_in | all | top 16 bits of address becomes scaler bus address, 32 bit read is the corresponding scaler data
9 | ro | lemo_in | all | read state of LEMO inputs
10/0xA | ro | gpio_in | all | read state of GPIO inputs
11/0xB | rw | regB_lemo_out | all | LEMO output data
12/0xC | rw | regC_gpio_out | all | GPIO output data
13/0xD | rw | regD_out_enable_out | all | enable output tristates: [31:24] - LEMO_OUT, [17:0] - GPIO_OUT
14/0xE | rw | regE, reconfig_out | 0x5b6de806 | FPGA reboot: write inverted firmware revision (reg0) to reboot the FPGA
15/0xF | ro | regF_input_num_in | 0x5b89e4b4 | number of chronobox inputs (to read scalers, add 1 for the clock counter)
16/0x10 | ro | reg10_fifo_status | 0x5b8de2b0 | data fifo status, see below
17/0x11 | ro | reg11_fifo_data | 0x5b8de2b0 | data fifo data, see below
18/0x12 | rw | cb_invert_a | 0x5bf7557e | invert inputs 31..0
19/0x13 | rw | cb_invert_b | 0x5bf7557e | invert inputs 63..32
20/0x14 | rw | cb_enable_le_a | 0x5bf7557e | enable TSC leading edge inputs 31..0
21/0x15 | rw | cb_enable_le_b | 0x5bf7557e | enable TSC leading edge inputs 63..32
22/0x16 | rw | cb_enable_te_a | 0x5bf7557e | enable TSC trailing edge inputs 31..0
23/0x17 | rw | cb_enable_te_b | 0x5bf7557e | enable TSC trailing edge inputs 63..32
24/0x18 | ro | fc_ext_clk_100_counter | 0x5bf7557e | external clock frequency counter 100MHz reference
25/0x19 | ro | fc_ext_clk_ext_counter | 0x5bf7557e | external clock frequency counter
26/0x1A | ro | fc_ts_clk_100_counter | 0x5bf7557e | timestamp clock frequency counter 100MHz reference
27/0x1B | ro | fc_ts_clk_ts_counter | 0x5bf7557e | timestamp clock frequency counter
28/0x1C | ro | ts_clk_pll_status | 0x5bf7557e | timestamp clock PLL status
29/0x1D | rw | cb_lemo_out_mux_ctrl | 0x5bfdc798 | 8*4 bits to control 8 LEMO output multiplexers (4 bits/16 options each mux, see [[#LEMO outputs]])
30/0x1E | rw | cb_sync_mask[31:0] | 0x607f6709 | source of chronobox sync signal, low bits
31/0x1F | rw | cb_sync_mask[63:32] | 0x607f6709 | source of chronobox sync signal, high bits
32 | rw | cb_sync_reg[31:0], cb_sync_status[31:0] | 0x607f6709 | control of timestamp sync
33 | ro | tdc_fifo_status | DLTDC | TDC fifo status
34 | ro | tdc_fifo_data_lo | DLTDC | TDC fifo low 32-bits
35 | ro | tdc_fifo_data_hi | DLTDC | TDC fifo high 32-bits and fifo rdack
36 | rw | dl_input_mask | DLTDC | DL trigger input mask
37 | rw | dl_ctrl | DLTDC | DL trigger control
38 | rw | tdc_input_mask | DLTDC | TDC input mask
39 | ro | axi_fifo_status | DLTDC | AXI fifo status
</pre>

== reg 0x00 write bits ==

<pre>
bit | fw revision | quartus signal | description
0 | all | | latch scalers
1 | all | | zero scalers
2 | ... | fifo_rdreq_out | fifo_rdreq_out (not used in version 0x607f6709 and later)
3 | ... | ts_clk_pll_extswitch_out | clear ts_clk_pll_extswitch_out
4 | ... | ts_clk_pll_extswitch_out | set ts_clk_pll_extswitch_out
</pre>

== reg 16 fifo status ==

Data fifo status bits:
<pre>
31: fifo_full - data fifo is current full
30: fifo_empty - data fifo is currently empty
29: cb_fifo_ch_full - TSC per-channel fifos have overflown at some point
28: fifo_full_latch - data fifo has overflown at some point
24+4: 0
0+24: fifo_usedw
</pre>

== reg 28 ==

Timestamp clock PLL status bits:
<pre>
31 : PLL locked
30 : PLL active clock (0=internal, 1=external
29 : external clock bad
28 : internal clock bad
27 : ts_clk_pll_extswitch
0..26 : not used
</pre>

== reg 32 timestamp sync ==

Timestamp synchronization register bits:
<pre>
31 : write 1 to arm timestamp sync circuit, scalers and TSCs are placed in reset state
30 : write 1 to disarm timestamp sync circuit, reset is released
...
16 : write 1 to send a timestamp sync signal
15 : sync circuit armed
14 : sync done
13 : sync signal received (cleared by writing bits 31 or 30)
12 : 0
11 : sync circuit armed, clk_ts section
10 : sync done, clk_ts section
9 : sync signal received, clk_ts section
8 : 0
7 : unused
...
0 : unused
</pre>

nominal sequence for synchronizing timestamps:
* make sure nothing is sending the external sync signal (i.e. run is stopped, etc)
* arm the sync circuit: cb_write32(32, 0x80000000); cb_write32(32, 0);
* check that the arming was successful: cb_read32(32), only bits 0x8800 should be set
* scalers are in reset state, not incrementing
* TSCs are in reset state, no data in the TSC FIFO
* some time later, send the external sync signal
* or send the internal sync signal: cb_write32(32, 0x10000); cb_write32(32, 0);
* check that the timestamp reset happened: cb_read32(32), bits 0x6600 should be set, bits 0x8800 should be cleared
* check that the scalers are counting, check that there is TSC data in the TSC FIFO

== reg 33, 39 TDC and AXI FIFO status ==

<pre>
bit | mask | quartus signal | description
31 | 0x80000000 | fifo empty
8 | 0x00000100 | fifo full
7:0 | 0x000000FF | fifo usedw (64-bit words)
</pre>

== Timestamp clock ==

Timestamp clock is 10 MHz selectable from internal oscillator or external reference on the CLK_IN input.

CLK_IN input can be selected using 2 two-position jumpers:
* NIM input: CLK<->NIM/TTL and CLK<->NIM

To select the clock from command line, use:
* test_cb.exe intclk # select internal clock
* test_cb.exe extclk # select external clock

From software:
<pre>
Chronobox* cb = ...;
cb->cb_int_clock(); # select internal clock
cb->cb_ext_clock(); # select external clock
</pre>

To see current status, run "test_cb.exe clocks":
<pre>
# ./test_cb.exe clocks
...
Chronobox firmware revision: 0x5bf7557e
...
clock status: ext_clk: counter 0x00cccf2a, freq 10000450.9 Hz, ts_clk: counter 0x00cccf2a, freq 10000450.9 Hz, PLL status 0xc0000000
</pre>

Reported is external clock frequency, currently selected timestamp clock frequency and PLL status (register 0x1C).

Normal values for the PLL status:
* internal clock: 0x80000000
* external clock: 0xC0000000
* external clock selected, but invalid: 0x60000000
* internal clock selected, external clock invalid: 0xa0000000

Disconnected/absent/broken external clock will report ext_clk frequency zero, bit 0x20000000 in the PLL status register 0x1C.

If external clock is CDM, set chronobox clock jumpers to "CLK NIM/TTL" and "NIM", use CDM 10 MHz clock output LEMO3B.

If external clock is another chronobox (usually LEMO output 0), set clock jumpers to "CLK NIM/TTL" and "TTL".

== LEMO outputs ==

LEMO connectors can be used as TTL level outputs:

* set the "bank a" and/or "bank b" jumpers for "output"
* set the lemo output multiplexor bits in register 0x1D
* set the "lemo output enable" bit in register 0x0D, use bits 24..31 for LEMO outputs 0..7.
* observe the corresponding LED is on or off according to the LEMO output TTL logic level

The function of each LEMO output is controlled by the lemo output multiplexor. Up to 16 different
signals can be routed into each output. This is controlled by register 0x1D.

Register 0x1D multiplexor control is 32 bits organized into 8 groups of 4 bits, per each of the 8 LEMO outputs: 0x76543210,
i.e. value 0x00000001 routes signal function 1 into output 0, and signal function 0 into outputs 1..7.

For each output, there are 16 possible signal functions (4 bits):

<pre>
bit | firmware signal | firmware revision | signal description
0 | cb_lemo_out_reg[n] | 0x5bfdc798 | output is controlled by register 0xB bits 0..7 for outputs 0..7
1 | clk_ts | 0x5bfdc798 | output is the 10MHz timestamp clock
2 | cb_sync_in_clk_ts | 0x607f6709 | daisy-chained timestamp sync signal (from control register or from sync input, see registers 30 and 31. see bit 0x10000 in register 32)
3..30 | gnd | 0x5bfdc798 | not used
31 | vcc | 0x5bfdc798 | logic level 1
</pre>

== front panel LEDs ==

The front panel LEDs are numbered 0..7 per [[#Chronobox_connectors]]

Each LED can be individually lit by setting a bit in register 0x1 bits 8..15.

If LEMO outputs are active, corresponding LEDs will show LEMO output status (logic level 1 -> LED is on, logic level 0 -> LED is off).

If LEMO inputs are active ...

== Synchronization of multiple chronoboxes ==

To operate several chronoboxes as one unit, they must have two common signals, a clock and a sync signal.

Each chronobox must be configured as:
* master: this will issue the sync signal
* slave: will receive the clock and sync signals from master
* slave daisy-chain: and pass them to the next slave down the chain
* (one can use the CDM or the TRG as sync masters)

For the purpose of this example (recommended configuration), set the LEMO direction jumpers:
* bank A: set to "out": master and slave daisy-chain clock and sync output
* bank B: set to "in": slave sync input

Clock connections:
* sync master can be configured with external or internal clock (CLK_IN input)
* sync slave must be configured with external clock (CLK_IN input)
<pre>
sync master LEMO #0 -> slave CLK_IN, LEMO #0 -> next slave CLK_IN, LEMO #0 -> ...
10 MHz clock from CDM & etc -> sync master CLK_IN, LEMO #0 -> slave CLK_IN, ...
</pre>

Sync connections:
* sync signal can be generated externally by the CDM or TRG
* sync signal can be generated internally by writing 0x10000 into reg 32 of sync master
* (sync must be armed on the master and all slaves before sending the first sync signal, write 0x80000000 into reg 32)
<pre>
sync master LEMO #1 -> slave LEMO #4, LEMO #1 -> next slave LEMO #4 -> ...
external sync -> master LEMO #4, LEMO #1 -> slave LEMO #4 -> ...
</pre>

Sync configuration: (see register 32 for explanation!)
* master and slave: disarm sync: write 0x40000000 to reg 32, write 0 to reg 32, bits 0x8800 and 0x6600 should clear
* master and slave daisy chain: setup clock and sync outputs:
** register 29 lemo output mux to 0xXXXX'XX21 (2=output sync signal, 1=output clock)
** register 13 lemo output enable, set bits 0x0F00'0000 (set bank A jumper for "out")
* slave and slave daisy chain: enable external sync from LEMO #4:
** register 30, write 0
** register 31, write 0x10
* master: switch to external or internal clock, as needed
* slave: switch to external clock
* master and slave: arm sync: write 0x80000000 to reg 32, write 0 to reg 32, bits 0x8800 should turn on.
* timestamps, scalers and data fifo go into the reset state, all old data is cleared
* when sync is received, timestamp is reset to zero, reset state is cleared and there should be data into FIFO. reg 32 will read 0x6600.
* if using external sync (no master), wait for reg 32 bits to become 0x6600 (sync completed)
* master: issue sync signal, write 0x10000 to reg 32, write 0 to reg 32. master reg 32 should read 0x6600, slave reg 32 should read 0x6600.

== FIFO data format ==

* 0x8ntttttt: TSC data, 24 bits "tttttt" of timestamp, 7 bits "nn" of channel number, top bit set to 1. Low bit of "t" indicates 0=leading edge, 1=trailing edge.
* 0xffTTmmmm: (before 20220420_ko_0x62608957) timestamp wrap around marker: "TT" is the top 8 bits of the timestamp, "mmmm" is a 16 bit counter
* 0xff8mmmmm: timestamp wrap around marker: bit 24 is the top bit of the timestamp (0/8), "mmmmm" is a 23 bit counter
* 0xfe00nnnn: scaler data, following "nnnn" words are the latched scalers
* 0xfd000000: start of data after chronobox sync (cbtrg only, for now)

Time range is (before 20220420_ko_0x62608957):
* 24 bits of "tttttt"
* 15 bits of "mmmm"
* computation:
<pre>
(gdb) p (100.0*1.0*0x00007FFF*1.0*0x00FFFFFF)/(1e9)/3600.0
$22 = 15.270527886249999 ### in hours
</pre>

Time range is:
* 24 bits of "tttttt"
* 22 bits of "mmmmm"
* computation:
<pre>
(gdb) p (100.0*1.0*0x003FFFFF*1.0*0x00FFFFFF)/(1e9)/3600.0
$2 = 1954.6867557262499 ### in hours
$3 = 81.445281488593736 ### in days
</pre>

== timestamp wrap around marker ==

The timestamp data is only 24 bits, to allow timestamping
with longer time range, wrap around markers are added to the
data stream.

For input signals that arrive close to the time of timestamp wrap around,
there is ambiguity in the ordering of the data fifo: does the wrap around
marker or the signal timestamp show up first? For example for rare
signals, one can see this:
<pre>
wrap 1
wrap 2
timestamp 0x00000003
wrap 3
wrap 4
</pre>
does the hit belong with wrap marker 2 (written to the fifo just after wrap marker 2)
or with marker 3 (written to the fifo just before wrap marker 3)?

To remove this ambiguity, additional markers are written to the data stream
half way between the wrap arounds, making it obvious that the signal
arrived right after wrap marker 3 (but was written to the FIFO before the marker):
<pre>
wrap 1 0x00
wrap 1 0x80
wrap 2 0x00
wrap 2 0x80
timestamp 0x00000003
wrap 3 0x00
wrap 3 0x80
</pre>

= test_cb.exe =

test_cb.exe is the general test program for the chronobox.

* test_cb.exe 0 # read chronobox register 0
* test_cb.exe 4 0x1234 # write to chronobox register 4
* test_cb.exe fpga 0 # read FPGA LW bridge address 0
* test_cb.exe fpga 0 0x12345678 # write 0x12345678 to FPGA LW bridge address 0
* test_cb.exe reboot # reboot the FPGA (the ARM CPU keeps running)
* test_cb.exe scalers # read all scalers in a loop
* test_cb.exe fifo # read the data fifo in a loop
* test_cb.exe tsfifo # read the timestamp fifo in a loop (do not latch scalers)
* test_cb.exe intclk # select internal timestamp clock
* test_cb.exe extclk # select external timestamp clock (10MHz)
* test_cb.exe clocks # report current status of timestamp clock

= Errata =

* 0x607f6709 - after FIFO reset (timestamp sync, etc), the first word in the FIFO is always 0x00000000, not a real timestamps.
* 20220420_ko_0x62608957 - after FIFO reset (timestamp sync), the first word in the FIFO is 0xFF000000, a timestamp overflow marker, as expected. after FPGA reboot (before timestamp sync), the first word in the FIFO is also 0xFF000000 for reasons unknown.
* linux - after power up, chronobox registers are not accessible, check that the FPGA bridges are enabled, if any bridge reports "disabled", reboot linux. do NOT cycle power.
<pre>
root@cb04:~# cat /sys/class/fpga_bridge/br*/state
enabled
enabled
enabled
enabled
root@cb04:~#
</pre>

= TODO =

* FIXED 23apr2021 - use updated "bootcmd". figure out why FPGA bridges are disabled on first power up
* figure out how to load FPGA sof from Linux, probably need new kernel
* FIXED apr2022, use fw_printenv build from source - fix fw_printenv, probably requires using newer uboot
* add mmap driver for FPGA LW bridge, probably need new kernel
* figure out how to build linux kernel from git (now using kernel from GHRD demo kit)
* enable watchdog timer to auto-reboot on hang
* figure out why ssh takes 30 second to start. read this: https://daniel-lange.com/archives/152-Openssh-taking-minutes-to-become-available,-booting-takes-half-an-hour-...-because-your-server-waits-for-a-few-bytes-of-randomness.html https://lwn.net/Articles/800509/
* FIXED 20220420_ko_0x62608957 - fix problem on startup first word in the FIFO is 0x00000000.
* FIXED 20220420_ko_0x62608957 - increase number of bits in the timestamp wraparound counter: 0xFF8mmmmm -> 23 bits is possible, keep high bit 0x00800000 as is.

= ZZZ =

Main Page

2024-01-31T21:50:02Z

Olchansk: /* Links */

This is the new wiki for the ALPHA-g detector and daq.

== Links ==

* agdaq at CERN: https://alphacpc05.cern.ch/agdaq/
* elog at CERN: https://alphacpc05.cern.ch/elog/Detectors/
* agmini midas status page: https://daq16.triumf.ca
* elog: https://daq.triumf.ca/elog-alphag/alphag/
* old elog at TRIUMF: https://daq.triumf.ca/elog-alphag-old/alphag/

== temporary index ==

* [[daq]] -- DAQ manual
* [[Equipment]] -- Equipment manuals

== Documentation ==

General information about the Alpha-g Radial Time Projection Chamber (rTPC)

* [[Detector Overview]] : Design note
* [[Detector Simulations]] : Simulation and track recontruction
* [[Mechanical Design]] : Mechanical design of the rTPC
* [[Detector Data Acquistion]] : Computer and Back-end considerations
* [[Detector Calibration]] : Laser calibration scheme
* [[Detector Electronics]] : Front-end and digitizers
* [[Detector Services]] : Gas, Water cooling, Power distribution
* [[Barrel Scintillator]] : Cosmic veto detector

* [[File:Top rTPC and BS Channel Numbering - RH.pdf|thumb|rTPC and BS Channel Numbering -- TOP view]]

* [[File:BV mapping.pdf|thumb|BV DAQ channels assignment]]

* [[Magnetometry]]

== Mediawiki default blurb ==

<strong>MediaWiki has been installed.</strong>

Consult the [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide] for information on using the wiki software.

== Getting started ==
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:Configuration_settings Configuration settings list]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
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PWB

2023-06-16T18:35:02Z

Olchansk: /* Hardware */

= Links =

* https://bitbucket.org/expalpha/pwb_rev1_firmware
* https://edev-group.triumf.ca/fw/exp/alphag/feam/rev1
* https://edev-group.triumf.ca/hw/alphag/feam/rev1
* https://ladd00.triumf.ca/daqinv/frontend/list/170 - PWB inventory database

= Schematics =

* [[Image:pwb_rev0.pdf]]
* [[Image:Pwb-rev1-after.pdf]]
* [[Image:AlphaG Rev1.pdf]]

= Manuals =

* [[Image:AFTER_MANUAL_V1.pdf]] AFTER SCA manual v1
* [[Image:AFTER_DataSheet1_1.pdf]] AFTER SCA manual v1.1
* [[Image:AFTER_SCA_table2.pdf]] AFTER SCA channel map

= Hardware =

== On board ==

* FPGA Cyclone 5 GX, 5CGXFC7C7F23C8N

== Power distribution and monitoring ==

External power supply is:
* +5V
* +2V

Central board:

* Ext_5V - F1 - RS1 (0.1R) - Fuse_5V
* Ext_2V - F2/F3 - RS2 (0.1R) - Idig2-
* LDO3 - Fuse_5V - DIG_3.3V - selfenable - ADM7154
* LDO5 - Fuse_5V - DIG_2.5V - selfenable - ADM7154
* LDO_CLN - Fuse5V - CLN_3.3V - selfenable -
* VREG - DIG_3.3V - -2.5V SCA BIAS - selfenable - LTC1983ES6-3#TRMPBF
* LDO7 - DIG_2.5V - DDR3_VRef - enable DDR3_1P5V, DDR3_PG, DDR3_VttEN
* LDO2 - Idig2V- - DIG_1.1V - enable DIG_3.3V - LT3071
* LDO6 - Idig2V- - DDR3_1P5V - enable DIG_3.3V - LT3083

SCA Wing:

* Ext_5V - F1 - RS1 (0.3R) - Isca- - SCA_Fuse5V
* LDO1 - SCA_Fuse5V - SCA3.3V - enable ADC_PWR_EN - ADM7154
* LDO2 - SCA3.3V - ADC1.8V - selfenable - ADM7154
* LDO3 - SCA3.3V - TRN2.5V - selfenable - LT1761
* REF - SCA3.3V - 1.45V Vicm - selfenable - LM4121

esper variables:

* board/i_sca12, i_sca34, v_sca12, v_sca34: voltage and current into LDO1, after fuse F1 (wing board)
* board/i_p2, v_p2: voltage and current on 2V bus after fuses F2/F3
* board/i_p5, v_p5: voltage and current on 5V bus after fuse F1 (central board)

== Trigger and Clock distribution ==

Clock (62.5MHz) and trigger are distributed to the PWB columns via the [https://edev-group.triumf.ca/hw/alphag/trigger-card-sata-adapter/rev1 trigger SATA adapter].

The two miniSAS cables from cdm03 port 5 and 6 are connected to a miniSAS-SATA splitter 1-to-4 (CS Electronics "iSAS SATA adapter" ADP-887P-1X). Since there are only 8 columns and the clock and trigger signals are daisy-chained across the 8 rows, this scheme is sufficient to provide the necessary inputs to all 64 PWBs.

[https://www.techcable.com/sas-mini-sas-cables/sata-cables/ SATA 6Gb/s Cable with Latching Clip. Straight Pinout 1-1 247726-L 40in]

== Optical Link ==

Main data uplink.

SFP (Small Form Pluggable) Avago Technologies AFBR-57M5APZ [[File:AVAGO SFP specs.pdf|SFP (Small Form Pluggable) Avago Technologies AFBR-57M5APZ]]

Fiber optic Tripp Lite N820 - 10 m [[File:FiberOptic TrippLite specs.pdf|Fiber optic Tripp Lite N820 - 10 m]]

== SATA Link ==

Secondary data uplink, capable also to deliver clock and trigger.

The SATA link connects PWB from adjacent columuns on the same row.

The SATA cable is a "crossed cable".

== Modifications from schematic ==

Unless the schematic has been updated, these modifications need to be made, ideally before assembly:

* no capacitors CF5, CF6, CF7, CF8 on external SPI connector (MagBoard connector)
* SCA baseline resistors R37, R38 next to each AFTER chip need to be 1.2k, so voltage divider R38/R39 should be 1.2k/2.1k

= Firmware =

== Firmware update ==

PWB firmware update is done using "esper-tool".

<pre>
esper-tool -v upload -f file.rpd http://pwbNN update factory_rpd
esper-tool -v upload -f file.rpd http://pwbNN update file_rpd
</pre>

As of PWB firmware pwb_rev1_20200706_ko:

Permission to write into the flash memory is controlled by esper variables:

* allow_write set to "false": "esper-tool upload" does a "verify": successful upload means epcq flash content is same as rpd file, error means content is not the same.
* allow_write set to "true": "esper-tool upload" updates the epcq flash from the rpd file: for each data block, read the epcq flash, compare to rpd data, if different, erase the flash block, write the flash, read the flash, if there is a mismatch (bad write), return an error.
* allow_factory_write set to "true" to enable writing to the "factory_rpd". DO NOT SET IT TO "true" UNLESS YOU MEAN TO UPDATE THE PWB BOOTLOADER. IF YOU FLASH BUM FIRMWARE or IF THERE IS A POWER OUTAGE WHILE UPDATING, THE PWB WILL BE BRICKED and has to be recovered by connecting a USB blaster.

To update firmware of multiple boards to correct version, recommended is the script "update_pwb.perl":
<pre>
cd ~/online/src
./update_pwb.perl pwb12 pwb06 pwb78
</pre>

== Factory page and user page firmware boot ==

Each PWB board has 2 firmware images: boot loader (factory page)
and data acquisition (user page). On power up, the FPGA loads and runs
the boot loader firmware from the factory page, later the control
software reboots the FPGA into the data acquisition firmware from
the user page.

Because loading defective firmware can brick https://en.wikipedia.org/wiki/Brick_(electronics)
the PWB, new firmware images are loaded into the user page, if anything is wrong,
the PWB can still boot from the factory page and one can use the firmware update
function to load a good firmware image into the user page.

The boot loader firmware in the factory page is not intended for data acquisition, it is only meant to provide three functions:
* boot enough hardware and software to communicate via the ethernet and the sata link
* firmware update (both factory page and user page)
* reboot into the user page

The boot loader firmware in the factory page is usually never updated unless absolutely
needed to fix a problem with these three functions (i.e. compatibility with sata link communications).

If factory image is corrupted or the contains defective firmware and the PWB does not boot (no dhcp, no ping, no esper),
the only way to unbrick it is by loading good firmware using a jtag flash programmer (usb-blaster). Connecting it requires
physical access to the jtag connector on the PWB board. It is impossible when the detector is fully assembled in the experiment.

The PWB has a 32 Mbyte EPCQ flash memory chip, it is divided into 2 pages 16 Mbytes of factory page and 16 Mbytes of user page.

A complete firmware image generally contains 3 pieces:
* FPGA firmware and NIOS "feam_bootloader" software RAM image (sof file)
* NIOS "feam" software RAM image (feam.elf.flash.hex) - all the C code for esper communications and PWB data acquisition
* NIOS filesystem image (feam.webpkg.hex) - esper web pages

This is the boot sequence:
* on power-up the FPGA automatically loads the sof file from address 0 of the EPCQ flash (this is the factory image sof file)
* the FPGA is "started"
* the NIOS CPU starts executing the "feam_bootloader" C code embedded in the sof file (NIOS project hdl/software/feam_bootloader)
* feam_bootloader initializes the hardware (clocks, DDR memory, etc)
* feam_bootloader write-protects the EPCQ flash memory
* feam_bootloader copies the "feam" software from EPCQ flash to the DDR memory (after checking for correct checkum)
* feam_bootloader restarts the NIOS CPU
* the NIOS CPU starts running from DDR memory, executes the "feam" software (NIOS project hdl/software/feam)
* call main() in hdl/software/feam/src/task_init.c
* call task_init() in the same file
* infinite loop waiting for IP address via DHCP
* after have IP address, call task_esper() from hdl/software/feam/src/task_esper.c
* task_esper() creates all the esper modules, esper variables, etc,
* mod_http.c starts the mongoose web server
* PWB is open for business

This is the protection against booting corrupted firmware:
* FPGA hardware loads the sof file from epcq flash and checks for correct checksum before "starting" it
* NIOS CPU is part of the sof file, protected by sof file checksum
* NIOS feam_bootloader C code is part of the sof file, protected by the sof checksum
* feam_bootloader checks for correct signatures and checksums of the DDR memory image
* "feam" C code is protected by the checksum of the DDR memory image

== NIOS terminal ==

<pre>
$ ssh agmini@daq16
$ /opt/intelFPGA/16.1/quartus/bin/jtagconfig
1) USB-Blaster [2-1.2]
02B030DD 5CGTFD7(B5|C5|D5)/5CGXBC7B6/..
$ /opt/intelFPGA/17.0/quartus/bin/nios2-terminal
nios2-terminal: connected to hardware target using JTAG UART on cable
nios2-terminal: "USB-Blaster [2-1.2]", device 1, instance 0
nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)
PWB Revision 1 Boot Loader
Ver 2.0 Build 357 - Wed Jun 6 15:05:35 PDT 2018
...
</pre>

== Flash boot loader firmware via jtag ==

<pre>
$ ssh agmini@daq16
$ /opt/intelFPGA/16.1/quartus/bin/jtagconfig
1) USB-Blaster [2-1.2]
02B030DD 5CGTFD7(B5|C5|D5)/5CGXBC7B6/..
$ cd ~/online/firmware/pwb_rev1
$ ls -l
$ /opt/intelFPGA/17.1/quartus/bin/quartus_pgmw
... auto detect
... load the jic file
... in menu tools->programmer, enable "unprotect device"
... start program/configure operation
</pre>

== Flash user page firmware via esper-tool ==

<pre>
$ ssh agmini@daq16
$ cd online/src
$ more update_pwb.perl ### check that $fw is set to the desired firmware file
$ ./update_pwb.perl pwb06 ### or give more PWB names or give "all"
</pre>

== Build firmware ==

=== quartus version to use ===

* quartus 16.1 should be used for jtag (jtagconfig and jtagd)
* quartus 17.0 should be used to build the PWB firmware (17.1 is not compatible)

=== start license server ===

<pre>
ssh agmini@daq16
/opt/intelFPGA/17.0/quartus/linux64/lmgrd -c ~agmini/online/license-daq16.dat
</pre>

=== prepare the build environment ===

<pre>
$ ssh agmini@daq16
$ /opt/intelFPGA/17.0/nios2eds/nios2_command_shell.sh
</pre>

=== get latest version of the code and build it ===

<pre>
$ cd online/firmware/git/pwb_rev1_firmware
$ git pull
$ git checkout alphag
$ git pull
$ ./scripts/compile_project.sh
... about 30-40 minutes ...
$ ls -l bin/*.sof bin/*.jic bin/*.rpd
-rw-r--r-- 1 agmini alpha 12727389 Jan 24 2018 bin/feam_rev1_auto.rpd
-rw-r--r-- 1 agmini alpha 33554661 Jan 24 2018 bin/feam_rev1.jic
-rw-r--r-- 1 agmini alpha 6974754 Jan 24 2018 bin/rev1.sof
$ ### feam.jic is loaded via jtag
$ ### feam_auto.rpd is loaded via esper
$ ### feam.sof is used to attach the quartus signal tap logic analyzer
</pre>

=== firmware build order and sequence ===

* erase previous build
* regenerate qsys
* regenerate NIOS BSP "feam_bootloader_bsp" and "feam_bsp"
* build NIOS projects "feam_bootloader" and "feam"
* build quartus sof file (with the "feam_bootloader" nios project inside)
* build jic and rpd files (with the quartus sof file and the "feam" nios project inside)
* load sof file into the FPGA using jtag (be careful about compatible "feam" nios project already in the epcq flash)
* load jic file into the epcq factory page using jtag (cycle power for them to take effect)
* load rpd file into the epcq factory or user page using esper

=== scripts for building the firmware ===

* scripts/compile_project.sh - build everything from scratch:
* scripts/compile_qsys.sh - regenerate the main qsys component
* scripts/compile_nios.sh - regenerate the BSPs, then same as compile_elf.sh
* scripts/compile_elf.sh - build the BSPs, "feam_bootloader" and "feam" NIOS projects
* scripts/update_elf.sh - regenerate the rpd and jic files to include the new "feam" NIOS build (keeps the old "feam_bootloader" in the sof file)
* scripts/update_bootloader.sh - also regenerate the sof file to include the new "feam_bootloader" build
* scripts/clean_quartus.sh - prepare quartus fpga sof file to build from scratch
* scripts/compile_quartus.sh - build the quartus fpga sof file incrementally (run clean_quartus.sh to build from scratch).
* scripts/load_jtag_sof.pl bin/rev1.sof - load sof file into the FPGA. this will boot the new fpga firmware, the new feam_bootloader (if update_bootloader.sh was run), but with the old "feam" already in epcq flash. (beware of incompatible sof, "feam_bootloader" and "feam" builds!)
* scripts/load_jtag_jic.pl bin/feam_rev1.jic - load jic file into the EPCQ flash, same as using the graphical flash programmer tool. (this will leave the FPGA running the quartus jtag flash loader firmware, not the PWB firmware. Cycle power for new jic file to take effect).

== ESPER Variables ==

* Board
** invert_ext_trig - invert trigger signal from CDM before it drives any logic (to undo incorrect signal polarity)
** reset_nios - goggle up, them down to reset NIOS subsystem

* Signalproc
** test_mode - ADC data is replaced with a test pattern, see test mode bits in sca_x_ch_ctrl.
** sca_a_ch_ctrl, sca_b_ch_ctrl, sca_c_ch_ctrl, sca_d_ch_ctrl - channel control bits:
<pre>
11..0 - threshold - channel suppression threshold
14..12 - ctrl_test_mode - test mode:
0=fixed patter 0xa5a,
1=time bin counter,
2=time bin counter with channel number,
3=sequential adc sample counter,
4={ch_crossed_out,trig_pos,trig_neg,adc[8:0]},
5={trig,adc[10:0]},
6={ch_crossed_min,adc[10:0]}
15 - ctrl_supp_mode - channel suppression mode: 0=adc<=(baseline-threshold), 1=adc<=threshold
</pre>

* Link
** link_ctrl - sata link control. The bits are:
<pre>
0 - sata_link_udp_stream_in_enable - permit data flow from sata link to OFFLOAD_SATA
1 - udp_stream_out_enable - permit sca data flow to sata link
2 - sata_to_eth_enable - permit ethernet data flow from sata link to TSE_MAC
3 - eth_to_sata_enable - permit ethernet data flow from TSE MAC to sata link
4 - enable_stop_our_tx - enable flow control: allow stop_tx
#5 - stop_our_tx - manually activate the flow control signal into link_tx
6 - enable_stop_remote_tx - enable flow control: allow send "stop_tx"
#7 - stop_remote_tx - manually activate the flow control signal into link_tx
8 - tx_test_pattern_udp - udp data is replaced by test pattern 0x11111111, 0x22222222, etc.
9 - tx_test_pattern_eth - nios-to-sata data is replaced by test pattern 0x11111111, 0x22222222, etc.
10 - udp_delay_enable - delay between udp packets, see udp_delay_value below
11 - reboot_tx - send K_REBOOT command to the sata link mate, where it has same effect as board/reset_nios.
12 - sata_to_nios_disable
13 - nios_to_sata_disable
14 -
15 -
16 -
24..31 - udp_delay_value - delay between udp packets (top 8 bits of a 20-bit counter)
</pre>

== Firmware data path ==

Main data path:
<pre>
feam_top
|
sca_sigproc
|
sca_event_control
4 * sca_control (sca_channel.sv)
4 * channel_fifo (1024 samples)
</pre>
<pre>
sca_control (sca_channel.sv)
|
state machine to control SCA read and write enables
|
sca_write_control (what does it do?!?)
sca_read_control
</pre>
<pre>
sca_read_control
|
state machine to store ADC samples into per-channel FIFOs (channel_fifo)
selector to replace ADC samples with a test pattern
79*sca_trig_one -> ch_crossed_out - channel hit detector
</pre>
<pre>
sca_event_control
|
event_fifo (hdl/mf/event_descriptor_fifo)
state machine to take ADC data from 4 per-channel FIFOs (channel_fifo) and store it into DDR memory (write addr increment is 510*8 (number of samples)*8 = 4080).
state machine to read transposed ADC data from DDR memory (read addr increment is 8+8=16 - 2 samples * 2 bytes * 4 sca = 16) and create 4 per-sca data streams
</pre>
<pre>
data stream:
4 per-sca data streams from sca_event_control -> sca_sigproc(event_dat)
|
packet_chunker (hdl/lib/packet_chunker.sv) (4*event_dat -> event_segment_dat) - multiplex 4 data streams into 1 stream of UDP-sized packets
|
packet_length_prepender (hdl/lib/packet_length_prepender.sv) (event_segment_dat -> udp_event_val_out)
|
udp_event_val -> info qsys (udp_stream_sca) and into sata link (mux channel 2).
</pre>

== Firmware build instructions from Bryerton (obsolete) ==

This is the old README.md file from the firmware git repository.

These instructions are not used to build the firmware (use scrips/compile_project.sh).

They are still useful for figuring out which buttons to push in the altera gui programs.

<pre>
# ALPHAg FrontEnd Acquisition Module (FEAM) - REV0

Welcome to the ALPHAg FEAM Project

# Table of Contents

* [Overview](#overview)
* [Inital Setup](#initial-setup)
* [Quartus Setup](#quartus-setup)
* [Create the .cdf](#create-the-cdf)
* [NIOS Setup](#nios-Setup)
* [Create the project files](#create-the-project-files)
* [Build Instructions](#build-instructions)
* [Building from Quartus GUI](#building-from-quartus-gui)
* [Generate the QSys File](#generate-the-qsys-file)
* [Compile the NIOSII Project](#compile-the-niosii-project)
* [Compile the Quartus Project](#compile-the-quartus-project)
* [Building from Scripts](#building-from-scripts)
* [Installing from JTAG](#installing-from-jtag)
* [Installing from ESPER](#installing-from-esper)

# Overview

The FEAM is a digitizer located on the ALPHAg detector. Each FEAM consists of 4 AFTER SCAs for a total of 288 channels.

# Initial Setup

## Quartus Setup

### Create the .cdf
1. Open Quartus Prime Standard Edition
2. Click on **Tools -> Programmer**. The **Programmer** window will appear
3. In the **Programmer** window, click **Auto Detect**. A **Select Device** dialog box will appear
1. (Optional) If **Auto Detect** is greyed out, click on **Hardware Setup**. The **Hardware Setup** dialog box will appear
2. Under **Hardware Settings**, double-click on the USB JTAG hardware you wish to use
3. Click **Close**. The **Hardware Setup** dialog box will close
5. Click on **File -> Save As**. The **Save As** dialog box will appear
6. In the **Save As** dialog box, browse to the **/\<project_dir\>/bin/** directory
7. Make sure the **Add file to current project** checkbox is checked
7. In the **File name** input box, type "alphag_feam.cdf" and click **Save**
8. Close the **Programmer** window
9. Done!

## NIOS Setup

### Create the project files
1. Open Quartus Prime Standard Edition
2. Open the NIOS II Software Build Tools by clicking **Tools -> NIOS II Software Build Tools for Eclipse**
3. The **Workspace Launcher** window will appear, click *OK* to accept the default workspace.
4. Click **File -> Import...**. The **Import** dialog box will appear
5. Click on **General -> Existing Projects into Workspace**
6. Click **Next \>**
7. Next to **Select root directory** click **Browse...**. A **Browse for Folder** dialog box will appear
8. Browse to **/\<project_dir\>/hdl/software** and click **OK**
8. Four Projects should appear in the **Projects** panel:
* alphag_feam
* alphag\_feam\_bsp
* alphag\_feam\_bootloader
* alphag\_feam\_bootloader\_bsp
9. Click **Select All**
10. Click **Finish**
11. Done!

# Build Instructions

## Building from Quartus GUI

**Warning: Please use Quartus Prime Standard Edition 16.1**
### Generate the QSys File
1. Open Quartus Standard Edition 16.1
1. Open QSys by clicking **Tools -> QSys**
2. Click on **File -> Open** (CTRL+O). An **Open File** dialog box should appear.
3. Select the **alphag_feam.qsys** file from the **/\<project_dir\>/hdl** directory and click **Open**
4. Modify as necessary. NOTE: Any change to the QSys, even cosmetic such as expanding or collapsing components will cause the QSys to desire a re-generate.
5. Click **File -> Save** (CTRL+S)
6. Click **Generate HDL**. A **Generation** dialog box will appear
7. Select the settings you desire to be changed, if any
8. Click **Generate**
9. Wait for the generation to complete.
10. Done!

### Compile the NIOSII Project
1. Open the NIOS II Software Build Tools by clicking **Tools -> NIOS II Software Build Tools for Eclipse**
2. (Optional) If the QSys file has been re-generated performing the following
1. Right-click on **alphag\_feam\_bsp** and select **NIOS II -> Generate BSP**. The BSP will regenerate
2. Right-click on **alphag\_feam\_bootloader\_bsp** and select **NIOS II -> Generate BSP**. The BSP will regenerate
3. Modify files as needed. WARNING: Do not modify any BSP files by hand! All changes will be lost on next generate.
4. Click **Project -> Build All** (CTRL+B). If your workspace as multiple projects, it is recommend to close all but the ones related to the FEAM.
5. Right-click on **alphag\_feam\_bootloader** and select **Make Targets -> Build...**. The **Make Targets** dialog box will appear
6. In the **Make Targets** dialog box, select **mem\_init\_generate** and click **Build**
7. Done!

### Compile the Quartus Project
1. Open Quartus Standard Edition 16.1
1. Under **Processing** click **Start Compilation** (CTRL+L)
2. Wait about 16-30 minutes.
3. Done!

**Note:** If Quartus crashed while compiling, delete the **\<project_dir\>/hdl/db** and **\<project_dir\>/hdl/incremental_db** directories and try again

## Installing from JTAG
1. Generate the .jic file using the provided /bin/alphag\_feam\_jic.cof
1. In the main Quartus window, click **File -> Convert Programming Files**, A **Convert Programming Files** window will appear
2. In the **Convert Programming Files** window, click **Open Conversion Setup Data**. An **Open** dialog box will appear
3. In the **Open** dialog box, select the **alphag_feam.cof** file located in **/bin/**
4. Click **Open**. The **Open dialog box will close
* Note the **File name** field, it should display /\<project\_dir\>/bin/alphag\_feam.jic
5. In the **Convert Programming Files** window, click **Generate**
6. When the .jic is done being generated, a small dialog box will appear, click **OK**
7. In the **Convert Programming Files** window, click **Close**
2. Load the .JIC file using the Programmer
1. In the main Quartus window in the **Project Navigator** drop-down input select **Files**.
2. Scroll down the window and find the **alphag_feam.cdf**, and double-click it. The **Programmer** window will open
3. Click on the icon labelled **5CGXFC4C6**
4. Click on the **Change File** button. The **Select New Programming File** dialog box will appear
5. Browse to **/\<project_dir\>/bin/** and select **alphag\_feam.jic**
6. Click Open. The **Select New Programming File** dialog box will close
7. In the main panel, check the **Program/Configure** box on the line that starts **./bin/alphag\_feam.jic**
8. Click the **Start** button
9. Wait for the **Progress** bar to go to 100% and stop
10. Done!
</pre>

= Internal test pulser =

Documentation from Bryerton:

<pre>
---------- Forwarded message ---------
From: Bryerton Shaw <bryerton@triumf.ca>
Date: Tue, 24 Apr 2018 at 16:18
Subject: RE: PWB/FEAM internal test pulse
To: Lars Martin <lmartin@triumf.ca>
Cc: Andrea Capra <acapra@triumf.ca>

Hi Lars (and Andrea),

In the new(er) firmware the test pulse code has been modified slightly to
fit in better with the upgraded trigger system. I can add an option to
allow it to be triggered by the external trigger (currently it has an
interval option, or you can hit the manual trigger to fire it, if it’s
enabled)

The *options for the test pulser* are under the *signalproc module*:

*test_pulse_ena*

An array of four booleans, that control turning on the test pulse for each
SCA. If this is False, the other options below will do nothings for that SCA

*test_pulse_interval_ena*

An array of four booleans, that control turning on the interval trigger for
each SCA

*test_pulse_interval*

An unsigned 32-bit value that marks how many 16ns clock cycles occur
between interval triggers. Only one value, as there is only one interval
timer.

*test_pulse_wdt*

An array of four 16-bit unsigned integers that control the width of the
pulse for each SCA when the trigger occurs.

Now, there is a second set of options to control the delay of the *test
pulse interval trigger*. These options are located under the *trigger
module*

*intp_trig_ena*

Boolean value enabling/disabling the interval test pulse trigger.

*intp_trig_delay*

Unsigned 32-bit integer controlling the trigger delay, which is the time
between when the trigger is requested, and when the trigger actually fires.

You can setup the interval trigger and use that to create event packets
with the test pulse on set intervals. If the interval trigger is
insufficient, I can create another option, which is to fire the test pulse
for enabled SCAs when the external trigger goes. If so, I’ll add this
option in the *signalproc *module for you:

*test_pulse_on_ext*

An array of four Booleans, that control if the test pulse for that SCA
fires on external trigger.

Remember, in order to use the SCA test pulse at all, you must also set the
SCA to test mode. You can do this by going into the *sca0-3 modules* and
setting *test* to *functionality *(the value is *3* if you want to set it
via esper-tool)

Btw currently the SCAs are hard-coded to have all 72 channels receive the
test pulse on firing, and the option to de-select/select which channels to
fire is not offered. Would you like this ability? And if so do you want it
to set all four SCAs the same, or have an option for all 288 channels?

The waveform viewer on the webpage was removed for technical reasons, and
so all viewing is done via the MIDAS DAQ. There are some preliminary tools
I’ve created to verify the event packets and their waveforms, but I
wouldn’t call them easy to setup or use at the moment. (Or very useful for
fine comparisons). If KO doesn’t have a way of saving the events to disk, I
could deliver something that captured and saved waveforms quite quickly.

Regards,
Bryerton

*From:* Lars Martin
*Sent:* April 23, 2018 5:10 PM
*To:* Bryerton Shaw <bryerton@triumf.ca>
*Cc:* Andrea Capra <acapra@triumf.ca>
*Subject:* PWB/FEAM internal test pulse

Hi Bryerton,

Andrea and I would like to check the response function of the PWBs. For
that Daryl suggested to first look at the internal test pulse.

Can you point us to what settings are required to make that go? And to use
the external trigger if we want to acquire the data?

Ideally we would acquire Midas data from that, but it's unclear if KO's
frontend allows for that right now. Can we access the data with Esper
instead?

Finally, we haven't had the waveform display on the web page for a while,
but Daryl said you guys use it. Are we using a different page somehow?

Hope all is well with the baby, cheers,

Lars
</pre>

= TODO =

* IMPOSSIBLE (ext clock only connected to clock cleaner) add frequency counter for the external clock (62.5 MHz)
* DONE add random delay before memtest
* DONE add 4 more bits to udp_delay
* DONE fix crash on boot if run is active and triggers arrive (check that trigger is off on boot) (do not set trigger/enable_all, ext_trig_ena, inp_trig_ena, signal_proc/force_run to 1 after boot)
* DONE (kludge jtag uart write()) increase size of jtag uart output buffer, make it unlimited if possible.
* DONE (kludge jtag uart write()) on dhcp timeout, reboot the fpga - reboot of nios does not clear the jtag uart, which becomes full and nios stops.
* DONE add NIOS watchdog timeout for fectrl
* DONE do not use external clock until instructed by fectrl (clock cleaner default is pin select mode, default pin mode is input with pull down, so clock 0 is selected, this is the ext clock. but we can drive clock select pins from the fpga).
* DONE change clock cleaner power up: use the 2 lines status_clkin0 and status_clkin1 to tell clock cleaner to use the internal clock (clkin2) - from the FPGA drive first line low, second line high. Also change all NIOS code that programs the clock cleaner to keep these two lines in the "input" mode. Current code switches them to "output" mode.
* DONE clock cleaner power up state is wrong for both choices of clock: 62.5 MHz ext clock and 125 MHz internal clock, see explanation in feam_top.sv. It looks like I need to drive status_clkin0 and status_clkin1 to "holdover" mode, both logic level 1. Currently status_clkin0 is used as SPI read line, this has to be moved to a different line first.
* add watchdog timeout that works in factory mode ("remote update" watchdog only works in user mode)
* DONE enable HTTP pipelining - copy changes on mongoose from ADC project.
* reset everything if it looks like NIOS TCP/IP code has crashed, but enough code is still running to prevent tripping of the fpga-remote-update watchdog timer. such crash tends to happens when the sata link mate is rebooted and incomplete data arrives from the disrupted ethernet data path.
* DONE when loading AFTER ASIC do not go into infinite loop if read-back is broken (always mismatch).
* DONE read and report error status information bits for 2983fc.pdf voltages, currents and temperatures monitoring chip. note that SCA12, SCA34, 2V and 5V voltages are flagged 0x0B "ADC out of range, sensor over range" correctly, see 2983fc.pdf table 63 fix explanation of "normal" and "usable" voltage ranges. (5V voltage divider is 2-to-1)
* add provisions for coded trigger
* DONE verify readout of MV2 Hall magnetometer (all registers and bits from device are visible in esper)

= ZZZ =

ZZZ

Daq

2023-06-14T19:03:13Z

Olchansk: /* Inventory database */

= Links =

* https://alphacpc05.cern.ch/agdaq/ -- midas daq page for the agdaq system at CERN
* https://daq16.triumf.ca -- midas daq page for the agmini system at TRIUMF
* https://daq.triumf.ca/elog-alphag/alphag/ -- elog
* https://daqstore.triumf.ca/AgWiki/index.php/Main_Page -- this wiki
* https://bitbucket.org/expalpha/agdaq - git repository for agdaq
* https://bitbucket.org/expalpha/agana - git repository for agana
* https://bitbucket.org/expalpha -- git repository on bitbucket
* https://edev-group.triumf.ca/fw/exp/alphag -- git repository on edev gitlab

= Inventory database =

* https://ladd00.triumf.ca/daqinv/frontend/list/170 - PWB inventory database
* https://ladd00.triumf.ca/daqinv/frontend/list/168 - ADC (GRIF-16) inventory, FMC-ADC32rev0,rev1 inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/176 - FMC-ADC32rev1.1 inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/174 - BSC RTM inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/173 - BSC ASD inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/171 - TMB inventory

= Hardware manuals =

* [[TRG]] - trigger board (GRIF-C) manual
* CDM - https://daq.triumf.ca/DaqWiki/index.php/VME-CDM -- clock VME-CDM manual
* ADC - https://daq.triumf.ca/DaqWiki/index.php/VME-GRIF-ADC16-Rev1 -- GRIF-16 ADC manual
* [[PWB]] - TPC Pad Wing Board manual
* TDC - https://daq.triumf.ca/DaqWiki/index.php/GSI_TRB3
* [[chronobox]] - chronobox manual
* [[ASD]] - BSC preamp board
* [[RTM]] - BSC VME rear transition board

= Performance =

Full system: (ADC fw rel-20201112-ko, PWB fw 20201005_ko)
* 1 Hz stable, ADC adc32 9 supp off rate 0.3 M/s, adc16 off, PWB udp_delay 25 supp off active 64 rate 6.6+4+6+4.6=21.2 M/s, TDC off, total rate 21 M/s
* 500 Hz stable, ADC adc32 9 supp 1500 rate 6 M/s, adc16 off, PWB udp_delay 10 supp 100 active 63 rate 3+4+3+3=13 M/s, TDC off, total rate 19 M/s

== Single ADC: (fw rel-20201112-ko) ==

Fully suppressed data, sthreshold 5000
* 1 Hz: stable
* 500 Hz: stable (nominal max trigger rate)
* 6700 Hz: stable, 8 Mbytes/sec
* 6800 Hz: evb eventually confused
* 6850 Hz: evb confused, no lost triggers in the ADC, no crash in the ADC

All data, 510 samples/event, sthreshold 10 (fw rel-20201122-ko)
* 1 Hz: stable
* 100 Hz: stable, 3.4 Mbytes/sec
* 500 Hz: stable, 17 Mbytes/sec (nominal max trigger rate)
* 1000 Hz: stable, 32 Mbytes/sec
* 3100 Hz: stable, 106 M/s (approaching saturation of 1gige ethernet)
* 3200 Hz: stable, 110 M/s - TRG communication is in trouble
* 3300 Hz: stable, 116 M/s
* 3400 Hz: incomplete events, no ADC crash ("dropped due to full" counting, "dropped due to busy" are zero, this is as expected).

no suppression (different fpga data path)
* 1 Hz: stable
* 100 Hz: stable
* 500 Hz: stable, 17 M/s (nominal max trigger rate)
* 1000 Hz: stable, 32 M/s
* 3000 Hz: stable, 100 M/s (approaching saturation of 1gige ethernet)
* 3300 Hz: incomplete events, no ADC crash ("dropped due to full" counting, "dropped due to busy" are zero, this is as expected).

== Single PWB, fw 20201005_ko, see https://alphacpc05.cern.ch/elog/Detectors/5563 ==

Fully suppressed data:
* up to 500 Hz, stable

All pads firing (FW pulser)
* 4 SCA: up to 272 Hz, 81.6 Mbytes/sec, at higher rate: event fifo overflow
* 2 SCA: up to 295 Hz, 44.25 Mbytes/sec, at higher rate: event fifo overflow
* 1 SCA: up to 295 Hz, 22.5 Mbytes/sec, at higher rate: event fifo overflow

Conclusion:
* max PWB date rate 80 Mbytes/sec,
* max non-suppressed PWB trigger rate: 295 Hz
* max suppressed PWB trigger rate: 500 Hz (1.6 ms sca readout time)

= Network connections =

The experiment private network number is: 192.168.1.x, gateway 192.168.1.1, netmask 255.255.255.0

network map:
<pre>
---- TRIUMF/CERN network --1gige-- alphagdaq --10gige-- juniper switch --1gige-- centrecom switch
</pre>

== alphagdaq network connections ==

on the rear of the machine:
<pre>
-----------------------------------------
| | rj45 | rj45 | | sfp | sfp |
-----------------------------------------

- left rj45 - copper 1gige - eno1 - spare (inactive)
- right rj45 - copper 1gige - eno2 - dhcp - cern/triumf network
- left sfp - 10gige - enp1s0f1 - spare (inactive)
- right sfp - 10gige - enp1s0f0 - static 192.168.1.1
</pre>

== connections between switches ==

* alphagdaq to juniper switch: direct attach (DAC) 10gige cable into any port of juniper switch
* juniper switch to centrecom switch: rj45 sfp in any port of juniper switch - cat5e/cat6 cable - to any port of centrecom switch
* cat5e/cat6 cable from any port of centrecom switch to the XXX port on the back of the juniper switch

== juniper switch ==

connected to juniper switch front is:

* everything that sends event data to alphagdaq, specifically:
** TRG (rj45 sfp)
** 16x ADC (fiber sfp)
** 64x PWB (fiber sfp)
* 10gige uplink to alphagdaq (10gige DAC cable)
* 1gige link to centrecom switch (rj45 sfp)
* 40gige ports are not used

connected to the juniper switch rear:

* CON is the serial console via RJ45-to-DB9 to USB-serial adapter to alphagdaq USB port (9600bps, 8N1, no flow control)
* C0 is the management ethernet interface port, connect to any port on the centrecom switch (juniper-private will ping)

== centrecom switch ==

* everything with copper rj45 connections, specifically:
** CDM boards
** HV, LV and VME power supplies
** RaspberryPi3 boards
** gas handling MFCs (algas)
** cooling system controller (moxa01)

= USB connections =

Note:
* alphagdaq has USB2 and USB3 connections. They are not the same, they are not generally interchangeable.
* USB3 connections and cables are generally blue coloured.

List of USB connections from alphagdaq:

* front USB3 port (blue): USB-A-to-B cable to USB blaster connected to the trigger board (front of rack)
* rear USB3 port (blue): USB3 short jumper to USB3 hub
* rear USB2 port (black): USB2 unpowered hub (Logiix) to USB-A-to-B cable to UPS USB connector
* rear USB2 port (black): USB-to-Serial adaper to DB9 to RJ45 adapter to Juniper switch console port

Note: UPS USB connection does not work with alphagdaq USB ports (both usb2 and usb3), but combination
using the unpowered USB2 hub seems to work ok.

List of USB connections from the USB hub:

* this is a powered USB3 hub
* USB-A-to-MicroUSB - to lvdb boards
* USB-A-to-Wiener interlock cable

= Clock and trigger distribution =

== Explanation ==

Trigger is generated by the trigger board (aka TRG, aka GRIF-C),
from the TRG eSATA output through the eSATA splitter it is fed into
the master CDM. The master CDM outputs the trigger on all MiniSAS output ports.
One of the master CDM MiniSAS outputs is connected to the CDM slave eSATA input.
The same as the master CDM, the slave CDM outputs the trigger on all MiniSAS output ports.

The master 62.5MHz clock is generated by the master CDM using the internal 10MHz oscillator
or the external 10MHz AD clock. Also on MiniSAS port 6 the master CDM generates
the 200MHz clock for the TDC. This clock is frequency-locked to the master 62.5MHz clock.

Master CDM clock selection (external CD 10MHz clock or internal oscillator 10MHz clock)
is done by a magic esper command (see below).

From the master CDM, the clock is fed to: the slave CDM, the TRG (via the eSATA splitter)
and to the TDC (via the RJ45 splitter).

The slave CDM sends the clock and the trigger to the ADCs and PWBs.

== Chronobox connections ==

Chronoboxes are synchronized with the daq using two signals: 10 MHz timestamp clock and TTL sync.

The sync signal used is the trigger signal - timestamps are reset by the 1st event - which is not a physics event, but the first trigger in the trigger sync sequence.

All chronoboxes are configured in "slave" and "chain" mode.

Slave mode: 10 MHz timestamp clock goes into the CLK_IN input (configured as NIM on the first chronobox and TTL on all others), sync signal goes into TTL input LEMO 4. (bank B direction set to "in").

Chain mode: 10 MHz timestamp clock is TTL output LEMO 0, sync is TTL output LEMO 1. (bank A direction set to "out"). These signals feed into CLK_IN (TTL mode) and TTL input LEMO 4 in the next chronobox in the chain.

The first chronobox receives the 10 MHz timestamp clock and sync signals from the master CDM per diagrams below.

* CDM 10 MHz clock output is NIM, feeds directly into the chronobox CLK_IN (NIM mode).
* CDM "trigger" ("sync") output is NIM, has to go through a NIM-to-TTL converter before feeding chronobox TTL input LEMO 4. I use a LeCroy 222 "gate and delay generator" module. NIM input goes into the "Start" input, TTL output is taken from the "TTL" output. Signal width is adjusted to around 100-1000 ns. Any other sutable NIM-to-TTL converter can also be used.
* "sync" output must be enabled in the master CDM:
<pre>
esper-tool cdm00
cd cdm
write multi_sync 2
</pre>

== Schematic ==

<pre>
TRG (GRIF-C)
------------
eSATA <------> eSATA splitter

eSATA splitter
--------------
trigger ---> eSATA ---> CDM-Master eSATA (trigger signal)
clock <--- (eSATA --- MiniSAS) <--- CDM MiniSAS (62.5MHz clock)
</pre>

<pre>
CDM-Master
----------
LEMO1B <----- 10 MHz AD clock (NIM)
LEMO2A --> (only if there is no external clock) 4ns lemo cable --> LEMO1B (62.5 MHz frequency monitor)
LEMO2B --> chronobox sync (NIM) --> NIM-to-TTL --> long lemo cable to chronobox sync input (TTL)
LEMO3B --> long lemo cable to chronobox clock input (NIM) (CLK_IN configured for NIM input)
eSATA <--- eSATA splitter <--- eSATA from TRG (trigger signal)
MiniSAS 1 --> (MiniSAS --- eSATA) --> CDM-Slave eSATA (62.5 MHz)
MiniSAS 6 --> (MiniSAS --- eSATA) --> eSATA splitter --> RJ45 --> TDC (200 MHz)
</pre>

<pre>
CDM-Slave
---------
LEMO2A --> 4ns lemo cable --> LEMO1B (62.5 MHz frequency monitor)
eSATA <--- trigger and 62.5MHz clock from CDM-Master
MiniSAS 1 --> ADC trigger and 62.5MHz clock
MiniSAS 2 --> same
MiniSAS 3 --> same
MiniSAS 4 --> same
MiniSAS 5 --> PWB trigger and 62.5MHz clock
MiniSAS 6 --> same
</pre>

[[File:VME_Crate_CERN.jpeg|800x450px|Layout of the VME crate at CERN.]]

Layout of the VME crate at CERN. The ALPHA-T module is in the rightmost slot. The Master CDM is next to it and it's labelled as #02. The Slave CDM is on the lefmost position and labelled by #03.

== Setup of CDM boards ==

ALPHA-g uses the Rev3 CDM boards. The 4 CDM boards that belong to ALPHA-g
have serial numbers 0, 1, 2 and 3 and are labeled cdm00, cdm01, cdm02, cdm03.

All the boards can be used as master and slave positions, but have to be
configured appropriately.

=== Slave setup ===

* install the board
* connect ethernet
* connect esata external clock
* esper-tool cdmNN ### i.e. esper-tool cdm01
* cd template
* write current_setup 4
* cd /cdm
* read
* observe clock frequency counters report correct values. "ext_clk" will only count if the lemo jumper is installed (see below)
<pre>
11 esata_clk uint32 R [62500246]
12 ext_clk uint32 R [62500246]
</pre>
* cd /lmk
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
156 ld1_counter uint32 RW [3]
157 ld2_counter uint32 RW [3]
</pre>

If needed, check correct operation of the pll lock monitoring:

* unplug the esata cable from the master CDM
* "red" light should go off
* read of lmk should report "pll1_ld" value 0 and "ld1_counter" and "ld2_counter" should increment
* reconnect the esata cable
* "red" light should return
* read of lmk should report both pll1_ld and pll2_ld locked (values "1").

=== Master setup ===

* install the board
* connect ethernet
* esper-tool cdmNN ### i.e. esper-tool cdm01
* cd template
* write current_setup 3
* cd /lmk
* write clkin_sel_mode 0
* cd /cdm
* read
* observe clock frequency counters report correct values. "ext_clk" will only count if the "clock loopback" lemo jumper is installed (see below)
<pre>
12 ext_clk uint32 R [62500189]
</pre>
* cd /lmk
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
156 ld1_counter uint32 RW [3]
157 ld2_counter uint32 RW [3]
</pre>

Check the 200MHz clock:
* connect MiniSAS-eSATA splitter cable to MiniSAS output 6, connect eSATA end to CDM eSATA input
* in esper-tool, read cdm: esata_clk should report 200MHz clock
<pre>
11 esata_clk uint32 R [200000603]
12 ext_clk uint32 R [62500188]
</pre>

=== Master setup with external 10 MHz clock ===

* setup master CDM as above (using internal clock)
* connect 10MHz external clock to LEMO1A
* esper-tool cdmNN
* cd /cdm
* write sel_nim 1 # if clock is NIM signal
* write sel_nim 0 # if clock is TTL signal (i.e. chronobox LEMO output)
* read ext_clk
<pre>
[http://cdm00:/cdm]> read ext_clk
9999556
</pre>
* if ext_clk reads 0 or does not read something close to 10MHz, stop here. debug the signal, try changing sel_nim, etc.
* cd /lmk
* write clkin_sel_mode 2 # select external clock
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
150 clkin2_sel bool R [True]
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
</pre>
* on the MIDAS TRG page, observe that TRG measured external clock frequency is close to 62.5 MHz

== clkin_sel_mode positions ==

* 0 = 10MHz internal oscillator (use on master CDM in standalone mode)
* 1 = eSATA clock (use on slave CDM)
* 2 = external clock, should be 10MHz (use on master CDM to run from AD clock)

== LEMO connections ==

LEMO connectors:

<pre>
|
|LEMO1A|LEMO1B
|LEMO2A|LEMO2B
|LEMO3A|LEMO3B
|eSATA
|RJ45 ETH
|minisas
|
</pre>

* clock loopback jumper: to read the frequency of the generated 62.5MHz clock, connect LEMO cable from LEMO2B to LEMO1A
* 10MHz internal clock jumper: to feed 10MHz internal oscillator to the external clock, connect LEMO cable from LEMO3A to the LEMO1A
* 10MHz external clock: to feed 10MHz external clock, connect LEMO cable to LEMO1A

= MIDAS frontends =

== UDP ==

feudp receives udp packets from the ADC and PWB boards. For each udp packet 1 midas event is created,
with 1 data bank containing the udp data. Events are sent into the MIDAS event buffer BUFUDP. The names
of the data banks are assigned in ODB /eq/feudp/settings.

{ADC,PWB} --> 1gige --> switch --> 10gige --> alphagdaq --> feudp -> BUFUDP

== CTRL ==

fectrl controls all the ADC, PWB and trigger boards. It provides run start and stop sequencing,
runs the event synchronization sequence at the begin of the run, and records slow controls data (temperatures,
voltages, etc).

fectrl receives UDP data packets from the trigger board and sends them to the MIDAS event buffer BUFUDP.

fectrl receives commands from the control web pages (for ADC, PWB and trigger) to reboot, initialize, etc the boards.

fectrl configures the event builder via odb /eq/fectrl/evbconfig.

ADC <-> http esper <-> fectrl -> slow control data into midas history

PWB <-> http esper <-> fectrl -> slow control data into midas history

TRG <-> udp comm <-> fectrl -> BUFUDP, slow control and counters into midas history

fectrl <-> midas rpc <-> mhttpd <-> json rpc <-> control web pages for ADC, PWB and trigger

== EVB ==

feevb receives udp packet data from the MIDAS event buffer BUFUDP, inspects the packet timestamps
and collects the data with matching timestamps into physics events. feevb has provisions to do
data suppression, reduction and compression in addition to the data reduction done
in the ADC and PWB firmware.

feevb event synchronization relies on the event synchronization sequence done by fectrl when a run is started.

{ADC, PWB, TRG} -> BUFUDP -> feevb -> SYSTEM -> mlogger -> compression -> disk storage

=== internal structure ===

* event buffer readers, instances for BUFTRG, BUFTDC, BUFADC, BUFUDP
<pre>
BufferReader class - reads one midas event buffer:
- BufferReaderThread()
-- in batches of 1000 events
--- lock
--- TickLocked()
----- ReadEvent() -> bm_receive_event_alloc()
----- fHandler->HandleEvent()
-- fHandler->XMaybeFlushBank()
-- sleep 100 usec
</pre>
* event header decoder and intermediate buffer
<pre>
Handler class - accumulates events, sends them to the EVB in batches

- HandleEvent() <- BufferReaderThread() - receive incoming events
-- loop over all banks, examine bank name
--- call AddAdcBank(), AddPwbBank(), AddTrgBank(), AddTdcBank() according to bank name
---- AddXxxBank() -> XAddBank()
--- unknown banks go directly to evb->SendQueue
-- check if synchronization has completed

- XAddBank() - save BankBuf objects in a buffer

- XMaybeFlushBank(), XFlushBank() - send all accumulated data to the Evb class
-- evb->lock()
-- for each buffered BankBuf objects,
--- call evb->AddBankLocked()
-- buffer is now empty
</pre>
* event builder
<pre>
Evb class - assemble event fragments according to timestamps

- fEvents fifo (deque) - time sorted list of partially assembled events
-- new entries are added by FindEvent()
-- entries are modified by MergeSlot()
-- old entries are removed by GetLocked()

- AddBankLocked() <- XFlushBank() <- BufferReaderThread()
-- call fSync->Add()
-- transform BankBuf to EvbEventBuf
-- push it into per-module buffer fBuf[imodule]

- EvbThread()
-- EvbTickLocked()
--- BuildLocked()
---- in a loop, for no more than 1 sec
----- loop over all per-module buffers fBuf
------ pop first entry, pass it to BuildSlot()
------- call FindEvent()
------- call MergeSlot()
------- call CheckEvent()
--- in a loop
---- get all completed events via GetLocked() pass them to SendQueue->PushEvent()
-- if done nothing, sleep 100 usec, otherwise nominal sleep to free the evb lock

- GetNext() <- GetLocked() <- EvbThread() - get completed events
-- examine oldest EvbEvent entry in fEvents:
-- pop it if it is complete
-- pop it if it is too old (to prevent old incomplete events from stalling the evb) ("pop age" on the evb page)
-- pop it if a following event is complete ("pop following" on the evb page)
</pre>
* send queue
<pre>
SendQueue class - prepare events for writing to midas SYSTEM event buffer

- PushEvent() <- EvbThread()
-- push FragmentBuf into the queue

- SendQueueThread()
-- in a batch of 1000 events, call Tick()
--- pop FragmentBuf from the queue, call SendEvent()
--- compose midas event (memcpy()!)
--- TMFE fEq->SendEvent()
--- bm_send_event()
-- sleep 100 usec
</pre>
* equipment object
<pre>
EvbEq class - implements the midas equipment
- HandleBeginRun()
- HandleEndRun()
- HandlePeriodic()
</pre>

=== multithreading ===

* BufferReaderThread() one per midas event buffer
** high CPU use: bm_receive_event(), AddXxxBank()
** lock contention: midas event buffer lock, evb lock into XFlushBank->AddBankLocked()
* EvbThread()
** O(size of fEvents): FindEvent(), GetNext()
** lock contention: evb lock against XFlushBank(), SendQueue lock (1 per output event)
* SendQueueThread()
** high CPU use: memcpy() in SendEvent(), memcpy() in bm_send_event
** lock contention: event queue lock against EvbThread, midas event buffer lock
* main thread
** lock contention: evb lock in ReportEvb() and elsewhere

= ODB entries =

== /Equipment/CTRL/Settings ==
* TBW

== /Equipment/CTRL/Settings/Pulser ==

* ClockFreqHz - unit of 1/sec (Hz), set to 62500000, the TRG 62.5 MHz clock frequency (16 ns)
* PulseWidthClk - unit of 16 ns clocks, set to 25. (400 ns). width of internal pulser signal (used to go to a TRG external output, absent on GRIF-C boards)
* PulsePeriodClk - unit of 16 ns clocks, pulser in clock periods (+1), set to zero.
* PulseFreqHz - unit of 1/sec (Hz), requested pulser frequency, actual frequency is rounded to 16 ns clock granularity, change this value to select desired clock frequency
* BurstCtrl - enable burst of pulses 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses
* OutputEnable - enable TRG pulser external output (absent on GRIF-C boards)
* Enable - allow the pulser to run (bit 3 in TRG conf_trig_enable register)

== /Equipment/CTRL/Settings/TrigSrc - trigger source selection ==
* TrigPulser - trigger on the pulser
* TrigEsataNimGrandOr - trigger on external NIM inputs of GRIF-16 ADC modules
* TrigAdc16GrandOr - trigger on any adc16 signals (see adc16_masks)
* TrigAdc32GrandOr - trigger on any adc32 signals (see adc32_masks)
* TrigAdcGrandOr - trigger on adc16_grand_or or adc32_grand_or
* (removed from trg firmware) Trig1ormore - trigger on adc16 multiplicity 1 or more
* (removed from trg firmware) Trig2ormore - ditto, 2 or more
* (removed from trg firmware) Trig3ormore - ditto, 3 or more
* (removed from trg firmware) Trig4ormore - ditto, 4 or more
* (removed from trg firmware) TrigAwCoincA - trigger on TPC AW coincidence (see [[TRG]] manual)
* (removed from trg firmware) TrigAwCoincB - ditto
* (removed from trg firmware) TrigAwCoincC - ditto
* (removed from trg firmware) TrigAwCoincD - ditto
* (removed from trg firmware) TrigAwCoinc - ditto
* (removed from trg firmware) TrigAw1ormore - trigger on TPC AW per-preamp multiplicity 1 or more (see [[TRG]] manual)
* (removed from trg firmware) TrigAw2ormore - ditto, 2 or more
* (removed from trg firmware) TrigAw3ormore - ditto, 3 or more
* (removed from trg firmware) TrigAw4ormore - ditto, 4 or more
* TrigAwMLU - trigger on TPC AW MLU signal (see [[TRG]] manual)
* TrigBscGrandOr - trigger on any BSC signal
* TrigBscMult - trigger on predefined BSC multiplicity (see [[TRG]] manual)
* TrigCoinc - trigger on predefined coincidence of TPC AW, BSC and external signal (see [[TRG]] manual)

== /Equipment/CTRL/Settings/TRG - trigger settings ==
* Enable - if set to "n", fectrl will not do anything with the trigger board. Normal value "y"
* Modules - hostnames of the trigger board. Normal value "alphat01"
* NimMask - 32-bit mask for the 32x NIM inputs (see TRG manual). Normal value 0, unless external trigger is in use.
* EsataMask - 32-bit mask for the 32x eSATA signals (see TRG manual). Normal value 0.
* adc16_mask[16] - 16x 16-bit mask for the 100MHz GRIF-16 onboard ADCs (see TRG manual). Normal value 0xFFFF for all 16 sas links.
* adc32_mask[16] - 16x 32-bit mask for the 62.5MHz FMC-ADC32 ADCs (see TRG manual). Normal value 0xFFFFFFFF for all 16 sas links.
* PassThrough - if set to "y", trigger is passed through the trigger module without generating any events and without causing deadtime.
* AwCoincA, B, C and D - 32-bit masks for the aw16 coincidence trigger (see TRG manual)
* Aw16FromAdc16 - route AW trigger (aw16) from adc16 (100MHz ADCs 0..15)
* Aw16FromAdc32a - route AW trigger (aw16) from adc32 group 15..0 (62.5MHz FMC-ADC32 minisas links 0..7)
* Aw16FromAdc32b - route AW trigger (aw16) from adc32 group 31..16 (62.5MHz FMC-ADC32 minisas links 8..15)
* MluDir, MluFiles - location of aw16 MLU bit patterns
* MluSelectedFile - currently selected/loaded MLU file. 0="grand or", 1="2 or more hit clusters", 2="2 or more hit clusters, with gap 2 or more", 3="3 or more hit clusters"
* MluPrompt - length of aw16_prompt_run gate in units of 8 ns clock, see [[TRG#aw16_mlu]]
* MluWait - length of aw_prompt_wait gate in units of 8 ns clock, see [[TRG#aw16_mlu]]
* MluTrigDelayClk - "TrigDelay" when triggered of aw16 MLU, in units of 16 ns clock
* (BSC settings, TBW)
* BscFromAdc16a - (at CERN, set to "y") route BSC trigger data (bsc64_bus) from 100 MHz adc16 digitizers minisas links 0..7
* BscFromAdc16b - route BSC trigger data (bsc64_bus) from 100 MHz adc16 digitizers minisas links 8..15
* BscBotOnly - route BSC trigger data from bottom ASD cards, bsc64_bus = bot
* BscTopOnly - route BSC trigger data from top ASD cards, bsc64_bus = top
* BscBotTopOr - (set to "y") use bsc64_bus = (top OR bottom)
* BscBotTopAnd - use bsc64_bus = (top AND bottom)
* BscMultiplicityMin - (set to 2) BSC multiplicity trigger - minimum multiplicity
* BscMultiplicityWindowClk8 - (set to 80) BSC multiplicity window, 8 ns clocks
* BscEmptyWindowClk8 - (set to 80) BSC empty window, 8 ns clocks, see [[TRG#bsc64_multiplicity_trigger]]
* BscGrandOrDelayClk16 - (not implemented) trigger delay used by fectrl when TrigSrc/TrigBscGrandOr is selected
* BscMultTrigDelayClk16 - trigger delay used by fectrl when TrigSrc/TrigBscMult is selected
* CoincStart - set same as CoincRequire
* CoincRequire - 0x5: (BSC grand or)*(TPC aw16_grand_or), 0x9: (BSC multiplicity)*(TWC aw16_grand_or), 0x6: (BSC grand or)*(AW16 MLU), see [[TRG#Coincidence_trigger]] and [[TRG#conf_coinc_control bits]]
* CoincWindow - length of coincidence window in 8ns clocks.
* CoincTrigDelayClk16 - trigger delay used by fectrl when TrigSrc/TrigCoinc is selected

== /Equipment/CTRL/Settings/PWB - PWB settings ==
* Enable - if set to "n", fectrl will not do anything with PWBs. Normal value "y".
* enable_boot_user_page - if set to "n", fectrl will not try to reboot PWBs into the user page firmware. Normal value "y".
* enable_trigger - if set to "n", all PWBs will be set to ignore the trigger. Normal value "y".
* enable_trigger_group_a - field wire pulser defeats the data suppression (every channel has a pulse) resulting in too much data overwhelming the DAQ (lost UDP packets). To permit correct data taking of field wire pulser data, PWBs are split into two groups (a and b), only one of the two groups should be enabled for field wire pulser runs. Both groups should be enabled for normal data taking. Normal value is "y"
* enable_trigger_group_b - see "enable_trigger_group_a". Normal value is "y".
* modules[64] - hostnames of PWB boards
* boot_user_page[64] - if set to "y" and enable_boot_user_page is "y", fectrl will reboot the corresponding PWB to the user page firmware.
* trigger[64] - if set to "y" and enable_trigget is "y", fectrl will set the PWB to accept the trigger.
* ch_enable - if set to "n" disables all PWB channels. Normal value is "y".
* ch_force - is set to "y" disables channel suppression (all PWB channels are read)
* suppress_reset - if set to "y" enables channel suppression for reset channels (threshold has to be set correctly)
* suppress_fpn - if set to "y" enables channel suppression for fpn channels (threshold has to be set correctly)
* suppress_pads - set to "y" enables channel suppression for TPC pad channels (threshold has to be set correctly)
* disable_reset1 - data suppression algorithm does not work for the channel "reset1" and it has to be suppressed explicitly by setting this value to "y". Normal value is "y".
* baseline_{reset,fpn,pads}[64] - waveform baseline for each PWB position
* threshold_{reset,fpn,pads} - waveform suppression threshold, see below:
* ch_threshold - PWB sca_N_ch_threshold, if set to 0, threshold is computed as "baseline_pads[seqpwb]-threshold_pads". Normal value is 0.
* test_mode - enable PWB test mode, the ADC data is replaced with a test pattern, see PWB esper variable signalproc/test_mode

== /Equipment/CTRL/Settings/TDC - TDC settings ==
* Enable - if set to "n", fectrl will tell the event builder that the TDC is not running. Normal value is "y".

== /Equipment/CTRL/Variables ==

* Scalers - TRG scalers and counters. from fectrl.cxx ReadTrgLocked()
<pre>
// 0..15 read the 16 base scalers at 0x100
// 16..31 read the adc16 scalers at 0x430
// 32..63 read the adc32 scalers at 0x440
// 64..79 read the 16 additional scalers at 0x110
// 80..95 read the 16 counters_adc_selected scalers at 0x460
// 96..159 read the 64 bar scalers at 0x470
// additional scalers should be appended at the end.
</pre>

== /Equipment/CTRL/EvbConfig - EVB configuration ==
All arrays have the same size corresponding to the number of EVB slots.
* name[] - slot name for the web page (trg01, adc01, adc01/adc32, pwb31/0, tdc01, etc)
* type[] - slot type: 1=TRG, 2=ADC16 and ADC32, 3=obsolete PWB, 4=obsolete PWB, 5=PWB, 6=TDC
* module[] - module number (adcNN, adcNN+100, pwbNN, etc)
* nbanks[] - number of expected banks (16 for ADC16, 32 for ADC32, not used, set to 1 for all others)
* tsfreq[] - timestamp frequency in Hz.

== /Equipment/ADC_UDP - ADC UDP configuration ==

* Common/Buffer - "BUFADC" - event buffer to use, name is hardwired in feevb.cxx
* Settings/udp_port - 50006 - UDP port number, also used by fectrl to configure the ADC modules
* Settings/rcv_bufsize - 209715200 - udp socket buffer size set by setsockopt(SOL_SOCKET, SO_RCVBUF). must have a corresponding command in /etc/rc.local to increase maximum system socket size: "/usr/sbin/sysctl -w net.core.rmem_max=200000000"
* Settings/packet_size - 1500 - non-jumbo-frame UDP packet maximum size
* Settings/max_buffered_packets - 40000 - maximum size of internal packet fifo. If it overflows, extra packets are discarded.
* Settings/max_packets_per_event - 8000 - how many UDP packets to pack into one midas event==

== /Equipment/PWB_X_UDP - PWB UDP configuration ==

For explanation see ADC_UDP above.

* Common/Buffer - "BUFUDP" - event buffer to use, name is hardwired in feevb.cxx
* Settings/udp_port - 50007, 50008, 50009, 50010 - for A, B, C and D UDP receivers respectively, also used by fectrl to configure the PWB modules
* Settings/rcv_bufsize - 209715200
* Settings/packet_size - 1500
* Settings/max_buffered_packets - 10000
* Settings/max_packets_per_event - 8000

= Trigger configuration =

These trigger modes are implemented:
* (manual trigger from web page)
* software pulser trigger (from fectrl)
* hardware pulser trigger (from the trigger board)
* NIM and eSATA trigger from ADC front panel inputs
* adc16 and adc32 discriminator triggers:
** adc16 grand-or trigger
** adc32 grand-or trigger
** adc (adc16+adc32) grand-or trigger
** adc16 multiplicity trigger (1ormore, 2ormore, 3ormore, 4ormore) for use with barrel scintillator
** anode wire multiplicity trigger (1ormore, 2ormore, 3ormore, 4ormore) (anode wire signals can be fed from adc16 or from adc32 signals)
** anode wire coincidence trigger
** anode wire MLU (memory lookup) trigger

== NIM trigger from ADC front panel ==

Trigger path:
<pre>
NIM signal --> LEMO input on ADC front panel --> data encoder --> data link to trigger board --> data decoder --> mask --> nim-esata-grand-or --> trigger
</pre>

To enable NIM trigger, do this:
* connect NIM signal to ADC front panel input
** Note1: NIM signal must be inverted
** Note2: LEMO connectors should be set to "NIM input" mode by ADC on-board jumpers (see ADC manual)
* observe correct bit goes to zero in the TRG web page: data link high work should change:
<pre>
0xNF00'0000 (N is the module id) to
0xN700'0000 (left lemo) or
0xNB00'0000 (right lemo)
</pre>
* Note3: if data link bits do not change, most likely the LEMO connectors are set to "DAC output" mode. Try to use LEMO inputs of a different ADC.
* compute the NIM mask: there are 32 bits, 2 bits per ADC data link. Bit 0x1 is right LEMO, bit 0x2 is left LEMO
* for example, to use left LEMO of ADC data link 12, set nim mask to (0x2)<<(2*12) = 0x02000000
* development branch of the git repository contains ''scripts/nim_mask.py'', which can compute forwards and backwards
* initialize the trigger board (on the TRG web page press button "initialize"), or start a new run
* on the history plot with "NIM grand or" counter, the rate should change from zero
* if a run is active, if one of the ADC LEMO outputs is set to output the trigger signal as a NIM pulse, one should see it fire use a scope. The delay or jitter between NIM trigger in and NIM trigger out should be around 100-200 ns (FIXME - measure this!)
* to set the DAQ to trigger on the NIM signal, on the run start page, check the box "TrigEsataNimGrandOr".
** Note: remember to set the scaledown to 0 if so desired.

= TPC field wire pulser =

The TPC field wire pulser input should be connected directly to the DAC output of ADC[0] (right lemo connector).

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for pulsing PWBs, baseline -1V, pulse height +2V (maximum possible pulse height in PWBs. Overdrives the AW ADC waveforms)
** dac_baseline: -8000
** dac_amplitude: 8000
** ramp_up_rate: 128
** ramp_down_rate: 70
** ramp_top_len: 128

* for pulsing AW, baseline -0.25V, pulse height +0.7V (AW ADC waveforms are in range. PWB waveforms are too small for goor time resolution)
** dac_baseline: -2000
** dac_amplitude: 4000
** ramp_up_rate: 20
** ramp_down_rate: 20
** ramp_top_len: 128

= BSC pulser =

The BSC pulser input on the BSC VME rear transition board (RTM) should be connected directly to the DAC output of ADC[4,5,6,7] (right lemo connector). (8 RTMs, but 4 ADCs, each signal is split using a LEMO "T" connector).

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for pulsing BSC, baseline -0.950V, pulse height +1.4V
** dac_baseline: -8000
** dac_amplitude: 4000
** ramp_up_rate: 64
** ramp_down_rate: 64
** ramp_top_len: 128

= NIM output =

To configure ADC analog output for NIM compatible pulse:

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for output of NIM pulse: baseline 0V, pulse height -0.9V, pulse width 100 ns
** dac_baseline: 0
** dac_amplitude: 8000
** ramp_up_rate: 128
** ramp_down_rate: 128
** ramp_top_len: 4
** dac_xor: 1 (invert the signal)

= TDC connections =

* SFP8 - fiber SFP to Juniper switch
* right RJ45 - 200MHz clock
* left RJ45 - external trigger

= MIDAS Data banks =

* ATAT - fectrl - UDP packets from GRIF-C/TRG trigger board
* TRBA - fetdc - TDC data
* TRTM - fetdc - TDC FPGA temperatures, TID_FLOAT[5].
* AAnn - feudp - UDP packets from GRIF-16 ADC (before the event builder), "nn" is the ADC module number: adc01 is AA01 through adc20 is AA20.
* BBxx - feudp - UDP packets from PWB, obsolete
* Bnnm, Cnnm - feevb - EVB output banks: ADC data, "nn" is the ADC module number (1..20), "m" is the channel number (0..9,A..F), format is same as AAnn banks.
* PAnn - feudp - UDP packets from PWB, "nn" is the PWB module number (00..99), obsolete
* PBnn - feudp - UDP packets from PWB, "nn" is the PWB module number (00..99), PB01 is pwb01, PB78 is pwb78
* PCnn - feevb - EVB output banks: PWB data, "nn" is the PWB module number (00..99), same as above, format is same as PBnn banks

= ZZZ =

ZZZ

PWB

2023-03-23T19:20:31Z

Olchansk: /* TODO */

= Links =

* https://bitbucket.org/expalpha/pwb_rev1_firmware
* https://edev-group.triumf.ca/fw/exp/alphag/feam/rev1
* https://edev-group.triumf.ca/hw/alphag/feam/rev1
* https://ladd00.triumf.ca/daqinv/frontend/list/170 - PWB inventory database

= Schematics =

* [[Image:pwb_rev0.pdf]]
* [[Image:Pwb-rev1-after.pdf]]
* [[Image:AlphaG Rev1.pdf]]

= Manuals =

* [[Image:AFTER_MANUAL_V1.pdf]] AFTER SCA manual v1
* [[Image:AFTER_DataSheet1_1.pdf]] AFTER SCA manual v1.1
* [[Image:AFTER_SCA_table2.pdf]] AFTER SCA channel map

= Hardware =

== Power distribution and monitoring ==

External power supply is:
* +5V
* +2V

Central board:

* Ext_5V - F1 - RS1 (0.1R) - Fuse_5V
* Ext_2V - F2/F3 - RS2 (0.1R) - Idig2-
* LDO3 - Fuse_5V - DIG_3.3V - selfenable - ADM7154
* LDO5 - Fuse_5V - DIG_2.5V - selfenable - ADM7154
* LDO_CLN - Fuse5V - CLN_3.3V - selfenable -
* VREG - DIG_3.3V - -2.5V SCA BIAS - selfenable - LTC1983ES6-3#TRMPBF
* LDO7 - DIG_2.5V - DDR3_VRef - enable DDR3_1P5V, DDR3_PG, DDR3_VttEN
* LDO2 - Idig2V- - DIG_1.1V - enable DIG_3.3V - LT3071
* LDO6 - Idig2V- - DDR3_1P5V - enable DIG_3.3V - LT3083

SCA Wing:

* Ext_5V - F1 - RS1 (0.3R) - Isca- - SCA_Fuse5V
* LDO1 - SCA_Fuse5V - SCA3.3V - enable ADC_PWR_EN - ADM7154
* LDO2 - SCA3.3V - ADC1.8V - selfenable - ADM7154
* LDO3 - SCA3.3V - TRN2.5V - selfenable - LT1761
* REF - SCA3.3V - 1.45V Vicm - selfenable - LM4121

esper variables:

* board/i_sca12, i_sca34, v_sca12, v_sca34: voltage and current into LDO1, after fuse F1 (wing board)
* board/i_p2, v_p2: voltage and current on 2V bus after fuses F2/F3
* board/i_p5, v_p5: voltage and current on 5V bus after fuse F1 (central board)

== Trigger and Clock distribution ==

Clock (62.5MHz) and trigger are distributed to the PWB columns via the [https://edev-group.triumf.ca/hw/alphag/trigger-card-sata-adapter/rev1 trigger SATA adapter].

The two miniSAS cables from cdm03 port 5 and 6 are connected to a miniSAS-SATA splitter 1-to-4 (CS Electronics "iSAS SATA adapter" ADP-887P-1X). Since there are only 8 columns and the clock and trigger signals are daisy-chained across the 8 rows, this scheme is sufficient to provide the necessary inputs to all 64 PWBs.

[https://www.techcable.com/sas-mini-sas-cables/sata-cables/ SATA 6Gb/s Cable with Latching Clip. Straight Pinout 1-1 247726-L 40in]

== Optical Link ==

Main data uplink.

SFP (Small Form Pluggable) Avago Technologies AFBR-57M5APZ [[File:AVAGO SFP specs.pdf|SFP (Small Form Pluggable) Avago Technologies AFBR-57M5APZ]]

Fiber optic Tripp Lite N820 - 10 m [[File:FiberOptic TrippLite specs.pdf|Fiber optic Tripp Lite N820 - 10 m]]

== SATA Link ==

Secondary data uplink, capable also to deliver clock and trigger.

The SATA link connects PWB from adjacent columuns on the same row.

The SATA cable is a "crossed cable".

= Firmware =

== Firmware update ==

PWB firmware update is done using "esper-tool".

<pre>
esper-tool -v upload -f file.rpd http://pwbNN update factory_rpd
esper-tool -v upload -f file.rpd http://pwbNN update file_rpd
</pre>

As of PWB firmware pwb_rev1_20200706_ko:

Permission to write into the flash memory is controlled by esper variables:

* allow_write set to "false": "esper-tool upload" does a "verify": successful upload means epcq flash content is same as rpd file, error means content is not the same.
* allow_write set to "true": "esper-tool upload" updates the epcq flash from the rpd file: for each data block, read the epcq flash, compare to rpd data, if different, erase the flash block, write the flash, read the flash, if there is a mismatch (bad write), return an error.
* allow_factory_write set to "true" to enable writing to the "factory_rpd". DO NOT SET IT TO "true" UNLESS YOU MEAN TO UPDATE THE PWB BOOTLOADER. IF YOU FLASH BUM FIRMWARE or IF THERE IS A POWER OUTAGE WHILE UPDATING, THE PWB WILL BE BRICKED and has to be recovered by connecting a USB blaster.

To update firmware of multiple boards to correct version, recommended is the script "update_pwb.perl":
<pre>
cd ~/online/src
./update_pwb.perl pwb12 pwb06 pwb78
</pre>

== Factory page and user page firmware boot ==

Each PWB board has 2 firmware images: boot loader (factory page)
and data acquisition (user page). On power up, the FPGA loads and runs
the boot loader firmware from the factory page, later the control
software reboots the FPGA into the data acquisition firmware from
the user page.

Because loading defective firmware can brick https://en.wikipedia.org/wiki/Brick_(electronics)
the PWB, new firmware images are loaded into the user page, if anything is wrong,
the PWB can still boot from the factory page and one can use the firmware update
function to load a good firmware image into the user page.

The boot loader firmware in the factory page is not intended for data acquisition, it is only meant to provide three functions:
* boot enough hardware and software to communicate via the ethernet and the sata link
* firmware update (both factory page and user page)
* reboot into the user page

The boot loader firmware in the factory page is usually never updated unless absolutely
needed to fix a problem with these three functions (i.e. compatibility with sata link communications).

If factory image is corrupted or the contains defective firmware and the PWB does not boot (no dhcp, no ping, no esper),
the only way to unbrick it is by loading good firmware using a jtag flash programmer (usb-blaster). Connecting it requires
physical access to the jtag connector on the PWB board. It is impossible when the detector is fully assembled in the experiment.

The PWB has a 32 Mbyte EPCQ flash memory chip, it is divided into 2 pages 16 Mbytes of factory page and 16 Mbytes of user page.

A complete firmware image generally contains 3 pieces:
* FPGA firmware and NIOS "feam_bootloader" software RAM image (sof file)
* NIOS "feam" software RAM image (feam.elf.flash.hex) - all the C code for esper communications and PWB data acquisition
* NIOS filesystem image (feam.webpkg.hex) - esper web pages

This is the boot sequence:
* on power-up the FPGA automatically loads the sof file from address 0 of the EPCQ flash (this is the factory image sof file)
* the FPGA is "started"
* the NIOS CPU starts executing the "feam_bootloader" C code embedded in the sof file (NIOS project hdl/software/feam_bootloader)
* feam_bootloader initializes the hardware (clocks, DDR memory, etc)
* feam_bootloader write-protects the EPCQ flash memory
* feam_bootloader copies the "feam" software from EPCQ flash to the DDR memory (after checking for correct checkum)
* feam_bootloader restarts the NIOS CPU
* the NIOS CPU starts running from DDR memory, executes the "feam" software (NIOS project hdl/software/feam)
* call main() in hdl/software/feam/src/task_init.c
* call task_init() in the same file
* infinite loop waiting for IP address via DHCP
* after have IP address, call task_esper() from hdl/software/feam/src/task_esper.c
* task_esper() creates all the esper modules, esper variables, etc,
* mod_http.c starts the mongoose web server
* PWB is open for business

This is the protection against booting corrupted firmware:
* FPGA hardware loads the sof file from epcq flash and checks for correct checksum before "starting" it
* NIOS CPU is part of the sof file, protected by sof file checksum
* NIOS feam_bootloader C code is part of the sof file, protected by the sof checksum
* feam_bootloader checks for correct signatures and checksums of the DDR memory image
* "feam" C code is protected by the checksum of the DDR memory image

== NIOS terminal ==

<pre>
$ ssh agmini@daq16
$ /opt/intelFPGA/16.1/quartus/bin/jtagconfig
1) USB-Blaster [2-1.2]
02B030DD 5CGTFD7(B5|C5|D5)/5CGXBC7B6/..
$ /opt/intelFPGA/17.0/quartus/bin/nios2-terminal
nios2-terminal: connected to hardware target using JTAG UART on cable
nios2-terminal: "USB-Blaster [2-1.2]", device 1, instance 0
nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)
PWB Revision 1 Boot Loader
Ver 2.0 Build 357 - Wed Jun 6 15:05:35 PDT 2018
...
</pre>

== Flash boot loader firmware via jtag ==

<pre>
$ ssh agmini@daq16
$ /opt/intelFPGA/16.1/quartus/bin/jtagconfig
1) USB-Blaster [2-1.2]
02B030DD 5CGTFD7(B5|C5|D5)/5CGXBC7B6/..
$ cd ~/online/firmware/pwb_rev1
$ ls -l
$ /opt/intelFPGA/17.1/quartus/bin/quartus_pgmw
... auto detect
... load the jic file
... in menu tools->programmer, enable "unprotect device"
... start program/configure operation
</pre>

== Flash user page firmware via esper-tool ==

<pre>
$ ssh agmini@daq16
$ cd online/src
$ more update_pwb.perl ### check that $fw is set to the desired firmware file
$ ./update_pwb.perl pwb06 ### or give more PWB names or give "all"
</pre>

== Build firmware ==

=== quartus version to use ===

* quartus 16.1 should be used for jtag (jtagconfig and jtagd)
* quartus 17.0 should be used to build the PWB firmware (17.1 is not compatible)

=== start license server ===

<pre>
ssh agmini@daq16
/opt/intelFPGA/17.0/quartus/linux64/lmgrd -c ~agmini/online/license-daq16.dat
</pre>

=== prepare the build environment ===

<pre>
$ ssh agmini@daq16
$ /opt/intelFPGA/17.0/nios2eds/nios2_command_shell.sh
</pre>

=== get latest version of the code and build it ===

<pre>
$ cd online/firmware/git/pwb_rev1_firmware
$ git pull
$ git checkout alphag
$ git pull
$ ./scripts/compile_project.sh
... about 30-40 minutes ...
$ ls -l bin/*.sof bin/*.jic bin/*.rpd
-rw-r--r-- 1 agmini alpha 12727389 Jan 24 2018 bin/feam_rev1_auto.rpd
-rw-r--r-- 1 agmini alpha 33554661 Jan 24 2018 bin/feam_rev1.jic
-rw-r--r-- 1 agmini alpha 6974754 Jan 24 2018 bin/rev1.sof
$ ### feam.jic is loaded via jtag
$ ### feam_auto.rpd is loaded via esper
$ ### feam.sof is used to attach the quartus signal tap logic analyzer
</pre>

=== firmware build order and sequence ===

* erase previous build
* regenerate qsys
* regenerate NIOS BSP "feam_bootloader_bsp" and "feam_bsp"
* build NIOS projects "feam_bootloader" and "feam"
* build quartus sof file (with the "feam_bootloader" nios project inside)
* build jic and rpd files (with the quartus sof file and the "feam" nios project inside)
* load sof file into the FPGA using jtag (be careful about compatible "feam" nios project already in the epcq flash)
* load jic file into the epcq factory page using jtag (cycle power for them to take effect)
* load rpd file into the epcq factory or user page using esper

=== scripts for building the firmware ===

* scripts/compile_project.sh - build everything from scratch:
* scripts/compile_qsys.sh - regenerate the main qsys component
* scripts/compile_nios.sh - regenerate the BSPs, then same as compile_elf.sh
* scripts/compile_elf.sh - build the BSPs, "feam_bootloader" and "feam" NIOS projects
* scripts/update_elf.sh - regenerate the rpd and jic files to include the new "feam" NIOS build (keeps the old "feam_bootloader" in the sof file)
* scripts/update_bootloader.sh - also regenerate the sof file to include the new "feam_bootloader" build
* scripts/clean_quartus.sh - prepare quartus fpga sof file to build from scratch
* scripts/compile_quartus.sh - build the quartus fpga sof file incrementally (run clean_quartus.sh to build from scratch).
* scripts/load_jtag_sof.pl bin/rev1.sof - load sof file into the FPGA. this will boot the new fpga firmware, the new feam_bootloader (if update_bootloader.sh was run), but with the old "feam" already in epcq flash. (beware of incompatible sof, "feam_bootloader" and "feam" builds!)
* scripts/load_jtag_jic.pl bin/feam_rev1.jic - load jic file into the EPCQ flash, same as using the graphical flash programmer tool. (this will leave the FPGA running the quartus jtag flash loader firmware, not the PWB firmware. Cycle power for new jic file to take effect).

== ESPER Variables ==

* Board
** invert_ext_trig - invert trigger signal from CDM before it drives any logic (to undo incorrect signal polarity)
** reset_nios - goggle up, them down to reset NIOS subsystem

* Signalproc
** test_mode - ADC data is replaced with a test pattern, see test mode bits in sca_x_ch_ctrl.
** sca_a_ch_ctrl, sca_b_ch_ctrl, sca_c_ch_ctrl, sca_d_ch_ctrl - channel control bits:
<pre>
11..0 - threshold - channel suppression threshold
14..12 - ctrl_test_mode - test mode:
0=fixed patter 0xa5a,
1=time bin counter,
2=time bin counter with channel number,
3=sequential adc sample counter,
4={ch_crossed_out,trig_pos,trig_neg,adc[8:0]},
5={trig,adc[10:0]},
6={ch_crossed_min,adc[10:0]}
15 - ctrl_supp_mode - channel suppression mode: 0=adc<=(baseline-threshold), 1=adc<=threshold
</pre>

* Link
** link_ctrl - sata link control. The bits are:
<pre>
0 - sata_link_udp_stream_in_enable - permit data flow from sata link to OFFLOAD_SATA
1 - udp_stream_out_enable - permit sca data flow to sata link
2 - sata_to_eth_enable - permit ethernet data flow from sata link to TSE_MAC
3 - eth_to_sata_enable - permit ethernet data flow from TSE MAC to sata link
4 - enable_stop_our_tx - enable flow control: allow stop_tx
#5 - stop_our_tx - manually activate the flow control signal into link_tx
6 - enable_stop_remote_tx - enable flow control: allow send "stop_tx"
#7 - stop_remote_tx - manually activate the flow control signal into link_tx
8 - tx_test_pattern_udp - udp data is replaced by test pattern 0x11111111, 0x22222222, etc.
9 - tx_test_pattern_eth - nios-to-sata data is replaced by test pattern 0x11111111, 0x22222222, etc.
10 - udp_delay_enable - delay between udp packets, see udp_delay_value below
11 - reboot_tx - send K_REBOOT command to the sata link mate, where it has same effect as board/reset_nios.
12 - sata_to_nios_disable
13 - nios_to_sata_disable
14 -
15 -
16 -
24..31 - udp_delay_value - delay between udp packets (top 8 bits of a 20-bit counter)
</pre>

== Firmware data path ==

Main data path:
<pre>
feam_top
|
sca_sigproc
|
sca_event_control
4 * sca_control (sca_channel.sv)
4 * channel_fifo (1024 samples)
</pre>
<pre>
sca_control (sca_channel.sv)
|
state machine to control SCA read and write enables
|
sca_write_control (what does it do?!?)
sca_read_control
</pre>
<pre>
sca_read_control
|
state machine to store ADC samples into per-channel FIFOs (channel_fifo)
selector to replace ADC samples with a test pattern
79*sca_trig_one -> ch_crossed_out - channel hit detector
</pre>
<pre>
sca_event_control
|
event_fifo (hdl/mf/event_descriptor_fifo)
state machine to take ADC data from 4 per-channel FIFOs (channel_fifo) and store it into DDR memory (write addr increment is 510*8 (number of samples)*8 = 4080).
state machine to read transposed ADC data from DDR memory (read addr increment is 8+8=16 - 2 samples * 2 bytes * 4 sca = 16) and create 4 per-sca data streams
</pre>
<pre>
data stream:
4 per-sca data streams from sca_event_control -> sca_sigproc(event_dat)
|
packet_chunker (hdl/lib/packet_chunker.sv) (4*event_dat -> event_segment_dat) - multiplex 4 data streams into 1 stream of UDP-sized packets
|
packet_length_prepender (hdl/lib/packet_length_prepender.sv) (event_segment_dat -> udp_event_val_out)
|
udp_event_val -> info qsys (udp_stream_sca) and into sata link (mux channel 2).
</pre>

== Firmware build instructions from Bryerton (obsolete) ==

This is the old README.md file from the firmware git repository.

These instructions are not used to build the firmware (use scrips/compile_project.sh).

They are still useful for figuring out which buttons to push in the altera gui programs.

<pre>
# ALPHAg FrontEnd Acquisition Module (FEAM) - REV0

Welcome to the ALPHAg FEAM Project

# Table of Contents

* [Overview](#overview)
* [Inital Setup](#initial-setup)
* [Quartus Setup](#quartus-setup)
* [Create the .cdf](#create-the-cdf)
* [NIOS Setup](#nios-Setup)
* [Create the project files](#create-the-project-files)
* [Build Instructions](#build-instructions)
* [Building from Quartus GUI](#building-from-quartus-gui)
* [Generate the QSys File](#generate-the-qsys-file)
* [Compile the NIOSII Project](#compile-the-niosii-project)
* [Compile the Quartus Project](#compile-the-quartus-project)
* [Building from Scripts](#building-from-scripts)
* [Installing from JTAG](#installing-from-jtag)
* [Installing from ESPER](#installing-from-esper)

# Overview

The FEAM is a digitizer located on the ALPHAg detector. Each FEAM consists of 4 AFTER SCAs for a total of 288 channels.

# Initial Setup

## Quartus Setup

### Create the .cdf
1. Open Quartus Prime Standard Edition
2. Click on **Tools -> Programmer**. The **Programmer** window will appear
3. In the **Programmer** window, click **Auto Detect**. A **Select Device** dialog box will appear
1. (Optional) If **Auto Detect** is greyed out, click on **Hardware Setup**. The **Hardware Setup** dialog box will appear
2. Under **Hardware Settings**, double-click on the USB JTAG hardware you wish to use
3. Click **Close**. The **Hardware Setup** dialog box will close
5. Click on **File -> Save As**. The **Save As** dialog box will appear
6. In the **Save As** dialog box, browse to the **/\<project_dir\>/bin/** directory
7. Make sure the **Add file to current project** checkbox is checked
7. In the **File name** input box, type "alphag_feam.cdf" and click **Save**
8. Close the **Programmer** window
9. Done!

## NIOS Setup

### Create the project files
1. Open Quartus Prime Standard Edition
2. Open the NIOS II Software Build Tools by clicking **Tools -> NIOS II Software Build Tools for Eclipse**
3. The **Workspace Launcher** window will appear, click *OK* to accept the default workspace.
4. Click **File -> Import...**. The **Import** dialog box will appear
5. Click on **General -> Existing Projects into Workspace**
6. Click **Next \>**
7. Next to **Select root directory** click **Browse...**. A **Browse for Folder** dialog box will appear
8. Browse to **/\<project_dir\>/hdl/software** and click **OK**
8. Four Projects should appear in the **Projects** panel:
* alphag_feam
* alphag\_feam\_bsp
* alphag\_feam\_bootloader
* alphag\_feam\_bootloader\_bsp
9. Click **Select All**
10. Click **Finish**
11. Done!

# Build Instructions

## Building from Quartus GUI

**Warning: Please use Quartus Prime Standard Edition 16.1**
### Generate the QSys File
1. Open Quartus Standard Edition 16.1
1. Open QSys by clicking **Tools -> QSys**
2. Click on **File -> Open** (CTRL+O). An **Open File** dialog box should appear.
3. Select the **alphag_feam.qsys** file from the **/\<project_dir\>/hdl** directory and click **Open**
4. Modify as necessary. NOTE: Any change to the QSys, even cosmetic such as expanding or collapsing components will cause the QSys to desire a re-generate.
5. Click **File -> Save** (CTRL+S)
6. Click **Generate HDL**. A **Generation** dialog box will appear
7. Select the settings you desire to be changed, if any
8. Click **Generate**
9. Wait for the generation to complete.
10. Done!

### Compile the NIOSII Project
1. Open the NIOS II Software Build Tools by clicking **Tools -> NIOS II Software Build Tools for Eclipse**
2. (Optional) If the QSys file has been re-generated performing the following
1. Right-click on **alphag\_feam\_bsp** and select **NIOS II -> Generate BSP**. The BSP will regenerate
2. Right-click on **alphag\_feam\_bootloader\_bsp** and select **NIOS II -> Generate BSP**. The BSP will regenerate
3. Modify files as needed. WARNING: Do not modify any BSP files by hand! All changes will be lost on next generate.
4. Click **Project -> Build All** (CTRL+B). If your workspace as multiple projects, it is recommend to close all but the ones related to the FEAM.
5. Right-click on **alphag\_feam\_bootloader** and select **Make Targets -> Build...**. The **Make Targets** dialog box will appear
6. In the **Make Targets** dialog box, select **mem\_init\_generate** and click **Build**
7. Done!

### Compile the Quartus Project
1. Open Quartus Standard Edition 16.1
1. Under **Processing** click **Start Compilation** (CTRL+L)
2. Wait about 16-30 minutes.
3. Done!

**Note:** If Quartus crashed while compiling, delete the **\<project_dir\>/hdl/db** and **\<project_dir\>/hdl/incremental_db** directories and try again

## Installing from JTAG
1. Generate the .jic file using the provided /bin/alphag\_feam\_jic.cof
1. In the main Quartus window, click **File -> Convert Programming Files**, A **Convert Programming Files** window will appear
2. In the **Convert Programming Files** window, click **Open Conversion Setup Data**. An **Open** dialog box will appear
3. In the **Open** dialog box, select the **alphag_feam.cof** file located in **/bin/**
4. Click **Open**. The **Open dialog box will close
* Note the **File name** field, it should display /\<project\_dir\>/bin/alphag\_feam.jic
5. In the **Convert Programming Files** window, click **Generate**
6. When the .jic is done being generated, a small dialog box will appear, click **OK**
7. In the **Convert Programming Files** window, click **Close**
2. Load the .JIC file using the Programmer
1. In the main Quartus window in the **Project Navigator** drop-down input select **Files**.
2. Scroll down the window and find the **alphag_feam.cdf**, and double-click it. The **Programmer** window will open
3. Click on the icon labelled **5CGXFC4C6**
4. Click on the **Change File** button. The **Select New Programming File** dialog box will appear
5. Browse to **/\<project_dir\>/bin/** and select **alphag\_feam.jic**
6. Click Open. The **Select New Programming File** dialog box will close
7. In the main panel, check the **Program/Configure** box on the line that starts **./bin/alphag\_feam.jic**
8. Click the **Start** button
9. Wait for the **Progress** bar to go to 100% and stop
10. Done!
</pre>

= Internal test pulser =

Documentation from Bryerton:

<pre>
---------- Forwarded message ---------
From: Bryerton Shaw <bryerton@triumf.ca>
Date: Tue, 24 Apr 2018 at 16:18
Subject: RE: PWB/FEAM internal test pulse
To: Lars Martin <lmartin@triumf.ca>
Cc: Andrea Capra <acapra@triumf.ca>

Hi Lars (and Andrea),

In the new(er) firmware the test pulse code has been modified slightly to
fit in better with the upgraded trigger system. I can add an option to
allow it to be triggered by the external trigger (currently it has an
interval option, or you can hit the manual trigger to fire it, if it’s
enabled)

The *options for the test pulser* are under the *signalproc module*:

*test_pulse_ena*

An array of four booleans, that control turning on the test pulse for each
SCA. If this is False, the other options below will do nothings for that SCA

*test_pulse_interval_ena*

An array of four booleans, that control turning on the interval trigger for
each SCA

*test_pulse_interval*

An unsigned 32-bit value that marks how many 16ns clock cycles occur
between interval triggers. Only one value, as there is only one interval
timer.

*test_pulse_wdt*

An array of four 16-bit unsigned integers that control the width of the
pulse for each SCA when the trigger occurs.

Now, there is a second set of options to control the delay of the *test
pulse interval trigger*. These options are located under the *trigger
module*

*intp_trig_ena*

Boolean value enabling/disabling the interval test pulse trigger.

*intp_trig_delay*

Unsigned 32-bit integer controlling the trigger delay, which is the time
between when the trigger is requested, and when the trigger actually fires.

You can setup the interval trigger and use that to create event packets
with the test pulse on set intervals. If the interval trigger is
insufficient, I can create another option, which is to fire the test pulse
for enabled SCAs when the external trigger goes. If so, I’ll add this
option in the *signalproc *module for you:

*test_pulse_on_ext*

An array of four Booleans, that control if the test pulse for that SCA
fires on external trigger.

Remember, in order to use the SCA test pulse at all, you must also set the
SCA to test mode. You can do this by going into the *sca0-3 modules* and
setting *test* to *functionality *(the value is *3* if you want to set it
via esper-tool)

Btw currently the SCAs are hard-coded to have all 72 channels receive the
test pulse on firing, and the option to de-select/select which channels to
fire is not offered. Would you like this ability? And if so do you want it
to set all four SCAs the same, or have an option for all 288 channels?

The waveform viewer on the webpage was removed for technical reasons, and
so all viewing is done via the MIDAS DAQ. There are some preliminary tools
I’ve created to verify the event packets and their waveforms, but I
wouldn’t call them easy to setup or use at the moment. (Or very useful for
fine comparisons). If KO doesn’t have a way of saving the events to disk, I
could deliver something that captured and saved waveforms quite quickly.

Regards,
Bryerton

*From:* Lars Martin
*Sent:* April 23, 2018 5:10 PM
*To:* Bryerton Shaw <bryerton@triumf.ca>
*Cc:* Andrea Capra <acapra@triumf.ca>
*Subject:* PWB/FEAM internal test pulse

Hi Bryerton,

Andrea and I would like to check the response function of the PWBs. For
that Daryl suggested to first look at the internal test pulse.

Can you point us to what settings are required to make that go? And to use
the external trigger if we want to acquire the data?

Ideally we would acquire Midas data from that, but it's unclear if KO's
frontend allows for that right now. Can we access the data with Esper
instead?

Finally, we haven't had the waveform display on the web page for a while,
but Daryl said you guys use it. Are we using a different page somehow?

Hope all is well with the baby, cheers,

Lars
</pre>

= TODO =

* IMPOSSIBLE (ext clock only connected to clock cleaner) add frequency counter for the external clock (62.5 MHz)
* DONE add random delay before memtest
* DONE add 4 more bits to udp_delay
* DONE fix crash on boot if run is active and triggers arrive (check that trigger is off on boot) (do not set trigger/enable_all, ext_trig_ena, inp_trig_ena, signal_proc/force_run to 1 after boot)
* DONE (kludge jtag uart write()) increase size of jtag uart output buffer, make it unlimited if possible.
* DONE (kludge jtag uart write()) on dhcp timeout, reboot the fpga - reboot of nios does not clear the jtag uart, which becomes full and nios stops.
* DONE add NIOS watchdog timeout for fectrl
* DONE do not use external clock until instructed by fectrl (clock cleaner default is pin select mode, default pin mode is input with pull down, so clock 0 is selected, this is the ext clock. but we can drive clock select pins from the fpga).
* DONE change clock cleaner power up: use the 2 lines status_clkin0 and status_clkin1 to tell clock cleaner to use the internal clock (clkin2) - from the FPGA drive first line low, second line high. Also change all NIOS code that programs the clock cleaner to keep these two lines in the "input" mode. Current code switches them to "output" mode.
* DONE clock cleaner power up state is wrong for both choices of clock: 62.5 MHz ext clock and 125 MHz internal clock, see explanation in feam_top.sv. It looks like I need to drive status_clkin0 and status_clkin1 to "holdover" mode, both logic level 1. Currently status_clkin0 is used as SPI read line, this has to be moved to a different line first.
* add watchdog timeout that works in factory mode ("remote update" watchdog only works in user mode)
* DONE enable HTTP pipelining - copy changes on mongoose from ADC project.
* reset everything if it looks like NIOS TCP/IP code has crashed, but enough code is still running to prevent tripping of the fpga-remote-update watchdog timer. such crash tends to happens when the sata link mate is rebooted and incomplete data arrives from the disrupted ethernet data path.
* DONE when loading AFTER ASIC do not go into infinite loop if read-back is broken (always mismatch).
* DONE read and report error status information bits for 2983fc.pdf voltages, currents and temperatures monitoring chip. note that SCA12, SCA34, 2V and 5V voltages are flagged 0x0B "ADC out of range, sensor over range" correctly, see 2983fc.pdf table 63 fix explanation of "normal" and "usable" voltage ranges. (5V voltage divider is 2-to-1)
* add provisions for coded trigger
* DONE verify readout of MV2 Hall magnetometer (all registers and bits from device are visible in esper)

= ZZZ =

ZZZ

PWB

2023-03-23T18:18:26Z

Olchansk: /* TODO */

= Links =

* https://bitbucket.org/expalpha/pwb_rev1_firmware
* https://edev-group.triumf.ca/fw/exp/alphag/feam/rev1
* https://edev-group.triumf.ca/hw/alphag/feam/rev1
* https://ladd00.triumf.ca/daqinv/frontend/list/170 - PWB inventory database

= Schematics =

* [[Image:pwb_rev0.pdf]]
* [[Image:Pwb-rev1-after.pdf]]
* [[Image:AlphaG Rev1.pdf]]

= Manuals =

* [[Image:AFTER_MANUAL_V1.pdf]] AFTER SCA manual v1
* [[Image:AFTER_DataSheet1_1.pdf]] AFTER SCA manual v1.1
* [[Image:AFTER_SCA_table2.pdf]] AFTER SCA channel map

= Hardware =

== Power distribution and monitoring ==

External power supply is:
* +5V
* +2V

Central board:

* Ext_5V - F1 - RS1 (0.1R) - Fuse_5V
* Ext_2V - F2/F3 - RS2 (0.1R) - Idig2-
* LDO3 - Fuse_5V - DIG_3.3V - selfenable - ADM7154
* LDO5 - Fuse_5V - DIG_2.5V - selfenable - ADM7154
* LDO_CLN - Fuse5V - CLN_3.3V - selfenable -
* VREG - DIG_3.3V - -2.5V SCA BIAS - selfenable - LTC1983ES6-3#TRMPBF
* LDO7 - DIG_2.5V - DDR3_VRef - enable DDR3_1P5V, DDR3_PG, DDR3_VttEN
* LDO2 - Idig2V- - DIG_1.1V - enable DIG_3.3V - LT3071
* LDO6 - Idig2V- - DDR3_1P5V - enable DIG_3.3V - LT3083

SCA Wing:

* Ext_5V - F1 - RS1 (0.3R) - Isca- - SCA_Fuse5V
* LDO1 - SCA_Fuse5V - SCA3.3V - enable ADC_PWR_EN - ADM7154
* LDO2 - SCA3.3V - ADC1.8V - selfenable - ADM7154
* LDO3 - SCA3.3V - TRN2.5V - selfenable - LT1761
* REF - SCA3.3V - 1.45V Vicm - selfenable - LM4121

esper variables:

* board/i_sca12, i_sca34, v_sca12, v_sca34: voltage and current into LDO1, after fuse F1 (wing board)
* board/i_p2, v_p2: voltage and current on 2V bus after fuses F2/F3
* board/i_p5, v_p5: voltage and current on 5V bus after fuse F1 (central board)

== Trigger and Clock distribution ==

Clock (62.5MHz) and trigger are distributed to the PWB columns via the [https://edev-group.triumf.ca/hw/alphag/trigger-card-sata-adapter/rev1 trigger SATA adapter].

The two miniSAS cables from cdm03 port 5 and 6 are connected to a miniSAS-SATA splitter 1-to-4 (CS Electronics "iSAS SATA adapter" ADP-887P-1X). Since there are only 8 columns and the clock and trigger signals are daisy-chained across the 8 rows, this scheme is sufficient to provide the necessary inputs to all 64 PWBs.

[https://www.techcable.com/sas-mini-sas-cables/sata-cables/ SATA 6Gb/s Cable with Latching Clip. Straight Pinout 1-1 247726-L 40in]

== Optical Link ==

Main data uplink.

SFP (Small Form Pluggable) Avago Technologies AFBR-57M5APZ [[File:AVAGO SFP specs.pdf|SFP (Small Form Pluggable) Avago Technologies AFBR-57M5APZ]]

Fiber optic Tripp Lite N820 - 10 m [[File:FiberOptic TrippLite specs.pdf|Fiber optic Tripp Lite N820 - 10 m]]

== SATA Link ==

Secondary data uplink, capable also to deliver clock and trigger.

The SATA link connects PWB from adjacent columuns on the same row.

The SATA cable is a "crossed cable".

= Firmware =

== Firmware update ==

PWB firmware update is done using "esper-tool".

<pre>
esper-tool -v upload -f file.rpd http://pwbNN update factory_rpd
esper-tool -v upload -f file.rpd http://pwbNN update file_rpd
</pre>

As of PWB firmware pwb_rev1_20200706_ko:

Permission to write into the flash memory is controlled by esper variables:

* allow_write set to "false": "esper-tool upload" does a "verify": successful upload means epcq flash content is same as rpd file, error means content is not the same.
* allow_write set to "true": "esper-tool upload" updates the epcq flash from the rpd file: for each data block, read the epcq flash, compare to rpd data, if different, erase the flash block, write the flash, read the flash, if there is a mismatch (bad write), return an error.
* allow_factory_write set to "true" to enable writing to the "factory_rpd". DO NOT SET IT TO "true" UNLESS YOU MEAN TO UPDATE THE PWB BOOTLOADER. IF YOU FLASH BUM FIRMWARE or IF THERE IS A POWER OUTAGE WHILE UPDATING, THE PWB WILL BE BRICKED and has to be recovered by connecting a USB blaster.

To update firmware of multiple boards to correct version, recommended is the script "update_pwb.perl":
<pre>
cd ~/online/src
./update_pwb.perl pwb12 pwb06 pwb78
</pre>

== Factory page and user page firmware boot ==

Each PWB board has 2 firmware images: boot loader (factory page)
and data acquisition (user page). On power up, the FPGA loads and runs
the boot loader firmware from the factory page, later the control
software reboots the FPGA into the data acquisition firmware from
the user page.

Because loading defective firmware can brick https://en.wikipedia.org/wiki/Brick_(electronics)
the PWB, new firmware images are loaded into the user page, if anything is wrong,
the PWB can still boot from the factory page and one can use the firmware update
function to load a good firmware image into the user page.

The boot loader firmware in the factory page is not intended for data acquisition, it is only meant to provide three functions:
* boot enough hardware and software to communicate via the ethernet and the sata link
* firmware update (both factory page and user page)
* reboot into the user page

The boot loader firmware in the factory page is usually never updated unless absolutely
needed to fix a problem with these three functions (i.e. compatibility with sata link communications).

If factory image is corrupted or the contains defective firmware and the PWB does not boot (no dhcp, no ping, no esper),
the only way to unbrick it is by loading good firmware using a jtag flash programmer (usb-blaster). Connecting it requires
physical access to the jtag connector on the PWB board. It is impossible when the detector is fully assembled in the experiment.

The PWB has a 32 Mbyte EPCQ flash memory chip, it is divided into 2 pages 16 Mbytes of factory page and 16 Mbytes of user page.

A complete firmware image generally contains 3 pieces:
* FPGA firmware and NIOS "feam_bootloader" software RAM image (sof file)
* NIOS "feam" software RAM image (feam.elf.flash.hex) - all the C code for esper communications and PWB data acquisition
* NIOS filesystem image (feam.webpkg.hex) - esper web pages

This is the boot sequence:
* on power-up the FPGA automatically loads the sof file from address 0 of the EPCQ flash (this is the factory image sof file)
* the FPGA is "started"
* the NIOS CPU starts executing the "feam_bootloader" C code embedded in the sof file (NIOS project hdl/software/feam_bootloader)
* feam_bootloader initializes the hardware (clocks, DDR memory, etc)
* feam_bootloader write-protects the EPCQ flash memory
* feam_bootloader copies the "feam" software from EPCQ flash to the DDR memory (after checking for correct checkum)
* feam_bootloader restarts the NIOS CPU
* the NIOS CPU starts running from DDR memory, executes the "feam" software (NIOS project hdl/software/feam)
* call main() in hdl/software/feam/src/task_init.c
* call task_init() in the same file
* infinite loop waiting for IP address via DHCP
* after have IP address, call task_esper() from hdl/software/feam/src/task_esper.c
* task_esper() creates all the esper modules, esper variables, etc,
* mod_http.c starts the mongoose web server
* PWB is open for business

This is the protection against booting corrupted firmware:
* FPGA hardware loads the sof file from epcq flash and checks for correct checksum before "starting" it
* NIOS CPU is part of the sof file, protected by sof file checksum
* NIOS feam_bootloader C code is part of the sof file, protected by the sof checksum
* feam_bootloader checks for correct signatures and checksums of the DDR memory image
* "feam" C code is protected by the checksum of the DDR memory image

== NIOS terminal ==

<pre>
$ ssh agmini@daq16
$ /opt/intelFPGA/16.1/quartus/bin/jtagconfig
1) USB-Blaster [2-1.2]
02B030DD 5CGTFD7(B5|C5|D5)/5CGXBC7B6/..
$ /opt/intelFPGA/17.0/quartus/bin/nios2-terminal
nios2-terminal: connected to hardware target using JTAG UART on cable
nios2-terminal: "USB-Blaster [2-1.2]", device 1, instance 0
nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)
PWB Revision 1 Boot Loader
Ver 2.0 Build 357 - Wed Jun 6 15:05:35 PDT 2018
...
</pre>

== Flash boot loader firmware via jtag ==

<pre>
$ ssh agmini@daq16
$ /opt/intelFPGA/16.1/quartus/bin/jtagconfig
1) USB-Blaster [2-1.2]
02B030DD 5CGTFD7(B5|C5|D5)/5CGXBC7B6/..
$ cd ~/online/firmware/pwb_rev1
$ ls -l
$ /opt/intelFPGA/17.1/quartus/bin/quartus_pgmw
... auto detect
... load the jic file
... in menu tools->programmer, enable "unprotect device"
... start program/configure operation
</pre>

== Flash user page firmware via esper-tool ==

<pre>
$ ssh agmini@daq16
$ cd online/src
$ more update_pwb.perl ### check that $fw is set to the desired firmware file
$ ./update_pwb.perl pwb06 ### or give more PWB names or give "all"
</pre>

== Build firmware ==

=== quartus version to use ===

* quartus 16.1 should be used for jtag (jtagconfig and jtagd)
* quartus 17.0 should be used to build the PWB firmware (17.1 is not compatible)

=== start license server ===

<pre>
ssh agmini@daq16
/opt/intelFPGA/17.0/quartus/linux64/lmgrd -c ~agmini/online/license-daq16.dat
</pre>

=== prepare the build environment ===

<pre>
$ ssh agmini@daq16
$ /opt/intelFPGA/17.0/nios2eds/nios2_command_shell.sh
</pre>

=== get latest version of the code and build it ===

<pre>
$ cd online/firmware/git/pwb_rev1_firmware
$ git pull
$ git checkout alphag
$ git pull
$ ./scripts/compile_project.sh
... about 30-40 minutes ...
$ ls -l bin/*.sof bin/*.jic bin/*.rpd
-rw-r--r-- 1 agmini alpha 12727389 Jan 24 2018 bin/feam_rev1_auto.rpd
-rw-r--r-- 1 agmini alpha 33554661 Jan 24 2018 bin/feam_rev1.jic
-rw-r--r-- 1 agmini alpha 6974754 Jan 24 2018 bin/rev1.sof
$ ### feam.jic is loaded via jtag
$ ### feam_auto.rpd is loaded via esper
$ ### feam.sof is used to attach the quartus signal tap logic analyzer
</pre>

=== firmware build order and sequence ===

* erase previous build
* regenerate qsys
* regenerate NIOS BSP "feam_bootloader_bsp" and "feam_bsp"
* build NIOS projects "feam_bootloader" and "feam"
* build quartus sof file (with the "feam_bootloader" nios project inside)
* build jic and rpd files (with the quartus sof file and the "feam" nios project inside)
* load sof file into the FPGA using jtag (be careful about compatible "feam" nios project already in the epcq flash)
* load jic file into the epcq factory page using jtag (cycle power for them to take effect)
* load rpd file into the epcq factory or user page using esper

=== scripts for building the firmware ===

* scripts/compile_project.sh - build everything from scratch:
* scripts/compile_qsys.sh - regenerate the main qsys component
* scripts/compile_nios.sh - regenerate the BSPs, then same as compile_elf.sh
* scripts/compile_elf.sh - build the BSPs, "feam_bootloader" and "feam" NIOS projects
* scripts/update_elf.sh - regenerate the rpd and jic files to include the new "feam" NIOS build (keeps the old "feam_bootloader" in the sof file)
* scripts/update_bootloader.sh - also regenerate the sof file to include the new "feam_bootloader" build
* scripts/clean_quartus.sh - prepare quartus fpga sof file to build from scratch
* scripts/compile_quartus.sh - build the quartus fpga sof file incrementally (run clean_quartus.sh to build from scratch).
* scripts/load_jtag_sof.pl bin/rev1.sof - load sof file into the FPGA. this will boot the new fpga firmware, the new feam_bootloader (if update_bootloader.sh was run), but with the old "feam" already in epcq flash. (beware of incompatible sof, "feam_bootloader" and "feam" builds!)
* scripts/load_jtag_jic.pl bin/feam_rev1.jic - load jic file into the EPCQ flash, same as using the graphical flash programmer tool. (this will leave the FPGA running the quartus jtag flash loader firmware, not the PWB firmware. Cycle power for new jic file to take effect).

== ESPER Variables ==

* Board
** invert_ext_trig - invert trigger signal from CDM before it drives any logic (to undo incorrect signal polarity)
** reset_nios - goggle up, them down to reset NIOS subsystem

* Signalproc
** test_mode - ADC data is replaced with a test pattern, see test mode bits in sca_x_ch_ctrl.
** sca_a_ch_ctrl, sca_b_ch_ctrl, sca_c_ch_ctrl, sca_d_ch_ctrl - channel control bits:
<pre>
11..0 - threshold - channel suppression threshold
14..12 - ctrl_test_mode - test mode:
0=fixed patter 0xa5a,
1=time bin counter,
2=time bin counter with channel number,
3=sequential adc sample counter,
4={ch_crossed_out,trig_pos,trig_neg,adc[8:0]},
5={trig,adc[10:0]},
6={ch_crossed_min,adc[10:0]}
15 - ctrl_supp_mode - channel suppression mode: 0=adc<=(baseline-threshold), 1=adc<=threshold
</pre>

* Link
** link_ctrl - sata link control. The bits are:
<pre>
0 - sata_link_udp_stream_in_enable - permit data flow from sata link to OFFLOAD_SATA
1 - udp_stream_out_enable - permit sca data flow to sata link
2 - sata_to_eth_enable - permit ethernet data flow from sata link to TSE_MAC
3 - eth_to_sata_enable - permit ethernet data flow from TSE MAC to sata link
4 - enable_stop_our_tx - enable flow control: allow stop_tx
#5 - stop_our_tx - manually activate the flow control signal into link_tx
6 - enable_stop_remote_tx - enable flow control: allow send "stop_tx"
#7 - stop_remote_tx - manually activate the flow control signal into link_tx
8 - tx_test_pattern_udp - udp data is replaced by test pattern 0x11111111, 0x22222222, etc.
9 - tx_test_pattern_eth - nios-to-sata data is replaced by test pattern 0x11111111, 0x22222222, etc.
10 - udp_delay_enable - delay between udp packets, see udp_delay_value below
11 - reboot_tx - send K_REBOOT command to the sata link mate, where it has same effect as board/reset_nios.
12 - sata_to_nios_disable
13 - nios_to_sata_disable
14 -
15 -
16 -
24..31 - udp_delay_value - delay between udp packets (top 8 bits of a 20-bit counter)
</pre>

== Firmware data path ==

Main data path:
<pre>
feam_top
|
sca_sigproc
|
sca_event_control
4 * sca_control (sca_channel.sv)
4 * channel_fifo (1024 samples)
</pre>
<pre>
sca_control (sca_channel.sv)
|
state machine to control SCA read and write enables
|
sca_write_control (what does it do?!?)
sca_read_control
</pre>
<pre>
sca_read_control
|
state machine to store ADC samples into per-channel FIFOs (channel_fifo)
selector to replace ADC samples with a test pattern
79*sca_trig_one -> ch_crossed_out - channel hit detector
</pre>
<pre>
sca_event_control
|
event_fifo (hdl/mf/event_descriptor_fifo)
state machine to take ADC data from 4 per-channel FIFOs (channel_fifo) and store it into DDR memory (write addr increment is 510*8 (number of samples)*8 = 4080).
state machine to read transposed ADC data from DDR memory (read addr increment is 8+8=16 - 2 samples * 2 bytes * 4 sca = 16) and create 4 per-sca data streams
</pre>
<pre>
data stream:
4 per-sca data streams from sca_event_control -> sca_sigproc(event_dat)
|
packet_chunker (hdl/lib/packet_chunker.sv) (4*event_dat -> event_segment_dat) - multiplex 4 data streams into 1 stream of UDP-sized packets
|
packet_length_prepender (hdl/lib/packet_length_prepender.sv) (event_segment_dat -> udp_event_val_out)
|
udp_event_val -> info qsys (udp_stream_sca) and into sata link (mux channel 2).
</pre>

== Firmware build instructions from Bryerton (obsolete) ==

This is the old README.md file from the firmware git repository.

These instructions are not used to build the firmware (use scrips/compile_project.sh).

They are still useful for figuring out which buttons to push in the altera gui programs.

<pre>
# ALPHAg FrontEnd Acquisition Module (FEAM) - REV0

Welcome to the ALPHAg FEAM Project

# Table of Contents

* [Overview](#overview)
* [Inital Setup](#initial-setup)
* [Quartus Setup](#quartus-setup)
* [Create the .cdf](#create-the-cdf)
* [NIOS Setup](#nios-Setup)
* [Create the project files](#create-the-project-files)
* [Build Instructions](#build-instructions)
* [Building from Quartus GUI](#building-from-quartus-gui)
* [Generate the QSys File](#generate-the-qsys-file)
* [Compile the NIOSII Project](#compile-the-niosii-project)
* [Compile the Quartus Project](#compile-the-quartus-project)
* [Building from Scripts](#building-from-scripts)
* [Installing from JTAG](#installing-from-jtag)
* [Installing from ESPER](#installing-from-esper)

# Overview

The FEAM is a digitizer located on the ALPHAg detector. Each FEAM consists of 4 AFTER SCAs for a total of 288 channels.

# Initial Setup

## Quartus Setup

### Create the .cdf
1. Open Quartus Prime Standard Edition
2. Click on **Tools -> Programmer**. The **Programmer** window will appear
3. In the **Programmer** window, click **Auto Detect**. A **Select Device** dialog box will appear
1. (Optional) If **Auto Detect** is greyed out, click on **Hardware Setup**. The **Hardware Setup** dialog box will appear
2. Under **Hardware Settings**, double-click on the USB JTAG hardware you wish to use
3. Click **Close**. The **Hardware Setup** dialog box will close
5. Click on **File -> Save As**. The **Save As** dialog box will appear
6. In the **Save As** dialog box, browse to the **/\<project_dir\>/bin/** directory
7. Make sure the **Add file to current project** checkbox is checked
7. In the **File name** input box, type "alphag_feam.cdf" and click **Save**
8. Close the **Programmer** window
9. Done!

## NIOS Setup

### Create the project files
1. Open Quartus Prime Standard Edition
2. Open the NIOS II Software Build Tools by clicking **Tools -> NIOS II Software Build Tools for Eclipse**
3. The **Workspace Launcher** window will appear, click *OK* to accept the default workspace.
4. Click **File -> Import...**. The **Import** dialog box will appear
5. Click on **General -> Existing Projects into Workspace**
6. Click **Next \>**
7. Next to **Select root directory** click **Browse...**. A **Browse for Folder** dialog box will appear
8. Browse to **/\<project_dir\>/hdl/software** and click **OK**
8. Four Projects should appear in the **Projects** panel:
* alphag_feam
* alphag\_feam\_bsp
* alphag\_feam\_bootloader
* alphag\_feam\_bootloader\_bsp
9. Click **Select All**
10. Click **Finish**
11. Done!

# Build Instructions

## Building from Quartus GUI

**Warning: Please use Quartus Prime Standard Edition 16.1**
### Generate the QSys File
1. Open Quartus Standard Edition 16.1
1. Open QSys by clicking **Tools -> QSys**
2. Click on **File -> Open** (CTRL+O). An **Open File** dialog box should appear.
3. Select the **alphag_feam.qsys** file from the **/\<project_dir\>/hdl** directory and click **Open**
4. Modify as necessary. NOTE: Any change to the QSys, even cosmetic such as expanding or collapsing components will cause the QSys to desire a re-generate.
5. Click **File -> Save** (CTRL+S)
6. Click **Generate HDL**. A **Generation** dialog box will appear
7. Select the settings you desire to be changed, if any
8. Click **Generate**
9. Wait for the generation to complete.
10. Done!

### Compile the NIOSII Project
1. Open the NIOS II Software Build Tools by clicking **Tools -> NIOS II Software Build Tools for Eclipse**
2. (Optional) If the QSys file has been re-generated performing the following
1. Right-click on **alphag\_feam\_bsp** and select **NIOS II -> Generate BSP**. The BSP will regenerate
2. Right-click on **alphag\_feam\_bootloader\_bsp** and select **NIOS II -> Generate BSP**. The BSP will regenerate
3. Modify files as needed. WARNING: Do not modify any BSP files by hand! All changes will be lost on next generate.
4. Click **Project -> Build All** (CTRL+B). If your workspace as multiple projects, it is recommend to close all but the ones related to the FEAM.
5. Right-click on **alphag\_feam\_bootloader** and select **Make Targets -> Build...**. The **Make Targets** dialog box will appear
6. In the **Make Targets** dialog box, select **mem\_init\_generate** and click **Build**
7. Done!

### Compile the Quartus Project
1. Open Quartus Standard Edition 16.1
1. Under **Processing** click **Start Compilation** (CTRL+L)
2. Wait about 16-30 minutes.
3. Done!

**Note:** If Quartus crashed while compiling, delete the **\<project_dir\>/hdl/db** and **\<project_dir\>/hdl/incremental_db** directories and try again

## Installing from JTAG
1. Generate the .jic file using the provided /bin/alphag\_feam\_jic.cof
1. In the main Quartus window, click **File -> Convert Programming Files**, A **Convert Programming Files** window will appear
2. In the **Convert Programming Files** window, click **Open Conversion Setup Data**. An **Open** dialog box will appear
3. In the **Open** dialog box, select the **alphag_feam.cof** file located in **/bin/**
4. Click **Open**. The **Open dialog box will close
* Note the **File name** field, it should display /\<project\_dir\>/bin/alphag\_feam.jic
5. In the **Convert Programming Files** window, click **Generate**
6. When the .jic is done being generated, a small dialog box will appear, click **OK**
7. In the **Convert Programming Files** window, click **Close**
2. Load the .JIC file using the Programmer
1. In the main Quartus window in the **Project Navigator** drop-down input select **Files**.
2. Scroll down the window and find the **alphag_feam.cdf**, and double-click it. The **Programmer** window will open
3. Click on the icon labelled **5CGXFC4C6**
4. Click on the **Change File** button. The **Select New Programming File** dialog box will appear
5. Browse to **/\<project_dir\>/bin/** and select **alphag\_feam.jic**
6. Click Open. The **Select New Programming File** dialog box will close
7. In the main panel, check the **Program/Configure** box on the line that starts **./bin/alphag\_feam.jic**
8. Click the **Start** button
9. Wait for the **Progress** bar to go to 100% and stop
10. Done!
</pre>

= Internal test pulser =

Documentation from Bryerton:

<pre>
---------- Forwarded message ---------
From: Bryerton Shaw <bryerton@triumf.ca>
Date: Tue, 24 Apr 2018 at 16:18
Subject: RE: PWB/FEAM internal test pulse
To: Lars Martin <lmartin@triumf.ca>
Cc: Andrea Capra <acapra@triumf.ca>

Hi Lars (and Andrea),

In the new(er) firmware the test pulse code has been modified slightly to
fit in better with the upgraded trigger system. I can add an option to
allow it to be triggered by the external trigger (currently it has an
interval option, or you can hit the manual trigger to fire it, if it’s
enabled)

The *options for the test pulser* are under the *signalproc module*:

*test_pulse_ena*

An array of four booleans, that control turning on the test pulse for each
SCA. If this is False, the other options below will do nothings for that SCA

*test_pulse_interval_ena*

An array of four booleans, that control turning on the interval trigger for
each SCA

*test_pulse_interval*

An unsigned 32-bit value that marks how many 16ns clock cycles occur
between interval triggers. Only one value, as there is only one interval
timer.

*test_pulse_wdt*

An array of four 16-bit unsigned integers that control the width of the
pulse for each SCA when the trigger occurs.

Now, there is a second set of options to control the delay of the *test
pulse interval trigger*. These options are located under the *trigger
module*

*intp_trig_ena*

Boolean value enabling/disabling the interval test pulse trigger.

*intp_trig_delay*

Unsigned 32-bit integer controlling the trigger delay, which is the time
between when the trigger is requested, and when the trigger actually fires.

You can setup the interval trigger and use that to create event packets
with the test pulse on set intervals. If the interval trigger is
insufficient, I can create another option, which is to fire the test pulse
for enabled SCAs when the external trigger goes. If so, I’ll add this
option in the *signalproc *module for you:

*test_pulse_on_ext*

An array of four Booleans, that control if the test pulse for that SCA
fires on external trigger.

Remember, in order to use the SCA test pulse at all, you must also set the
SCA to test mode. You can do this by going into the *sca0-3 modules* and
setting *test* to *functionality *(the value is *3* if you want to set it
via esper-tool)

Btw currently the SCAs are hard-coded to have all 72 channels receive the
test pulse on firing, and the option to de-select/select which channels to
fire is not offered. Would you like this ability? And if so do you want it
to set all four SCAs the same, or have an option for all 288 channels?

The waveform viewer on the webpage was removed for technical reasons, and
so all viewing is done via the MIDAS DAQ. There are some preliminary tools
I’ve created to verify the event packets and their waveforms, but I
wouldn’t call them easy to setup or use at the moment. (Or very useful for
fine comparisons). If KO doesn’t have a way of saving the events to disk, I
could deliver something that captured and saved waveforms quite quickly.

Regards,
Bryerton

*From:* Lars Martin
*Sent:* April 23, 2018 5:10 PM
*To:* Bryerton Shaw <bryerton@triumf.ca>
*Cc:* Andrea Capra <acapra@triumf.ca>
*Subject:* PWB/FEAM internal test pulse

Hi Bryerton,

Andrea and I would like to check the response function of the PWBs. For
that Daryl suggested to first look at the internal test pulse.

Can you point us to what settings are required to make that go? And to use
the external trigger if we want to acquire the data?

Ideally we would acquire Midas data from that, but it's unclear if KO's
frontend allows for that right now. Can we access the data with Esper
instead?

Finally, we haven't had the waveform display on the web page for a while,
but Daryl said you guys use it. Are we using a different page somehow?

Hope all is well with the baby, cheers,

Lars
</pre>

= TODO =

* IMPOSSIBLE (ext clock only connected to clock cleaner) add frequency counter for the external clock (62.5 MHz)
* DONE add random delay before memtest
* DONE add 4 more bits to udp_delay
* DONE fix crash on boot if run is active and triggers arrive (check that trigger is off on boot) (do not set trigger/enable_all, ext_trig_ena, inp_trig_ena, signal_proc/force_run to 1 after boot)
* DONE (kludge jtag uart write()) increase size of jtag uart output buffer, make it unlimited if possible.
* DONE (kludge jtag uart write()) on dhcp timeout, reboot the fpga - reboot of nios does not clear the jtag uart, which becomes full and nios stops.
* DONE add NIOS watchdog timeout for fectrl
* DONE do not use external clock until instructed by fectrl (clock cleaner default is pin select mode, default pin mode is input with pull down, so clock 0 is selected, this is the ext clock. but we can drive clock select pins from the fpga).
* DONE change clock cleaner power up: use the 2 lines status_clkin0 and status_clkin1 to tell clock cleaner to use the internal clock (clkin2) - from the FPGA drive first line low, second line high. Also change all NIOS code that programs the clock cleaner to keep these two lines in the "input" mode. Current code switches them to "output" mode.
* DONE clock cleaner power up state is wrong for both choices of clock: 62.5 MHz ext clock and 125 MHz internal clock, see explanation in feam_top.sv. It looks like I need to drive status_clkin0 and status_clkin1 to "holdover" mode, both logic level 1. Currently status_clkin0 is used as SPI read line, this has to be moved to a different line first.
* add watchdog timeout that works in factory mode ("remote update" watchdog only works in user mode)
* enable HTTP pipelining - copy changes on mongoose from ADC project.
* reset everything if it looks like NIOS TCP/IP code has crashed, but enough code is still running to prevent tripping of the fpga-remote-update watchdog timer. such crash tends to happens when the sata link mate is rebooted and incomplete data arrives from the disrupted ethernet data path.
* DONE when loading AFTER ASIC do not go into infinite loop if read-back is broken (always mismatch).
* DONE read and report error status information bits for 2983fc.pdf voltages, currents and temperatures monitoring chip. note that SCA12, SCA34, 2V and 5V voltages are flagged 0x0B "ADC out of range, sensor over range" correctly, see 2983fc.pdf table 63 fix explanation of "normal" and "usable" voltage ranges. (5V voltage divider is 2-to-1)
* add provisions for coded trigger
* DONE verify readout of MV2 Hall magnetometer (all registers and bits from device are visible in esper)

= ZZZ =

ZZZ

PWB

2023-03-22T20:56:10Z

Olchansk: /* TODO */

= Links =

* https://bitbucket.org/expalpha/pwb_rev1_firmware
* https://edev-group.triumf.ca/fw/exp/alphag/feam/rev1
* https://edev-group.triumf.ca/hw/alphag/feam/rev1
* https://ladd00.triumf.ca/daqinv/frontend/list/170 - PWB inventory database

= Schematics =

* [[Image:pwb_rev0.pdf]]
* [[Image:Pwb-rev1-after.pdf]]
* [[Image:AlphaG Rev1.pdf]]

= Manuals =

* [[Image:AFTER_MANUAL_V1.pdf]] AFTER SCA manual v1
* [[Image:AFTER_DataSheet1_1.pdf]] AFTER SCA manual v1.1
* [[Image:AFTER_SCA_table2.pdf]] AFTER SCA channel map

= Hardware =

== Power distribution and monitoring ==

External power supply is:
* +5V
* +2V

Central board:

* Ext_5V - F1 - RS1 (0.1R) - Fuse_5V
* Ext_2V - F2/F3 - RS2 (0.1R) - Idig2-
* LDO3 - Fuse_5V - DIG_3.3V - selfenable - ADM7154
* LDO5 - Fuse_5V - DIG_2.5V - selfenable - ADM7154
* LDO_CLN - Fuse5V - CLN_3.3V - selfenable -
* VREG - DIG_3.3V - -2.5V SCA BIAS - selfenable - LTC1983ES6-3#TRMPBF
* LDO7 - DIG_2.5V - DDR3_VRef - enable DDR3_1P5V, DDR3_PG, DDR3_VttEN
* LDO2 - Idig2V- - DIG_1.1V - enable DIG_3.3V - LT3071
* LDO6 - Idig2V- - DDR3_1P5V - enable DIG_3.3V - LT3083

SCA Wing:

* Ext_5V - F1 - RS1 (0.3R) - Isca- - SCA_Fuse5V
* LDO1 - SCA_Fuse5V - SCA3.3V - enable ADC_PWR_EN - ADM7154
* LDO2 - SCA3.3V - ADC1.8V - selfenable - ADM7154
* LDO3 - SCA3.3V - TRN2.5V - selfenable - LT1761
* REF - SCA3.3V - 1.45V Vicm - selfenable - LM4121

esper variables:

* board/i_sca12, i_sca34, v_sca12, v_sca34: voltage and current into LDO1, after fuse F1 (wing board)
* board/i_p2, v_p2: voltage and current on 2V bus after fuses F2/F3
* board/i_p5, v_p5: voltage and current on 5V bus after fuse F1 (central board)

== Trigger and Clock distribution ==

Clock (62.5MHz) and trigger are distributed to the PWB columns via the [https://edev-group.triumf.ca/hw/alphag/trigger-card-sata-adapter/rev1 trigger SATA adapter].

The two miniSAS cables from cdm03 port 5 and 6 are connected to a miniSAS-SATA splitter 1-to-4 (CS Electronics "iSAS SATA adapter" ADP-887P-1X). Since there are only 8 columns and the clock and trigger signals are daisy-chained across the 8 rows, this scheme is sufficient to provide the necessary inputs to all 64 PWBs.

[https://www.techcable.com/sas-mini-sas-cables/sata-cables/ SATA 6Gb/s Cable with Latching Clip. Straight Pinout 1-1 247726-L 40in]

== Optical Link ==

Main data uplink.

SFP (Small Form Pluggable) Avago Technologies AFBR-57M5APZ [[File:AVAGO SFP specs.pdf|SFP (Small Form Pluggable) Avago Technologies AFBR-57M5APZ]]

Fiber optic Tripp Lite N820 - 10 m [[File:FiberOptic TrippLite specs.pdf|Fiber optic Tripp Lite N820 - 10 m]]

== SATA Link ==

Secondary data uplink, capable also to deliver clock and trigger.

The SATA link connects PWB from adjacent columuns on the same row.

The SATA cable is a "crossed cable".

= Firmware =

== Firmware update ==

PWB firmware update is done using "esper-tool".

<pre>
esper-tool -v upload -f file.rpd http://pwbNN update factory_rpd
esper-tool -v upload -f file.rpd http://pwbNN update file_rpd
</pre>

As of PWB firmware pwb_rev1_20200706_ko:

Permission to write into the flash memory is controlled by esper variables:

* allow_write set to "false": "esper-tool upload" does a "verify": successful upload means epcq flash content is same as rpd file, error means content is not the same.
* allow_write set to "true": "esper-tool upload" updates the epcq flash from the rpd file: for each data block, read the epcq flash, compare to rpd data, if different, erase the flash block, write the flash, read the flash, if there is a mismatch (bad write), return an error.
* allow_factory_write set to "true" to enable writing to the "factory_rpd". DO NOT SET IT TO "true" UNLESS YOU MEAN TO UPDATE THE PWB BOOTLOADER. IF YOU FLASH BUM FIRMWARE or IF THERE IS A POWER OUTAGE WHILE UPDATING, THE PWB WILL BE BRICKED and has to be recovered by connecting a USB blaster.

To update firmware of multiple boards to correct version, recommended is the script "update_pwb.perl":
<pre>
cd ~/online/src
./update_pwb.perl pwb12 pwb06 pwb78
</pre>

== Factory page and user page firmware boot ==

Each PWB board has 2 firmware images: boot loader (factory page)
and data acquisition (user page). On power up, the FPGA loads and runs
the boot loader firmware from the factory page, later the control
software reboots the FPGA into the data acquisition firmware from
the user page.

Because loading defective firmware can brick https://en.wikipedia.org/wiki/Brick_(electronics)
the PWB, new firmware images are loaded into the user page, if anything is wrong,
the PWB can still boot from the factory page and one can use the firmware update
function to load a good firmware image into the user page.

The boot loader firmware in the factory page is not intended for data acquisition, it is only meant to provide three functions:
* boot enough hardware and software to communicate via the ethernet and the sata link
* firmware update (both factory page and user page)
* reboot into the user page

The boot loader firmware in the factory page is usually never updated unless absolutely
needed to fix a problem with these three functions (i.e. compatibility with sata link communications).

If factory image is corrupted or the contains defective firmware and the PWB does not boot (no dhcp, no ping, no esper),
the only way to unbrick it is by loading good firmware using a jtag flash programmer (usb-blaster). Connecting it requires
physical access to the jtag connector on the PWB board. It is impossible when the detector is fully assembled in the experiment.

The PWB has a 32 Mbyte EPCQ flash memory chip, it is divided into 2 pages 16 Mbytes of factory page and 16 Mbytes of user page.

A complete firmware image generally contains 3 pieces:
* FPGA firmware and NIOS "feam_bootloader" software RAM image (sof file)
* NIOS "feam" software RAM image (feam.elf.flash.hex) - all the C code for esper communications and PWB data acquisition
* NIOS filesystem image (feam.webpkg.hex) - esper web pages

This is the boot sequence:
* on power-up the FPGA automatically loads the sof file from address 0 of the EPCQ flash (this is the factory image sof file)
* the FPGA is "started"
* the NIOS CPU starts executing the "feam_bootloader" C code embedded in the sof file (NIOS project hdl/software/feam_bootloader)
* feam_bootloader initializes the hardware (clocks, DDR memory, etc)
* feam_bootloader write-protects the EPCQ flash memory
* feam_bootloader copies the "feam" software from EPCQ flash to the DDR memory (after checking for correct checkum)
* feam_bootloader restarts the NIOS CPU
* the NIOS CPU starts running from DDR memory, executes the "feam" software (NIOS project hdl/software/feam)
* call main() in hdl/software/feam/src/task_init.c
* call task_init() in the same file
* infinite loop waiting for IP address via DHCP
* after have IP address, call task_esper() from hdl/software/feam/src/task_esper.c
* task_esper() creates all the esper modules, esper variables, etc,
* mod_http.c starts the mongoose web server
* PWB is open for business

This is the protection against booting corrupted firmware:
* FPGA hardware loads the sof file from epcq flash and checks for correct checksum before "starting" it
* NIOS CPU is part of the sof file, protected by sof file checksum
* NIOS feam_bootloader C code is part of the sof file, protected by the sof checksum
* feam_bootloader checks for correct signatures and checksums of the DDR memory image
* "feam" C code is protected by the checksum of the DDR memory image

== NIOS terminal ==

<pre>
$ ssh agmini@daq16
$ /opt/intelFPGA/16.1/quartus/bin/jtagconfig
1) USB-Blaster [2-1.2]
02B030DD 5CGTFD7(B5|C5|D5)/5CGXBC7B6/..
$ /opt/intelFPGA/17.0/quartus/bin/nios2-terminal
nios2-terminal: connected to hardware target using JTAG UART on cable
nios2-terminal: "USB-Blaster [2-1.2]", device 1, instance 0
nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)
PWB Revision 1 Boot Loader
Ver 2.0 Build 357 - Wed Jun 6 15:05:35 PDT 2018
...
</pre>

== Flash boot loader firmware via jtag ==

<pre>
$ ssh agmini@daq16
$ /opt/intelFPGA/16.1/quartus/bin/jtagconfig
1) USB-Blaster [2-1.2]
02B030DD 5CGTFD7(B5|C5|D5)/5CGXBC7B6/..
$ cd ~/online/firmware/pwb_rev1
$ ls -l
$ /opt/intelFPGA/17.1/quartus/bin/quartus_pgmw
... auto detect
... load the jic file
... in menu tools->programmer, enable "unprotect device"
... start program/configure operation
</pre>

== Flash user page firmware via esper-tool ==

<pre>
$ ssh agmini@daq16
$ cd online/src
$ more update_pwb.perl ### check that $fw is set to the desired firmware file
$ ./update_pwb.perl pwb06 ### or give more PWB names or give "all"
</pre>

== Build firmware ==

=== quartus version to use ===

* quartus 16.1 should be used for jtag (jtagconfig and jtagd)
* quartus 17.0 should be used to build the PWB firmware (17.1 is not compatible)

=== start license server ===

<pre>
ssh agmini@daq16
/opt/intelFPGA/17.0/quartus/linux64/lmgrd -c ~agmini/online/license-daq16.dat
</pre>

=== prepare the build environment ===

<pre>
$ ssh agmini@daq16
$ /opt/intelFPGA/17.0/nios2eds/nios2_command_shell.sh
</pre>

=== get latest version of the code and build it ===

<pre>
$ cd online/firmware/git/pwb_rev1_firmware
$ git pull
$ git checkout alphag
$ git pull
$ ./scripts/compile_project.sh
... about 30-40 minutes ...
$ ls -l bin/*.sof bin/*.jic bin/*.rpd
-rw-r--r-- 1 agmini alpha 12727389 Jan 24 2018 bin/feam_rev1_auto.rpd
-rw-r--r-- 1 agmini alpha 33554661 Jan 24 2018 bin/feam_rev1.jic
-rw-r--r-- 1 agmini alpha 6974754 Jan 24 2018 bin/rev1.sof
$ ### feam.jic is loaded via jtag
$ ### feam_auto.rpd is loaded via esper
$ ### feam.sof is used to attach the quartus signal tap logic analyzer
</pre>

=== firmware build order and sequence ===

* erase previous build
* regenerate qsys
* regenerate NIOS BSP "feam_bootloader_bsp" and "feam_bsp"
* build NIOS projects "feam_bootloader" and "feam"
* build quartus sof file (with the "feam_bootloader" nios project inside)
* build jic and rpd files (with the quartus sof file and the "feam" nios project inside)
* load sof file into the FPGA using jtag (be careful about compatible "feam" nios project already in the epcq flash)
* load jic file into the epcq factory page using jtag (cycle power for them to take effect)
* load rpd file into the epcq factory or user page using esper

=== scripts for building the firmware ===

* scripts/compile_project.sh - build everything from scratch:
* scripts/compile_qsys.sh - regenerate the main qsys component
* scripts/compile_nios.sh - regenerate the BSPs, then same as compile_elf.sh
* scripts/compile_elf.sh - build the BSPs, "feam_bootloader" and "feam" NIOS projects
* scripts/update_elf.sh - regenerate the rpd and jic files to include the new "feam" NIOS build (keeps the old "feam_bootloader" in the sof file)
* scripts/update_bootloader.sh - also regenerate the sof file to include the new "feam_bootloader" build
* scripts/clean_quartus.sh - prepare quartus fpga sof file to build from scratch
* scripts/compile_quartus.sh - build the quartus fpga sof file incrementally (run clean_quartus.sh to build from scratch).
* scripts/load_jtag_sof.pl bin/rev1.sof - load sof file into the FPGA. this will boot the new fpga firmware, the new feam_bootloader (if update_bootloader.sh was run), but with the old "feam" already in epcq flash. (beware of incompatible sof, "feam_bootloader" and "feam" builds!)
* scripts/load_jtag_jic.pl bin/feam_rev1.jic - load jic file into the EPCQ flash, same as using the graphical flash programmer tool. (this will leave the FPGA running the quartus jtag flash loader firmware, not the PWB firmware. Cycle power for new jic file to take effect).

== ESPER Variables ==

* Board
** invert_ext_trig - invert trigger signal from CDM before it drives any logic (to undo incorrect signal polarity)
** reset_nios - goggle up, them down to reset NIOS subsystem

* Signalproc
** test_mode - ADC data is replaced with a test pattern, see test mode bits in sca_x_ch_ctrl.
** sca_a_ch_ctrl, sca_b_ch_ctrl, sca_c_ch_ctrl, sca_d_ch_ctrl - channel control bits:
<pre>
11..0 - threshold - channel suppression threshold
14..12 - ctrl_test_mode - test mode:
0=fixed patter 0xa5a,
1=time bin counter,
2=time bin counter with channel number,
3=sequential adc sample counter,
4={ch_crossed_out,trig_pos,trig_neg,adc[8:0]},
5={trig,adc[10:0]},
6={ch_crossed_min,adc[10:0]}
15 - ctrl_supp_mode - channel suppression mode: 0=adc<=(baseline-threshold), 1=adc<=threshold
</pre>

* Link
** link_ctrl - sata link control. The bits are:
<pre>
0 - sata_link_udp_stream_in_enable - permit data flow from sata link to OFFLOAD_SATA
1 - udp_stream_out_enable - permit sca data flow to sata link
2 - sata_to_eth_enable - permit ethernet data flow from sata link to TSE_MAC
3 - eth_to_sata_enable - permit ethernet data flow from TSE MAC to sata link
4 - enable_stop_our_tx - enable flow control: allow stop_tx
#5 - stop_our_tx - manually activate the flow control signal into link_tx
6 - enable_stop_remote_tx - enable flow control: allow send "stop_tx"
#7 - stop_remote_tx - manually activate the flow control signal into link_tx
8 - tx_test_pattern_udp - udp data is replaced by test pattern 0x11111111, 0x22222222, etc.
9 - tx_test_pattern_eth - nios-to-sata data is replaced by test pattern 0x11111111, 0x22222222, etc.
10 - udp_delay_enable - delay between udp packets, see udp_delay_value below
11 - reboot_tx - send K_REBOOT command to the sata link mate, where it has same effect as board/reset_nios.
12 - sata_to_nios_disable
13 - nios_to_sata_disable
14 -
15 -
16 -
24..31 - udp_delay_value - delay between udp packets (top 8 bits of a 20-bit counter)
</pre>

== Firmware data path ==

Main data path:
<pre>
feam_top
|
sca_sigproc
|
sca_event_control
4 * sca_control (sca_channel.sv)
4 * channel_fifo (1024 samples)
</pre>
<pre>
sca_control (sca_channel.sv)
|
state machine to control SCA read and write enables
|
sca_write_control (what does it do?!?)
sca_read_control
</pre>
<pre>
sca_read_control
|
state machine to store ADC samples into per-channel FIFOs (channel_fifo)
selector to replace ADC samples with a test pattern
79*sca_trig_one -> ch_crossed_out - channel hit detector
</pre>
<pre>
sca_event_control
|
event_fifo (hdl/mf/event_descriptor_fifo)
state machine to take ADC data from 4 per-channel FIFOs (channel_fifo) and store it into DDR memory (write addr increment is 510*8 (number of samples)*8 = 4080).
state machine to read transposed ADC data from DDR memory (read addr increment is 8+8=16 - 2 samples * 2 bytes * 4 sca = 16) and create 4 per-sca data streams
</pre>
<pre>
data stream:
4 per-sca data streams from sca_event_control -> sca_sigproc(event_dat)
|
packet_chunker (hdl/lib/packet_chunker.sv) (4*event_dat -> event_segment_dat) - multiplex 4 data streams into 1 stream of UDP-sized packets
|
packet_length_prepender (hdl/lib/packet_length_prepender.sv) (event_segment_dat -> udp_event_val_out)
|
udp_event_val -> info qsys (udp_stream_sca) and into sata link (mux channel 2).
</pre>

== Firmware build instructions from Bryerton (obsolete) ==

This is the old README.md file from the firmware git repository.

These instructions are not used to build the firmware (use scrips/compile_project.sh).

They are still useful for figuring out which buttons to push in the altera gui programs.

<pre>
# ALPHAg FrontEnd Acquisition Module (FEAM) - REV0

Welcome to the ALPHAg FEAM Project

# Table of Contents

* [Overview](#overview)
* [Inital Setup](#initial-setup)
* [Quartus Setup](#quartus-setup)
* [Create the .cdf](#create-the-cdf)
* [NIOS Setup](#nios-Setup)
* [Create the project files](#create-the-project-files)
* [Build Instructions](#build-instructions)
* [Building from Quartus GUI](#building-from-quartus-gui)
* [Generate the QSys File](#generate-the-qsys-file)
* [Compile the NIOSII Project](#compile-the-niosii-project)
* [Compile the Quartus Project](#compile-the-quartus-project)
* [Building from Scripts](#building-from-scripts)
* [Installing from JTAG](#installing-from-jtag)
* [Installing from ESPER](#installing-from-esper)

# Overview

The FEAM is a digitizer located on the ALPHAg detector. Each FEAM consists of 4 AFTER SCAs for a total of 288 channels.

# Initial Setup

## Quartus Setup

### Create the .cdf
1. Open Quartus Prime Standard Edition
2. Click on **Tools -> Programmer**. The **Programmer** window will appear
3. In the **Programmer** window, click **Auto Detect**. A **Select Device** dialog box will appear
1. (Optional) If **Auto Detect** is greyed out, click on **Hardware Setup**. The **Hardware Setup** dialog box will appear
2. Under **Hardware Settings**, double-click on the USB JTAG hardware you wish to use
3. Click **Close**. The **Hardware Setup** dialog box will close
5. Click on **File -> Save As**. The **Save As** dialog box will appear
6. In the **Save As** dialog box, browse to the **/\<project_dir\>/bin/** directory
7. Make sure the **Add file to current project** checkbox is checked
7. In the **File name** input box, type "alphag_feam.cdf" and click **Save**
8. Close the **Programmer** window
9. Done!

## NIOS Setup

### Create the project files
1. Open Quartus Prime Standard Edition
2. Open the NIOS II Software Build Tools by clicking **Tools -> NIOS II Software Build Tools for Eclipse**
3. The **Workspace Launcher** window will appear, click *OK* to accept the default workspace.
4. Click **File -> Import...**. The **Import** dialog box will appear
5. Click on **General -> Existing Projects into Workspace**
6. Click **Next \>**
7. Next to **Select root directory** click **Browse...**. A **Browse for Folder** dialog box will appear
8. Browse to **/\<project_dir\>/hdl/software** and click **OK**
8. Four Projects should appear in the **Projects** panel:
* alphag_feam
* alphag\_feam\_bsp
* alphag\_feam\_bootloader
* alphag\_feam\_bootloader\_bsp
9. Click **Select All**
10. Click **Finish**
11. Done!

# Build Instructions

## Building from Quartus GUI

**Warning: Please use Quartus Prime Standard Edition 16.1**
### Generate the QSys File
1. Open Quartus Standard Edition 16.1
1. Open QSys by clicking **Tools -> QSys**
2. Click on **File -> Open** (CTRL+O). An **Open File** dialog box should appear.
3. Select the **alphag_feam.qsys** file from the **/\<project_dir\>/hdl** directory and click **Open**
4. Modify as necessary. NOTE: Any change to the QSys, even cosmetic such as expanding or collapsing components will cause the QSys to desire a re-generate.
5. Click **File -> Save** (CTRL+S)
6. Click **Generate HDL**. A **Generation** dialog box will appear
7. Select the settings you desire to be changed, if any
8. Click **Generate**
9. Wait for the generation to complete.
10. Done!

### Compile the NIOSII Project
1. Open the NIOS II Software Build Tools by clicking **Tools -> NIOS II Software Build Tools for Eclipse**
2. (Optional) If the QSys file has been re-generated performing the following
1. Right-click on **alphag\_feam\_bsp** and select **NIOS II -> Generate BSP**. The BSP will regenerate
2. Right-click on **alphag\_feam\_bootloader\_bsp** and select **NIOS II -> Generate BSP**. The BSP will regenerate
3. Modify files as needed. WARNING: Do not modify any BSP files by hand! All changes will be lost on next generate.
4. Click **Project -> Build All** (CTRL+B). If your workspace as multiple projects, it is recommend to close all but the ones related to the FEAM.
5. Right-click on **alphag\_feam\_bootloader** and select **Make Targets -> Build...**. The **Make Targets** dialog box will appear
6. In the **Make Targets** dialog box, select **mem\_init\_generate** and click **Build**
7. Done!

### Compile the Quartus Project
1. Open Quartus Standard Edition 16.1
1. Under **Processing** click **Start Compilation** (CTRL+L)
2. Wait about 16-30 minutes.
3. Done!

**Note:** If Quartus crashed while compiling, delete the **\<project_dir\>/hdl/db** and **\<project_dir\>/hdl/incremental_db** directories and try again

## Installing from JTAG
1. Generate the .jic file using the provided /bin/alphag\_feam\_jic.cof
1. In the main Quartus window, click **File -> Convert Programming Files**, A **Convert Programming Files** window will appear
2. In the **Convert Programming Files** window, click **Open Conversion Setup Data**. An **Open** dialog box will appear
3. In the **Open** dialog box, select the **alphag_feam.cof** file located in **/bin/**
4. Click **Open**. The **Open dialog box will close
* Note the **File name** field, it should display /\<project\_dir\>/bin/alphag\_feam.jic
5. In the **Convert Programming Files** window, click **Generate**
6. When the .jic is done being generated, a small dialog box will appear, click **OK**
7. In the **Convert Programming Files** window, click **Close**
2. Load the .JIC file using the Programmer
1. In the main Quartus window in the **Project Navigator** drop-down input select **Files**.
2. Scroll down the window and find the **alphag_feam.cdf**, and double-click it. The **Programmer** window will open
3. Click on the icon labelled **5CGXFC4C6**
4. Click on the **Change File** button. The **Select New Programming File** dialog box will appear
5. Browse to **/\<project_dir\>/bin/** and select **alphag\_feam.jic**
6. Click Open. The **Select New Programming File** dialog box will close
7. In the main panel, check the **Program/Configure** box on the line that starts **./bin/alphag\_feam.jic**
8. Click the **Start** button
9. Wait for the **Progress** bar to go to 100% and stop
10. Done!
</pre>

= Internal test pulser =

Documentation from Bryerton:

<pre>
---------- Forwarded message ---------
From: Bryerton Shaw <bryerton@triumf.ca>
Date: Tue, 24 Apr 2018 at 16:18
Subject: RE: PWB/FEAM internal test pulse
To: Lars Martin <lmartin@triumf.ca>
Cc: Andrea Capra <acapra@triumf.ca>

Hi Lars (and Andrea),

In the new(er) firmware the test pulse code has been modified slightly to
fit in better with the upgraded trigger system. I can add an option to
allow it to be triggered by the external trigger (currently it has an
interval option, or you can hit the manual trigger to fire it, if it’s
enabled)

The *options for the test pulser* are under the *signalproc module*:

*test_pulse_ena*

An array of four booleans, that control turning on the test pulse for each
SCA. If this is False, the other options below will do nothings for that SCA

*test_pulse_interval_ena*

An array of four booleans, that control turning on the interval trigger for
each SCA

*test_pulse_interval*

An unsigned 32-bit value that marks how many 16ns clock cycles occur
between interval triggers. Only one value, as there is only one interval
timer.

*test_pulse_wdt*

An array of four 16-bit unsigned integers that control the width of the
pulse for each SCA when the trigger occurs.

Now, there is a second set of options to control the delay of the *test
pulse interval trigger*. These options are located under the *trigger
module*

*intp_trig_ena*

Boolean value enabling/disabling the interval test pulse trigger.

*intp_trig_delay*

Unsigned 32-bit integer controlling the trigger delay, which is the time
between when the trigger is requested, and when the trigger actually fires.

You can setup the interval trigger and use that to create event packets
with the test pulse on set intervals. If the interval trigger is
insufficient, I can create another option, which is to fire the test pulse
for enabled SCAs when the external trigger goes. If so, I’ll add this
option in the *signalproc *module for you:

*test_pulse_on_ext*

An array of four Booleans, that control if the test pulse for that SCA
fires on external trigger.

Remember, in order to use the SCA test pulse at all, you must also set the
SCA to test mode. You can do this by going into the *sca0-3 modules* and
setting *test* to *functionality *(the value is *3* if you want to set it
via esper-tool)

Btw currently the SCAs are hard-coded to have all 72 channels receive the
test pulse on firing, and the option to de-select/select which channels to
fire is not offered. Would you like this ability? And if so do you want it
to set all four SCAs the same, or have an option for all 288 channels?

The waveform viewer on the webpage was removed for technical reasons, and
so all viewing is done via the MIDAS DAQ. There are some preliminary tools
I’ve created to verify the event packets and their waveforms, but I
wouldn’t call them easy to setup or use at the moment. (Or very useful for
fine comparisons). If KO doesn’t have a way of saving the events to disk, I
could deliver something that captured and saved waveforms quite quickly.

Regards,
Bryerton

*From:* Lars Martin
*Sent:* April 23, 2018 5:10 PM
*To:* Bryerton Shaw <bryerton@triumf.ca>
*Cc:* Andrea Capra <acapra@triumf.ca>
*Subject:* PWB/FEAM internal test pulse

Hi Bryerton,

Andrea and I would like to check the response function of the PWBs. For
that Daryl suggested to first look at the internal test pulse.

Can you point us to what settings are required to make that go? And to use
the external trigger if we want to acquire the data?

Ideally we would acquire Midas data from that, but it's unclear if KO's
frontend allows for that right now. Can we access the data with Esper
instead?

Finally, we haven't had the waveform display on the web page for a while,
but Daryl said you guys use it. Are we using a different page somehow?

Hope all is well with the baby, cheers,

Lars
</pre>

= TODO =

* IMPOSSIBLE (ext clock only connected to clock cleaner) add frequency counter for the external clock (62.5 MHz)
* DONE add random delay before memtest
* DONE add 4 more bits to udp_delay
* DONE fix crash on boot if run is active and triggers arrive (check that trigger is off on boot) (do not set trigger/enable_all, ext_trig_ena, inp_trig_ena, signal_proc/force_run to 1 after boot)
* DONE (kludge jtag uart write()) increase size of jtag uart output buffer, make it unlimited if possible.
* DONE (kludge jtag uart write()) on dhcp timeout, reboot the fpga - reboot of nios does not clear the jtag uart, which becomes full and nios stops.
* DONE add NIOS watchdog timeout for fectrl
* DONE do not use external clock until instructed by fectrl (clock cleaner default is pin select mode, default pin mode is input with pull down, so clock 0 is selected, this is the ext clock. but we can drive clock select pins from the fpga).
* DONE change clock cleaner power up: use the 2 lines status_clkin0 and status_clkin1 to tell clock cleaner to use the internal clock (clkin2) - from the FPGA drive first line low, second line high. Also change all NIOS code that programs the clock cleaner to keep these two lines in the "input" mode. Current code switches them to "output" mode.
* DONE clock cleaner power up state is wrong for both choices of clock: 62.5 MHz ext clock and 125 MHz internal clock, see explanation in feam_top.sv. It looks like I need to drive status_clkin0 and status_clkin1 to "holdover" mode, both logic level 1. Currently status_clkin0 is used as SPI read line, this has to be moved to a different line first.
* add watchdog timeout that works in factory mode ("remote update" watchdog only works in user mode)
* enable HTTP pipelining - copy changes on mongoose from ADC project.
* reset everything if it looks like NIOS TCP/IP code has crashed, but enough code is still running to prevent tripping of the fpga-remote-update watchdog timer. such crash tends to happens when the sata link mate is rebooted and incomplete data arrives from the disrupted ethernet data path.
* DONE when loading AFTER ASIC do not go into infinite loop if read-back is broken (always mismatch).
* read and report error status information bits for 2983fc.pdf voltages, currents and temperatures chip
* add provisions for coded trigger
* DONE verify readout of MV2 Hall magnetometer (all registers and bits from device are visible in esper)

= ZZZ =

ZZZ

PWB

2023-03-22T20:44:34Z

Olchansk: /* TODO */

= Links =

* https://bitbucket.org/expalpha/pwb_rev1_firmware
* https://edev-group.triumf.ca/fw/exp/alphag/feam/rev1
* https://edev-group.triumf.ca/hw/alphag/feam/rev1
* https://ladd00.triumf.ca/daqinv/frontend/list/170 - PWB inventory database

= Schematics =

* [[Image:pwb_rev0.pdf]]
* [[Image:Pwb-rev1-after.pdf]]
* [[Image:AlphaG Rev1.pdf]]

= Manuals =

* [[Image:AFTER_MANUAL_V1.pdf]] AFTER SCA manual v1
* [[Image:AFTER_DataSheet1_1.pdf]] AFTER SCA manual v1.1
* [[Image:AFTER_SCA_table2.pdf]] AFTER SCA channel map

= Hardware =

== Power distribution and monitoring ==

External power supply is:
* +5V
* +2V

Central board:

* Ext_5V - F1 - RS1 (0.1R) - Fuse_5V
* Ext_2V - F2/F3 - RS2 (0.1R) - Idig2-
* LDO3 - Fuse_5V - DIG_3.3V - selfenable - ADM7154
* LDO5 - Fuse_5V - DIG_2.5V - selfenable - ADM7154
* LDO_CLN - Fuse5V - CLN_3.3V - selfenable -
* VREG - DIG_3.3V - -2.5V SCA BIAS - selfenable - LTC1983ES6-3#TRMPBF
* LDO7 - DIG_2.5V - DDR3_VRef - enable DDR3_1P5V, DDR3_PG, DDR3_VttEN
* LDO2 - Idig2V- - DIG_1.1V - enable DIG_3.3V - LT3071
* LDO6 - Idig2V- - DDR3_1P5V - enable DIG_3.3V - LT3083

SCA Wing:

* Ext_5V - F1 - RS1 (0.3R) - Isca- - SCA_Fuse5V
* LDO1 - SCA_Fuse5V - SCA3.3V - enable ADC_PWR_EN - ADM7154
* LDO2 - SCA3.3V - ADC1.8V - selfenable - ADM7154
* LDO3 - SCA3.3V - TRN2.5V - selfenable - LT1761
* REF - SCA3.3V - 1.45V Vicm - selfenable - LM4121

esper variables:

* board/i_sca12, i_sca34, v_sca12, v_sca34: voltage and current into LDO1, after fuse F1 (wing board)
* board/i_p2, v_p2: voltage and current on 2V bus after fuses F2/F3
* board/i_p5, v_p5: voltage and current on 5V bus after fuse F1 (central board)

== Trigger and Clock distribution ==

Clock (62.5MHz) and trigger are distributed to the PWB columns via the [https://edev-group.triumf.ca/hw/alphag/trigger-card-sata-adapter/rev1 trigger SATA adapter].

The two miniSAS cables from cdm03 port 5 and 6 are connected to a miniSAS-SATA splitter 1-to-4 (CS Electronics "iSAS SATA adapter" ADP-887P-1X). Since there are only 8 columns and the clock and trigger signals are daisy-chained across the 8 rows, this scheme is sufficient to provide the necessary inputs to all 64 PWBs.

[https://www.techcable.com/sas-mini-sas-cables/sata-cables/ SATA 6Gb/s Cable with Latching Clip. Straight Pinout 1-1 247726-L 40in]

== Optical Link ==

Main data uplink.

SFP (Small Form Pluggable) Avago Technologies AFBR-57M5APZ [[File:AVAGO SFP specs.pdf|SFP (Small Form Pluggable) Avago Technologies AFBR-57M5APZ]]

Fiber optic Tripp Lite N820 - 10 m [[File:FiberOptic TrippLite specs.pdf|Fiber optic Tripp Lite N820 - 10 m]]

== SATA Link ==

Secondary data uplink, capable also to deliver clock and trigger.

The SATA link connects PWB from adjacent columuns on the same row.

The SATA cable is a "crossed cable".

= Firmware =

== Firmware update ==

PWB firmware update is done using "esper-tool".

<pre>
esper-tool -v upload -f file.rpd http://pwbNN update factory_rpd
esper-tool -v upload -f file.rpd http://pwbNN update file_rpd
</pre>

As of PWB firmware pwb_rev1_20200706_ko:

Permission to write into the flash memory is controlled by esper variables:

* allow_write set to "false": "esper-tool upload" does a "verify": successful upload means epcq flash content is same as rpd file, error means content is not the same.
* allow_write set to "true": "esper-tool upload" updates the epcq flash from the rpd file: for each data block, read the epcq flash, compare to rpd data, if different, erase the flash block, write the flash, read the flash, if there is a mismatch (bad write), return an error.
* allow_factory_write set to "true" to enable writing to the "factory_rpd". DO NOT SET IT TO "true" UNLESS YOU MEAN TO UPDATE THE PWB BOOTLOADER. IF YOU FLASH BUM FIRMWARE or IF THERE IS A POWER OUTAGE WHILE UPDATING, THE PWB WILL BE BRICKED and has to be recovered by connecting a USB blaster.

To update firmware of multiple boards to correct version, recommended is the script "update_pwb.perl":
<pre>
cd ~/online/src
./update_pwb.perl pwb12 pwb06 pwb78
</pre>

== Factory page and user page firmware boot ==

Each PWB board has 2 firmware images: boot loader (factory page)
and data acquisition (user page). On power up, the FPGA loads and runs
the boot loader firmware from the factory page, later the control
software reboots the FPGA into the data acquisition firmware from
the user page.

Because loading defective firmware can brick https://en.wikipedia.org/wiki/Brick_(electronics)
the PWB, new firmware images are loaded into the user page, if anything is wrong,
the PWB can still boot from the factory page and one can use the firmware update
function to load a good firmware image into the user page.

The boot loader firmware in the factory page is not intended for data acquisition, it is only meant to provide three functions:
* boot enough hardware and software to communicate via the ethernet and the sata link
* firmware update (both factory page and user page)
* reboot into the user page

The boot loader firmware in the factory page is usually never updated unless absolutely
needed to fix a problem with these three functions (i.e. compatibility with sata link communications).

If factory image is corrupted or the contains defective firmware and the PWB does not boot (no dhcp, no ping, no esper),
the only way to unbrick it is by loading good firmware using a jtag flash programmer (usb-blaster). Connecting it requires
physical access to the jtag connector on the PWB board. It is impossible when the detector is fully assembled in the experiment.

The PWB has a 32 Mbyte EPCQ flash memory chip, it is divided into 2 pages 16 Mbytes of factory page and 16 Mbytes of user page.

A complete firmware image generally contains 3 pieces:
* FPGA firmware and NIOS "feam_bootloader" software RAM image (sof file)
* NIOS "feam" software RAM image (feam.elf.flash.hex) - all the C code for esper communications and PWB data acquisition
* NIOS filesystem image (feam.webpkg.hex) - esper web pages

This is the boot sequence:
* on power-up the FPGA automatically loads the sof file from address 0 of the EPCQ flash (this is the factory image sof file)
* the FPGA is "started"
* the NIOS CPU starts executing the "feam_bootloader" C code embedded in the sof file (NIOS project hdl/software/feam_bootloader)
* feam_bootloader initializes the hardware (clocks, DDR memory, etc)
* feam_bootloader write-protects the EPCQ flash memory
* feam_bootloader copies the "feam" software from EPCQ flash to the DDR memory (after checking for correct checkum)
* feam_bootloader restarts the NIOS CPU
* the NIOS CPU starts running from DDR memory, executes the "feam" software (NIOS project hdl/software/feam)
* call main() in hdl/software/feam/src/task_init.c
* call task_init() in the same file
* infinite loop waiting for IP address via DHCP
* after have IP address, call task_esper() from hdl/software/feam/src/task_esper.c
* task_esper() creates all the esper modules, esper variables, etc,
* mod_http.c starts the mongoose web server
* PWB is open for business

This is the protection against booting corrupted firmware:
* FPGA hardware loads the sof file from epcq flash and checks for correct checksum before "starting" it
* NIOS CPU is part of the sof file, protected by sof file checksum
* NIOS feam_bootloader C code is part of the sof file, protected by the sof checksum
* feam_bootloader checks for correct signatures and checksums of the DDR memory image
* "feam" C code is protected by the checksum of the DDR memory image

== NIOS terminal ==

<pre>
$ ssh agmini@daq16
$ /opt/intelFPGA/16.1/quartus/bin/jtagconfig
1) USB-Blaster [2-1.2]
02B030DD 5CGTFD7(B5|C5|D5)/5CGXBC7B6/..
$ /opt/intelFPGA/17.0/quartus/bin/nios2-terminal
nios2-terminal: connected to hardware target using JTAG UART on cable
nios2-terminal: "USB-Blaster [2-1.2]", device 1, instance 0
nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)
PWB Revision 1 Boot Loader
Ver 2.0 Build 357 - Wed Jun 6 15:05:35 PDT 2018
...
</pre>

== Flash boot loader firmware via jtag ==

<pre>
$ ssh agmini@daq16
$ /opt/intelFPGA/16.1/quartus/bin/jtagconfig
1) USB-Blaster [2-1.2]
02B030DD 5CGTFD7(B5|C5|D5)/5CGXBC7B6/..
$ cd ~/online/firmware/pwb_rev1
$ ls -l
$ /opt/intelFPGA/17.1/quartus/bin/quartus_pgmw
... auto detect
... load the jic file
... in menu tools->programmer, enable "unprotect device"
... start program/configure operation
</pre>

== Flash user page firmware via esper-tool ==

<pre>
$ ssh agmini@daq16
$ cd online/src
$ more update_pwb.perl ### check that $fw is set to the desired firmware file
$ ./update_pwb.perl pwb06 ### or give more PWB names or give "all"
</pre>

== Build firmware ==

=== quartus version to use ===

* quartus 16.1 should be used for jtag (jtagconfig and jtagd)
* quartus 17.0 should be used to build the PWB firmware (17.1 is not compatible)

=== start license server ===

<pre>
ssh agmini@daq16
/opt/intelFPGA/17.0/quartus/linux64/lmgrd -c ~agmini/online/license-daq16.dat
</pre>

=== prepare the build environment ===

<pre>
$ ssh agmini@daq16
$ /opt/intelFPGA/17.0/nios2eds/nios2_command_shell.sh
</pre>

=== get latest version of the code and build it ===

<pre>
$ cd online/firmware/git/pwb_rev1_firmware
$ git pull
$ git checkout alphag
$ git pull
$ ./scripts/compile_project.sh
... about 30-40 minutes ...
$ ls -l bin/*.sof bin/*.jic bin/*.rpd
-rw-r--r-- 1 agmini alpha 12727389 Jan 24 2018 bin/feam_rev1_auto.rpd
-rw-r--r-- 1 agmini alpha 33554661 Jan 24 2018 bin/feam_rev1.jic
-rw-r--r-- 1 agmini alpha 6974754 Jan 24 2018 bin/rev1.sof
$ ### feam.jic is loaded via jtag
$ ### feam_auto.rpd is loaded via esper
$ ### feam.sof is used to attach the quartus signal tap logic analyzer
</pre>

=== firmware build order and sequence ===

* erase previous build
* regenerate qsys
* regenerate NIOS BSP "feam_bootloader_bsp" and "feam_bsp"
* build NIOS projects "feam_bootloader" and "feam"
* build quartus sof file (with the "feam_bootloader" nios project inside)
* build jic and rpd files (with the quartus sof file and the "feam" nios project inside)
* load sof file into the FPGA using jtag (be careful about compatible "feam" nios project already in the epcq flash)
* load jic file into the epcq factory page using jtag (cycle power for them to take effect)
* load rpd file into the epcq factory or user page using esper

=== scripts for building the firmware ===

* scripts/compile_project.sh - build everything from scratch:
* scripts/compile_qsys.sh - regenerate the main qsys component
* scripts/compile_nios.sh - regenerate the BSPs, then same as compile_elf.sh
* scripts/compile_elf.sh - build the BSPs, "feam_bootloader" and "feam" NIOS projects
* scripts/update_elf.sh - regenerate the rpd and jic files to include the new "feam" NIOS build (keeps the old "feam_bootloader" in the sof file)
* scripts/update_bootloader.sh - also regenerate the sof file to include the new "feam_bootloader" build
* scripts/clean_quartus.sh - prepare quartus fpga sof file to build from scratch
* scripts/compile_quartus.sh - build the quartus fpga sof file incrementally (run clean_quartus.sh to build from scratch).
* scripts/load_jtag_sof.pl bin/rev1.sof - load sof file into the FPGA. this will boot the new fpga firmware, the new feam_bootloader (if update_bootloader.sh was run), but with the old "feam" already in epcq flash. (beware of incompatible sof, "feam_bootloader" and "feam" builds!)
* scripts/load_jtag_jic.pl bin/feam_rev1.jic - load jic file into the EPCQ flash, same as using the graphical flash programmer tool. (this will leave the FPGA running the quartus jtag flash loader firmware, not the PWB firmware. Cycle power for new jic file to take effect).

== ESPER Variables ==

* Board
** invert_ext_trig - invert trigger signal from CDM before it drives any logic (to undo incorrect signal polarity)
** reset_nios - goggle up, them down to reset NIOS subsystem

* Signalproc
** test_mode - ADC data is replaced with a test pattern, see test mode bits in sca_x_ch_ctrl.
** sca_a_ch_ctrl, sca_b_ch_ctrl, sca_c_ch_ctrl, sca_d_ch_ctrl - channel control bits:
<pre>
11..0 - threshold - channel suppression threshold
14..12 - ctrl_test_mode - test mode:
0=fixed patter 0xa5a,
1=time bin counter,
2=time bin counter with channel number,
3=sequential adc sample counter,
4={ch_crossed_out,trig_pos,trig_neg,adc[8:0]},
5={trig,adc[10:0]},
6={ch_crossed_min,adc[10:0]}
15 - ctrl_supp_mode - channel suppression mode: 0=adc<=(baseline-threshold), 1=adc<=threshold
</pre>

* Link
** link_ctrl - sata link control. The bits are:
<pre>
0 - sata_link_udp_stream_in_enable - permit data flow from sata link to OFFLOAD_SATA
1 - udp_stream_out_enable - permit sca data flow to sata link
2 - sata_to_eth_enable - permit ethernet data flow from sata link to TSE_MAC
3 - eth_to_sata_enable - permit ethernet data flow from TSE MAC to sata link
4 - enable_stop_our_tx - enable flow control: allow stop_tx
#5 - stop_our_tx - manually activate the flow control signal into link_tx
6 - enable_stop_remote_tx - enable flow control: allow send "stop_tx"
#7 - stop_remote_tx - manually activate the flow control signal into link_tx
8 - tx_test_pattern_udp - udp data is replaced by test pattern 0x11111111, 0x22222222, etc.
9 - tx_test_pattern_eth - nios-to-sata data is replaced by test pattern 0x11111111, 0x22222222, etc.
10 - udp_delay_enable - delay between udp packets, see udp_delay_value below
11 - reboot_tx - send K_REBOOT command to the sata link mate, where it has same effect as board/reset_nios.
12 - sata_to_nios_disable
13 - nios_to_sata_disable
14 -
15 -
16 -
24..31 - udp_delay_value - delay between udp packets (top 8 bits of a 20-bit counter)
</pre>

== Firmware data path ==

Main data path:
<pre>
feam_top
|
sca_sigproc
|
sca_event_control
4 * sca_control (sca_channel.sv)
4 * channel_fifo (1024 samples)
</pre>
<pre>
sca_control (sca_channel.sv)
|
state machine to control SCA read and write enables
|
sca_write_control (what does it do?!?)
sca_read_control
</pre>
<pre>
sca_read_control
|
state machine to store ADC samples into per-channel FIFOs (channel_fifo)
selector to replace ADC samples with a test pattern
79*sca_trig_one -> ch_crossed_out - channel hit detector
</pre>
<pre>
sca_event_control
|
event_fifo (hdl/mf/event_descriptor_fifo)
state machine to take ADC data from 4 per-channel FIFOs (channel_fifo) and store it into DDR memory (write addr increment is 510*8 (number of samples)*8 = 4080).
state machine to read transposed ADC data from DDR memory (read addr increment is 8+8=16 - 2 samples * 2 bytes * 4 sca = 16) and create 4 per-sca data streams
</pre>
<pre>
data stream:
4 per-sca data streams from sca_event_control -> sca_sigproc(event_dat)
|
packet_chunker (hdl/lib/packet_chunker.sv) (4*event_dat -> event_segment_dat) - multiplex 4 data streams into 1 stream of UDP-sized packets
|
packet_length_prepender (hdl/lib/packet_length_prepender.sv) (event_segment_dat -> udp_event_val_out)
|
udp_event_val -> info qsys (udp_stream_sca) and into sata link (mux channel 2).
</pre>

== Firmware build instructions from Bryerton (obsolete) ==

This is the old README.md file from the firmware git repository.

These instructions are not used to build the firmware (use scrips/compile_project.sh).

They are still useful for figuring out which buttons to push in the altera gui programs.

<pre>
# ALPHAg FrontEnd Acquisition Module (FEAM) - REV0

Welcome to the ALPHAg FEAM Project

# Table of Contents

* [Overview](#overview)
* [Inital Setup](#initial-setup)
* [Quartus Setup](#quartus-setup)
* [Create the .cdf](#create-the-cdf)
* [NIOS Setup](#nios-Setup)
* [Create the project files](#create-the-project-files)
* [Build Instructions](#build-instructions)
* [Building from Quartus GUI](#building-from-quartus-gui)
* [Generate the QSys File](#generate-the-qsys-file)
* [Compile the NIOSII Project](#compile-the-niosii-project)
* [Compile the Quartus Project](#compile-the-quartus-project)
* [Building from Scripts](#building-from-scripts)
* [Installing from JTAG](#installing-from-jtag)
* [Installing from ESPER](#installing-from-esper)

# Overview

The FEAM is a digitizer located on the ALPHAg detector. Each FEAM consists of 4 AFTER SCAs for a total of 288 channels.

# Initial Setup

## Quartus Setup

### Create the .cdf
1. Open Quartus Prime Standard Edition
2. Click on **Tools -> Programmer**. The **Programmer** window will appear
3. In the **Programmer** window, click **Auto Detect**. A **Select Device** dialog box will appear
1. (Optional) If **Auto Detect** is greyed out, click on **Hardware Setup**. The **Hardware Setup** dialog box will appear
2. Under **Hardware Settings**, double-click on the USB JTAG hardware you wish to use
3. Click **Close**. The **Hardware Setup** dialog box will close
5. Click on **File -> Save As**. The **Save As** dialog box will appear
6. In the **Save As** dialog box, browse to the **/\<project_dir\>/bin/** directory
7. Make sure the **Add file to current project** checkbox is checked
7. In the **File name** input box, type "alphag_feam.cdf" and click **Save**
8. Close the **Programmer** window
9. Done!

## NIOS Setup

### Create the project files
1. Open Quartus Prime Standard Edition
2. Open the NIOS II Software Build Tools by clicking **Tools -> NIOS II Software Build Tools for Eclipse**
3. The **Workspace Launcher** window will appear, click *OK* to accept the default workspace.
4. Click **File -> Import...**. The **Import** dialog box will appear
5. Click on **General -> Existing Projects into Workspace**
6. Click **Next \>**
7. Next to **Select root directory** click **Browse...**. A **Browse for Folder** dialog box will appear
8. Browse to **/\<project_dir\>/hdl/software** and click **OK**
8. Four Projects should appear in the **Projects** panel:
* alphag_feam
* alphag\_feam\_bsp
* alphag\_feam\_bootloader
* alphag\_feam\_bootloader\_bsp
9. Click **Select All**
10. Click **Finish**
11. Done!

# Build Instructions

## Building from Quartus GUI

**Warning: Please use Quartus Prime Standard Edition 16.1**
### Generate the QSys File
1. Open Quartus Standard Edition 16.1
1. Open QSys by clicking **Tools -> QSys**
2. Click on **File -> Open** (CTRL+O). An **Open File** dialog box should appear.
3. Select the **alphag_feam.qsys** file from the **/\<project_dir\>/hdl** directory and click **Open**
4. Modify as necessary. NOTE: Any change to the QSys, even cosmetic such as expanding or collapsing components will cause the QSys to desire a re-generate.
5. Click **File -> Save** (CTRL+S)
6. Click **Generate HDL**. A **Generation** dialog box will appear
7. Select the settings you desire to be changed, if any
8. Click **Generate**
9. Wait for the generation to complete.
10. Done!

### Compile the NIOSII Project
1. Open the NIOS II Software Build Tools by clicking **Tools -> NIOS II Software Build Tools for Eclipse**
2. (Optional) If the QSys file has been re-generated performing the following
1. Right-click on **alphag\_feam\_bsp** and select **NIOS II -> Generate BSP**. The BSP will regenerate
2. Right-click on **alphag\_feam\_bootloader\_bsp** and select **NIOS II -> Generate BSP**. The BSP will regenerate
3. Modify files as needed. WARNING: Do not modify any BSP files by hand! All changes will be lost on next generate.
4. Click **Project -> Build All** (CTRL+B). If your workspace as multiple projects, it is recommend to close all but the ones related to the FEAM.
5. Right-click on **alphag\_feam\_bootloader** and select **Make Targets -> Build...**. The **Make Targets** dialog box will appear
6. In the **Make Targets** dialog box, select **mem\_init\_generate** and click **Build**
7. Done!

### Compile the Quartus Project
1. Open Quartus Standard Edition 16.1
1. Under **Processing** click **Start Compilation** (CTRL+L)
2. Wait about 16-30 minutes.
3. Done!

**Note:** If Quartus crashed while compiling, delete the **\<project_dir\>/hdl/db** and **\<project_dir\>/hdl/incremental_db** directories and try again

## Installing from JTAG
1. Generate the .jic file using the provided /bin/alphag\_feam\_jic.cof
1. In the main Quartus window, click **File -> Convert Programming Files**, A **Convert Programming Files** window will appear
2. In the **Convert Programming Files** window, click **Open Conversion Setup Data**. An **Open** dialog box will appear
3. In the **Open** dialog box, select the **alphag_feam.cof** file located in **/bin/**
4. Click **Open**. The **Open dialog box will close
* Note the **File name** field, it should display /\<project\_dir\>/bin/alphag\_feam.jic
5. In the **Convert Programming Files** window, click **Generate**
6. When the .jic is done being generated, a small dialog box will appear, click **OK**
7. In the **Convert Programming Files** window, click **Close**
2. Load the .JIC file using the Programmer
1. In the main Quartus window in the **Project Navigator** drop-down input select **Files**.
2. Scroll down the window and find the **alphag_feam.cdf**, and double-click it. The **Programmer** window will open
3. Click on the icon labelled **5CGXFC4C6**
4. Click on the **Change File** button. The **Select New Programming File** dialog box will appear
5. Browse to **/\<project_dir\>/bin/** and select **alphag\_feam.jic**
6. Click Open. The **Select New Programming File** dialog box will close
7. In the main panel, check the **Program/Configure** box on the line that starts **./bin/alphag\_feam.jic**
8. Click the **Start** button
9. Wait for the **Progress** bar to go to 100% and stop
10. Done!
</pre>

= Internal test pulser =

Documentation from Bryerton:

<pre>
---------- Forwarded message ---------
From: Bryerton Shaw <bryerton@triumf.ca>
Date: Tue, 24 Apr 2018 at 16:18
Subject: RE: PWB/FEAM internal test pulse
To: Lars Martin <lmartin@triumf.ca>
Cc: Andrea Capra <acapra@triumf.ca>

Hi Lars (and Andrea),

In the new(er) firmware the test pulse code has been modified slightly to
fit in better with the upgraded trigger system. I can add an option to
allow it to be triggered by the external trigger (currently it has an
interval option, or you can hit the manual trigger to fire it, if it’s
enabled)

The *options for the test pulser* are under the *signalproc module*:

*test_pulse_ena*

An array of four booleans, that control turning on the test pulse for each
SCA. If this is False, the other options below will do nothings for that SCA

*test_pulse_interval_ena*

An array of four booleans, that control turning on the interval trigger for
each SCA

*test_pulse_interval*

An unsigned 32-bit value that marks how many 16ns clock cycles occur
between interval triggers. Only one value, as there is only one interval
timer.

*test_pulse_wdt*

An array of four 16-bit unsigned integers that control the width of the
pulse for each SCA when the trigger occurs.

Now, there is a second set of options to control the delay of the *test
pulse interval trigger*. These options are located under the *trigger
module*

*intp_trig_ena*

Boolean value enabling/disabling the interval test pulse trigger.

*intp_trig_delay*

Unsigned 32-bit integer controlling the trigger delay, which is the time
between when the trigger is requested, and when the trigger actually fires.

You can setup the interval trigger and use that to create event packets
with the test pulse on set intervals. If the interval trigger is
insufficient, I can create another option, which is to fire the test pulse
for enabled SCAs when the external trigger goes. If so, I’ll add this
option in the *signalproc *module for you:

*test_pulse_on_ext*

An array of four Booleans, that control if the test pulse for that SCA
fires on external trigger.

Remember, in order to use the SCA test pulse at all, you must also set the
SCA to test mode. You can do this by going into the *sca0-3 modules* and
setting *test* to *functionality *(the value is *3* if you want to set it
via esper-tool)

Btw currently the SCAs are hard-coded to have all 72 channels receive the
test pulse on firing, and the option to de-select/select which channels to
fire is not offered. Would you like this ability? And if so do you want it
to set all four SCAs the same, or have an option for all 288 channels?

The waveform viewer on the webpage was removed for technical reasons, and
so all viewing is done via the MIDAS DAQ. There are some preliminary tools
I’ve created to verify the event packets and their waveforms, but I
wouldn’t call them easy to setup or use at the moment. (Or very useful for
fine comparisons). If KO doesn’t have a way of saving the events to disk, I
could deliver something that captured and saved waveforms quite quickly.

Regards,
Bryerton

*From:* Lars Martin
*Sent:* April 23, 2018 5:10 PM
*To:* Bryerton Shaw <bryerton@triumf.ca>
*Cc:* Andrea Capra <acapra@triumf.ca>
*Subject:* PWB/FEAM internal test pulse

Hi Bryerton,

Andrea and I would like to check the response function of the PWBs. For
that Daryl suggested to first look at the internal test pulse.

Can you point us to what settings are required to make that go? And to use
the external trigger if we want to acquire the data?

Ideally we would acquire Midas data from that, but it's unclear if KO's
frontend allows for that right now. Can we access the data with Esper
instead?

Finally, we haven't had the waveform display on the web page for a while,
but Daryl said you guys use it. Are we using a different page somehow?

Hope all is well with the baby, cheers,

Lars
</pre>

= TODO =

* IMPOSSIBLE (ext clock only connected to clock cleaner) add frequency counter for the external clock (62.5 MHz)
* DONE add random delay before memtest
* DONE add 4 more bits to udp_delay
* DONE fix crash on boot if run is active and triggers arrive (check that trigger is off on boot) (do not set trigger/enable_all, ext_trig_ena, inp_trig_ena, signal_proc/force_run to 1 after boot)
* DONE (kludge jtag uart write()) increase size of jtag uart output buffer, make it unlimited if possible.
* DONE (kludge jtag uart write()) on dhcp timeout, reboot the fpga - reboot of nios does not clear the jtag uart, which becomes full and nios stops.
* DONE add NIOS watchdog timeout for fectrl
* DONE do not use external clock until instructed by fectrl (clock cleaner default is pin select mode, default pin mode is input with pull down, so clock 0 is selected, this is the ext clock. but we can drive clock select pins from the fpga).
* DONE change clock cleaner power up: use the 2 lines status_clkin0 and status_clkin1 to tell clock cleaner to use the internal clock (clkin2) - from the FPGA drive first line low, second line high. Also change all NIOS code that programs the clock cleaner to keep these two lines in the "input" mode. Current code switches them to "output" mode.
* DONE clock cleaner power up state is wrong for both choices of clock: 62.5 MHz ext clock and 125 MHz internal clock, see explanation in feam_top.sv. It looks like I need to drive status_clkin0 and status_clkin1 to "holdover" mode, both logic level 1. Currently status_clkin0 is used as SPI read line, this has to be moved to a different line first.
* add watchdog timeout that works in factory mode ("remote update" watchdog only works in user mode)
* enable HTTP pipelining - copy changes on mongoose from ADC project.
* reset everything if it looks like NIOS TCP/IP code has crashed, but enough code is still running to prevent tripping of the fpga-remote-update watchdog timer. such crash tends to happens when the sata link mate is rebooted and incomplete data arrives from the disrupted ethernet data path.
* DONE when loading AFTER ASIC do not go into infinite loop if read-back is broken (always mismatch).
* read and report error status information bits for 2983fc.pdf voltages, currents and temperatures chip
* add provisions for coded trigger

= ZZZ =

ZZZ

PWB

2023-03-22T20:40:17Z

Olchansk: /* TODO */

= Links =

* https://bitbucket.org/expalpha/pwb_rev1_firmware
* https://edev-group.triumf.ca/fw/exp/alphag/feam/rev1
* https://edev-group.triumf.ca/hw/alphag/feam/rev1
* https://ladd00.triumf.ca/daqinv/frontend/list/170 - PWB inventory database

= Schematics =

* [[Image:pwb_rev0.pdf]]
* [[Image:Pwb-rev1-after.pdf]]
* [[Image:AlphaG Rev1.pdf]]

= Manuals =

* [[Image:AFTER_MANUAL_V1.pdf]] AFTER SCA manual v1
* [[Image:AFTER_DataSheet1_1.pdf]] AFTER SCA manual v1.1
* [[Image:AFTER_SCA_table2.pdf]] AFTER SCA channel map

= Hardware =

== Power distribution and monitoring ==

External power supply is:
* +5V
* +2V

Central board:

* Ext_5V - F1 - RS1 (0.1R) - Fuse_5V
* Ext_2V - F2/F3 - RS2 (0.1R) - Idig2-
* LDO3 - Fuse_5V - DIG_3.3V - selfenable - ADM7154
* LDO5 - Fuse_5V - DIG_2.5V - selfenable - ADM7154
* LDO_CLN - Fuse5V - CLN_3.3V - selfenable -
* VREG - DIG_3.3V - -2.5V SCA BIAS - selfenable - LTC1983ES6-3#TRMPBF
* LDO7 - DIG_2.5V - DDR3_VRef - enable DDR3_1P5V, DDR3_PG, DDR3_VttEN
* LDO2 - Idig2V- - DIG_1.1V - enable DIG_3.3V - LT3071
* LDO6 - Idig2V- - DDR3_1P5V - enable DIG_3.3V - LT3083

SCA Wing:

* Ext_5V - F1 - RS1 (0.3R) - Isca- - SCA_Fuse5V
* LDO1 - SCA_Fuse5V - SCA3.3V - enable ADC_PWR_EN - ADM7154
* LDO2 - SCA3.3V - ADC1.8V - selfenable - ADM7154
* LDO3 - SCA3.3V - TRN2.5V - selfenable - LT1761
* REF - SCA3.3V - 1.45V Vicm - selfenable - LM4121

esper variables:

* board/i_sca12, i_sca34, v_sca12, v_sca34: voltage and current into LDO1, after fuse F1 (wing board)
* board/i_p2, v_p2: voltage and current on 2V bus after fuses F2/F3
* board/i_p5, v_p5: voltage and current on 5V bus after fuse F1 (central board)

== Trigger and Clock distribution ==

Clock (62.5MHz) and trigger are distributed to the PWB columns via the [https://edev-group.triumf.ca/hw/alphag/trigger-card-sata-adapter/rev1 trigger SATA adapter].

The two miniSAS cables from cdm03 port 5 and 6 are connected to a miniSAS-SATA splitter 1-to-4 (CS Electronics "iSAS SATA adapter" ADP-887P-1X). Since there are only 8 columns and the clock and trigger signals are daisy-chained across the 8 rows, this scheme is sufficient to provide the necessary inputs to all 64 PWBs.

[https://www.techcable.com/sas-mini-sas-cables/sata-cables/ SATA 6Gb/s Cable with Latching Clip. Straight Pinout 1-1 247726-L 40in]

== Optical Link ==

Main data uplink.

SFP (Small Form Pluggable) Avago Technologies AFBR-57M5APZ [[File:AVAGO SFP specs.pdf|SFP (Small Form Pluggable) Avago Technologies AFBR-57M5APZ]]

Fiber optic Tripp Lite N820 - 10 m [[File:FiberOptic TrippLite specs.pdf|Fiber optic Tripp Lite N820 - 10 m]]

== SATA Link ==

Secondary data uplink, capable also to deliver clock and trigger.

The SATA link connects PWB from adjacent columuns on the same row.

The SATA cable is a "crossed cable".

= Firmware =

== Firmware update ==

PWB firmware update is done using "esper-tool".

<pre>
esper-tool -v upload -f file.rpd http://pwbNN update factory_rpd
esper-tool -v upload -f file.rpd http://pwbNN update file_rpd
</pre>

As of PWB firmware pwb_rev1_20200706_ko:

Permission to write into the flash memory is controlled by esper variables:

* allow_write set to "false": "esper-tool upload" does a "verify": successful upload means epcq flash content is same as rpd file, error means content is not the same.
* allow_write set to "true": "esper-tool upload" updates the epcq flash from the rpd file: for each data block, read the epcq flash, compare to rpd data, if different, erase the flash block, write the flash, read the flash, if there is a mismatch (bad write), return an error.
* allow_factory_write set to "true" to enable writing to the "factory_rpd". DO NOT SET IT TO "true" UNLESS YOU MEAN TO UPDATE THE PWB BOOTLOADER. IF YOU FLASH BUM FIRMWARE or IF THERE IS A POWER OUTAGE WHILE UPDATING, THE PWB WILL BE BRICKED and has to be recovered by connecting a USB blaster.

To update firmware of multiple boards to correct version, recommended is the script "update_pwb.perl":
<pre>
cd ~/online/src
./update_pwb.perl pwb12 pwb06 pwb78
</pre>

== Factory page and user page firmware boot ==

Each PWB board has 2 firmware images: boot loader (factory page)
and data acquisition (user page). On power up, the FPGA loads and runs
the boot loader firmware from the factory page, later the control
software reboots the FPGA into the data acquisition firmware from
the user page.

Because loading defective firmware can brick https://en.wikipedia.org/wiki/Brick_(electronics)
the PWB, new firmware images are loaded into the user page, if anything is wrong,
the PWB can still boot from the factory page and one can use the firmware update
function to load a good firmware image into the user page.

The boot loader firmware in the factory page is not intended for data acquisition, it is only meant to provide three functions:
* boot enough hardware and software to communicate via the ethernet and the sata link
* firmware update (both factory page and user page)
* reboot into the user page

The boot loader firmware in the factory page is usually never updated unless absolutely
needed to fix a problem with these three functions (i.e. compatibility with sata link communications).

If factory image is corrupted or the contains defective firmware and the PWB does not boot (no dhcp, no ping, no esper),
the only way to unbrick it is by loading good firmware using a jtag flash programmer (usb-blaster). Connecting it requires
physical access to the jtag connector on the PWB board. It is impossible when the detector is fully assembled in the experiment.

The PWB has a 32 Mbyte EPCQ flash memory chip, it is divided into 2 pages 16 Mbytes of factory page and 16 Mbytes of user page.

A complete firmware image generally contains 3 pieces:
* FPGA firmware and NIOS "feam_bootloader" software RAM image (sof file)
* NIOS "feam" software RAM image (feam.elf.flash.hex) - all the C code for esper communications and PWB data acquisition
* NIOS filesystem image (feam.webpkg.hex) - esper web pages

This is the boot sequence:
* on power-up the FPGA automatically loads the sof file from address 0 of the EPCQ flash (this is the factory image sof file)
* the FPGA is "started"
* the NIOS CPU starts executing the "feam_bootloader" C code embedded in the sof file (NIOS project hdl/software/feam_bootloader)
* feam_bootloader initializes the hardware (clocks, DDR memory, etc)
* feam_bootloader write-protects the EPCQ flash memory
* feam_bootloader copies the "feam" software from EPCQ flash to the DDR memory (after checking for correct checkum)
* feam_bootloader restarts the NIOS CPU
* the NIOS CPU starts running from DDR memory, executes the "feam" software (NIOS project hdl/software/feam)
* call main() in hdl/software/feam/src/task_init.c
* call task_init() in the same file
* infinite loop waiting for IP address via DHCP
* after have IP address, call task_esper() from hdl/software/feam/src/task_esper.c
* task_esper() creates all the esper modules, esper variables, etc,
* mod_http.c starts the mongoose web server
* PWB is open for business

This is the protection against booting corrupted firmware:
* FPGA hardware loads the sof file from epcq flash and checks for correct checksum before "starting" it
* NIOS CPU is part of the sof file, protected by sof file checksum
* NIOS feam_bootloader C code is part of the sof file, protected by the sof checksum
* feam_bootloader checks for correct signatures and checksums of the DDR memory image
* "feam" C code is protected by the checksum of the DDR memory image

== NIOS terminal ==

<pre>
$ ssh agmini@daq16
$ /opt/intelFPGA/16.1/quartus/bin/jtagconfig
1) USB-Blaster [2-1.2]
02B030DD 5CGTFD7(B5|C5|D5)/5CGXBC7B6/..
$ /opt/intelFPGA/17.0/quartus/bin/nios2-terminal
nios2-terminal: connected to hardware target using JTAG UART on cable
nios2-terminal: "USB-Blaster [2-1.2]", device 1, instance 0
nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)
PWB Revision 1 Boot Loader
Ver 2.0 Build 357 - Wed Jun 6 15:05:35 PDT 2018
...
</pre>

== Flash boot loader firmware via jtag ==

<pre>
$ ssh agmini@daq16
$ /opt/intelFPGA/16.1/quartus/bin/jtagconfig
1) USB-Blaster [2-1.2]
02B030DD 5CGTFD7(B5|C5|D5)/5CGXBC7B6/..
$ cd ~/online/firmware/pwb_rev1
$ ls -l
$ /opt/intelFPGA/17.1/quartus/bin/quartus_pgmw
... auto detect
... load the jic file
... in menu tools->programmer, enable "unprotect device"
... start program/configure operation
</pre>

== Flash user page firmware via esper-tool ==

<pre>
$ ssh agmini@daq16
$ cd online/src
$ more update_pwb.perl ### check that $fw is set to the desired firmware file
$ ./update_pwb.perl pwb06 ### or give more PWB names or give "all"
</pre>

== Build firmware ==

=== quartus version to use ===

* quartus 16.1 should be used for jtag (jtagconfig and jtagd)
* quartus 17.0 should be used to build the PWB firmware (17.1 is not compatible)

=== start license server ===

<pre>
ssh agmini@daq16
/opt/intelFPGA/17.0/quartus/linux64/lmgrd -c ~agmini/online/license-daq16.dat
</pre>

=== prepare the build environment ===

<pre>
$ ssh agmini@daq16
$ /opt/intelFPGA/17.0/nios2eds/nios2_command_shell.sh
</pre>

=== get latest version of the code and build it ===

<pre>
$ cd online/firmware/git/pwb_rev1_firmware
$ git pull
$ git checkout alphag
$ git pull
$ ./scripts/compile_project.sh
... about 30-40 minutes ...
$ ls -l bin/*.sof bin/*.jic bin/*.rpd
-rw-r--r-- 1 agmini alpha 12727389 Jan 24 2018 bin/feam_rev1_auto.rpd
-rw-r--r-- 1 agmini alpha 33554661 Jan 24 2018 bin/feam_rev1.jic
-rw-r--r-- 1 agmini alpha 6974754 Jan 24 2018 bin/rev1.sof
$ ### feam.jic is loaded via jtag
$ ### feam_auto.rpd is loaded via esper
$ ### feam.sof is used to attach the quartus signal tap logic analyzer
</pre>

=== firmware build order and sequence ===

* erase previous build
* regenerate qsys
* regenerate NIOS BSP "feam_bootloader_bsp" and "feam_bsp"
* build NIOS projects "feam_bootloader" and "feam"
* build quartus sof file (with the "feam_bootloader" nios project inside)
* build jic and rpd files (with the quartus sof file and the "feam" nios project inside)
* load sof file into the FPGA using jtag (be careful about compatible "feam" nios project already in the epcq flash)
* load jic file into the epcq factory page using jtag (cycle power for them to take effect)
* load rpd file into the epcq factory or user page using esper

=== scripts for building the firmware ===

* scripts/compile_project.sh - build everything from scratch:
* scripts/compile_qsys.sh - regenerate the main qsys component
* scripts/compile_nios.sh - regenerate the BSPs, then same as compile_elf.sh
* scripts/compile_elf.sh - build the BSPs, "feam_bootloader" and "feam" NIOS projects
* scripts/update_elf.sh - regenerate the rpd and jic files to include the new "feam" NIOS build (keeps the old "feam_bootloader" in the sof file)
* scripts/update_bootloader.sh - also regenerate the sof file to include the new "feam_bootloader" build
* scripts/clean_quartus.sh - prepare quartus fpga sof file to build from scratch
* scripts/compile_quartus.sh - build the quartus fpga sof file incrementally (run clean_quartus.sh to build from scratch).
* scripts/load_jtag_sof.pl bin/rev1.sof - load sof file into the FPGA. this will boot the new fpga firmware, the new feam_bootloader (if update_bootloader.sh was run), but with the old "feam" already in epcq flash. (beware of incompatible sof, "feam_bootloader" and "feam" builds!)
* scripts/load_jtag_jic.pl bin/feam_rev1.jic - load jic file into the EPCQ flash, same as using the graphical flash programmer tool. (this will leave the FPGA running the quartus jtag flash loader firmware, not the PWB firmware. Cycle power for new jic file to take effect).

== ESPER Variables ==

* Board
** invert_ext_trig - invert trigger signal from CDM before it drives any logic (to undo incorrect signal polarity)
** reset_nios - goggle up, them down to reset NIOS subsystem

* Signalproc
** test_mode - ADC data is replaced with a test pattern, see test mode bits in sca_x_ch_ctrl.
** sca_a_ch_ctrl, sca_b_ch_ctrl, sca_c_ch_ctrl, sca_d_ch_ctrl - channel control bits:
<pre>
11..0 - threshold - channel suppression threshold
14..12 - ctrl_test_mode - test mode:
0=fixed patter 0xa5a,
1=time bin counter,
2=time bin counter with channel number,
3=sequential adc sample counter,
4={ch_crossed_out,trig_pos,trig_neg,adc[8:0]},
5={trig,adc[10:0]},
6={ch_crossed_min,adc[10:0]}
15 - ctrl_supp_mode - channel suppression mode: 0=adc<=(baseline-threshold), 1=adc<=threshold
</pre>

* Link
** link_ctrl - sata link control. The bits are:
<pre>
0 - sata_link_udp_stream_in_enable - permit data flow from sata link to OFFLOAD_SATA
1 - udp_stream_out_enable - permit sca data flow to sata link
2 - sata_to_eth_enable - permit ethernet data flow from sata link to TSE_MAC
3 - eth_to_sata_enable - permit ethernet data flow from TSE MAC to sata link
4 - enable_stop_our_tx - enable flow control: allow stop_tx
#5 - stop_our_tx - manually activate the flow control signal into link_tx
6 - enable_stop_remote_tx - enable flow control: allow send "stop_tx"
#7 - stop_remote_tx - manually activate the flow control signal into link_tx
8 - tx_test_pattern_udp - udp data is replaced by test pattern 0x11111111, 0x22222222, etc.
9 - tx_test_pattern_eth - nios-to-sata data is replaced by test pattern 0x11111111, 0x22222222, etc.
10 - udp_delay_enable - delay between udp packets, see udp_delay_value below
11 - reboot_tx - send K_REBOOT command to the sata link mate, where it has same effect as board/reset_nios.
12 - sata_to_nios_disable
13 - nios_to_sata_disable
14 -
15 -
16 -
24..31 - udp_delay_value - delay between udp packets (top 8 bits of a 20-bit counter)
</pre>

== Firmware data path ==

Main data path:
<pre>
feam_top
|
sca_sigproc
|
sca_event_control
4 * sca_control (sca_channel.sv)
4 * channel_fifo (1024 samples)
</pre>
<pre>
sca_control (sca_channel.sv)
|
state machine to control SCA read and write enables
|
sca_write_control (what does it do?!?)
sca_read_control
</pre>
<pre>
sca_read_control
|
state machine to store ADC samples into per-channel FIFOs (channel_fifo)
selector to replace ADC samples with a test pattern
79*sca_trig_one -> ch_crossed_out - channel hit detector
</pre>
<pre>
sca_event_control
|
event_fifo (hdl/mf/event_descriptor_fifo)
state machine to take ADC data from 4 per-channel FIFOs (channel_fifo) and store it into DDR memory (write addr increment is 510*8 (number of samples)*8 = 4080).
state machine to read transposed ADC data from DDR memory (read addr increment is 8+8=16 - 2 samples * 2 bytes * 4 sca = 16) and create 4 per-sca data streams
</pre>
<pre>
data stream:
4 per-sca data streams from sca_event_control -> sca_sigproc(event_dat)
|
packet_chunker (hdl/lib/packet_chunker.sv) (4*event_dat -> event_segment_dat) - multiplex 4 data streams into 1 stream of UDP-sized packets
|
packet_length_prepender (hdl/lib/packet_length_prepender.sv) (event_segment_dat -> udp_event_val_out)
|
udp_event_val -> info qsys (udp_stream_sca) and into sata link (mux channel 2).
</pre>

== Firmware build instructions from Bryerton (obsolete) ==

This is the old README.md file from the firmware git repository.

These instructions are not used to build the firmware (use scrips/compile_project.sh).

They are still useful for figuring out which buttons to push in the altera gui programs.

<pre>
# ALPHAg FrontEnd Acquisition Module (FEAM) - REV0

Welcome to the ALPHAg FEAM Project

# Table of Contents

* [Overview](#overview)
* [Inital Setup](#initial-setup)
* [Quartus Setup](#quartus-setup)
* [Create the .cdf](#create-the-cdf)
* [NIOS Setup](#nios-Setup)
* [Create the project files](#create-the-project-files)
* [Build Instructions](#build-instructions)
* [Building from Quartus GUI](#building-from-quartus-gui)
* [Generate the QSys File](#generate-the-qsys-file)
* [Compile the NIOSII Project](#compile-the-niosii-project)
* [Compile the Quartus Project](#compile-the-quartus-project)
* [Building from Scripts](#building-from-scripts)
* [Installing from JTAG](#installing-from-jtag)
* [Installing from ESPER](#installing-from-esper)

# Overview

The FEAM is a digitizer located on the ALPHAg detector. Each FEAM consists of 4 AFTER SCAs for a total of 288 channels.

# Initial Setup

## Quartus Setup

### Create the .cdf
1. Open Quartus Prime Standard Edition
2. Click on **Tools -> Programmer**. The **Programmer** window will appear
3. In the **Programmer** window, click **Auto Detect**. A **Select Device** dialog box will appear
1. (Optional) If **Auto Detect** is greyed out, click on **Hardware Setup**. The **Hardware Setup** dialog box will appear
2. Under **Hardware Settings**, double-click on the USB JTAG hardware you wish to use
3. Click **Close**. The **Hardware Setup** dialog box will close
5. Click on **File -> Save As**. The **Save As** dialog box will appear
6. In the **Save As** dialog box, browse to the **/\<project_dir\>/bin/** directory
7. Make sure the **Add file to current project** checkbox is checked
7. In the **File name** input box, type "alphag_feam.cdf" and click **Save**
8. Close the **Programmer** window
9. Done!

## NIOS Setup

### Create the project files
1. Open Quartus Prime Standard Edition
2. Open the NIOS II Software Build Tools by clicking **Tools -> NIOS II Software Build Tools for Eclipse**
3. The **Workspace Launcher** window will appear, click *OK* to accept the default workspace.
4. Click **File -> Import...**. The **Import** dialog box will appear
5. Click on **General -> Existing Projects into Workspace**
6. Click **Next \>**
7. Next to **Select root directory** click **Browse...**. A **Browse for Folder** dialog box will appear
8. Browse to **/\<project_dir\>/hdl/software** and click **OK**
8. Four Projects should appear in the **Projects** panel:
* alphag_feam
* alphag\_feam\_bsp
* alphag\_feam\_bootloader
* alphag\_feam\_bootloader\_bsp
9. Click **Select All**
10. Click **Finish**
11. Done!

# Build Instructions

## Building from Quartus GUI

**Warning: Please use Quartus Prime Standard Edition 16.1**
### Generate the QSys File
1. Open Quartus Standard Edition 16.1
1. Open QSys by clicking **Tools -> QSys**
2. Click on **File -> Open** (CTRL+O). An **Open File** dialog box should appear.
3. Select the **alphag_feam.qsys** file from the **/\<project_dir\>/hdl** directory and click **Open**
4. Modify as necessary. NOTE: Any change to the QSys, even cosmetic such as expanding or collapsing components will cause the QSys to desire a re-generate.
5. Click **File -> Save** (CTRL+S)
6. Click **Generate HDL**. A **Generation** dialog box will appear
7. Select the settings you desire to be changed, if any
8. Click **Generate**
9. Wait for the generation to complete.
10. Done!

### Compile the NIOSII Project
1. Open the NIOS II Software Build Tools by clicking **Tools -> NIOS II Software Build Tools for Eclipse**
2. (Optional) If the QSys file has been re-generated performing the following
1. Right-click on **alphag\_feam\_bsp** and select **NIOS II -> Generate BSP**. The BSP will regenerate
2. Right-click on **alphag\_feam\_bootloader\_bsp** and select **NIOS II -> Generate BSP**. The BSP will regenerate
3. Modify files as needed. WARNING: Do not modify any BSP files by hand! All changes will be lost on next generate.
4. Click **Project -> Build All** (CTRL+B). If your workspace as multiple projects, it is recommend to close all but the ones related to the FEAM.
5. Right-click on **alphag\_feam\_bootloader** and select **Make Targets -> Build...**. The **Make Targets** dialog box will appear
6. In the **Make Targets** dialog box, select **mem\_init\_generate** and click **Build**
7. Done!

### Compile the Quartus Project
1. Open Quartus Standard Edition 16.1
1. Under **Processing** click **Start Compilation** (CTRL+L)
2. Wait about 16-30 minutes.
3. Done!

**Note:** If Quartus crashed while compiling, delete the **\<project_dir\>/hdl/db** and **\<project_dir\>/hdl/incremental_db** directories and try again

## Installing from JTAG
1. Generate the .jic file using the provided /bin/alphag\_feam\_jic.cof
1. In the main Quartus window, click **File -> Convert Programming Files**, A **Convert Programming Files** window will appear
2. In the **Convert Programming Files** window, click **Open Conversion Setup Data**. An **Open** dialog box will appear
3. In the **Open** dialog box, select the **alphag_feam.cof** file located in **/bin/**
4. Click **Open**. The **Open dialog box will close
* Note the **File name** field, it should display /\<project\_dir\>/bin/alphag\_feam.jic
5. In the **Convert Programming Files** window, click **Generate**
6. When the .jic is done being generated, a small dialog box will appear, click **OK**
7. In the **Convert Programming Files** window, click **Close**
2. Load the .JIC file using the Programmer
1. In the main Quartus window in the **Project Navigator** drop-down input select **Files**.
2. Scroll down the window and find the **alphag_feam.cdf**, and double-click it. The **Programmer** window will open
3. Click on the icon labelled **5CGXFC4C6**
4. Click on the **Change File** button. The **Select New Programming File** dialog box will appear
5. Browse to **/\<project_dir\>/bin/** and select **alphag\_feam.jic**
6. Click Open. The **Select New Programming File** dialog box will close
7. In the main panel, check the **Program/Configure** box on the line that starts **./bin/alphag\_feam.jic**
8. Click the **Start** button
9. Wait for the **Progress** bar to go to 100% and stop
10. Done!
</pre>

= Internal test pulser =

Documentation from Bryerton:

<pre>
---------- Forwarded message ---------
From: Bryerton Shaw <bryerton@triumf.ca>
Date: Tue, 24 Apr 2018 at 16:18
Subject: RE: PWB/FEAM internal test pulse
To: Lars Martin <lmartin@triumf.ca>
Cc: Andrea Capra <acapra@triumf.ca>

Hi Lars (and Andrea),

In the new(er) firmware the test pulse code has been modified slightly to
fit in better with the upgraded trigger system. I can add an option to
allow it to be triggered by the external trigger (currently it has an
interval option, or you can hit the manual trigger to fire it, if it’s
enabled)

The *options for the test pulser* are under the *signalproc module*:

*test_pulse_ena*

An array of four booleans, that control turning on the test pulse for each
SCA. If this is False, the other options below will do nothings for that SCA

*test_pulse_interval_ena*

An array of four booleans, that control turning on the interval trigger for
each SCA

*test_pulse_interval*

An unsigned 32-bit value that marks how many 16ns clock cycles occur
between interval triggers. Only one value, as there is only one interval
timer.

*test_pulse_wdt*

An array of four 16-bit unsigned integers that control the width of the
pulse for each SCA when the trigger occurs.

Now, there is a second set of options to control the delay of the *test
pulse interval trigger*. These options are located under the *trigger
module*

*intp_trig_ena*

Boolean value enabling/disabling the interval test pulse trigger.

*intp_trig_delay*

Unsigned 32-bit integer controlling the trigger delay, which is the time
between when the trigger is requested, and when the trigger actually fires.

You can setup the interval trigger and use that to create event packets
with the test pulse on set intervals. If the interval trigger is
insufficient, I can create another option, which is to fire the test pulse
for enabled SCAs when the external trigger goes. If so, I’ll add this
option in the *signalproc *module for you:

*test_pulse_on_ext*

An array of four Booleans, that control if the test pulse for that SCA
fires on external trigger.

Remember, in order to use the SCA test pulse at all, you must also set the
SCA to test mode. You can do this by going into the *sca0-3 modules* and
setting *test* to *functionality *(the value is *3* if you want to set it
via esper-tool)

Btw currently the SCAs are hard-coded to have all 72 channels receive the
test pulse on firing, and the option to de-select/select which channels to
fire is not offered. Would you like this ability? And if so do you want it
to set all four SCAs the same, or have an option for all 288 channels?

The waveform viewer on the webpage was removed for technical reasons, and
so all viewing is done via the MIDAS DAQ. There are some preliminary tools
I’ve created to verify the event packets and their waveforms, but I
wouldn’t call them easy to setup or use at the moment. (Or very useful for
fine comparisons). If KO doesn’t have a way of saving the events to disk, I
could deliver something that captured and saved waveforms quite quickly.

Regards,
Bryerton

*From:* Lars Martin
*Sent:* April 23, 2018 5:10 PM
*To:* Bryerton Shaw <bryerton@triumf.ca>
*Cc:* Andrea Capra <acapra@triumf.ca>
*Subject:* PWB/FEAM internal test pulse

Hi Bryerton,

Andrea and I would like to check the response function of the PWBs. For
that Daryl suggested to first look at the internal test pulse.

Can you point us to what settings are required to make that go? And to use
the external trigger if we want to acquire the data?

Ideally we would acquire Midas data from that, but it's unclear if KO's
frontend allows for that right now. Can we access the data with Esper
instead?

Finally, we haven't had the waveform display on the web page for a while,
but Daryl said you guys use it. Are we using a different page somehow?

Hope all is well with the baby, cheers,

Lars
</pre>

= TODO =

* IMPOSSIBLE (ext clock only connected to clock cleaner) add frequency counter for the external clock (62.5 MHz)
* DONE add random delay before memtest
* DONE add 4 more bits to udp_delay
* DONE fix crash on boot if run is active and triggers arrive (check that trigger is off on boot) (do not set trigger/enable_all, ext_trig_ena, inp_trig_ena, signal_proc/force_run to 1 after boot)
* DONE (kludge jtag uart write()) increase size of jtag uart output buffer, make it unlimited if possible.
* DONE (kludge jtag uart write()) on dhcp timeout, reboot the fpga - reboot of nios does not clear the jtag uart, which becomes full and nios stops.
* DONE add NIOS watchdog timeout for fectrl
* DONE do not use external clock until instructed by fectrl (clock cleaner default is pin select mode, default pin mode is input with pull down, so clock 0 is selected, this is the ext clock. but we can drive clock select pins from the fpga).
* DONE change clock cleaner power up: use the 2 lines status_clkin0 and status_clkin1 to tell clock cleaner to use the internal clock (clkin2) - from the FPGA drive first line low, second line high. Also change all NIOS code that programs the clock cleaner to keep these two lines in the "input" mode. Current code switches them to "output" mode.
* DONE clock cleaner power up state is wrong for both choices of clock: 62.5 MHz ext clock and 125 MHz internal clock, see explanation in feam_top.sv. It looks like I need to drive status_clkin0 and status_clkin1 to "holdover" mode, both logic level 1. Currently status_clkin0 is used as SPI read line, this has to be moved to a different line first.
* add watchdog timeout that works in factory mode ("remote update" watchdog only works in user mode)
* enable HTTP pipelining - copy changes on mongoose from ADC project.
* reset everything if it looks like NIOS TCP/IP code has crashed, but enough code is still running to prevent tripping of the fpga-remote-update watchdog timer. such crash tends to happens when the sata link mate is rebooted and incomplete data arrives from the disrupted ethernet data path.
* DONE when loading AFTER ASIC do not go into infinite loop if read-back is broken (always mismatch).
* read and report error status information bits for 2983fc.pdf
* add provisions for coded trigger

= ZZZ =

ZZZ

Daq

2022-10-17T21:09:02Z

Olchansk: /* Links */

= Links =

* https://alphacpc05.cern.ch/agdaq/ -- midas daq page for the agdaq system at CERN
* https://daq16.triumf.ca -- midas daq page for the agmini system at TRIUMF
* https://daq.triumf.ca/elog-alphag/alphag/ -- elog
* https://daqstore.triumf.ca/AgWiki/index.php/Main_Page -- this wiki
* https://bitbucket.org/expalpha/agdaq - git repository for agdaq
* https://bitbucket.org/expalpha/agana - git repository for agana
* https://bitbucket.org/expalpha -- git repository on bitbucket
* https://edev-group.triumf.ca/fw/exp/alphag -- git repository on edev gitlab

= Inventory database =

* https://ladd00.triumf.ca/daqinv/frontend/list/170 - PWB inventory database
* https://ladd00.triumf.ca/daqinv/frontend/list/168 - ADC (GRIF-16) inventory, FMC-ADC32rev0,rev1 inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/176 - FMC-ADC32rev1.1 inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/174 - BSC RTM inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/173 - BSC ASD inventory

= Hardware manuals =

* [[TRG]] - trigger board (GRIF-C) manual
* CDM - https://daq.triumf.ca/DaqWiki/index.php/VME-CDM -- clock VME-CDM manual
* ADC - https://daq.triumf.ca/DaqWiki/index.php/VME-GRIF-ADC16-Rev1 -- GRIF-16 ADC manual
* [[PWB]] - TPC Pad Wing Board manual
* TDC - https://daq.triumf.ca/DaqWiki/index.php/GSI_TRB3
* [[chronobox]] - chronobox manual
* [[ASD]] - BSC preamp board
* [[RTM]] - BSC VME rear transition board

= Performance =

Full system: (ADC fw rel-20201112-ko, PWB fw 20201005_ko)
* 1 Hz stable, ADC adc32 9 supp off rate 0.3 M/s, adc16 off, PWB udp_delay 25 supp off active 64 rate 6.6+4+6+4.6=21.2 M/s, TDC off, total rate 21 M/s
* 500 Hz stable, ADC adc32 9 supp 1500 rate 6 M/s, adc16 off, PWB udp_delay 10 supp 100 active 63 rate 3+4+3+3=13 M/s, TDC off, total rate 19 M/s

== Single ADC: (fw rel-20201112-ko) ==

Fully suppressed data, sthreshold 5000
* 1 Hz: stable
* 500 Hz: stable (nominal max trigger rate)
* 6700 Hz: stable, 8 Mbytes/sec
* 6800 Hz: evb eventually confused
* 6850 Hz: evb confused, no lost triggers in the ADC, no crash in the ADC

All data, 510 samples/event, sthreshold 10 (fw rel-20201122-ko)
* 1 Hz: stable
* 100 Hz: stable, 3.4 Mbytes/sec
* 500 Hz: stable, 17 Mbytes/sec (nominal max trigger rate)
* 1000 Hz: stable, 32 Mbytes/sec
* 3100 Hz: stable, 106 M/s (approaching saturation of 1gige ethernet)
* 3200 Hz: stable, 110 M/s - TRG communication is in trouble
* 3300 Hz: stable, 116 M/s
* 3400 Hz: incomplete events, no ADC crash ("dropped due to full" counting, "dropped due to busy" are zero, this is as expected).

no suppression (different fpga data path)
* 1 Hz: stable
* 100 Hz: stable
* 500 Hz: stable, 17 M/s (nominal max trigger rate)
* 1000 Hz: stable, 32 M/s
* 3000 Hz: stable, 100 M/s (approaching saturation of 1gige ethernet)
* 3300 Hz: incomplete events, no ADC crash ("dropped due to full" counting, "dropped due to busy" are zero, this is as expected).

== Single PWB, fw 20201005_ko, see https://alphacpc05.cern.ch/elog/Detectors/5563 ==

Fully suppressed data:
* up to 500 Hz, stable

All pads firing (FW pulser)
* 4 SCA: up to 272 Hz, 81.6 Mbytes/sec, at higher rate: event fifo overflow
* 2 SCA: up to 295 Hz, 44.25 Mbytes/sec, at higher rate: event fifo overflow
* 1 SCA: up to 295 Hz, 22.5 Mbytes/sec, at higher rate: event fifo overflow

Conclusion:
* max PWB date rate 80 Mbytes/sec,
* max non-suppressed PWB trigger rate: 295 Hz
* max suppressed PWB trigger rate: 500 Hz (1.6 ms sca readout time)

= Network connections =

The experiment private network number is: 192.168.1.x, gateway 192.168.1.1, netmask 255.255.255.0

network map:
<pre>
---- TRIUMF/CERN network --1gige-- alphagdaq --10gige-- juniper switch --1gige-- centrecom switch
</pre>

== alphagdaq network connections ==

on the rear of the machine:
<pre>
-----------------------------------------
| | rj45 | rj45 | | sfp | sfp |
-----------------------------------------

- left rj45 - copper 1gige - eno1 - spare (inactive)
- right rj45 - copper 1gige - eno2 - dhcp - cern/triumf network
- left sfp - 10gige - enp1s0f1 - spare (inactive)
- right sfp - 10gige - enp1s0f0 - static 192.168.1.1
</pre>

== connections between switches ==

* alphagdaq to juniper switch: direct attach (DAC) 10gige cable into any port of juniper switch
* juniper switch to centrecom switch: rj45 sfp in any port of juniper switch - cat5e/cat6 cable - to any port of centrecom switch
* cat5e/cat6 cable from any port of centrecom switch to the XXX port on the back of the juniper switch

== juniper switch ==

connected to juniper switch front is:

* everything that sends event data to alphagdaq, specifically:
** TRG (rj45 sfp)
** 16x ADC (fiber sfp)
** 64x PWB (fiber sfp)
* 10gige uplink to alphagdaq (10gige DAC cable)
* 1gige link to centrecom switch (rj45 sfp)
* 40gige ports are not used

connected to the juniper switch rear:

* CON is the serial console via RJ45-to-DB9 to USB-serial adapter to alphagdaq USB port (9600bps, 8N1, no flow control)
* C0 is the management ethernet interface port, connect to any port on the centrecom switch (juniper-private will ping)

== centrecom switch ==

* everything with copper rj45 connections, specifically:
** CDM boards
** HV, LV and VME power supplies
** RaspberryPi3 boards
** gas handling MFCs (algas)
** cooling system controller (moxa01)

= USB connections =

Note:
* alphagdaq has USB2 and USB3 connections. They are not the same, they are not generally interchangeable.
* USB3 connections and cables are generally blue coloured.

List of USB connections from alphagdaq:

* front USB3 port (blue): USB-A-to-B cable to USB blaster connected to the trigger board (front of rack)
* rear USB3 port (blue): USB3 short jumper to USB3 hub
* rear USB2 port (black): USB2 unpowered hub (Logiix) to USB-A-to-B cable to UPS USB connector
* rear USB2 port (black): USB-to-Serial adaper to DB9 to RJ45 adapter to Juniper switch console port

Note: UPS USB connection does not work with alphagdaq USB ports (both usb2 and usb3), but combination
using the unpowered USB2 hub seems to work ok.

List of USB connections from the USB hub:

* this is a powered USB3 hub
* USB-A-to-MicroUSB - to lvdb boards
* USB-A-to-Wiener interlock cable

= Clock and trigger distribution =

== Explanation ==

Trigger is generated by the trigger board (aka TRG, aka GRIF-C),
from the TRG eSATA output through the eSATA splitter it is fed into
the master CDM. The master CDM outputs the trigger on all MiniSAS output ports.
One of the master CDM MiniSAS outputs is connected to the CDM slave eSATA input.
The same as the master CDM, the slave CDM outputs the trigger on all MiniSAS output ports.

The master 62.5MHz clock is generated by the master CDM using the internal 10MHz oscillator
or the external 10MHz AD clock. Also on MiniSAS port 6 the master CDM generates
the 200MHz clock for the TDC. This clock is frequency-locked to the master 62.5MHz clock.

Master CDM clock selection (external CD 10MHz clock or internal oscillator 10MHz clock)
is done by a magic esper command (see below).

From the master CDM, the clock is fed to: the slave CDM, the TRG (via the eSATA splitter)
and to the TDC (via the RJ45 splitter).

The slave CDM sends the clock and the trigger to the ADCs and PWBs.

== Chronobox connections ==

Chronoboxes are synchronized with the daq using two signals: 10 MHz timestamp clock and TTL sync.

The sync signal used is the trigger signal - timestamps are reset by the 1st event - which is not a physics event, but the first trigger in the trigger sync sequence.

All chronoboxes are configured in "slave" and "chain" mode.

Slave mode: 10 MHz timestamp clock goes into the CLK_IN input (configured as NIM on the first chronobox and TTL on all others), sync signal goes into TTL input LEMO 4. (bank B direction set to "in").

Chain mode: 10 MHz timestamp clock is TTL output LEMO 0, sync is TTL output LEMO 1. (bank A direction set to "out"). These signals feed into CLK_IN (TTL mode) and TTL input LEMO 4 in the next chronobox in the chain.

The first chronobox receives the 10 MHz timestamp clock and sync signals from the master CDM per diagrams below.

* CDM 10 MHz clock output is NIM, feeds directly into the chronobox CLK_IN (NIM mode).
* CDM "trigger" ("sync") output is NIM, has to go through a NIM-to-TTL converter before feeding chronobox TTL input LEMO 4. I use a LeCroy 222 "gate and delay generator" module. NIM input goes into the "Start" input, TTL output is taken from the "TTL" output. Signal width is adjusted to around 100-1000 ns. Any other sutable NIM-to-TTL converter can also be used.
* "sync" output must be enabled in the master CDM:
<pre>
esper-tool cdm00
cd cdm
write multi_sync 2
</pre>

== Schematic ==

<pre>
TRG (GRIF-C)
------------
eSATA <------> eSATA splitter

eSATA splitter
--------------
trigger ---> eSATA ---> CDM-Master eSATA (trigger signal)
clock <--- (eSATA --- MiniSAS) <--- CDM MiniSAS (62.5MHz clock)
</pre>

<pre>
CDM-Master
----------
LEMO1B <----- 10 MHz AD clock (NIM)
LEMO2A --> (only if there is no external clock) 4ns lemo cable --> LEMO1B (62.5 MHz frequency monitor)
LEMO2B --> chronobox sync (NIM) --> NIM-to-TTL --> long lemo cable to chronobox sync input (TTL)
LEMO3B --> long lemo cable to chronobox clock input (NIM) (CLK_IN configured for NIM input)
eSATA <--- eSATA splitter <--- eSATA from TRG (trigger signal)
MiniSAS 1 --> (MiniSAS --- eSATA) --> CDM-Slave eSATA (62.5 MHz)
MiniSAS 6 --> (MiniSAS --- eSATA) --> eSATA splitter --> RJ45 --> TDC (200 MHz)
</pre>

<pre>
CDM-Slave
---------
LEMO2A --> 4ns lemo cable --> LEMO1B (62.5 MHz frequency monitor)
eSATA <--- trigger and 62.5MHz clock from CDM-Master
MiniSAS 1 --> ADC trigger and 62.5MHz clock
MiniSAS 2 --> same
MiniSAS 3 --> same
MiniSAS 4 --> same
MiniSAS 5 --> PWB trigger and 62.5MHz clock
MiniSAS 6 --> same
</pre>

[[File:VME_Crate_CERN.jpeg|800x450px|Layout of the VME crate at CERN.]]

Layout of the VME crate at CERN. The ALPHA-T module is in the rightmost slot. The Master CDM is next to it and it's labelled as #02. The Slave CDM is on the lefmost position and labelled by #03.

== Setup of CDM boards ==

ALPHA-g uses the Rev3 CDM boards. The 4 CDM boards that belong to ALPHA-g
have serial numbers 0, 1, 2 and 3 and are labeled cdm00, cdm01, cdm02, cdm03.

All the boards can be used as master and slave positions, but have to be
configured appropriately.

=== Slave setup ===

* install the board
* connect ethernet
* connect esata external clock
* esper-tool cdmNN ### i.e. esper-tool cdm01
* cd template
* write current_setup 4
* cd /cdm
* read
* observe clock frequency counters report correct values. "ext_clk" will only count if the lemo jumper is installed (see below)
<pre>
11 esata_clk uint32 R [62500246]
12 ext_clk uint32 R [62500246]
</pre>
* cd /lmk
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
156 ld1_counter uint32 RW [3]
157 ld2_counter uint32 RW [3]
</pre>

If needed, check correct operation of the pll lock monitoring:

* unplug the esata cable from the master CDM
* "red" light should go off
* read of lmk should report "pll1_ld" value 0 and "ld1_counter" and "ld2_counter" should increment
* reconnect the esata cable
* "red" light should return
* read of lmk should report both pll1_ld and pll2_ld locked (values "1").

=== Master setup ===

* install the board
* connect ethernet
* esper-tool cdmNN ### i.e. esper-tool cdm01
* cd template
* write current_setup 3
* cd /lmk
* write clkin_sel_mode 0
* cd /cdm
* read
* observe clock frequency counters report correct values. "ext_clk" will only count if the "clock loopback" lemo jumper is installed (see below)
<pre>
12 ext_clk uint32 R [62500189]
</pre>
* cd /lmk
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
156 ld1_counter uint32 RW [3]
157 ld2_counter uint32 RW [3]
</pre>

Check the 200MHz clock:
* connect MiniSAS-eSATA splitter cable to MiniSAS output 6, connect eSATA end to CDM eSATA input
* in esper-tool, read cdm: esata_clk should report 200MHz clock
<pre>
11 esata_clk uint32 R [200000603]
12 ext_clk uint32 R [62500188]
</pre>

=== Master setup with external 10 MHz clock ===

* setup master CDM as above (using internal clock)
* connect 10MHz external clock to LEMO1A
* esper-tool cdmNN
* cd /cdm
* write sel_nim 1 # if clock is NIM signal
* write sel_nim 0 # if clock is TTL signal (i.e. chronobox LEMO output)
* read ext_clk
<pre>
[http://cdm00:/cdm]> read ext_clk
9999556
</pre>
* if ext_clk reads 0 or does not read something close to 10MHz, stop here. debug the signal, try changing sel_nim, etc.
* cd /lmk
* write clkin_sel_mode 2 # select external clock
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
150 clkin2_sel bool R [True]
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
</pre>
* on the MIDAS TRG page, observe that TRG measured external clock frequency is close to 62.5 MHz

== clkin_sel_mode positions ==

* 0 = 10MHz internal oscillator (use on master CDM in standalone mode)
* 1 = eSATA clock (use on slave CDM)
* 2 = external clock, should be 10MHz (use on master CDM to run from AD clock)

== LEMO connections ==

LEMO connectors:

<pre>
|
|LEMO1A|LEMO1B
|LEMO2A|LEMO2B
|LEMO3A|LEMO3B
|eSATA
|RJ45 ETH
|minisas
|
</pre>

* clock loopback jumper: to read the frequency of the generated 62.5MHz clock, connect LEMO cable from LEMO2B to LEMO1A
* 10MHz internal clock jumper: to feed 10MHz internal oscillator to the external clock, connect LEMO cable from LEMO3A to the LEMO1A
* 10MHz external clock: to feed 10MHz external clock, connect LEMO cable to LEMO1A

= MIDAS frontends =

== UDP ==

feudp receives udp packets from the ADC and PWB boards. For each udp packet 1 midas event is created,
with 1 data bank containing the udp data. Events are sent into the MIDAS event buffer BUFUDP. The names
of the data banks are assigned in ODB /eq/feudp/settings.

{ADC,PWB} --> 1gige --> switch --> 10gige --> alphagdaq --> feudp -> BUFUDP

== CTRL ==

fectrl controls all the ADC, PWB and trigger boards. It provides run start and stop sequencing,
runs the event synchronization sequence at the begin of the run, and records slow controls data (temperatures,
voltages, etc).

fectrl receives UDP data packets from the trigger board and sends them to the MIDAS event buffer BUFUDP.

fectrl receives commands from the control web pages (for ADC, PWB and trigger) to reboot, initialize, etc the boards.

fectrl configures the event builder via odb /eq/fectrl/evbconfig.

ADC <-> http esper <-> fectrl -> slow control data into midas history

PWB <-> http esper <-> fectrl -> slow control data into midas history

TRG <-> udp comm <-> fectrl -> BUFUDP, slow control and counters into midas history

fectrl <-> midas rpc <-> mhttpd <-> json rpc <-> control web pages for ADC, PWB and trigger

== EVB ==

feevb receives udp packet data from the MIDAS event buffer BUFUDP, inspects the packet timestamps
and collects the data with matching timestamps into physics events. feevb has provisions to do
data suppression, reduction and compression in addition to the data reduction done
in the ADC and PWB firmware.

feevb event synchronization relies on the event synchronization sequence done by fectrl when a run is started.

{ADC, PWB, TRG} -> BUFUDP -> feevb -> SYSTEM -> mlogger -> compression -> disk storage

=== internal structure ===

* event buffer readers, instances for BUFTRG, BUFTDC, BUFADC, BUFUDP
<pre>
BufferReader class - reads one midas event buffer:
- BufferReaderThread()
-- in batches of 1000 events
--- lock
--- TickLocked()
----- ReadEvent() -> bm_receive_event_alloc()
----- fHandler->HandleEvent()
-- fHandler->XMaybeFlushBank()
-- sleep 100 usec
</pre>
* event header decoder and intermediate buffer
<pre>
Handler class - accumulates events, sends them to the EVB in batches

- HandleEvent() <- BufferReaderThread() - receive incoming events
-- loop over all banks, examine bank name
--- call AddAdcBank(), AddPwbBank(), AddTrgBank(), AddTdcBank() according to bank name
---- AddXxxBank() -> XAddBank()
--- unknown banks go directly to evb->SendQueue
-- check if synchronization has completed

- XAddBank() - save BankBuf objects in a buffer

- XMaybeFlushBank(), XFlushBank() - send all accumulated data to the Evb class
-- evb->lock()
-- for each buffered BankBuf objects,
--- call evb->AddBankLocked()
-- buffer is now empty
</pre>
* event builder
<pre>
Evb class - assemble event fragments according to timestamps

- fEvents fifo (deque) - time sorted list of partially assembled events
-- new entries are added by FindEvent()
-- entries are modified by MergeSlot()
-- old entries are removed by GetLocked()

- AddBankLocked() <- XFlushBank() <- BufferReaderThread()
-- call fSync->Add()
-- transform BankBuf to EvbEventBuf
-- push it into per-module buffer fBuf[imodule]

- EvbThread()
-- EvbTickLocked()
--- BuildLocked()
---- in a loop, for no more than 1 sec
----- loop over all per-module buffers fBuf
------ pop first entry, pass it to BuildSlot()
------- call FindEvent()
------- call MergeSlot()
------- call CheckEvent()
--- in a loop
---- get all completed events via GetLocked() pass them to SendQueue->PushEvent()
-- if done nothing, sleep 100 usec, otherwise nominal sleep to free the evb lock

- GetNext() <- GetLocked() <- EvbThread() - get completed events
-- examine oldest EvbEvent entry in fEvents:
-- pop it if it is complete
-- pop it if it is too old (to prevent old incomplete events from stalling the evb) ("pop age" on the evb page)
-- pop it if a following event is complete ("pop following" on the evb page)
</pre>
* send queue
<pre>
SendQueue class - prepare events for writing to midas SYSTEM event buffer

- PushEvent() <- EvbThread()
-- push FragmentBuf into the queue

- SendQueueThread()
-- in a batch of 1000 events, call Tick()
--- pop FragmentBuf from the queue, call SendEvent()
--- compose midas event (memcpy()!)
--- TMFE fEq->SendEvent()
--- bm_send_event()
-- sleep 100 usec
</pre>
* equipment object
<pre>
EvbEq class - implements the midas equipment
- HandleBeginRun()
- HandleEndRun()
- HandlePeriodic()
</pre>

=== multithreading ===

* BufferReaderThread() one per midas event buffer
** high CPU use: bm_receive_event(), AddXxxBank()
** lock contention: midas event buffer lock, evb lock into XFlushBank->AddBankLocked()
* EvbThread()
** O(size of fEvents): FindEvent(), GetNext()
** lock contention: evb lock against XFlushBank(), SendQueue lock (1 per output event)
* SendQueueThread()
** high CPU use: memcpy() in SendEvent(), memcpy() in bm_send_event
** lock contention: event queue lock against EvbThread, midas event buffer lock
* main thread
** lock contention: evb lock in ReportEvb() and elsewhere

= ODB entries =

== /Equipment/CTRL/Settings ==
* TBW

== /Equipment/CTRL/Settings/Pulser ==

* ClockFreqHz - unit of 1/sec (Hz), set to 62500000, the TRG 62.5 MHz clock frequency (16 ns)
* PulseWidthClk - unit of 16 ns clocks, set to 25. (400 ns). width of internal pulser signal (used to go to a TRG external output, absent on GRIF-C boards)
* PulsePeriodClk - unit of 16 ns clocks, pulser in clock periods (+1), set to zero.
* PulseFreqHz - unit of 1/sec (Hz), requested pulser frequency, actual frequency is rounded to 16 ns clock granularity, change this value to select desired clock frequency
* BurstCtrl - enable burst of pulses 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses
* OutputEnable - enable TRG pulser external output (absent on GRIF-C boards)
* Enable - allow the pulser to run (bit 3 in TRG conf_trig_enable register)

== /Equipment/CTRL/Settings/TrigSrc - trigger source selection ==
* TrigPulser - trigger on the pulser
* TrigEsataNimGrandOr - trigger on external NIM inputs of GRIF-16 ADC modules
* TrigAdc16GrandOr - trigger on any adc16 signals (see adc16_masks)
* TrigAdc32GrandOr - trigger on any adc32 signals (see adc32_masks)
* TrigAdcGrandOr - trigger on adc16_grand_or or adc32_grand_or
* (removed from trg firmware) Trig1ormore - trigger on adc16 multiplicity 1 or more
* (removed from trg firmware) Trig2ormore - ditto, 2 or more
* (removed from trg firmware) Trig3ormore - ditto, 3 or more
* (removed from trg firmware) Trig4ormore - ditto, 4 or more
* (removed from trg firmware) TrigAwCoincA - trigger on TPC AW coincidence (see [[TRG]] manual)
* (removed from trg firmware) TrigAwCoincB - ditto
* (removed from trg firmware) TrigAwCoincC - ditto
* (removed from trg firmware) TrigAwCoincD - ditto
* (removed from trg firmware) TrigAwCoinc - ditto
* (removed from trg firmware) TrigAw1ormore - trigger on TPC AW per-preamp multiplicity 1 or more (see [[TRG]] manual)
* (removed from trg firmware) TrigAw2ormore - ditto, 2 or more
* (removed from trg firmware) TrigAw3ormore - ditto, 3 or more
* (removed from trg firmware) TrigAw4ormore - ditto, 4 or more
* TrigAwMLU - trigger on TPC AW MLU signal (see [[TRG]] manual)
* TrigBscGrandOr - trigger on any BSC signal
* TrigBscMult - trigger on predefined BSC multiplicity (see [[TRG]] manual)
* TrigCoinc - trigger on predefined coincidence of TPC AW, BSC and external signal (see [[TRG]] manual)

== /Equipment/CTRL/Settings/TRG - trigger settings ==
* Enable - if set to "n", fectrl will not do anything with the trigger board. Normal value "y"
* Modules - hostnames of the trigger board. Normal value "alphat01"
* NimMask - 32-bit mask for the 32x NIM inputs (see TRG manual). Normal value 0, unless external trigger is in use.
* EsataMask - 32-bit mask for the 32x eSATA signals (see TRG manual). Normal value 0.
* adc16_mask[16] - 16x 16-bit mask for the 100MHz GRIF-16 onboard ADCs (see TRG manual). Normal value 0xFFFF for all 16 sas links.
* adc32_mask[16] - 16x 32-bit mask for the 62.5MHz FMC-ADC32 ADCs (see TRG manual). Normal value 0xFFFFFFFF for all 16 sas links.
* PassThrough - if set to "y", trigger is passed through the trigger module without generating any events and without causing deadtime.
* AwCoincA, B, C and D - 32-bit masks for the aw16 coincidence trigger (see TRG manual)
* Aw16FromAdc16 - route AW trigger (aw16) from adc16 (100MHz ADCs 0..15)
* Aw16FromAdc32a - route AW trigger (aw16) from adc32 group 15..0 (62.5MHz FMC-ADC32 minisas links 0..7)
* Aw16FromAdc32b - route AW trigger (aw16) from adc32 group 31..16 (62.5MHz FMC-ADC32 minisas links 8..15)
* MluDir, MluFiles - location of aw16 MLU bit patterns
* MluSelectedFile - currently selected/loaded MLU file. 0="grand or", 1="2 or more hit clusters", 2="2 or more hit clusters, with gap 2 or more", 3="3 or more hit clusters"
* MluPrompt - length of aw16_prompt_run gate in units of 8 ns clock, see [[TRG#aw16_mlu]]
* MluWait - length of aw_prompt_wait gate in units of 8 ns clock, see [[TRG#aw16_mlu]]
* MluTrigDelayClk - "TrigDelay" when triggered of aw16 MLU, in units of 16 ns clock
* (BSC settings, TBW)
* BscFromAdc16a - (at CERN, set to "y") route BSC trigger data (bsc64_bus) from 100 MHz adc16 digitizers minisas links 0..7
* BscFromAdc16b - route BSC trigger data (bsc64_bus) from 100 MHz adc16 digitizers minisas links 8..15
* BscBotOnly - route BSC trigger data from bottom ASD cards, bsc64_bus = bot
* BscTopOnly - route BSC trigger data from top ASD cards, bsc64_bus = top
* BscBotTopOr - (set to "y") use bsc64_bus = (top OR bottom)
* BscBotTopAnd - use bsc64_bus = (top AND bottom)
* BscMultiplicityMin - (set to 2) BSC multiplicity trigger - minimum multiplicity
* BscMultiplicityWindowClk8 - (set to 80) BSC multiplicity window, 8 ns clocks
* BscEmptyWindowClk8 - (set to 80) BSC empty window, 8 ns clocks, see [[TRG#bsc64_multiplicity_trigger]]
* BscGrandOrDelayClk16 - (not implemented) trigger delay used by fectrl when TrigSrc/TrigBscGrandOr is selected
* BscMultTrigDelayClk16 - trigger delay used by fectrl when TrigSrc/TrigBscMult is selected
* CoincStart - set same as CoincRequire
* CoincRequire - 0x5: (BSC grand or)*(TPC aw16_grand_or), 0x9: (BSC multiplicity)*(TWC aw16_grand_or), 0x6: (BSC grand or)*(AW16 MLU), see [[TRG#Coincidence_trigger]] and [[TRG#conf_coinc_control bits]]
* CoincWindow - length of coincidence window in 8ns clocks.
* CoincTrigDelayClk16 - trigger delay used by fectrl when TrigSrc/TrigCoinc is selected

== /Equipment/CTRL/Settings/PWB - PWB settings ==
* Enable - if set to "n", fectrl will not do anything with PWBs. Normal value "y".
* enable_boot_user_page - if set to "n", fectrl will not try to reboot PWBs into the user page firmware. Normal value "y".
* enable_trigger - if set to "n", all PWBs will be set to ignore the trigger. Normal value "y".
* enable_trigger_group_a - field wire pulser defeats the data suppression (every channel has a pulse) resulting in too much data overwhelming the DAQ (lost UDP packets). To permit correct data taking of field wire pulser data, PWBs are split into two groups (a and b), only one of the two groups should be enabled for field wire pulser runs. Both groups should be enabled for normal data taking. Normal value is "y"
* enable_trigger_group_b - see "enable_trigger_group_a". Normal value is "y".
* modules[64] - hostnames of PWB boards
* boot_user_page[64] - if set to "y" and enable_boot_user_page is "y", fectrl will reboot the corresponding PWB to the user page firmware.
* trigger[64] - if set to "y" and enable_trigget is "y", fectrl will set the PWB to accept the trigger.
* ch_enable - if set to "n" disables all PWB channels. Normal value is "y".
* ch_force - is set to "y" disables channel suppression (all PWB channels are read)
* suppress_reset - if set to "y" enables channel suppression for reset channels (threshold has to be set correctly)
* suppress_fpn - if set to "y" enables channel suppression for fpn channels (threshold has to be set correctly)
* suppress_pads - set to "y" enables channel suppression for TPC pad channels (threshold has to be set correctly)
* disable_reset1 - data suppression algorithm does not work for the channel "reset1" and it has to be suppressed explicitly by setting this value to "y". Normal value is "y".
* baseline_{reset,fpn,pads}[64] - waveform baseline for each PWB position
* threshold_{reset,fpn,pads} - waveform suppression threshold, see below:
* ch_threshold - PWB sca_N_ch_threshold, if set to 0, threshold is computed as "baseline_pads[seqpwb]-threshold_pads". Normal value is 0.
* test_mode - enable PWB test mode, the ADC data is replaced with a test pattern, see PWB esper variable signalproc/test_mode

== /Equipment/CTRL/Settings/TDC - TDC settings ==
* Enable - if set to "n", fectrl will tell the event builder that the TDC is not running. Normal value is "y".

== /Equipment/CTRL/Variables ==

* Scalers - TRG scalers and counters. from fectrl.cxx ReadTrgLocked()
<pre>
// 0..15 read the 16 base scalers at 0x100
// 16..31 read the adc16 scalers at 0x430
// 32..63 read the adc32 scalers at 0x440
// 64..79 read the 16 additional scalers at 0x110
// 80..95 read the 16 counters_adc_selected scalers at 0x460
// 96..159 read the 64 bar scalers at 0x470
// additional scalers should be appended at the end.
</pre>

== /Equipment/CTRL/EvbConfig - EVB configuration ==
All arrays have the same size corresponding to the number of EVB slots.
* name[] - slot name for the web page (trg01, adc01, adc01/adc32, pwb31/0, tdc01, etc)
* type[] - slot type: 1=TRG, 2=ADC16 and ADC32, 3=obsolete PWB, 4=obsolete PWB, 5=PWB, 6=TDC
* module[] - module number (adcNN, adcNN+100, pwbNN, etc)
* nbanks[] - number of expected banks (16 for ADC16, 32 for ADC32, not used, set to 1 for all others)
* tsfreq[] - timestamp frequency in Hz.

== /Equipment/ADC_UDP - ADC UDP configuration ==

* Common/Buffer - "BUFADC" - event buffer to use, name is hardwired in feevb.cxx
* Settings/udp_port - 50006 - UDP port number, also used by fectrl to configure the ADC modules
* Settings/rcv_bufsize - 209715200 - udp socket buffer size set by setsockopt(SOL_SOCKET, SO_RCVBUF). must have a corresponding command in /etc/rc.local to increase maximum system socket size: "/usr/sbin/sysctl -w net.core.rmem_max=200000000"
* Settings/packet_size - 1500 - non-jumbo-frame UDP packet maximum size
* Settings/max_buffered_packets - 40000 - maximum size of internal packet fifo. If it overflows, extra packets are discarded.
* Settings/max_packets_per_event - 8000 - how many UDP packets to pack into one midas event==

== /Equipment/PWB_X_UDP - PWB UDP configuration ==

For explanation see ADC_UDP above.

* Common/Buffer - "BUFUDP" - event buffer to use, name is hardwired in feevb.cxx
* Settings/udp_port - 50007, 50008, 50009, 50010 - for A, B, C and D UDP receivers respectively, also used by fectrl to configure the PWB modules
* Settings/rcv_bufsize - 209715200
* Settings/packet_size - 1500
* Settings/max_buffered_packets - 10000
* Settings/max_packets_per_event - 8000

= Trigger configuration =

These trigger modes are implemented:
* (manual trigger from web page)
* software pulser trigger (from fectrl)
* hardware pulser trigger (from the trigger board)
* NIM and eSATA trigger from ADC front panel inputs
* adc16 and adc32 discriminator triggers:
** adc16 grand-or trigger
** adc32 grand-or trigger
** adc (adc16+adc32) grand-or trigger
** adc16 multiplicity trigger (1ormore, 2ormore, 3ormore, 4ormore) for use with barrel scintillator
** anode wire multiplicity trigger (1ormore, 2ormore, 3ormore, 4ormore) (anode wire signals can be fed from adc16 or from adc32 signals)
** anode wire coincidence trigger
** anode wire MLU (memory lookup) trigger

== NIM trigger from ADC front panel ==

Trigger path:
<pre>
NIM signal --> LEMO input on ADC front panel --> data encoder --> data link to trigger board --> data decoder --> mask --> nim-esata-grand-or --> trigger
</pre>

To enable NIM trigger, do this:
* connect NIM signal to ADC front panel input
** Note1: NIM signal must be inverted
** Note2: LEMO connectors should be set to "NIM input" mode by ADC on-board jumpers (see ADC manual)
* observe correct bit goes to zero in the TRG web page: data link high work should change:
<pre>
0xNF00'0000 (N is the module id) to
0xN700'0000 (left lemo) or
0xNB00'0000 (right lemo)
</pre>
* Note3: if data link bits do not change, most likely the LEMO connectors are set to "DAC output" mode. Try to use LEMO inputs of a different ADC.
* compute the NIM mask: there are 32 bits, 2 bits per ADC data link. Bit 0x1 is right LEMO, bit 0x2 is left LEMO
* for example, to use left LEMO of ADC data link 12, set nim mask to (0x2)<<(2*12) = 0x02000000
* development branch of the git repository contains ''scripts/nim_mask.py'', which can compute forwards and backwards
* initialize the trigger board (on the TRG web page press button "initialize"), or start a new run
* on the history plot with "NIM grand or" counter, the rate should change from zero
* if a run is active, if one of the ADC LEMO outputs is set to output the trigger signal as a NIM pulse, one should see it fire use a scope. The delay or jitter between NIM trigger in and NIM trigger out should be around 100-200 ns (FIXME - measure this!)
* to set the DAQ to trigger on the NIM signal, on the run start page, check the box "TrigEsataNimGrandOr".
** Note: remember to set the scaledown to 0 if so desired.

= TPC field wire pulser =

The TPC field wire pulser input should be connected directly to the DAC output of ADC[0] (right lemo connector).

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for pulsing PWBs, baseline -1V, pulse height +2V (maximum possible pulse height in PWBs. Overdrives the AW ADC waveforms)
** dac_baseline: -8000
** dac_amplitude: 8000
** ramp_up_rate: 128
** ramp_down_rate: 70
** ramp_top_len: 128

* for pulsing AW, baseline -0.25V, pulse height +0.7V (AW ADC waveforms are in range. PWB waveforms are too small for goor time resolution)
** dac_baseline: -2000
** dac_amplitude: 4000
** ramp_up_rate: 20
** ramp_down_rate: 20
** ramp_top_len: 128

= BSC pulser =

The BSC pulser input on the BSC VME rear transition board (RTM) should be connected directly to the DAC output of ADC[4,5,6,7] (right lemo connector). (8 RTMs, but 4 ADCs, each signal is split using a LEMO "T" connector).

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for pulsing BSC, baseline -0.950V, pulse height +1.4V
** dac_baseline: -8000
** dac_amplitude: 4000
** ramp_up_rate: 64
** ramp_down_rate: 64
** ramp_top_len: 128

= NIM output =

To configure ADC analog output for NIM compatible pulse:

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for output of NIM pulse: baseline 0V, pulse height -0.9V, pulse width 100 ns
** dac_baseline: 0
** dac_amplitude: 8000
** ramp_up_rate: 128
** ramp_down_rate: 128
** ramp_top_len: 4
** dac_xor: 1 (invert the signal)

= TDC connections =

* SFP8 - fiber SFP to Juniper switch
* right RJ45 - 200MHz clock
* left RJ45 - external trigger

= MIDAS Data banks =

* ATAT - fectrl - UDP packets from GRIF-C/TRG trigger board
* TRBA - fetdc - TDC data
* TRTM - fetdc - TDC FPGA temperatures, TID_FLOAT[5].
* AAnn - feudp - UDP packets from GRIF-16 ADC (before the event builder), "nn" is the ADC module number: adc01 is AA01 through adc20 is AA20.
* BBxx - feudp - UDP packets from PWB, obsolete
* Bnnm, Cnnm - feevb - EVB output banks: ADC data, "nn" is the ADC module number (1..20), "m" is the channel number (0..9,A..F), format is same as AAnn banks.
* PAnn - feudp - UDP packets from PWB, "nn" is the PWB module number (00..99), obsolete
* PBnn - feudp - UDP packets from PWB, "nn" is the PWB module number (00..99), PB01 is pwb01, PB78 is pwb78
* PCnn - feevb - EVB output banks: PWB data, "nn" is the PWB module number (00..99), same as above, format is same as PBnn banks

= ZZZ =

ZZZ

User talk:Ina

2022-09-20T16:50:20Z

Olchansk: Welcome!

'''Welcome to ''AgWiki''!'''
We hope you will contribute much and well.
You will probably want to read the [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents help pages].
Again, welcome and have fun! [[User:Olchansk|Olchansk]] ([[User talk:Olchansk|talk]]) 09:50, 20 September 2022 (PDT)

Daq

2022-07-25T22:46:23Z

Olchansk: /* Performance */

= Links =

* https://alphacpc05.cern.ch/agdaq/ -- midas daq page for the agdaq system at CERN
* https://daq16.triumf.ca -- midas daq page for the agmini system at TRIUMF
* https://daq.triumf.ca/elog-alphag/alphag/ -- elog
* https://daqstore.triumf.ca/AgWiki/index.php/Main_Page -- this wiki
* https://bitbucket.org/ttriumfdaq/agdaq - git repository for agdaq
* https://bitbucket.org/expalpha -- git repository on bitbucket
* https://edev-group.triumf.ca/fw/exp/alphag -- git repository on edev gitlab

= Inventory database =

* https://ladd00.triumf.ca/daqinv/frontend/list/170 - PWB inventory database
* https://ladd00.triumf.ca/daqinv/frontend/list/168 - ADC (GRIF-16) inventory, FMC-ADC32rev0,rev1 inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/176 - FMC-ADC32rev1.1 inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/174 - BSC RTM inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/173 - BSC ASD inventory

= Hardware manuals =

* [[TRG]] - trigger board (GRIF-C) manual
* CDM - https://daq.triumf.ca/DaqWiki/index.php/VME-CDM -- clock VME-CDM manual
* ADC - https://daq.triumf.ca/DaqWiki/index.php/VME-GRIF-ADC16-Rev1 -- GRIF-16 ADC manual
* [[PWB]] - TPC Pad Wing Board manual
* TDC - https://daq.triumf.ca/DaqWiki/index.php/GSI_TRB3
* [[chronobox]] - chronobox manual
* [[ASD]] - BSC preamp board
* [[RTM]] - BSC VME rear transition board

= Performance =

Full system: (ADC fw rel-20201112-ko, PWB fw 20201005_ko)
* 1 Hz stable, ADC adc32 9 supp off rate 0.3 M/s, adc16 off, PWB udp_delay 25 supp off active 64 rate 6.6+4+6+4.6=21.2 M/s, TDC off, total rate 21 M/s
* 500 Hz stable, ADC adc32 9 supp 1500 rate 6 M/s, adc16 off, PWB udp_delay 10 supp 100 active 63 rate 3+4+3+3=13 M/s, TDC off, total rate 19 M/s

== Single ADC: (fw rel-20201112-ko) ==

Fully suppressed data, sthreshold 5000
* 1 Hz: stable
* 500 Hz: stable (nominal max trigger rate)
* 6700 Hz: stable, 8 Mbytes/sec
* 6800 Hz: evb eventually confused
* 6850 Hz: evb confused, no lost triggers in the ADC, no crash in the ADC

All data, 510 samples/event, sthreshold 10 (fw rel-20201122-ko)
* 1 Hz: stable
* 100 Hz: stable, 3.4 Mbytes/sec
* 500 Hz: stable, 17 Mbytes/sec (nominal max trigger rate)
* 1000 Hz: stable, 32 Mbytes/sec
* 3100 Hz: stable, 106 M/s (approaching saturation of 1gige ethernet)
* 3200 Hz: stable, 110 M/s - TRG communication is in trouble
* 3300 Hz: stable, 116 M/s
* 3400 Hz: incomplete events, no ADC crash ("dropped due to full" counting, "dropped due to busy" are zero, this is as expected).

no suppression (different fpga data path)
* 1 Hz: stable
* 100 Hz: stable
* 500 Hz: stable, 17 M/s (nominal max trigger rate)
* 1000 Hz: stable, 32 M/s
* 3000 Hz: stable, 100 M/s (approaching saturation of 1gige ethernet)
* 3300 Hz: incomplete events, no ADC crash ("dropped due to full" counting, "dropped due to busy" are zero, this is as expected).

== Single PWB, fw 20201005_ko, see https://alphacpc05.cern.ch/elog/Detectors/5563 ==

Fully suppressed data:
* up to 500 Hz, stable

All pads firing (FW pulser)
* 4 SCA: up to 272 Hz, 81.6 Mbytes/sec, at higher rate: event fifo overflow
* 2 SCA: up to 295 Hz, 44.25 Mbytes/sec, at higher rate: event fifo overflow
* 1 SCA: up to 295 Hz, 22.5 Mbytes/sec, at higher rate: event fifo overflow

Conclusion:
* max PWB date rate 80 Mbytes/sec,
* max non-suppressed PWB trigger rate: 295 Hz
* max suppressed PWB trigger rate: 500 Hz (1.6 ms sca readout time)

= Network connections =

The experiment private network number is: 192.168.1.x, gateway 192.168.1.1, netmask 255.255.255.0

network map:
<pre>
---- TRIUMF/CERN network --1gige-- alphagdaq --10gige-- juniper switch --1gige-- centrecom switch
</pre>

== alphagdaq network connections ==

on the rear of the machine:
<pre>
-----------------------------------------
| | rj45 | rj45 | | sfp | sfp |
-----------------------------------------

- left rj45 - copper 1gige - eno1 - spare (inactive)
- right rj45 - copper 1gige - eno2 - dhcp - cern/triumf network
- left sfp - 10gige - enp1s0f1 - spare (inactive)
- right sfp - 10gige - enp1s0f0 - static 192.168.1.1
</pre>

== connections between switches ==

* alphagdaq to juniper switch: direct attach (DAC) 10gige cable into any port of juniper switch
* juniper switch to centrecom switch: rj45 sfp in any port of juniper switch - cat5e/cat6 cable - to any port of centrecom switch
* cat5e/cat6 cable from any port of centrecom switch to the XXX port on the back of the juniper switch

== juniper switch ==

connected to juniper switch front is:

* everything that sends event data to alphagdaq, specifically:
** TRG (rj45 sfp)
** 16x ADC (fiber sfp)
** 64x PWB (fiber sfp)
* 10gige uplink to alphagdaq (10gige DAC cable)
* 1gige link to centrecom switch (rj45 sfp)
* 40gige ports are not used

connected to the juniper switch rear:

* CON is the serial console via RJ45-to-DB9 to USB-serial adapter to alphagdaq USB port (9600bps, 8N1, no flow control)
* C0 is the management ethernet interface port, connect to any port on the centrecom switch (juniper-private will ping)

== centrecom switch ==

* everything with copper rj45 connections, specifically:
** CDM boards
** HV, LV and VME power supplies
** RaspberryPi3 boards
** gas handling MFCs (algas)
** cooling system controller (moxa01)

= USB connections =

Note:
* alphagdaq has USB2 and USB3 connections. They are not the same, they are not generally interchangeable.
* USB3 connections and cables are generally blue coloured.

List of USB connections from alphagdaq:

* front USB3 port (blue): USB-A-to-B cable to USB blaster connected to the trigger board (front of rack)
* rear USB3 port (blue): USB3 short jumper to USB3 hub
* rear USB2 port (black): USB2 unpowered hub (Logiix) to USB-A-to-B cable to UPS USB connector
* rear USB2 port (black): USB-to-Serial adaper to DB9 to RJ45 adapter to Juniper switch console port

Note: UPS USB connection does not work with alphagdaq USB ports (both usb2 and usb3), but combination
using the unpowered USB2 hub seems to work ok.

List of USB connections from the USB hub:

* this is a powered USB3 hub
* USB-A-to-MicroUSB - to lvdb boards
* USB-A-to-Wiener interlock cable

= Clock and trigger distribution =

== Explanation ==

Trigger is generated by the trigger board (aka TRG, aka GRIF-C),
from the TRG eSATA output through the eSATA splitter it is fed into
the master CDM. The master CDM outputs the trigger on all MiniSAS output ports.
One of the master CDM MiniSAS outputs is connected to the CDM slave eSATA input.
The same as the master CDM, the slave CDM outputs the trigger on all MiniSAS output ports.

The master 62.5MHz clock is generated by the master CDM using the internal 10MHz oscillator
or the external 10MHz AD clock. Also on MiniSAS port 6 the master CDM generates
the 200MHz clock for the TDC. This clock is frequency-locked to the master 62.5MHz clock.

Master CDM clock selection (external CD 10MHz clock or internal oscillator 10MHz clock)
is done by a magic esper command (see below).

From the master CDM, the clock is fed to: the slave CDM, the TRG (via the eSATA splitter)
and to the TDC (via the RJ45 splitter).

The slave CDM sends the clock and the trigger to the ADCs and PWBs.

== Chronobox connections ==

Chronoboxes are synchronized with the daq using two signals: 10 MHz timestamp clock and TTL sync.

The sync signal used is the trigger signal - timestamps are reset by the 1st event - which is not a physics event, but the first trigger in the trigger sync sequence.

All chronoboxes are configured in "slave" and "chain" mode.

Slave mode: 10 MHz timestamp clock goes into the CLK_IN input (configured as NIM on the first chronobox and TTL on all others), sync signal goes into TTL input LEMO 4. (bank B direction set to "in").

Chain mode: 10 MHz timestamp clock is TTL output LEMO 0, sync is TTL output LEMO 1. (bank A direction set to "out"). These signals feed into CLK_IN (TTL mode) and TTL input LEMO 4 in the next chronobox in the chain.

The first chronobox receives the 10 MHz timestamp clock and sync signals from the master CDM per diagrams below.

* CDM 10 MHz clock output is NIM, feeds directly into the chronobox CLK_IN (NIM mode).
* CDM "trigger" ("sync") output is NIM, has to go through a NIM-to-TTL converter before feeding chronobox TTL input LEMO 4. I use a LeCroy 222 "gate and delay generator" module. NIM input goes into the "Start" input, TTL output is taken from the "TTL" output. Signal width is adjusted to around 100-1000 ns. Any other sutable NIM-to-TTL converter can also be used.
* "sync" output must be enabled in the master CDM:
<pre>
esper-tool cdm00
cd cdm
write multi_sync 2
</pre>

== Schematic ==

<pre>
TRG (GRIF-C)
------------
eSATA <------> eSATA splitter

eSATA splitter
--------------
trigger ---> eSATA ---> CDM-Master eSATA (trigger signal)
clock <--- (eSATA --- MiniSAS) <--- CDM MiniSAS (62.5MHz clock)
</pre>

<pre>
CDM-Master
----------
LEMO1B <----- 10 MHz AD clock (NIM)
LEMO2A --> (only if there is no external clock) 4ns lemo cable --> LEMO1B (62.5 MHz frequency monitor)
LEMO2B --> chronobox sync (NIM) --> NIM-to-TTL --> long lemo cable to chronobox sync input (TTL)
LEMO3B --> long lemo cable to chronobox clock input (NIM) (CLK_IN configured for NIM input)
eSATA <--- eSATA splitter <--- eSATA from TRG (trigger signal)
MiniSAS 1 --> (MiniSAS --- eSATA) --> CDM-Slave eSATA (62.5 MHz)
MiniSAS 6 --> (MiniSAS --- eSATA) --> eSATA splitter --> RJ45 --> TDC (200 MHz)
</pre>

<pre>
CDM-Slave
---------
LEMO2A --> 4ns lemo cable --> LEMO1B (62.5 MHz frequency monitor)
eSATA <--- trigger and 62.5MHz clock from CDM-Master
MiniSAS 1 --> ADC trigger and 62.5MHz clock
MiniSAS 2 --> same
MiniSAS 3 --> same
MiniSAS 4 --> same
MiniSAS 5 --> PWB trigger and 62.5MHz clock
MiniSAS 6 --> same
</pre>

[[File:VME_Crate_CERN.jpeg|800x450px|Layout of the VME crate at CERN.]]

Layout of the VME crate at CERN. The ALPHA-T module is in the rightmost slot. The Master CDM is next to it and it's labelled as #02. The Slave CDM is on the lefmost position and labelled by #03.

== Setup of CDM boards ==

ALPHA-g uses the Rev3 CDM boards. The 4 CDM boards that belong to ALPHA-g
have serial numbers 0, 1, 2 and 3 and are labeled cdm00, cdm01, cdm02, cdm03.

All the boards can be used as master and slave positions, but have to be
configured appropriately.

=== Slave setup ===

* install the board
* connect ethernet
* connect esata external clock
* esper-tool cdmNN ### i.e. esper-tool cdm01
* cd template
* write current_setup 4
* cd /cdm
* read
* observe clock frequency counters report correct values. "ext_clk" will only count if the lemo jumper is installed (see below)
<pre>
11 esata_clk uint32 R [62500246]
12 ext_clk uint32 R [62500246]
</pre>
* cd /lmk
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
156 ld1_counter uint32 RW [3]
157 ld2_counter uint32 RW [3]
</pre>

If needed, check correct operation of the pll lock monitoring:

* unplug the esata cable from the master CDM
* "red" light should go off
* read of lmk should report "pll1_ld" value 0 and "ld1_counter" and "ld2_counter" should increment
* reconnect the esata cable
* "red" light should return
* read of lmk should report both pll1_ld and pll2_ld locked (values "1").

=== Master setup ===

* install the board
* connect ethernet
* esper-tool cdmNN ### i.e. esper-tool cdm01
* cd template
* write current_setup 3
* cd /lmk
* write clkin_sel_mode 0
* cd /cdm
* read
* observe clock frequency counters report correct values. "ext_clk" will only count if the "clock loopback" lemo jumper is installed (see below)
<pre>
12 ext_clk uint32 R [62500189]
</pre>
* cd /lmk
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
156 ld1_counter uint32 RW [3]
157 ld2_counter uint32 RW [3]
</pre>

Check the 200MHz clock:
* connect MiniSAS-eSATA splitter cable to MiniSAS output 6, connect eSATA end to CDM eSATA input
* in esper-tool, read cdm: esata_clk should report 200MHz clock
<pre>
11 esata_clk uint32 R [200000603]
12 ext_clk uint32 R [62500188]
</pre>

=== Master setup with external 10 MHz clock ===

* setup master CDM as above (using internal clock)
* connect 10MHz external clock to LEMO1A
* esper-tool cdmNN
* cd /cdm
* write sel_nim 1 # if clock is NIM signal
* write sel_nim 0 # if clock is TTL signal (i.e. chronobox LEMO output)
* read ext_clk
<pre>
[http://cdm00:/cdm]> read ext_clk
9999556
</pre>
* if ext_clk reads 0 or does not read something close to 10MHz, stop here. debug the signal, try changing sel_nim, etc.
* cd /lmk
* write clkin_sel_mode 2 # select external clock
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
150 clkin2_sel bool R [True]
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
</pre>
* on the MIDAS TRG page, observe that TRG measured external clock frequency is close to 62.5 MHz

== clkin_sel_mode positions ==

* 0 = 10MHz internal oscillator (use on master CDM in standalone mode)
* 1 = eSATA clock (use on slave CDM)
* 2 = external clock, should be 10MHz (use on master CDM to run from AD clock)

== LEMO connections ==

LEMO connectors:

<pre>
|
|LEMO1A|LEMO1B
|LEMO2A|LEMO2B
|LEMO3A|LEMO3B
|eSATA
|RJ45 ETH
|minisas
|
</pre>

* clock loopback jumper: to read the frequency of the generated 62.5MHz clock, connect LEMO cable from LEMO2B to LEMO1A
* 10MHz internal clock jumper: to feed 10MHz internal oscillator to the external clock, connect LEMO cable from LEMO3A to the LEMO1A
* 10MHz external clock: to feed 10MHz external clock, connect LEMO cable to LEMO1A

= MIDAS frontends =

== UDP ==

feudp receives udp packets from the ADC and PWB boards. For each udp packet 1 midas event is created,
with 1 data bank containing the udp data. Events are sent into the MIDAS event buffer BUFUDP. The names
of the data banks are assigned in ODB /eq/feudp/settings.

{ADC,PWB} --> 1gige --> switch --> 10gige --> alphagdaq --> feudp -> BUFUDP

== CTRL ==

fectrl controls all the ADC, PWB and trigger boards. It provides run start and stop sequencing,
runs the event synchronization sequence at the begin of the run, and records slow controls data (temperatures,
voltages, etc).

fectrl receives UDP data packets from the trigger board and sends them to the MIDAS event buffer BUFUDP.

fectrl receives commands from the control web pages (for ADC, PWB and trigger) to reboot, initialize, etc the boards.

fectrl configures the event builder via odb /eq/fectrl/evbconfig.

ADC <-> http esper <-> fectrl -> slow control data into midas history

PWB <-> http esper <-> fectrl -> slow control data into midas history

TRG <-> udp comm <-> fectrl -> BUFUDP, slow control and counters into midas history

fectrl <-> midas rpc <-> mhttpd <-> json rpc <-> control web pages for ADC, PWB and trigger

== EVB ==

feevb receives udp packet data from the MIDAS event buffer BUFUDP, inspects the packet timestamps
and collects the data with matching timestamps into physics events. feevb has provisions to do
data suppression, reduction and compression in addition to the data reduction done
in the ADC and PWB firmware.

feevb event synchronization relies on the event synchronization sequence done by fectrl when a run is started.

{ADC, PWB, TRG} -> BUFUDP -> feevb -> SYSTEM -> mlogger -> compression -> disk storage

=== internal structure ===

* event buffer readers, instances for BUFTRG, BUFTDC, BUFADC, BUFUDP
<pre>
BufferReader class - reads one midas event buffer:
- BufferReaderThread()
-- in batches of 1000 events
--- lock
--- TickLocked()
----- ReadEvent() -> bm_receive_event_alloc()
----- fHandler->HandleEvent()
-- fHandler->XMaybeFlushBank()
-- sleep 100 usec
</pre>
* event header decoder and intermediate buffer
<pre>
Handler class - accumulates events, sends them to the EVB in batches

- HandleEvent() <- BufferReaderThread() - receive incoming events
-- loop over all banks, examine bank name
--- call AddAdcBank(), AddPwbBank(), AddTrgBank(), AddTdcBank() according to bank name
---- AddXxxBank() -> XAddBank()
--- unknown banks go directly to evb->SendQueue
-- check if synchronization has completed

- XAddBank() - save BankBuf objects in a buffer

- XMaybeFlushBank(), XFlushBank() - send all accumulated data to the Evb class
-- evb->lock()
-- for each buffered BankBuf objects,
--- call evb->AddBankLocked()
-- buffer is now empty
</pre>
* event builder
<pre>
Evb class - assemble event fragments according to timestamps

- fEvents fifo (deque) - time sorted list of partially assembled events
-- new entries are added by FindEvent()
-- entries are modified by MergeSlot()
-- old entries are removed by GetLocked()

- AddBankLocked() <- XFlushBank() <- BufferReaderThread()
-- call fSync->Add()
-- transform BankBuf to EvbEventBuf
-- push it into per-module buffer fBuf[imodule]

- EvbThread()
-- EvbTickLocked()
--- BuildLocked()
---- in a loop, for no more than 1 sec
----- loop over all per-module buffers fBuf
------ pop first entry, pass it to BuildSlot()
------- call FindEvent()
------- call MergeSlot()
------- call CheckEvent()
--- in a loop
---- get all completed events via GetLocked() pass them to SendQueue->PushEvent()
-- if done nothing, sleep 100 usec, otherwise nominal sleep to free the evb lock

- GetNext() <- GetLocked() <- EvbThread() - get completed events
-- examine oldest EvbEvent entry in fEvents:
-- pop it if it is complete
-- pop it if it is too old (to prevent old incomplete events from stalling the evb) ("pop age" on the evb page)
-- pop it if a following event is complete ("pop following" on the evb page)
</pre>
* send queue
<pre>
SendQueue class - prepare events for writing to midas SYSTEM event buffer

- PushEvent() <- EvbThread()
-- push FragmentBuf into the queue

- SendQueueThread()
-- in a batch of 1000 events, call Tick()
--- pop FragmentBuf from the queue, call SendEvent()
--- compose midas event (memcpy()!)
--- TMFE fEq->SendEvent()
--- bm_send_event()
-- sleep 100 usec
</pre>
* equipment object
<pre>
EvbEq class - implements the midas equipment
- HandleBeginRun()
- HandleEndRun()
- HandlePeriodic()
</pre>

=== multithreading ===

* BufferReaderThread() one per midas event buffer
** high CPU use: bm_receive_event(), AddXxxBank()
** lock contention: midas event buffer lock, evb lock into XFlushBank->AddBankLocked()
* EvbThread()
** O(size of fEvents): FindEvent(), GetNext()
** lock contention: evb lock against XFlushBank(), SendQueue lock (1 per output event)
* SendQueueThread()
** high CPU use: memcpy() in SendEvent(), memcpy() in bm_send_event
** lock contention: event queue lock against EvbThread, midas event buffer lock
* main thread
** lock contention: evb lock in ReportEvb() and elsewhere

= ODB entries =

== /Equipment/CTRL/Settings ==
* TBW

== /Equipment/CTRL/Settings/Pulser ==

* ClockFreqHz - unit of 1/sec (Hz), set to 62500000, the TRG 62.5 MHz clock frequency (16 ns)
* PulseWidthClk - unit of 16 ns clocks, set to 25. (400 ns). width of internal pulser signal (used to go to a TRG external output, absent on GRIF-C boards)
* PulsePeriodClk - unit of 16 ns clocks, pulser in clock periods (+1), set to zero.
* PulseFreqHz - unit of 1/sec (Hz), requested pulser frequency, actual frequency is rounded to 16 ns clock granularity, change this value to select desired clock frequency
* BurstCtrl - enable burst of pulses 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses
* OutputEnable - enable TRG pulser external output (absent on GRIF-C boards)
* Enable - allow the pulser to run (bit 3 in TRG conf_trig_enable register)

== /Equipment/CTRL/Settings/TrigSrc - trigger source selection ==
* TrigPulser - trigger on the pulser
* TrigEsataNimGrandOr - trigger on external NIM inputs of GRIF-16 ADC modules
* TrigAdc16GrandOr - trigger on any adc16 signals (see adc16_masks)
* TrigAdc32GrandOr - trigger on any adc32 signals (see adc32_masks)
* TrigAdcGrandOr - trigger on adc16_grand_or or adc32_grand_or
* (removed from trg firmware) Trig1ormore - trigger on adc16 multiplicity 1 or more
* (removed from trg firmware) Trig2ormore - ditto, 2 or more
* (removed from trg firmware) Trig3ormore - ditto, 3 or more
* (removed from trg firmware) Trig4ormore - ditto, 4 or more
* (removed from trg firmware) TrigAwCoincA - trigger on TPC AW coincidence (see [[TRG]] manual)
* (removed from trg firmware) TrigAwCoincB - ditto
* (removed from trg firmware) TrigAwCoincC - ditto
* (removed from trg firmware) TrigAwCoincD - ditto
* (removed from trg firmware) TrigAwCoinc - ditto
* (removed from trg firmware) TrigAw1ormore - trigger on TPC AW per-preamp multiplicity 1 or more (see [[TRG]] manual)
* (removed from trg firmware) TrigAw2ormore - ditto, 2 or more
* (removed from trg firmware) TrigAw3ormore - ditto, 3 or more
* (removed from trg firmware) TrigAw4ormore - ditto, 4 or more
* TrigAwMLU - trigger on TPC AW MLU signal (see [[TRG]] manual)
* TrigBscGrandOr - trigger on any BSC signal
* TrigBscMult - trigger on predefined BSC multiplicity (see [[TRG]] manual)
* TrigCoinc - trigger on predefined coincidence of TPC AW, BSC and external signal (see [[TRG]] manual)

== /Equipment/CTRL/Settings/TRG - trigger settings ==
* Enable - if set to "n", fectrl will not do anything with the trigger board. Normal value "y"
* Modules - hostnames of the trigger board. Normal value "alphat01"
* NimMask - 32-bit mask for the 32x NIM inputs (see TRG manual). Normal value 0, unless external trigger is in use.
* EsataMask - 32-bit mask for the 32x eSATA signals (see TRG manual). Normal value 0.
* adc16_mask[16] - 16x 16-bit mask for the 100MHz GRIF-16 onboard ADCs (see TRG manual). Normal value 0xFFFF for all 16 sas links.
* adc32_mask[16] - 16x 32-bit mask for the 62.5MHz FMC-ADC32 ADCs (see TRG manual). Normal value 0xFFFFFFFF for all 16 sas links.
* PassThrough - if set to "y", trigger is passed through the trigger module without generating any events and without causing deadtime.
* AwCoincA, B, C and D - 32-bit masks for the aw16 coincidence trigger (see TRG manual)
* Aw16FromAdc16 - route AW trigger (aw16) from adc16 (100MHz ADCs 0..15)
* Aw16FromAdc32a - route AW trigger (aw16) from adc32 group 15..0 (62.5MHz FMC-ADC32 minisas links 0..7)
* Aw16FromAdc32b - route AW trigger (aw16) from adc32 group 31..16 (62.5MHz FMC-ADC32 minisas links 8..15)
* MluDir, MluFiles - location of aw16 MLU bit patterns
* MluSelectedFile - currently selected/loaded MLU file. 0="grand or", 1="2 or more hit clusters", 2="2 or more hit clusters, with gap 2 or more", 3="3 or more hit clusters"
* MluPrompt - length of aw16_prompt_run gate in units of 8 ns clock, see [[TRG#aw16_mlu]]
* MluWait - length of aw_prompt_wait gate in units of 8 ns clock, see [[TRG#aw16_mlu]]
* MluTrigDelayClk - "TrigDelay" when triggered of aw16 MLU, in units of 16 ns clock
* (BSC settings, TBW)
* BscFromAdc16a - (at CERN, set to "y") route BSC trigger data (bsc64_bus) from 100 MHz adc16 digitizers minisas links 0..7
* BscFromAdc16b - route BSC trigger data (bsc64_bus) from 100 MHz adc16 digitizers minisas links 8..15
* BscBotOnly - route BSC trigger data from bottom ASD cards, bsc64_bus = bot
* BscTopOnly - route BSC trigger data from top ASD cards, bsc64_bus = top
* BscBotTopOr - (set to "y") use bsc64_bus = (top OR bottom)
* BscBotTopAnd - use bsc64_bus = (top AND bottom)
* BscMultiplicityMin - (set to 2) BSC multiplicity trigger - minimum multiplicity
* BscMultiplicityWindowClk8 - (set to 80) BSC multiplicity window, 8 ns clocks
* BscEmptyWindowClk8 - (set to 80) BSC empty window, 8 ns clocks, see [[TRG#bsc64_multiplicity_trigger]]
* BscGrandOrDelayClk16 - (not implemented) trigger delay used by fectrl when TrigSrc/TrigBscGrandOr is selected
* BscMultTrigDelayClk16 - trigger delay used by fectrl when TrigSrc/TrigBscMult is selected
* CoincStart - set same as CoincRequire
* CoincRequire - 0x5: (BSC grand or)*(TPC aw16_grand_or), 0x9: (BSC multiplicity)*(TWC aw16_grand_or), 0x6: (BSC grand or)*(AW16 MLU), see [[TRG#Coincidence_trigger]] and [[TRG#conf_coinc_control bits]]
* CoincWindow - length of coincidence window in 8ns clocks.
* CoincTrigDelayClk16 - trigger delay used by fectrl when TrigSrc/TrigCoinc is selected

== /Equipment/CTRL/Settings/PWB - PWB settings ==
* Enable - if set to "n", fectrl will not do anything with PWBs. Normal value "y".
* enable_boot_user_page - if set to "n", fectrl will not try to reboot PWBs into the user page firmware. Normal value "y".
* enable_trigger - if set to "n", all PWBs will be set to ignore the trigger. Normal value "y".
* enable_trigger_group_a - field wire pulser defeats the data suppression (every channel has a pulse) resulting in too much data overwhelming the DAQ (lost UDP packets). To permit correct data taking of field wire pulser data, PWBs are split into two groups (a and b), only one of the two groups should be enabled for field wire pulser runs. Both groups should be enabled for normal data taking. Normal value is "y"
* enable_trigger_group_b - see "enable_trigger_group_a". Normal value is "y".
* modules[64] - hostnames of PWB boards
* boot_user_page[64] - if set to "y" and enable_boot_user_page is "y", fectrl will reboot the corresponding PWB to the user page firmware.
* trigger[64] - if set to "y" and enable_trigget is "y", fectrl will set the PWB to accept the trigger.
* ch_enable - if set to "n" disables all PWB channels. Normal value is "y".
* ch_force - is set to "y" disables channel suppression (all PWB channels are read)
* suppress_reset - if set to "y" enables channel suppression for reset channels (threshold has to be set correctly)
* suppress_fpn - if set to "y" enables channel suppression for fpn channels (threshold has to be set correctly)
* suppress_pads - set to "y" enables channel suppression for TPC pad channels (threshold has to be set correctly)
* disable_reset1 - data suppression algorithm does not work for the channel "reset1" and it has to be suppressed explicitly by setting this value to "y". Normal value is "y".
* baseline_{reset,fpn,pads}[64] - waveform baseline for each PWB position
* threshold_{reset,fpn,pads} - waveform suppression threshold, see below:
* ch_threshold - PWB sca_N_ch_threshold, if set to 0, threshold is computed as "baseline_pads[seqpwb]-threshold_pads". Normal value is 0.
* test_mode - enable PWB test mode, the ADC data is replaced with a test pattern, see PWB esper variable signalproc/test_mode

== /Equipment/CTRL/Settings/TDC - TDC settings ==
* Enable - if set to "n", fectrl will tell the event builder that the TDC is not running. Normal value is "y".

== /Equipment/CTRL/Variables ==

* Scalers - TRG scalers and counters. from fectrl.cxx ReadTrgLocked()
<pre>
// 0..15 read the 16 base scalers at 0x100
// 16..31 read the adc16 scalers at 0x430
// 32..63 read the adc32 scalers at 0x440
// 64..79 read the 16 additional scalers at 0x110
// 80..95 read the 16 counters_adc_selected scalers at 0x460
// 96..159 read the 64 bar scalers at 0x470
// additional scalers should be appended at the end.
</pre>

== /Equipment/CTRL/EvbConfig - EVB configuration ==
All arrays have the same size corresponding to the number of EVB slots.
* name[] - slot name for the web page (trg01, adc01, adc01/adc32, pwb31/0, tdc01, etc)
* type[] - slot type: 1=TRG, 2=ADC16 and ADC32, 3=obsolete PWB, 4=obsolete PWB, 5=PWB, 6=TDC
* module[] - module number (adcNN, adcNN+100, pwbNN, etc)
* nbanks[] - number of expected banks (16 for ADC16, 32 for ADC32, not used, set to 1 for all others)
* tsfreq[] - timestamp frequency in Hz.

== /Equipment/ADC_UDP - ADC UDP configuration ==

* Common/Buffer - "BUFADC" - event buffer to use, name is hardwired in feevb.cxx
* Settings/udp_port - 50006 - UDP port number, also used by fectrl to configure the ADC modules
* Settings/rcv_bufsize - 209715200 - udp socket buffer size set by setsockopt(SOL_SOCKET, SO_RCVBUF). must have a corresponding command in /etc/rc.local to increase maximum system socket size: "/usr/sbin/sysctl -w net.core.rmem_max=200000000"
* Settings/packet_size - 1500 - non-jumbo-frame UDP packet maximum size
* Settings/max_buffered_packets - 40000 - maximum size of internal packet fifo. If it overflows, extra packets are discarded.
* Settings/max_packets_per_event - 8000 - how many UDP packets to pack into one midas event==

== /Equipment/PWB_X_UDP - PWB UDP configuration ==

For explanation see ADC_UDP above.

* Common/Buffer - "BUFUDP" - event buffer to use, name is hardwired in feevb.cxx
* Settings/udp_port - 50007, 50008, 50009, 50010 - for A, B, C and D UDP receivers respectively, also used by fectrl to configure the PWB modules
* Settings/rcv_bufsize - 209715200
* Settings/packet_size - 1500
* Settings/max_buffered_packets - 10000
* Settings/max_packets_per_event - 8000

= Trigger configuration =

These trigger modes are implemented:
* (manual trigger from web page)
* software pulser trigger (from fectrl)
* hardware pulser trigger (from the trigger board)
* NIM and eSATA trigger from ADC front panel inputs
* adc16 and adc32 discriminator triggers:
** adc16 grand-or trigger
** adc32 grand-or trigger
** adc (adc16+adc32) grand-or trigger
** adc16 multiplicity trigger (1ormore, 2ormore, 3ormore, 4ormore) for use with barrel scintillator
** anode wire multiplicity trigger (1ormore, 2ormore, 3ormore, 4ormore) (anode wire signals can be fed from adc16 or from adc32 signals)
** anode wire coincidence trigger
** anode wire MLU (memory lookup) trigger

== NIM trigger from ADC front panel ==

Trigger path:
<pre>
NIM signal --> LEMO input on ADC front panel --> data encoder --> data link to trigger board --> data decoder --> mask --> nim-esata-grand-or --> trigger
</pre>

To enable NIM trigger, do this:
* connect NIM signal to ADC front panel input
** Note1: NIM signal must be inverted
** Note2: LEMO connectors should be set to "NIM input" mode by ADC on-board jumpers (see ADC manual)
* observe correct bit goes to zero in the TRG web page: data link high work should change:
<pre>
0xNF00'0000 (N is the module id) to
0xN700'0000 (left lemo) or
0xNB00'0000 (right lemo)
</pre>
* Note3: if data link bits do not change, most likely the LEMO connectors are set to "DAC output" mode. Try to use LEMO inputs of a different ADC.
* compute the NIM mask: there are 32 bits, 2 bits per ADC data link. Bit 0x1 is right LEMO, bit 0x2 is left LEMO
* for example, to use left LEMO of ADC data link 12, set nim mask to (0x2)<<(2*12) = 0x02000000
* development branch of the git repository contains ''scripts/nim_mask.py'', which can compute forwards and backwards
* initialize the trigger board (on the TRG web page press button "initialize"), or start a new run
* on the history plot with "NIM grand or" counter, the rate should change from zero
* if a run is active, if one of the ADC LEMO outputs is set to output the trigger signal as a NIM pulse, one should see it fire use a scope. The delay or jitter between NIM trigger in and NIM trigger out should be around 100-200 ns (FIXME - measure this!)
* to set the DAQ to trigger on the NIM signal, on the run start page, check the box "TrigEsataNimGrandOr".
** Note: remember to set the scaledown to 0 if so desired.

= TPC field wire pulser =

The TPC field wire pulser input should be connected directly to the DAC output of ADC[0] (right lemo connector).

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for pulsing PWBs, baseline -1V, pulse height +2V (maximum possible pulse height in PWBs. Overdrives the AW ADC waveforms)
** dac_baseline: -8000
** dac_amplitude: 8000
** ramp_up_rate: 128
** ramp_down_rate: 70
** ramp_top_len: 128

* for pulsing AW, baseline -0.25V, pulse height +0.7V (AW ADC waveforms are in range. PWB waveforms are too small for goor time resolution)
** dac_baseline: -2000
** dac_amplitude: 4000
** ramp_up_rate: 20
** ramp_down_rate: 20
** ramp_top_len: 128

= BSC pulser =

The BSC pulser input on the BSC VME rear transition board (RTM) should be connected directly to the DAC output of ADC[4,5,6,7] (right lemo connector). (8 RTMs, but 4 ADCs, each signal is split using a LEMO "T" connector).

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for pulsing BSC, baseline -0.950V, pulse height +1.4V
** dac_baseline: -8000
** dac_amplitude: 4000
** ramp_up_rate: 64
** ramp_down_rate: 64
** ramp_top_len: 128

= NIM output =

To configure ADC analog output for NIM compatible pulse:

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for output of NIM pulse: baseline 0V, pulse height -0.9V, pulse width 100 ns
** dac_baseline: 0
** dac_amplitude: 8000
** ramp_up_rate: 128
** ramp_down_rate: 128
** ramp_top_len: 4
** dac_xor: 1 (invert the signal)

= TDC connections =

* SFP8 - fiber SFP to Juniper switch
* right RJ45 - 200MHz clock
* left RJ45 - external trigger

= MIDAS Data banks =

* ATAT - fectrl - UDP packets from GRIF-C/TRG trigger board
* TRBA - fetdc - TDC data
* TRTM - fetdc - TDC FPGA temperatures, TID_FLOAT[5].
* AAnn - feudp - UDP packets from GRIF-16 ADC (before the event builder), "nn" is the ADC module number: adc01 is AA01 through adc20 is AA20.
* BBxx - feudp - UDP packets from PWB, obsolete
* Bnnm, Cnnm - feevb - EVB output banks: ADC data, "nn" is the ADC module number (1..20), "m" is the channel number (0..9,A..F), format is same as AAnn banks.
* PAnn - feudp - UDP packets from PWB, "nn" is the PWB module number (00..99), obsolete
* PBnn - feudp - UDP packets from PWB, "nn" is the PWB module number (00..99), PB01 is pwb01, PB78 is pwb78
* PCnn - feevb - EVB output banks: PWB data, "nn" is the PWB module number (00..99), same as above, format is same as PBnn banks

= ZZZ =

ZZZ

Daq

2022-07-25T22:45:57Z

Olchansk: /* Performance */

= Links =

* https://alphacpc05.cern.ch/agdaq/ -- midas daq page for the agdaq system at CERN
* https://daq16.triumf.ca -- midas daq page for the agmini system at TRIUMF
* https://daq.triumf.ca/elog-alphag/alphag/ -- elog
* https://daqstore.triumf.ca/AgWiki/index.php/Main_Page -- this wiki
* https://bitbucket.org/ttriumfdaq/agdaq - git repository for agdaq
* https://bitbucket.org/expalpha -- git repository on bitbucket
* https://edev-group.triumf.ca/fw/exp/alphag -- git repository on edev gitlab

= Inventory database =

* https://ladd00.triumf.ca/daqinv/frontend/list/170 - PWB inventory database
* https://ladd00.triumf.ca/daqinv/frontend/list/168 - ADC (GRIF-16) inventory, FMC-ADC32rev0,rev1 inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/176 - FMC-ADC32rev1.1 inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/174 - BSC RTM inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/173 - BSC ASD inventory

= Hardware manuals =

* [[TRG]] - trigger board (GRIF-C) manual
* CDM - https://daq.triumf.ca/DaqWiki/index.php/VME-CDM -- clock VME-CDM manual
* ADC - https://daq.triumf.ca/DaqWiki/index.php/VME-GRIF-ADC16-Rev1 -- GRIF-16 ADC manual
* [[PWB]] - TPC Pad Wing Board manual
* TDC - https://daq.triumf.ca/DaqWiki/index.php/GSI_TRB3
* [[chronobox]] - chronobox manual
* [[ASD]] - BSC preamp board
* [[RTM]] - BSC VME rear transition board

= Performance =

Full system: (ADC fw rel-20201112-ko, PWB fw 20201005_ko)
* 1 Hz stable, ADC adc32 9 supp off rate 0.3 M/s, adc16 off, PWB udp_delay 25 supp off active 64 rate 6.6+4+6+4.6=21.2 M/s, TDC off, total rate 21 M/s
* 500 Hz stable, ADC adc32 9 supp 1500 rate 6 M/s, adc16 off, PWB udp_delay 10 supp 100 active 63 rate 3+4+3+3=13 M/s, TDC off, total rate 19 M/s

Single ADC: (fw rel-20201112-ko)

Fully suppressed data, sthreshold 5000
* 1 Hz: stable
* 500 Hz: stable (nominal max trigger rate)
* 6700 Hz: stable, 8 Mbytes/sec
* 6800 Hz: evb eventually confused
* 6850 Hz: evb confused, no lost triggers in the ADC, no crash in the ADC

All data, 510 samples/event, sthreshold 10 (fw rel-20201122-ko)
* 1 Hz: stable
* 100 Hz: stable, 3.4 Mbytes/sec
* 500 Hz: stable, 17 Mbytes/sec (nominal max trigger rate)
* 1000 Hz: stable, 32 Mbytes/sec
* 3100 Hz: stable, 106 M/s (approaching saturation of 1gige ethernet)
* 3200 Hz: stable, 110 M/s - TRG communication is in trouble
* 3300 Hz: stable, 116 M/s
* 3400 Hz: incomplete events, no ADC crash ("dropped due to full" counting, "dropped due to busy" are zero, this is as expected).

no suppression (different fpga data path)
* 1 Hz: stable
* 100 Hz: stable
* 500 Hz: stable, 17 M/s (nominal max trigger rate)
* 1000 Hz: stable, 32 M/s
* 3000 Hz: stable, 100 M/s (approaching saturation of 1gige ethernet)
* 3300 Hz: incomplete events, no ADC crash ("dropped due to full" counting, "dropped due to busy" are zero, this is as expected).

Single PWB, fw 20201005_ko, see https://alphacpc05.cern.ch/elog/Detectors/5563

Fully suppressed data:
* up to 500 Hz, stable

All pads firing (FW pulser)
* 4 SCA: up to 272 Hz, 81.6 Mbytes/sec, at higher rate: event fifo overflow
* 2 SCA: up to 295 Hz, 44.25 Mbytes/sec, at higher rate: event fifo overflow
* 1 SCA: up to 295 Hz, 22.5 Mbytes/sec, at higher rate: event fifo overflow

Conclusion:
* max PWB date rate 80 Mbytes/sec,
* max non-suppressed PWB trigger rate: 295 Hz
* max suppressed PWB trigger rate: 500 Hz (1.6 ms sca readout time)

= Network connections =

The experiment private network number is: 192.168.1.x, gateway 192.168.1.1, netmask 255.255.255.0

network map:
<pre>
---- TRIUMF/CERN network --1gige-- alphagdaq --10gige-- juniper switch --1gige-- centrecom switch
</pre>

== alphagdaq network connections ==

on the rear of the machine:
<pre>
-----------------------------------------
| | rj45 | rj45 | | sfp | sfp |
-----------------------------------------

- left rj45 - copper 1gige - eno1 - spare (inactive)
- right rj45 - copper 1gige - eno2 - dhcp - cern/triumf network
- left sfp - 10gige - enp1s0f1 - spare (inactive)
- right sfp - 10gige - enp1s0f0 - static 192.168.1.1
</pre>

== connections between switches ==

* alphagdaq to juniper switch: direct attach (DAC) 10gige cable into any port of juniper switch
* juniper switch to centrecom switch: rj45 sfp in any port of juniper switch - cat5e/cat6 cable - to any port of centrecom switch
* cat5e/cat6 cable from any port of centrecom switch to the XXX port on the back of the juniper switch

== juniper switch ==

connected to juniper switch front is:

* everything that sends event data to alphagdaq, specifically:
** TRG (rj45 sfp)
** 16x ADC (fiber sfp)
** 64x PWB (fiber sfp)
* 10gige uplink to alphagdaq (10gige DAC cable)
* 1gige link to centrecom switch (rj45 sfp)
* 40gige ports are not used

connected to the juniper switch rear:

* CON is the serial console via RJ45-to-DB9 to USB-serial adapter to alphagdaq USB port (9600bps, 8N1, no flow control)
* C0 is the management ethernet interface port, connect to any port on the centrecom switch (juniper-private will ping)

== centrecom switch ==

* everything with copper rj45 connections, specifically:
** CDM boards
** HV, LV and VME power supplies
** RaspberryPi3 boards
** gas handling MFCs (algas)
** cooling system controller (moxa01)

= USB connections =

Note:
* alphagdaq has USB2 and USB3 connections. They are not the same, they are not generally interchangeable.
* USB3 connections and cables are generally blue coloured.

List of USB connections from alphagdaq:

* front USB3 port (blue): USB-A-to-B cable to USB blaster connected to the trigger board (front of rack)
* rear USB3 port (blue): USB3 short jumper to USB3 hub
* rear USB2 port (black): USB2 unpowered hub (Logiix) to USB-A-to-B cable to UPS USB connector
* rear USB2 port (black): USB-to-Serial adaper to DB9 to RJ45 adapter to Juniper switch console port

Note: UPS USB connection does not work with alphagdaq USB ports (both usb2 and usb3), but combination
using the unpowered USB2 hub seems to work ok.

List of USB connections from the USB hub:

* this is a powered USB3 hub
* USB-A-to-MicroUSB - to lvdb boards
* USB-A-to-Wiener interlock cable

= Clock and trigger distribution =

== Explanation ==

Trigger is generated by the trigger board (aka TRG, aka GRIF-C),
from the TRG eSATA output through the eSATA splitter it is fed into
the master CDM. The master CDM outputs the trigger on all MiniSAS output ports.
One of the master CDM MiniSAS outputs is connected to the CDM slave eSATA input.
The same as the master CDM, the slave CDM outputs the trigger on all MiniSAS output ports.

The master 62.5MHz clock is generated by the master CDM using the internal 10MHz oscillator
or the external 10MHz AD clock. Also on MiniSAS port 6 the master CDM generates
the 200MHz clock for the TDC. This clock is frequency-locked to the master 62.5MHz clock.

Master CDM clock selection (external CD 10MHz clock or internal oscillator 10MHz clock)
is done by a magic esper command (see below).

From the master CDM, the clock is fed to: the slave CDM, the TRG (via the eSATA splitter)
and to the TDC (via the RJ45 splitter).

The slave CDM sends the clock and the trigger to the ADCs and PWBs.

== Chronobox connections ==

Chronoboxes are synchronized with the daq using two signals: 10 MHz timestamp clock and TTL sync.

The sync signal used is the trigger signal - timestamps are reset by the 1st event - which is not a physics event, but the first trigger in the trigger sync sequence.

All chronoboxes are configured in "slave" and "chain" mode.

Slave mode: 10 MHz timestamp clock goes into the CLK_IN input (configured as NIM on the first chronobox and TTL on all others), sync signal goes into TTL input LEMO 4. (bank B direction set to "in").

Chain mode: 10 MHz timestamp clock is TTL output LEMO 0, sync is TTL output LEMO 1. (bank A direction set to "out"). These signals feed into CLK_IN (TTL mode) and TTL input LEMO 4 in the next chronobox in the chain.

The first chronobox receives the 10 MHz timestamp clock and sync signals from the master CDM per diagrams below.

* CDM 10 MHz clock output is NIM, feeds directly into the chronobox CLK_IN (NIM mode).
* CDM "trigger" ("sync") output is NIM, has to go through a NIM-to-TTL converter before feeding chronobox TTL input LEMO 4. I use a LeCroy 222 "gate and delay generator" module. NIM input goes into the "Start" input, TTL output is taken from the "TTL" output. Signal width is adjusted to around 100-1000 ns. Any other sutable NIM-to-TTL converter can also be used.
* "sync" output must be enabled in the master CDM:
<pre>
esper-tool cdm00
cd cdm
write multi_sync 2
</pre>

== Schematic ==

<pre>
TRG (GRIF-C)
------------
eSATA <------> eSATA splitter

eSATA splitter
--------------
trigger ---> eSATA ---> CDM-Master eSATA (trigger signal)
clock <--- (eSATA --- MiniSAS) <--- CDM MiniSAS (62.5MHz clock)
</pre>

<pre>
CDM-Master
----------
LEMO1B <----- 10 MHz AD clock (NIM)
LEMO2A --> (only if there is no external clock) 4ns lemo cable --> LEMO1B (62.5 MHz frequency monitor)
LEMO2B --> chronobox sync (NIM) --> NIM-to-TTL --> long lemo cable to chronobox sync input (TTL)
LEMO3B --> long lemo cable to chronobox clock input (NIM) (CLK_IN configured for NIM input)
eSATA <--- eSATA splitter <--- eSATA from TRG (trigger signal)
MiniSAS 1 --> (MiniSAS --- eSATA) --> CDM-Slave eSATA (62.5 MHz)
MiniSAS 6 --> (MiniSAS --- eSATA) --> eSATA splitter --> RJ45 --> TDC (200 MHz)
</pre>

<pre>
CDM-Slave
---------
LEMO2A --> 4ns lemo cable --> LEMO1B (62.5 MHz frequency monitor)
eSATA <--- trigger and 62.5MHz clock from CDM-Master
MiniSAS 1 --> ADC trigger and 62.5MHz clock
MiniSAS 2 --> same
MiniSAS 3 --> same
MiniSAS 4 --> same
MiniSAS 5 --> PWB trigger and 62.5MHz clock
MiniSAS 6 --> same
</pre>

[[File:VME_Crate_CERN.jpeg|800x450px|Layout of the VME crate at CERN.]]

Layout of the VME crate at CERN. The ALPHA-T module is in the rightmost slot. The Master CDM is next to it and it's labelled as #02. The Slave CDM is on the lefmost position and labelled by #03.

== Setup of CDM boards ==

ALPHA-g uses the Rev3 CDM boards. The 4 CDM boards that belong to ALPHA-g
have serial numbers 0, 1, 2 and 3 and are labeled cdm00, cdm01, cdm02, cdm03.

All the boards can be used as master and slave positions, but have to be
configured appropriately.

=== Slave setup ===

* install the board
* connect ethernet
* connect esata external clock
* esper-tool cdmNN ### i.e. esper-tool cdm01
* cd template
* write current_setup 4
* cd /cdm
* read
* observe clock frequency counters report correct values. "ext_clk" will only count if the lemo jumper is installed (see below)
<pre>
11 esata_clk uint32 R [62500246]
12 ext_clk uint32 R [62500246]
</pre>
* cd /lmk
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
156 ld1_counter uint32 RW [3]
157 ld2_counter uint32 RW [3]
</pre>

If needed, check correct operation of the pll lock monitoring:

* unplug the esata cable from the master CDM
* "red" light should go off
* read of lmk should report "pll1_ld" value 0 and "ld1_counter" and "ld2_counter" should increment
* reconnect the esata cable
* "red" light should return
* read of lmk should report both pll1_ld and pll2_ld locked (values "1").

=== Master setup ===

* install the board
* connect ethernet
* esper-tool cdmNN ### i.e. esper-tool cdm01
* cd template
* write current_setup 3
* cd /lmk
* write clkin_sel_mode 0
* cd /cdm
* read
* observe clock frequency counters report correct values. "ext_clk" will only count if the "clock loopback" lemo jumper is installed (see below)
<pre>
12 ext_clk uint32 R [62500189]
</pre>
* cd /lmk
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
156 ld1_counter uint32 RW [3]
157 ld2_counter uint32 RW [3]
</pre>

Check the 200MHz clock:
* connect MiniSAS-eSATA splitter cable to MiniSAS output 6, connect eSATA end to CDM eSATA input
* in esper-tool, read cdm: esata_clk should report 200MHz clock
<pre>
11 esata_clk uint32 R [200000603]
12 ext_clk uint32 R [62500188]
</pre>

=== Master setup with external 10 MHz clock ===

* setup master CDM as above (using internal clock)
* connect 10MHz external clock to LEMO1A
* esper-tool cdmNN
* cd /cdm
* write sel_nim 1 # if clock is NIM signal
* write sel_nim 0 # if clock is TTL signal (i.e. chronobox LEMO output)
* read ext_clk
<pre>
[http://cdm00:/cdm]> read ext_clk
9999556
</pre>
* if ext_clk reads 0 or does not read something close to 10MHz, stop here. debug the signal, try changing sel_nim, etc.
* cd /lmk
* write clkin_sel_mode 2 # select external clock
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
150 clkin2_sel bool R [True]
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
</pre>
* on the MIDAS TRG page, observe that TRG measured external clock frequency is close to 62.5 MHz

== clkin_sel_mode positions ==

* 0 = 10MHz internal oscillator (use on master CDM in standalone mode)
* 1 = eSATA clock (use on slave CDM)
* 2 = external clock, should be 10MHz (use on master CDM to run from AD clock)

== LEMO connections ==

LEMO connectors:

<pre>
|
|LEMO1A|LEMO1B
|LEMO2A|LEMO2B
|LEMO3A|LEMO3B
|eSATA
|RJ45 ETH
|minisas
|
</pre>

* clock loopback jumper: to read the frequency of the generated 62.5MHz clock, connect LEMO cable from LEMO2B to LEMO1A
* 10MHz internal clock jumper: to feed 10MHz internal oscillator to the external clock, connect LEMO cable from LEMO3A to the LEMO1A
* 10MHz external clock: to feed 10MHz external clock, connect LEMO cable to LEMO1A

= MIDAS frontends =

== UDP ==

feudp receives udp packets from the ADC and PWB boards. For each udp packet 1 midas event is created,
with 1 data bank containing the udp data. Events are sent into the MIDAS event buffer BUFUDP. The names
of the data banks are assigned in ODB /eq/feudp/settings.

{ADC,PWB} --> 1gige --> switch --> 10gige --> alphagdaq --> feudp -> BUFUDP

== CTRL ==

fectrl controls all the ADC, PWB and trigger boards. It provides run start and stop sequencing,
runs the event synchronization sequence at the begin of the run, and records slow controls data (temperatures,
voltages, etc).

fectrl receives UDP data packets from the trigger board and sends them to the MIDAS event buffer BUFUDP.

fectrl receives commands from the control web pages (for ADC, PWB and trigger) to reboot, initialize, etc the boards.

fectrl configures the event builder via odb /eq/fectrl/evbconfig.

ADC <-> http esper <-> fectrl -> slow control data into midas history

PWB <-> http esper <-> fectrl -> slow control data into midas history

TRG <-> udp comm <-> fectrl -> BUFUDP, slow control and counters into midas history

fectrl <-> midas rpc <-> mhttpd <-> json rpc <-> control web pages for ADC, PWB and trigger

== EVB ==

feevb receives udp packet data from the MIDAS event buffer BUFUDP, inspects the packet timestamps
and collects the data with matching timestamps into physics events. feevb has provisions to do
data suppression, reduction and compression in addition to the data reduction done
in the ADC and PWB firmware.

feevb event synchronization relies on the event synchronization sequence done by fectrl when a run is started.

{ADC, PWB, TRG} -> BUFUDP -> feevb -> SYSTEM -> mlogger -> compression -> disk storage

=== internal structure ===

* event buffer readers, instances for BUFTRG, BUFTDC, BUFADC, BUFUDP
<pre>
BufferReader class - reads one midas event buffer:
- BufferReaderThread()
-- in batches of 1000 events
--- lock
--- TickLocked()
----- ReadEvent() -> bm_receive_event_alloc()
----- fHandler->HandleEvent()
-- fHandler->XMaybeFlushBank()
-- sleep 100 usec
</pre>
* event header decoder and intermediate buffer
<pre>
Handler class - accumulates events, sends them to the EVB in batches

- HandleEvent() <- BufferReaderThread() - receive incoming events
-- loop over all banks, examine bank name
--- call AddAdcBank(), AddPwbBank(), AddTrgBank(), AddTdcBank() according to bank name
---- AddXxxBank() -> XAddBank()
--- unknown banks go directly to evb->SendQueue
-- check if synchronization has completed

- XAddBank() - save BankBuf objects in a buffer

- XMaybeFlushBank(), XFlushBank() - send all accumulated data to the Evb class
-- evb->lock()
-- for each buffered BankBuf objects,
--- call evb->AddBankLocked()
-- buffer is now empty
</pre>
* event builder
<pre>
Evb class - assemble event fragments according to timestamps

- fEvents fifo (deque) - time sorted list of partially assembled events
-- new entries are added by FindEvent()
-- entries are modified by MergeSlot()
-- old entries are removed by GetLocked()

- AddBankLocked() <- XFlushBank() <- BufferReaderThread()
-- call fSync->Add()
-- transform BankBuf to EvbEventBuf
-- push it into per-module buffer fBuf[imodule]

- EvbThread()
-- EvbTickLocked()
--- BuildLocked()
---- in a loop, for no more than 1 sec
----- loop over all per-module buffers fBuf
------ pop first entry, pass it to BuildSlot()
------- call FindEvent()
------- call MergeSlot()
------- call CheckEvent()
--- in a loop
---- get all completed events via GetLocked() pass them to SendQueue->PushEvent()
-- if done nothing, sleep 100 usec, otherwise nominal sleep to free the evb lock

- GetNext() <- GetLocked() <- EvbThread() - get completed events
-- examine oldest EvbEvent entry in fEvents:
-- pop it if it is complete
-- pop it if it is too old (to prevent old incomplete events from stalling the evb) ("pop age" on the evb page)
-- pop it if a following event is complete ("pop following" on the evb page)
</pre>
* send queue
<pre>
SendQueue class - prepare events for writing to midas SYSTEM event buffer

- PushEvent() <- EvbThread()
-- push FragmentBuf into the queue

- SendQueueThread()
-- in a batch of 1000 events, call Tick()
--- pop FragmentBuf from the queue, call SendEvent()
--- compose midas event (memcpy()!)
--- TMFE fEq->SendEvent()
--- bm_send_event()
-- sleep 100 usec
</pre>
* equipment object
<pre>
EvbEq class - implements the midas equipment
- HandleBeginRun()
- HandleEndRun()
- HandlePeriodic()
</pre>

=== multithreading ===

* BufferReaderThread() one per midas event buffer
** high CPU use: bm_receive_event(), AddXxxBank()
** lock contention: midas event buffer lock, evb lock into XFlushBank->AddBankLocked()
* EvbThread()
** O(size of fEvents): FindEvent(), GetNext()
** lock contention: evb lock against XFlushBank(), SendQueue lock (1 per output event)
* SendQueueThread()
** high CPU use: memcpy() in SendEvent(), memcpy() in bm_send_event
** lock contention: event queue lock against EvbThread, midas event buffer lock
* main thread
** lock contention: evb lock in ReportEvb() and elsewhere

= ODB entries =

== /Equipment/CTRL/Settings ==
* TBW

== /Equipment/CTRL/Settings/Pulser ==

* ClockFreqHz - unit of 1/sec (Hz), set to 62500000, the TRG 62.5 MHz clock frequency (16 ns)
* PulseWidthClk - unit of 16 ns clocks, set to 25. (400 ns). width of internal pulser signal (used to go to a TRG external output, absent on GRIF-C boards)
* PulsePeriodClk - unit of 16 ns clocks, pulser in clock periods (+1), set to zero.
* PulseFreqHz - unit of 1/sec (Hz), requested pulser frequency, actual frequency is rounded to 16 ns clock granularity, change this value to select desired clock frequency
* BurstCtrl - enable burst of pulses 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses
* OutputEnable - enable TRG pulser external output (absent on GRIF-C boards)
* Enable - allow the pulser to run (bit 3 in TRG conf_trig_enable register)

== /Equipment/CTRL/Settings/TrigSrc - trigger source selection ==
* TrigPulser - trigger on the pulser
* TrigEsataNimGrandOr - trigger on external NIM inputs of GRIF-16 ADC modules
* TrigAdc16GrandOr - trigger on any adc16 signals (see adc16_masks)
* TrigAdc32GrandOr - trigger on any adc32 signals (see adc32_masks)
* TrigAdcGrandOr - trigger on adc16_grand_or or adc32_grand_or
* (removed from trg firmware) Trig1ormore - trigger on adc16 multiplicity 1 or more
* (removed from trg firmware) Trig2ormore - ditto, 2 or more
* (removed from trg firmware) Trig3ormore - ditto, 3 or more
* (removed from trg firmware) Trig4ormore - ditto, 4 or more
* (removed from trg firmware) TrigAwCoincA - trigger on TPC AW coincidence (see [[TRG]] manual)
* (removed from trg firmware) TrigAwCoincB - ditto
* (removed from trg firmware) TrigAwCoincC - ditto
* (removed from trg firmware) TrigAwCoincD - ditto
* (removed from trg firmware) TrigAwCoinc - ditto
* (removed from trg firmware) TrigAw1ormore - trigger on TPC AW per-preamp multiplicity 1 or more (see [[TRG]] manual)
* (removed from trg firmware) TrigAw2ormore - ditto, 2 or more
* (removed from trg firmware) TrigAw3ormore - ditto, 3 or more
* (removed from trg firmware) TrigAw4ormore - ditto, 4 or more
* TrigAwMLU - trigger on TPC AW MLU signal (see [[TRG]] manual)
* TrigBscGrandOr - trigger on any BSC signal
* TrigBscMult - trigger on predefined BSC multiplicity (see [[TRG]] manual)
* TrigCoinc - trigger on predefined coincidence of TPC AW, BSC and external signal (see [[TRG]] manual)

== /Equipment/CTRL/Settings/TRG - trigger settings ==
* Enable - if set to "n", fectrl will not do anything with the trigger board. Normal value "y"
* Modules - hostnames of the trigger board. Normal value "alphat01"
* NimMask - 32-bit mask for the 32x NIM inputs (see TRG manual). Normal value 0, unless external trigger is in use.
* EsataMask - 32-bit mask for the 32x eSATA signals (see TRG manual). Normal value 0.
* adc16_mask[16] - 16x 16-bit mask for the 100MHz GRIF-16 onboard ADCs (see TRG manual). Normal value 0xFFFF for all 16 sas links.
* adc32_mask[16] - 16x 32-bit mask for the 62.5MHz FMC-ADC32 ADCs (see TRG manual). Normal value 0xFFFFFFFF for all 16 sas links.
* PassThrough - if set to "y", trigger is passed through the trigger module without generating any events and without causing deadtime.
* AwCoincA, B, C and D - 32-bit masks for the aw16 coincidence trigger (see TRG manual)
* Aw16FromAdc16 - route AW trigger (aw16) from adc16 (100MHz ADCs 0..15)
* Aw16FromAdc32a - route AW trigger (aw16) from adc32 group 15..0 (62.5MHz FMC-ADC32 minisas links 0..7)
* Aw16FromAdc32b - route AW trigger (aw16) from adc32 group 31..16 (62.5MHz FMC-ADC32 minisas links 8..15)
* MluDir, MluFiles - location of aw16 MLU bit patterns
* MluSelectedFile - currently selected/loaded MLU file. 0="grand or", 1="2 or more hit clusters", 2="2 or more hit clusters, with gap 2 or more", 3="3 or more hit clusters"
* MluPrompt - length of aw16_prompt_run gate in units of 8 ns clock, see [[TRG#aw16_mlu]]
* MluWait - length of aw_prompt_wait gate in units of 8 ns clock, see [[TRG#aw16_mlu]]
* MluTrigDelayClk - "TrigDelay" when triggered of aw16 MLU, in units of 16 ns clock
* (BSC settings, TBW)
* BscFromAdc16a - (at CERN, set to "y") route BSC trigger data (bsc64_bus) from 100 MHz adc16 digitizers minisas links 0..7
* BscFromAdc16b - route BSC trigger data (bsc64_bus) from 100 MHz adc16 digitizers minisas links 8..15
* BscBotOnly - route BSC trigger data from bottom ASD cards, bsc64_bus = bot
* BscTopOnly - route BSC trigger data from top ASD cards, bsc64_bus = top
* BscBotTopOr - (set to "y") use bsc64_bus = (top OR bottom)
* BscBotTopAnd - use bsc64_bus = (top AND bottom)
* BscMultiplicityMin - (set to 2) BSC multiplicity trigger - minimum multiplicity
* BscMultiplicityWindowClk8 - (set to 80) BSC multiplicity window, 8 ns clocks
* BscEmptyWindowClk8 - (set to 80) BSC empty window, 8 ns clocks, see [[TRG#bsc64_multiplicity_trigger]]
* BscGrandOrDelayClk16 - (not implemented) trigger delay used by fectrl when TrigSrc/TrigBscGrandOr is selected
* BscMultTrigDelayClk16 - trigger delay used by fectrl when TrigSrc/TrigBscMult is selected
* CoincStart - set same as CoincRequire
* CoincRequire - 0x5: (BSC grand or)*(TPC aw16_grand_or), 0x9: (BSC multiplicity)*(TWC aw16_grand_or), 0x6: (BSC grand or)*(AW16 MLU), see [[TRG#Coincidence_trigger]] and [[TRG#conf_coinc_control bits]]
* CoincWindow - length of coincidence window in 8ns clocks.
* CoincTrigDelayClk16 - trigger delay used by fectrl when TrigSrc/TrigCoinc is selected

== /Equipment/CTRL/Settings/PWB - PWB settings ==
* Enable - if set to "n", fectrl will not do anything with PWBs. Normal value "y".
* enable_boot_user_page - if set to "n", fectrl will not try to reboot PWBs into the user page firmware. Normal value "y".
* enable_trigger - if set to "n", all PWBs will be set to ignore the trigger. Normal value "y".
* enable_trigger_group_a - field wire pulser defeats the data suppression (every channel has a pulse) resulting in too much data overwhelming the DAQ (lost UDP packets). To permit correct data taking of field wire pulser data, PWBs are split into two groups (a and b), only one of the two groups should be enabled for field wire pulser runs. Both groups should be enabled for normal data taking. Normal value is "y"
* enable_trigger_group_b - see "enable_trigger_group_a". Normal value is "y".
* modules[64] - hostnames of PWB boards
* boot_user_page[64] - if set to "y" and enable_boot_user_page is "y", fectrl will reboot the corresponding PWB to the user page firmware.
* trigger[64] - if set to "y" and enable_trigget is "y", fectrl will set the PWB to accept the trigger.
* ch_enable - if set to "n" disables all PWB channels. Normal value is "y".
* ch_force - is set to "y" disables channel suppression (all PWB channels are read)
* suppress_reset - if set to "y" enables channel suppression for reset channels (threshold has to be set correctly)
* suppress_fpn - if set to "y" enables channel suppression for fpn channels (threshold has to be set correctly)
* suppress_pads - set to "y" enables channel suppression for TPC pad channels (threshold has to be set correctly)
* disable_reset1 - data suppression algorithm does not work for the channel "reset1" and it has to be suppressed explicitly by setting this value to "y". Normal value is "y".
* baseline_{reset,fpn,pads}[64] - waveform baseline for each PWB position
* threshold_{reset,fpn,pads} - waveform suppression threshold, see below:
* ch_threshold - PWB sca_N_ch_threshold, if set to 0, threshold is computed as "baseline_pads[seqpwb]-threshold_pads". Normal value is 0.
* test_mode - enable PWB test mode, the ADC data is replaced with a test pattern, see PWB esper variable signalproc/test_mode

== /Equipment/CTRL/Settings/TDC - TDC settings ==
* Enable - if set to "n", fectrl will tell the event builder that the TDC is not running. Normal value is "y".

== /Equipment/CTRL/Variables ==

* Scalers - TRG scalers and counters. from fectrl.cxx ReadTrgLocked()
<pre>
// 0..15 read the 16 base scalers at 0x100
// 16..31 read the adc16 scalers at 0x430
// 32..63 read the adc32 scalers at 0x440
// 64..79 read the 16 additional scalers at 0x110
// 80..95 read the 16 counters_adc_selected scalers at 0x460
// 96..159 read the 64 bar scalers at 0x470
// additional scalers should be appended at the end.
</pre>

== /Equipment/CTRL/EvbConfig - EVB configuration ==
All arrays have the same size corresponding to the number of EVB slots.
* name[] - slot name for the web page (trg01, adc01, adc01/adc32, pwb31/0, tdc01, etc)
* type[] - slot type: 1=TRG, 2=ADC16 and ADC32, 3=obsolete PWB, 4=obsolete PWB, 5=PWB, 6=TDC
* module[] - module number (adcNN, adcNN+100, pwbNN, etc)
* nbanks[] - number of expected banks (16 for ADC16, 32 for ADC32, not used, set to 1 for all others)
* tsfreq[] - timestamp frequency in Hz.

== /Equipment/ADC_UDP - ADC UDP configuration ==

* Common/Buffer - "BUFADC" - event buffer to use, name is hardwired in feevb.cxx
* Settings/udp_port - 50006 - UDP port number, also used by fectrl to configure the ADC modules
* Settings/rcv_bufsize - 209715200 - udp socket buffer size set by setsockopt(SOL_SOCKET, SO_RCVBUF). must have a corresponding command in /etc/rc.local to increase maximum system socket size: "/usr/sbin/sysctl -w net.core.rmem_max=200000000"
* Settings/packet_size - 1500 - non-jumbo-frame UDP packet maximum size
* Settings/max_buffered_packets - 40000 - maximum size of internal packet fifo. If it overflows, extra packets are discarded.
* Settings/max_packets_per_event - 8000 - how many UDP packets to pack into one midas event==

== /Equipment/PWB_X_UDP - PWB UDP configuration ==

For explanation see ADC_UDP above.

* Common/Buffer - "BUFUDP" - event buffer to use, name is hardwired in feevb.cxx
* Settings/udp_port - 50007, 50008, 50009, 50010 - for A, B, C and D UDP receivers respectively, also used by fectrl to configure the PWB modules
* Settings/rcv_bufsize - 209715200
* Settings/packet_size - 1500
* Settings/max_buffered_packets - 10000
* Settings/max_packets_per_event - 8000

= Trigger configuration =

These trigger modes are implemented:
* (manual trigger from web page)
* software pulser trigger (from fectrl)
* hardware pulser trigger (from the trigger board)
* NIM and eSATA trigger from ADC front panel inputs
* adc16 and adc32 discriminator triggers:
** adc16 grand-or trigger
** adc32 grand-or trigger
** adc (adc16+adc32) grand-or trigger
** adc16 multiplicity trigger (1ormore, 2ormore, 3ormore, 4ormore) for use with barrel scintillator
** anode wire multiplicity trigger (1ormore, 2ormore, 3ormore, 4ormore) (anode wire signals can be fed from adc16 or from adc32 signals)
** anode wire coincidence trigger
** anode wire MLU (memory lookup) trigger

== NIM trigger from ADC front panel ==

Trigger path:
<pre>
NIM signal --> LEMO input on ADC front panel --> data encoder --> data link to trigger board --> data decoder --> mask --> nim-esata-grand-or --> trigger
</pre>

To enable NIM trigger, do this:
* connect NIM signal to ADC front panel input
** Note1: NIM signal must be inverted
** Note2: LEMO connectors should be set to "NIM input" mode by ADC on-board jumpers (see ADC manual)
* observe correct bit goes to zero in the TRG web page: data link high work should change:
<pre>
0xNF00'0000 (N is the module id) to
0xN700'0000 (left lemo) or
0xNB00'0000 (right lemo)
</pre>
* Note3: if data link bits do not change, most likely the LEMO connectors are set to "DAC output" mode. Try to use LEMO inputs of a different ADC.
* compute the NIM mask: there are 32 bits, 2 bits per ADC data link. Bit 0x1 is right LEMO, bit 0x2 is left LEMO
* for example, to use left LEMO of ADC data link 12, set nim mask to (0x2)<<(2*12) = 0x02000000
* development branch of the git repository contains ''scripts/nim_mask.py'', which can compute forwards and backwards
* initialize the trigger board (on the TRG web page press button "initialize"), or start a new run
* on the history plot with "NIM grand or" counter, the rate should change from zero
* if a run is active, if one of the ADC LEMO outputs is set to output the trigger signal as a NIM pulse, one should see it fire use a scope. The delay or jitter between NIM trigger in and NIM trigger out should be around 100-200 ns (FIXME - measure this!)
* to set the DAQ to trigger on the NIM signal, on the run start page, check the box "TrigEsataNimGrandOr".
** Note: remember to set the scaledown to 0 if so desired.

= TPC field wire pulser =

The TPC field wire pulser input should be connected directly to the DAC output of ADC[0] (right lemo connector).

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for pulsing PWBs, baseline -1V, pulse height +2V (maximum possible pulse height in PWBs. Overdrives the AW ADC waveforms)
** dac_baseline: -8000
** dac_amplitude: 8000
** ramp_up_rate: 128
** ramp_down_rate: 70
** ramp_top_len: 128

* for pulsing AW, baseline -0.25V, pulse height +0.7V (AW ADC waveforms are in range. PWB waveforms are too small for goor time resolution)
** dac_baseline: -2000
** dac_amplitude: 4000
** ramp_up_rate: 20
** ramp_down_rate: 20
** ramp_top_len: 128

= BSC pulser =

The BSC pulser input on the BSC VME rear transition board (RTM) should be connected directly to the DAC output of ADC[4,5,6,7] (right lemo connector). (8 RTMs, but 4 ADCs, each signal is split using a LEMO "T" connector).

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for pulsing BSC, baseline -0.950V, pulse height +1.4V
** dac_baseline: -8000
** dac_amplitude: 4000
** ramp_up_rate: 64
** ramp_down_rate: 64
** ramp_top_len: 128

= NIM output =

To configure ADC analog output for NIM compatible pulse:

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for output of NIM pulse: baseline 0V, pulse height -0.9V, pulse width 100 ns
** dac_baseline: 0
** dac_amplitude: 8000
** ramp_up_rate: 128
** ramp_down_rate: 128
** ramp_top_len: 4
** dac_xor: 1 (invert the signal)

= TDC connections =

* SFP8 - fiber SFP to Juniper switch
* right RJ45 - 200MHz clock
* left RJ45 - external trigger

= MIDAS Data banks =

* ATAT - fectrl - UDP packets from GRIF-C/TRG trigger board
* TRBA - fetdc - TDC data
* TRTM - fetdc - TDC FPGA temperatures, TID_FLOAT[5].
* AAnn - feudp - UDP packets from GRIF-16 ADC (before the event builder), "nn" is the ADC module number: adc01 is AA01 through adc20 is AA20.
* BBxx - feudp - UDP packets from PWB, obsolete
* Bnnm, Cnnm - feevb - EVB output banks: ADC data, "nn" is the ADC module number (1..20), "m" is the channel number (0..9,A..F), format is same as AAnn banks.
* PAnn - feudp - UDP packets from PWB, "nn" is the PWB module number (00..99), obsolete
* PBnn - feudp - UDP packets from PWB, "nn" is the PWB module number (00..99), PB01 is pwb01, PB78 is pwb78
* PCnn - feevb - EVB output banks: PWB data, "nn" is the PWB module number (00..99), same as above, format is same as PBnn banks

= ZZZ =

ZZZ

TRG

2022-07-25T18:06:24Z

Olchansk: /* Firmware revisions */

= TRG, the trigger control board for the ALPHA-g detector =

= Links =

* xxx
* https://bitbucket.org/expalpha/trg_firmware - firmware sources on bitbucket

= General characteristics =

== Photos ==

== Board schematics ==

* https://bitbucket.org/expalpha/trg_firmware/src/master/3xFMC_VME_Motherboard.pdf

== Available hardware ==

* Altera Stratix IV - main FPGA
* Altera Max V - boot FPGA
* boot flash: PC28F512M29EW - 512 Mbit parallel NOR flash.

= TRG front panel connections =

From top to bottom:

<pre>
|
| minisas-C - links 8-11
| minisas-D - links 12-15
|
| ethernet sfp - use copper sfp only
| minisas - not used, do not connect
| esata - clock in, trigger out
|
| minisas-A - links 0-3
| minisas-B - links 4-7
|
| LEDs
|
</pre>

MiniSAS and SATA flail cable connections:

<pre>
P1 <--> link 3
P2 <--> link 2
P3 <--> link 1
P4 <--> link 0
</pre>

LEDs:

<pre>
--PCB-- (left)
LED[0] - trigger out - ag_trig_out
LED[1] - network packet received - sfp_rx_data_valid
LED[2] - Xilinx FPGA boot ok - FMC1_CFG_DONE
LED[3] - not used
(right)
</pre>

= TRG onboard jumpers and switches =

* rotary switches: select IP address: 00=192.168.1.50, 11=.51, 22=.52, 33=.53, 44=.54, otherwire=.251

= Firmware update procedure =

* use quartus to generate the grifc.pof file (use grifc.cof)
* open quartus programmer
* attach grifc.pof to the 1st CFI_512 flash
* mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
* check that "initiate configuration after programming" is set in tools->options
* say "start"
* should take about 5 minutes
* grifc should reboot into the new firmware

If CFI_512 flash is not visible to the quartus programmer, load correct
code into the MaxV CPLD:

* open quartus programmer,
* say "auto detect"
* change file for the 5M2210 device
* use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
* say "program", it should finish in 10-15 seconds
* say "auto detect"
* CFI_512 flash should be visible now.

= Firmware revisions =

* 0x5bc8f90f - original firmware used for all data
* 0x6147c0f9 - added cbtrg, etc. installed at CERN on 20 Sep 2021.
* 0x618376ae - bigger cbtrg fifo, data rate tested up to 30 Mbytes/sec
* 0x6189c7f3 - fix loss of trigger packets. (missing fifo between alphag block and ethernet mux)
* 0x618b790b - fix loss of timestamps. (cbtrg inputs stretched to 100 ns long). installed at CERN 10 Nov 2021.
* 0x62d32d95 - updated cbtrg, switched to edge-triggered cbtrg inputs, improved BSC multiplicity trigger, improved coinc trigger, added burst pulser. installed at CERN 19 Jul 2022.
* 0x62ded109 - fix cbtrg fifo data corruption, 1st fifo word was missing, 2nd fifo word sent twice.

= Firmware build =

* use quartus 20.1
* see Makefile in the trg_firmware project

= Jtag remote connection =

* ssh agmini@daq16
* /opt/intelFPGA/16.1/quartus/bin/jtagd --config /home/agmini/.jtagd.conf
* netstat -an | grep 1309 ### note listen address is "0.0.0.0", NOT "127.0.0.1"
<pre>
tcp 0 0 0.0.0.0:1309 0.0.0.0:* LISTEN
</pre>
* opt/intelFPGA/16.1/quartus/bin/jtagconfig ### should work
* ssh olchansk@daq01
* cd git/trg_firmware
* /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
* jtagconfig ### should work
<pre>
daq01:trg_firmware$ jtagconfig
1) DE-SoC on daq16 [2-1.2.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) USB-Blaster on daq16 [2-1.3]
024090DD EP4SGX230(.|ES)
020A40DD 5M(1270ZF324|2210Z)/EPM2210

daq01:trg_firmware$
</pre>

= ALPHA-g trigger functions =

Trigger options:
* software trigger
* pulser trigger
* trigger on GRIF16 ADC NIM and ESATA inputs ("external trigger")
* adc16 grand-or
* adc32 grand-or
* adc16 wire multiplicity
* TPC anode wire per-preamp trigger (aw16 section)
** trigger on coincidences of preamps (removed fw 0x62c77f0b)
** trigger on multiplicity of preamps (removed fw 0x62c77f0b)
** trigger on specific topology of preamps (multiplicity of preamp clusters, etc) via the aw16_mlu trigger
* BSC trigger
** BSC grand_or
** BSC bar multiplicity
* coincidence trigger - select coincidence of external trigger, TPC AW grand-or, TPC AW MLU, BSC grand-or and BSC bar multiplicity triggers

== software trigger ==

to programmatically fire the trigger, one should:
* set the conf_enable_sw_trigger bit in conf_trig_enable, this will permit the software trigger to fire the trigger
* write value 0x4 to register 0x2B, this will cause the software trigger to fire

== pulser trigger ==

To use the pulser trigger, one should program:
* pulser period (in clocks)
* pulser width (in clocks, use value 5, the pulser no longer goes outside of the trigger board, so changing the width does not do anything)
* set the run_pulser bit in conf_trig_enable, this will cause the pulser to run
* set the enable_pulser bit in conf_trig_enable, this will cause the pulser to fire the trigger
* set the output_pulser bit in conf_trig_enable, this will cause the pulser to be output from the alphag firmware block (the pulser no longer goes outside of the trigger board, so changing the bit does not do anything)

== timeout trigger ==

The event builder uses event timestamps to assemble physics events. The timestamps
are usually 32 bit wide and run at 125 MHz (8 ns) or 62.5 MHz (16 ns). If
triggers are generated often (1 per second or more), timestamp wrap around
is easily detected by the event builder. If triggers come infrequently,
timestamp wrap around may occur while there are no triggers, not be seen
by the event builder causing loss of event synchronization.

To avoid this problem in the event builder, a timeout trigger should be generated
if no triggers were generated inside a 10 second interval.

The guaranties that even if all physics triggers temporarily stop for any reason,
the event builder will stay synchronized. (0.1 Hz timeout trigger frequency).

To enable the timeout trigger:
* program timeout trigger timeout in reg 0x43 in units of 8 ns clock
* enable it in bit 23 of [[#conf_trig_enable bits]]

== adc16 multiplicity trigger ==

This trigger is intended for use with the barrel scintillator signals connected to adc16 digitizers. It does not work well with TPC AW signals.

The 16 adc16 trigger bits (16x16=256) are added together to form the hit multiplicity value (adc16_mult, 16 bits, actual range 0 to 256).

Four threshold signals are computed: adc16_mult_1ormore = adc16_mult>=1, 2ormore, 3ormore, 4ormore.

There is a counter for each of these four signals.

Each of these four signals can fire the trigger, see [[#conf_trig_enable bits]].

== TPC anode wire triggers ==

=== aw16 bus ===

TPC Anode Wire trigger is based on the aw16[15:0] (xaw16) bus.

Each bit corresponds to one AW preamp. 16 preamps, 16 bits.

The aw16[15:0] bus can be fed by
* adc16_or16[15:0] - or16 of 100 MHz ADCs, 16 ADC sas links
* adc32_or16[15:0] - or16 of 62.5 MHz ADCs, FMC-ADC32 has 32 channels, so 2 bits per ADC: low 16 channels and high 16 channels, sas links 7..0
* adc32_or16[31:16] - or16 of 62.5 MHz ADCs, ditto, sas links 15..8
as selected by conf_enable_aw_adc16, conf_enable_aw_adc32a, conf_enable_aw_adc32b in [[#conf_control bits]]

<pre>
///////////////////////////////////////////////////////////
// TPC Anode Wire trigger logic (aw16)
///////////////////////////////////////////////////////////

// map adc signals into aw16

wire [15:0] aw16 = ({16{conf_enable_aw_adc16}} & adc16_or16[15:0]) |
({16{conf_enable_aw_adc32a}} & adc32_or16[15:0]) |
({16{conf_enable_aw_adc32b}} & adc32_or16[31:16]);
...
ag_conditioner cond_adc16_or16_0(.clk(clk), .in(aw16[0]), .out(xxaw16[0]));
...
xaw16 <= xxaw16;
</pre>

=== aw16_grand_or ===

TPC AW "grand or" trigger: use aw16_mult_1ormore (before fw 0x62c77f0b)

(256 anode wires, 16 wires per preamp, 16 preamps, 16 aw16 signals)

=== aw16_mlu ===

TPC AW preamp MLU trigger: the MLU (memory lookup
table) implements an arbitrary logical function
to map the 16 aw16 preamp signals into 1 aw16_mlu_trig trigger output.

Description of the aw16 mlu trigger.

In words:

* any aw16 signal starts the aw16_prompt_run gate
* aw16 signals are collected for the duration of conf_mlu_prompt (125MHz/8ns clock)
* this corresponds to time spread of TPC AW signals due to the drift time in the AW drift cell and to the variation in signal transmission time from the ADC to the TRG (digital trigger data link).
* when this prompt time expires, the MLU looks at the accumulated aw16_prompt bit pattern and makes the "yes/no" trigger decision
* after the trigger decision is made, we wait for the TPC to become quiet:
* we wait until all aw16 signals are empty (no timeout)
* we run the aw16_prompt_wait gate, length conf_mlu_wait (8ns clock), if any aw16 signals arrive, we wait for aw16 empty again, rinse, repeat.
* now, after TPC aw16 have been empty for conf_mlu_wait clocks (8ns clock), MLU trigger is ready for the next event.

In logic: (see alphag.v)

* aw16_or <= grand-or of 16 aw16 signals
* "aw16_or" starts the "aw16_prompt_cnt" counter, opens the aw16_prompt_run gate
* during the aw16_prompt_run gate, aw16_prompt collects (latches) the aw16 bits (aw16_prompt <= aw16_prompt | aw16)
* this is the time when we wait for all "prompt" signals from the TPC to arrive into the trigger
* at the end of the aw16_prompt_run gate, the signal aw16_prompt_out is pulsed, latching the output of the MLU into aw16_mlu_trig
* this is the MLU trigger "yes/no" trigger decision.
* after the MLU trigger decision is made, we wait for the arrival and passing of all TPC drift signals
* the aw16_prompt_wait_cnt and aw_prompt_wait gate opens
* if any new aw16 signals arrive (they are TPC drift signals at this time), the aw16_prompt_wait gate is restarted
* if no aw16 signals arrive during the full run of the aw16_prompt_wait gate ("TPC quiet time")
* the aw16_prompt_wait and aw16_prompt gates are cleared and the MLU trigger is ready for the next event.

Good settings are:
* conf_mlu_prompt: 64 (512 ns)
* conf_mlu_wait: 128 (1024 ns)

== BSC trigger ==

=== bsc_adc16 bus ===

The BSC trigger is based on the [15:0]bsc_adc16[7:0] bus: 16 trigger discriminator bits from 8 ADC sas links. (8*16 = 64+64 bars, top and bottom).

The bsc_adc16 bus can be fed from sas links 0..7 or 8..15, controlled by conf_bsc_adc16_a and conf_bsc_adc16_b bits on [[#conf_bsc_control bits]].

bsc_adc16 can be fed only from GRIF-16 100 MHz ADC trigger discriminators.

=== bsc64_top and bsc64_bot buses ===

* firmware 0x5bc8f90f: bsc_adc16 is remapped into 64 bits of top (bsc64_top) and bottom (bsc64_bot):
<pre>
ag_bsc_remap bsc_remap_a(.adc(bsc_adc16[0]), .bsc_bot(bsc64_bot[7:0]), .bsc_top(bsc64_top[7:0]));
ag_bsc_remap bsc_remap_b(.adc(bsc_adc16[1]), .bsc_bot(bsc64_bot[8+7:8+0]), .bsc_top(bsc64_top[8+7:8+0]));
ag_bsc_remap bsc_remap_c(.adc(bsc_adc16[2]), .bsc_bot(bsc64_bot[2*8+7:2*8+0]), .bsc_top(bsc64_top[2*8+7:2*8+0]));
ag_bsc_remap bsc_remap_d(.adc(bsc_adc16[3]), .bsc_bot(bsc64_bot[3*8+7:3*8+0]), .bsc_top(bsc64_top[3*8+7:3*8+0]));

ag_bsc_remap bsc_remap_e(.adc(bsc_adc16[4]), .bsc_bot(bsc64_bot[4*8+7:4*8+0]), .bsc_top(bsc64_top[4*8+7:4*8+0]));
ag_bsc_remap bsc_remap_f(.adc(bsc_adc16[5]), .bsc_bot(bsc64_bot[5*8+7:5*8+0]), .bsc_top(bsc64_top[5*8+7:5*8+0]));
ag_bsc_remap bsc_remap_g(.adc(bsc_adc16[6]), .bsc_bot(bsc64_bot[6*8+7:6*8+0]), .bsc_top(bsc64_top[6*8+7:6*8+0]));
ag_bsc_remap bsc_remap_h(.adc(bsc_adc16[7]), .bsc_bot(bsc64_bot[7*8+7:7*8+0]), .bsc_top(bsc64_top[7*8+7:7*8+0]));

module ag_bsc_remap
(
input wire [15:0] adc,
output wire [7:0] bsc_bot,
output wire [7:0] bsc_top
);

assign bsc_top[3] = adc[0];
assign bsc_top[2] = adc[1];
assign bsc_top[1] = adc[2];
assign bsc_top[0] = adc[3];

assign bsc_top[7] = adc[4];
assign bsc_top[6] = adc[5];
assign bsc_top[5] = adc[6];
assign bsc_top[4] = adc[7];

assign bsc_bot[0] = adc[8];
assign bsc_bot[1] = adc[9];
assign bsc_bot[2] = adc[10];
assign bsc_bot[3] = adc[11];

assign bsc_bot[4] = adc[12];
assign bsc_bot[5] = adc[13];
assign bsc_bot[6] = adc[14];
assign bsc_bot[7] = adc[15];

endmodule
</pre>

=== bsc64 bus ===

the bsc64 bus is the 64 bars used by the trigger, formed from bsc64_top and bsc64_bot:
<pre>
if (conf_bsc64_bot_only) begin
bsc64 <= bsc64_bot;
end else if (conf_bsc64_top_only) begin
bsc64 <= bsc64_top;
end else if (conf_bsc64_bot_top_or) begin
bsc64 <= bsc64_bot | bsc64_top;
end else if (conf_bsc64_bot_top_and) begin
bsc64 <= bsc64_bot & bsc64_top;
end else begin
bsc64 <= 64'b0;
end
</pre>

=== bsc_grand_or_trig ===

bsc_grand_or_trig is the grand-or of 64 bits of the bsc64 bus

to enable triggering on bsc_grand_or_trig, set corresponding bit in [[#conf_trig_enable bits]]

=== old bsc_mult_trig ===

(from fw 0x62c77f0b, old bsc_mult_trig was replaced by new bsc64 multiplicity trigger)

* bsc64_mult is computed as multiplicity of the bsc64 bus (number of 64 bsc64 bits that fired)
* bsc_mult_trig is computed:
<pre>
if (bsc64_mult >= conf_bsc64_mult) begin
bsc_mult_trig <= 1;
end else begin
bsc_mult_trig <= 0;
end
</pre>

to enable the bsc multiplicity trigger, set the multiplicity value conf_bsc64_mult in [[#conf_bsc_control bits]] and enable the corresponding bit in [[#conf_trig_enable bits]].

=== bsc64 multiplicity trigger ===

bsc64 BSC bar multiplicity trigger uses a time window. this time window is started by bsc64_grand_or and runs for conf_bsc64_mult_window clocks (8 nc clock). During this time, hits in bsc64_bus are accumulated (latched) and their multiplicity is computed. If multiplicity condition is satisfied (bigger or equal to conf_bsc64_mult_min), bsc64_mult_trig is fired and the bsc64 bit pattern is saved to the UDP packet. Then trigger waits for the bsc64_bus to be empty. Then trigger waits for conf_bsc64_empty_window clocks, if there is any bsc64 hits, we wait for empty again. So after bsc64 has been empty for conf_bsc64_empty_window clocks, multiplicity trigger is ready for the next event. This scheme cannot implement max multiplicity.

recommended values:
* conf_bsc64_mult_window (8 bits): slightly longer than 3 cycles of SAS link: 3*18 = 54 clocks, good value is 80 (640 ns).
* conf_bsc64_mult_min (8 bits): 2
* conf_bsc64_empty_window (8 bits): 80 (640 ns)

== Coincidence trigger ==

Coincidence trigger provides a combination of TPC, BSC and external scintillator (esata_nim_grand_or) signals:

<pre>
assign coinc_input[0] = aw16_grand_or; // was aw16_mult_1ormore;
assign coinc_input[1] = aw16_mlu_trig;
assign coinc_input[2] = bsc_grand_or_trig;
assign coinc_input[3] = bsc_mult_trig;
assign coinc_input[4] = esata_nim_grand_or;
assign coinc_input[5] = 0;
assign coinc_input[6] = 0;
assign coinc_input[7] = 0;
</pre>

Coincidence trigger "start" mask selects which of the inputs can start the coincidence window.

Coincidence trigger "require" mask selects which inputs must have a hits for the coincidence to be satisfied.

Input hits are collected for the duration of the coincidence window, if all required inputs have hits, coinc_trig is fired.

Example settings:

* coincidence of external scintillator, BSC and TPC AW "grand or" signals: start 0x10, required 0x15
* coincidence of BSC grand-or and TPC AW grand-or signals: start 0x5, required 0x5
* coincidence of BSC multiplicity and TPC AW grand-or triggers: start 0x9, required 0x9

= Control registers =

== Register addresses ==

Note: all registers are 32 bits unless otherwise noted.

Note: RW means read-write register, RO means read-only, ROL means read-only, contents is latched by the "latch_out" bit

{| cellpadding="10" cellspacing="0" border="1"
! Address || Quartus Name || Access || FwRev || Description
|-
| 0x08 || num_sample || RW || GRIF-C || magic 16-bit register to control UDP packet size
|-
| 0x08 || scratch_reg || RW || 0x618b790b || 32-bit scratch register
|-
| 0x1F || compilation_time || RO || || Firmware revision
|-
| 0x20 || conf_trig_width || RW || || Trigger signal width, 16 ns clock
|-
| 0x21 || conf_busy_width || RW || || Busy signal width, 16 ns clock (not used)
|-
| 0x22 || conf_pulser_width || RW || || Pulser signal width, 16 ns clock
|-
| 0x23 || conf_pulser_period || RW || || Pulser signal period, 16 ns clock
|-
| 0x24 || conf_pulser_burst_ctrl || RW || 0x62d1c47e || Generate bursts of pulses: 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses, 16 ns clocks
|-
| 0x25 || conf_trig_enable || RW || || see [[#conf_trig_enable bits]]
|-
| 0x26 || || || not used
|-
| 0x27 || || || not used
|-
| 0x28 || || || not used
|-
| 0x29 || conf_nim_mask || RW || || enable bits for ADC NIM inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2A || conf_esata_mask || RW || || enable bits for ADC eSATA inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2B || reset_out, latch_out, trigger_out || W || || see [[#reg 0x2B bits]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x5bc8f90f || configure AW coincidence trigger, see [[#aw16_coinc]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x62c77f0b || removed
|-
| 0x2D || conf_aw16_coinc_b || RW || 0x5bc8f90f ||
|-
| 0x2E || conf_aw16_coinc_c || RW || 0x5bc8f90f ||
|-
| 0x2F || conf_aw16_coinc_d || RW || 0x5bc8f90f ||
|-
| 0x30 || sas_sd[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect for each link
|-
| 0x31 || pll_625_status || ROL || 0x5b2057f5 (12Jun18_16:32) || 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter
|-
| 0x32 || clk_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the system 125 MHz clock
|-
| 0x33 || clk_625_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625)
|-
| 0x34 || conf_control || RW || 0x5b398983 (01Jul18_19:10) || see [[#conf_control bits]] below
|-
| 0x35 || conf_drift_width || RW || 0x5b398983 (01Jul18_19:10) || width of drift time blank-out in 16 ns clocks
|-
| 0x36 || conf_scaledown || RW || 0x5b398983 (01Jul18_19:10) || trigger scaledown, 0=no scaledown, 1=divide-by-2, 2=divide-by-3, etc
|-
| 0x37 || conf_mlu || RW || 0x5b398983 (01Jul18_19:10) || AW MLU control bits, see [[#conf_mlu bits]]
|-
| 0x38 || conf_trig_delay || RW || 0x5baedfca (28Sep18_19:13) || delay the trigger pulse, 16 ns clock
|-
| 0x39 || esata_clk_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the TRG 125 MHz clock
|-
| 0x3A || esata_clk_esata_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the external clock (eSATA 62.5 MHz clock)
|-
| 0x3B || conf_counter_adc_select || RW || 0x5bb7f6ae (05Oct18_16:41) || select which 16 ADCs are connected to the selected adc counters, 0..15 - connect the adc16 signals, 16..47 connect the adc32 signals
|-
| 0x3C || sysreset_ts || RO || 0x5bb7f6ae (05Oct18_16:41) || 125MHz counter of VME-SYSRESET
|-
| 0x3C || || || 0x618b790b || not used
|-
| 0x3D || GRIF-C csr || RW || GRIF-C || <= csr & ~par_value; // Selective clear
|-
| 0x3E || GRIF-C csr || RW || GRIF-C || <= csr | par_value; // Selective set
|-
| 0x3F || GRIF-C csr || RW || GRIF-C || <= par_value; // write
|-
| 0x3D || || || 0x618b790b || not used
|-
| 0x3E || || || 0x618b790b || not used
|-
| 0x3F || || || 0x618b790b || not used
|-
| 0x40 || conf_bsc_control || RW || 0x5bc13541 (12Oct18_16:58) || Barrel Scintillator trigger control, see [[#conf_bsc_control bits]]
|-
| 0x41 || conf_coinc_control || RW || 0x5bc13541 (12Oct18_16:58) || Coincidence trigger control, see [[#conf_coinc_control bits]]
|-
| 0x42 || reconfig_out || WO || 0x5bc13541 (12Oct18_16:58) || reserved for rebooting the FPGA (does not work)
|-
| 0x43 || conf_trigger_timeout || RW || 0x5bc8f90f (18Oct18_14:20) || Generate timeout trigger if there is no other trigger after given timeout, in 8 ns clocks, must be enabled by bit conf_enable_timeout_trig in [[#conf_trig_enable bits]]
|-
| 0x44 || eth_clk_counter || ROL || 0x618b790b ||
|-
| 0x45 || eth_clk_eth_counter || ROL || 0x618b790b ||
|-
| 0x100 || ts_625 || ROL || || latched timestamp
|-
| 0x101 || counter_trig_out || ROL || || counter of issued triggers
|-
| 0x102 || counter_trig_in || ROL || || counter of triggers
|-
| 0x103 || counter_pulser || ROL || || counter of pulser
|-
| 0x104 || counter_adc16_grand_or || ROL ||
|-
| 0x105 || counter_adc32_grand_or || ROL ||
|-
| 0x106 || counter_adc_grand_or || ROL ||
|-
| 0x107 || counter_esata_nim_grand_or || ROL ||
|-
| 0x108 || counter_adc16_mult_1ormore || ROL ||
|-
| 0x109 || counter_adc16_mult_2ormore || ROL ||
|-
| 0x10A || counter_adc16_mult_3ormore || ROL ||
|-
| 0x10B || counter_adc16_mult_4ormore || ROL ||
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x5bc8f90f || counter of AW coincidence triggers
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x62c77f0b || removed
|-
| 0x10D || counter_aw16_coinc_b || ROL || 0x5bc8f90f ||
|-
| 0x10E || counter_aw16_coinc_c || ROL || 0x5bc8f90f ||
|-
| 0x10F || counter_aw16_coinc_d || ROL || 0x5bc8f90f ||
|-
| 0x110 || counter_drift || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the drift time blank-out
|-
| 0x111 || counter_scaledown || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the scaledown
|-
| 0x112 || counter_aw16_coinc || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW coincidence triggers
|-
| 0x113 || counter_aw16_mlu || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW MLU triggers
|-
| 0x114 || counter_aw16_grand_or || ROL || 0x62c77f0b || counter of AW grand-or triggers
|-
| 0x114 || counter_aw16_mult_1ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 1ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 2ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x62c77f0b || removed
|-
| 0x116 || counter_aw16_mult_3ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 3ormore triggers
|-
| 0x117 || counter_aw16_mult_4ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 4ormore triggers
|-
| 0x118 || counter_bsc_grand_or || ROL || 0x5bc13541 (12Oct18_16:58) || counter of BSC grand-or triggers
|-
| 0x119 || counter_bsc_mult || ROL || 0x5bc13541 (12Oct18_16:58) || counter of old BSC multiplicity triggers
|-
| 0x11A || counter_coinc || ROL || 0x5bc13541 (12Oct18_16:58) || counter of coincidence triggers
|-
| 0x11B || counter_timeout || ROL || 0x618b790b || counter of timeout triggers
|-
| 0x11C || counter_bsc_mult_start || ROL || 0x62c77f0b || counter of BSC multiplicity windows
|-
| 0x11D || counter_bsc_mult_trig || ROL || 0x62c77f0b || counter of BSC multiplicity triggers
|-
| 0x11E || counter_coinc_start || ROL || 0x62d1b152 || counter of coincidence windows
|-
| 0x11F || counter_aw16_mlu_start || ROL || 0x62d1b152 || counter of TPC AW MLU windows
|-
| 0x200..0x207 || conf_adc16_masks || RW || all || adc16 enable bits
|-
| 0x300..0x30F || conf_adc32_masks || RW || all || adc32 enable bits
|-
| 0x400..0x41F || sas_bits[15:0][63:0] || ROL || all || sas data bits for each link
|-
| 0x420..0x42F || sas_sd_counters[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect counter for each link
|-
| 0x430..0x43F || counters_adc16_or16[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 16 counters of adc16 ORes
|-
| 0x440..0x45F || counters_adc32_or16[31:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 32 counters of adc32 ORes
|-
| 0x460..0x46F || counters_adc_selected[15:0] || ROL || 0x5bb7f6ae (05Oct18_16:41) || 16 counters for selected group of adcs, see conf_counter_adc_select
|-
| 0x470..0x4AF || counters_bsc64[63:0] || ROL || 0x5bc13541 (12Oct18_16:58) || 64 counters for the BSC bars
|-
|}

== additional registers ==

<pre>
reg | rw/ro/rol | quartus name | firmware | description
-----------------------------------------------------------------
0x60 | rw | cb_control_out | 0x618b790b | chronobox control
0x61 | rw | cb_status | 0x618b790b | chronobox status
0x62 | rw | cb_invert_a_out | 0x618b790b | chronobox input invert
0x63 | rw | cb_invert_b_out | 0x618b790b |
0x64 | rw | cb_enable_le_a_out | 0x618b790b | timestamp enable leading edge
0x65 | rw | cb_enable_le_b_out | 0x618b790b |
0x66 | rw | cb_enable_te_a_out | 0x618b790b | timestamp enable traiing edge
0x67 | rw | cb_enable_te_b_out | 0x618b790b |
0x6A | ro | cb_input_num | 0x618b790b | chronobox number of inputs
0x6B | rw | cb_sync_mask_a_out | 0x618b790b | chronobox sync signal source
0x6C | rw | cb_sync_mask_b_out | 0x618b790b |
0x6D | rw | cb_sync_reg_out | 0x618b790b | chronobox sync register
0x6E | ro | cb_sync_status | 0x618b790b | chronobox sync status
0x6F | rw | cb_latch_period_out | 0x618b790b | chronobox scalers latch period
0x70 | ro | cb_fifo_status | 0x618b790b | chronobox data fifo status
0x71 | ro | cb_fifo_data | 0x618b790b | read chronobox data fifo (cb_fifo_rdack_out <= 1)
0x72 | rw | cb_udp_period_out | 0x618b790b | period for flushing fifo to UDP
0x73 | rw | cb_udp_threshold_out | 0x618b790b | byte threshold for flushing fifo to UDP
</pre>

== conf_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_clock_select || 0x5b3aa19f (02Jul18_15:05) || select 0=internal 62.5 MHz clock or 1=esata 62.5 MHz clock
|-
| 1 || conf_enable_aw_adc16 || 0x5baedfca (28Sep18_19:13) || select source of TPC AW aw16 bus, see [[#aw16 bus]]
|-
| 2 || conf_enable_aw_adc32a || 0x5baedfca (28Sep18_19:13) ||
|-
| 3 || conf_enable_aw_adc32b || 0x5baedfca (28Sep18_19:13) ||
|-
| 15..4 || || ||
|-
| 23..16 || conf_mlu_prompt || 0x5b3aa19f (02Jul18_15:05) || MLU trigger prompt window, see [[#aw16_mlu]]
|-
| 31..24 || conf_mlu_wait || 0x5b3aa19f (02Jul18_15:05) || MLU trigger wait window, see [[#aw16_mlu]]
|-
|}

== conf_mlu bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 31 || mlu_reset || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 30 || mlu_write || 0x5b3aa19f (02Jul18_15:05) || 1=write data bit into given address
|-
| 16 || mlu_data || 0x5b3aa19f (02Jul18_15:05) || data bit for writing to MLU RAM
|-
| 15..0 || mlu_write_addr || 0x5b3aa19f (02Jul18_15:05) || MLU RAM write address for writing the data bit
|-
|}

== conf_bsc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_bsc_adc_a || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 0..7
|-
| 1 || conf_bsc_adc_b || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 8..15
|-
| 2 || conf_bsc64_bot_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses bottom channels only
|-
| 3 || conf_bsc64_top_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses top channels only
|-
| 4 || conf_bsc64_bot_top_or || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "or" of top and bottom
|-
| 5 || conf_bsc64_bot_top_and || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "and" of top and bottom
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_bsc64_mult_min || 0x5bc13541 (12Oct18_16:58) || minimum bsc64 multiplicity
|-
| 23..16 || conf_bsc64_empty_wondow || 0x62d1c47e || bsc64 empty window length, 8 ns clocks
|-
| 31..24 || conf_bsc64_mult_window || 0x62c77f0b || bsc64 multiplicity window length, 8 ns clocks
|-
|}

== conf_coinc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_coinc_required[0] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mult_1ormore
|-
| 0 || conf_coinc_required[0] || 0x62c77f0b || enable aw16_grand_or
|-
| 1 || conf_coinc_required[1] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mlu_trig
|-
| 2 || conf_coinc_required[2] || 0x5bc13541 (12Oct18_16:58) || enable bsc_grand_or_trig
|-
| 3 || conf_coinc_required[3] || 0x5bc13541 (12Oct18_16:58) || enable bsc_mult_trig
|-
| 3 || conf_coinc_required[3] || 0x62c77f0b || enable bsc64_mult_trig
|-
| 4 || conf_coinc_required[4] || 0x5bc13541 (12Oct18_16:58) || enable esata_nim_grand_or
|-
| 5 || conf_coinc_required[5]
|-
| 6 || conf_coinc_required[6]
|-
| 7 || conf_coinc_required[7]
|-
| 15..8 || conf_coinc_window[7:0] || 0x5bc13541 (12Oct18_16:58) || coincidence window length in units of 125MHz clock (8 ns)
|-
| 23..16 || conf_coinc_start[7:0] || 0x5bc13541 (12Oct18_16:58) || start the coincidence window, same bits as "required"
|-
| 31..24 ||
|-
|}

== conf_trig_enable bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_enable_sw_trigger || || trigger on software trigger (how generated???)
|-
| 1 || conf_enable_pulser || || trigger on pulser
|-
| 2 || - || 0x5b120c9f (01Jun18_20:18) || not used
|-
| 3 || conf_pulser_run || || allow the pulser to run (frequency has to be set beforehand)
|-
| 4 || conf_output_pulser || 0x5bc8f90f || does nothing (top level ag_pulser_out is disconnected)
|-
| 4 || || 0x618b790b || not used
|-
| 5 || conf_enable_esata_nim || || trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand)
|-
| 6 || conf_enable_adc16 || || trigger on adc16_grand_or
|-
| 7 || conf_enable_adc32 || || trigger on adc32_grand_or
|-
| 8 || conf_enable_adc16_1ormore || || trigger on adc16_mult_1ormore "1 or more"
|-
| 9 || conf_enable_adc16_2ormore || || same, "2 or more"
|-
| 10 || conf_enable_adc16_3ormore || || same, "3 or more"
|-
| 11 || conf_enable_adc16_4ormore || || same, "4 or more"
|-
| 12 || - || 0x5b08938c (25May18_15:51) || not used
|-
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
|-
| 14 || - || 0x5bc8f90f || not used
|-
| 15 || conf_enable_adc || 0x5b120c9f (01Jun18_20:18) || trigger on adc_grand_or
|-
| 16 || conf_enable_aw16_coinc_a || 0x5bc8f90f || enable AW coincidence trigger, see [[#aw16_coinc]]
|-
| 16 || - || 0x62c77f0b || aw16_coinc_x removed
|-
| 17 || conf_enable_aw16_coinc_b || 0x5bc8f90f ||
|-
| 18 || conf_enable_aw16_coinc_c || 0x5bc8f90f ||
|-
| 19 || conf_enable_aw16_coinc_d || 0x5bc8f90f ||
|-
| 20 || - || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 20 || conf_enable_aw16_grand_or || 0x618b790b || enable trigger on aw16_grand_or
|-
| 21 || conf_enable_aw16_coinc || 0x5b3aa19f (02Jul18_15:05) || enable trigger on aw16_coinc_trig
|-
| 22 || conf_enable_aw16_mlu || 0x5b3aa19f (02Jul18_15:05) || enable AW MLU trigger
|-
| 23 || conf_enable_timeout_trig || 0x5bc8f90f (18Oct18_14:20) || enable trigger timeout trigger
|-
| 24 || conf_enable_aw16_1ormore || 0x5b3aa19f (02Jul18_15:05) || trigger on aw16_mult_1ormore "1 or more"
|-
| 24 || - || 0x62c77f0b || aw16_mult_xxx removed
|-
| 25 || conf_enable_aw16_2ormore || 0x5b3aa19f (02Jul18_15:05) || same, "2 or more"
|-
| 26 || conf_enable_aw16_3ormore || 0x5b3aa19f (02Jul18_15:05) || same, "3 or more"
|-
| 27 || conf_enable_aw16_4ormore || 0x5b3aa19f (02Jul18_15:05) || same, "4 or more"
|-
| 28 || conf_enable_bsc_grand_or || 0x5bc13541 (12Oct18_16:58) || trigger on BSC grand-or
|-
| 29 || conf_enable_bsc_mult || 0x5bc13541 (12Oct18_16:58) || trigger on BSC multiplicity
|-
| 30 || conf_enable_coinc || 0x5bc13541 (12Oct18_16:58) || trigger on TPC/BSC/ext coincidence trigger
|-
| 31 || - || || not used
|-
|}

== reg 0x2B bits ==

Write to this register will pulse corresponding fpga signals:

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || reset_out || 0x5b120c9f (01Jun18_20:18) || reset counters, etc
|-
| 1 || latch_out || 0x5b120c9f (01Jun18_20:18) || latch counters, sas bits, etc
|-
| 2 || trigger_out || 0x5b120c9f (01Jun18_20:18) || generate a software trigger
|-
|}

= UDP data format =

== general format ==

<pre>
trigger packet:

[0] udp packet counter
[1] 0x8ccccccc
...
[N] 0xEccccccc

different versions of trigger packets should be decoded according to packet length:
40 bytes: initial firmware
76 bytes: firmware 0x618b790b (Nov 2021)
80 bytes: firmware 0x62d1c47e (Jul 2022)

chronobox fifo packet, firmware 0x618b790b (Nov 2021)

[0] udp packet counter
[1] 0xCccccccc
[2] fifo status
[3] fifo data
...
[N] 0xEccccccc

0x0ccccccc is the 28 bit fifo packet counter

chronobox fifo packet, firmware 0x618b790b (Nov 2021)

[0] udp packet counter
[1] 0xDccccccc
[2] 0xDEADBEEF
[3] fifo status
[4] fifo data
...
[N] 0xEccccccc

0x0ccccccc is the 28 bit fifo packet counter
</pre>

== firmware 0x5bc8f90f ==

{| cellpadding="10" cellspacing="0" border="1"
! Offset || Name || Quartus name || FwRev || Description
|-
| 0 || packet counter || none || all || 31-bit UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
|-
| 1 || 0x8 packet header || || all || 28 bits of counter_trig_out
|-
| 2 || trigger timestamp || trig_ts || all || 62.5MHz trigger timestamp
|-
| 3 || accepted triggers || counter_trig_out || all || counter of accepted triggers
|-
| 4 || input triggers || counter_trig_in || all || counter of trigger input
|-
| 5 || pulser triggers || counter_pulser || all || counter of pulser triggers
|-
| 6 || trigger bitmap || udp_trig_bits || 0x5a48448d (30Dec17_17:59) || bitmap of trigger information, see below
|-
| 7 || nim bits || udp_nim_bits_masked || ??? || 32 bits of ADC NIM inputs (2 bits per ADC)
|-
| 8 || esata bits || udp_esata_bits_masked || ??? || 32 bits of ADC ESATA inputs (2 bits per ADC)
|-
| 9 || mlu bits || aw16_prompt || 0x5b398983 (01Jul18_19:10) || 16 bits of MLU input, 1 bit per preamp
|-
| 10 || drift-blank-off counter || udp_drift_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the drift blank-off
|-
| 11 || scaledown counter || udp_scaledown_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the scaledown
|-
| X || || || ||
|-
| 12 || 0xE packet footer || || all || 28 bits of counter_trig_out
|-
|}

== firmware 0x618b790b (Nov 2021) ==

packet size 76 bytes

<pre>
0 udp packet counter
1 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
2 udp_data_out <= udp_trig_ts_625;
3 udp_data_out <= udp_counter_trig_out;
4 udp_data_out <= udp_counter_trig_in;
5 udp_data_out <= udp_counter_pulser;
6 udp_data_out <= udp_trig_bits;
7 udp_data_out <= udp_nim_bits;
8 udp_data_out <= udp_esata_bits;
9 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
10 udp_data_out <= udp_counter_drift;
11 udp_data_out <= udp_counter_scaledown;
12 udp_data_out <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
13 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
14 udp_data_out <= { udp_bsc64_bus[31:0]};
15 udp_data_out <= { udp_bsc64_bus[63:32]};
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
17 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
18 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

== firmware 0x62d1c47e (Jul 2022) ==

packet size 80 bytes

<pre>
0 udp packet counter
1 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
2 udp_data_out <= udp_trig_ts_625;
3 udp_data_out <= udp_counter_trig_out;
4 udp_data_out <= udp_counter_trig_in;
5 udp_data_out <= udp_counter_pulser;
6 udp_data_out <= udp_trig_bits;
7 udp_data_out <= udp_nim_bits;
8 udp_data_out <= udp_esata_bits;
9 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
10 udp_data_out <= udp_counter_drift;
11 udp_data_out <= udp_counter_scaledown;
12 udp_data_out <= { 8'h00, 8'h00, 16'h0000 };
13 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
14 udp_data_out <= { udp_bsc64_bus[31:0]};
15 udp_data_out <= { udp_bsc64_bus[63:32]};
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
17 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
18 udp_data_out <= conf_fw_rev;
19 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

Values of udp_coinc_latch[7:0]:
* aaa

Values of udp_aw16_mult[7:0] and udp_aw16_bus[15:0]:
* aaa

Values of udp_bsc64_mult[7:0] and udp_bsc64_bus[63:0]
* aaa

== trigger bitmap ==

Firmware ??? (one of the very early revisions)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= adc16_coinc_top;
udp_trig_bits[5] <= adc16_coinc_bot;
udp_trig_bits[6] <= adc16_coinc;
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
udp_trig_bits[31:24] <= mult16[7:0];

</pre>

Firmware 0x5b08938c (25May18_15:51)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= 0; // not used
udp_trig_bits[31:24] <= mult16[7:0];
</pre>

Firmware 0x5b217dc4 (13Jun18_13:25)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5b3aa19f (02Jul18_15:05)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= udp_mlu_out;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5bc8f90f (18Oct18_14:20)

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_run_pulser
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = 0; // not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x618b790b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x62c77f0b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = 0; // aw16_coinc_a;
assign trig32_in[17] = 0; // aw16_coinc_b;
assign trig32_in[18] = 0; // aw16_coinc_c;
assign trig32_in[19] = 0; // aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = 0; // aw16_mult_1ormore;
assign trig32_in[25] = 0; // aw16_mult_2ormore;
assign trig32_in[26] = 0; // aw16_mult_3ormore;
assign trig32_in[27] = 0; // aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc64_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

= TRG chronobox inputs =

from trg_firmware/toplevel/grifc.v

<pre>
localparam CB_N = 23;
localparam CB_N1 = CB_N-1;

wire [CB_N1:0] cb_xinputs_async;

assign cb_xinputs_async[0] = ag_trig_out;
assign cb_xinputs_async[1] = ag_trig_scaledown_out;
assign cb_xinputs_async[2] = ag_trig_drift_out;
assign cb_xinputs_async[3] = ag_trig_received_out;

assign cb_xinputs_async[4] = ag_cb_sw_trig;
assign cb_xinputs_async[5] = ag_cb_pulser_trig;
assign cb_xinputs_async[6] = ag_cb_esata_nim_trig;
assign cb_xinputs_async[7] = ag_cb_adc16_grand_or_trig;
assign cb_xinputs_async[8] = ag_cb_adc32_grand_or_trig;

assign cb_xinputs_async[9] = ag_cb_aw16_grand_or_trig;
assign cb_xinputs_async[10] = ag_cb_aw16_mult_1ormore;
assign cb_xinputs_async[11] = ag_cb_aw16_mult_2ormore;
assign cb_xinputs_async[12] = ag_cb_aw16_mult_3ormore;
assign cb_xinputs_async[13] = ag_cb_aw16_mult_4ormore;
assign cb_xinputs_async[14] = ag_cb_aw16_mlu_trig;

assign cb_xinputs_async[15] = ag_cb_bsc64_grand_or_trig;
assign cb_xinputs_async[16] = ag_cb_bsc64_mult_1ormore;
assign cb_xinputs_async[17] = ag_cb_bsc64_mult_2ormore;
assign cb_xinputs_async[18] = ag_cb_bsc64_mult_3ormore;
assign cb_xinputs_async[19] = ag_cb_bsc64_mult_4ormore;
assign cb_xinputs_async[20] = ag_cb_bsc64_mult_trig;

assign cb_xinputs_async[21] = ag_cb_coinc_trig;

assign cb_xinputs_async[22] = ag_cb_timeout_trig;
</pre>

= Example UDP packets =

* trigger data, marker words 0x8

<pre>
ReadDataThread read 76
0: 0x003666ed -- UDP packet counter from UDP transmitter
1: 0x80000bf8 -- 0x8 is trigger data packet, 0xbf8 is the trigger counter from alphag.v
2: 0x2edf8b41 -- trigger data
3: 0x00000bf8
4: 0x00000bf8
5: 0x00000bee
6: 0x00000001
7: 0x00000000
8: 0x00000000
9: 0x00000003
10: 0x00000bf8
11: 0x00000bf8
12: 0x00000000
13: 0x00000000
14: 0x00000000
15: 0x00000000
16: 0x00000000
17: 0x00000000
18: 0xe0000bf8 -- 0xE is end of trigger data, counter 0xbf8 must match the counter in the 0x8 word.
ReadDataThread read 76 -- next packet
0: 0x003666ee -- UDP packet counter from UDP transmitter
...
</pre>

* chronobox fifo data, marker word 0xC, see [[Chronobox#FIFO_data_format]]

<pre>
ReadDataThread read 404
0: 0x003658ed -- UDP packet counter from UDP transmitter
1: 0xc000eacc -- 0xC is FIFO data, fifo packet counter 0xeacc from fifo_to_udp.v
2: 0x00000061 -- FIFO status, low bits the the word counter, so up to 0x61 fifo words are to follow
3: 0x87fb3d72 -- tsc hits
4: 0x8ffb3d74
5: 0x90fb3d74
6: 0x91fb3d74
7: 0x92fb3d74
8: 0x93fb3d74
9: 0x93fb3d75
10: 0x94fb3d74
11: 0x94fb3d77
12: 0x87fb3d77
13: 0x8ffb3d77
14: 0x90fb3d77
15: 0x91fb3d77
16: 0x92fb3d77
17: 0xfe000018 -- 0xFE scaler data starts, 0x18 words to follow
18: 0x00000000
19: 0x00000000
20: 0x00000000
21: 0x00000000
22: 0x00000000
23: 0x00000000
24: 0x00000000
25: 0x00000108
26: 0x00000000
27: 0x00000000
28: 0x00000000
29: 0x00000000
30: 0x00000000
31: 0x00000000
32: 0x00000000
33: 0x00000108
34: 0x00000108
35: 0x00000108
36: 0x00000108
37: 0x00000108
38: 0x00000108
39: 0x00000000
40: 0x00000000
41: 0xce56fa93 -- last word of scaler data is the sysclock counter (125 MHz)
42: 0xff800048 -- timestamp wraparound
43: 0x8f1f36e4 -- tsc hits
44: 0x901f36e4
45: 0x911f36e4
46: 0x921f36e4
47: 0x931f36e4
48: 0x941f36e4
49: 0x871f36e4
50: 0x871f36e7
51: 0x8f1f36e7
52: 0x901f36e9
53: 0x911f36e7
54: 0x921f36e9
55: 0x931f36e7
56: 0x941f36e9
57: 0x904330ac
58: 0x914330ac
59: 0x924330ac
60: 0x934330ac
61: 0x934330ad
62: 0x944330ac
63: 0x944330ad
64: 0x874330ac
65: 0x874330ad
66: 0x8f4330ac
67: 0x8f4330ad
68: 0x904330ad
69: 0x914330ad
70: 0x924330ad
71: 0x8f672a62
72: 0x90672a62
73: 0x91672a62
74: 0x92672a62
75: 0x93672a62
76: 0x94672a62
77: 0x87672a62
78: 0x87672a65
79: 0x8f672a65
80: 0x90672a65
81: 0x91672a65
82: 0x92672a65
83: 0x93672a65
84: 0x94672a65
85: 0xff000049
86: 0x878b2422
87: 0x8f8b2424
88: 0x908b2424
89: 0x918b2424
90: 0x928b2424
91: 0x938b2424
92: 0x938b2425
93: 0x948b2424
94: 0x948b2427
95: 0x878b2427
96: 0x8f8b2427
97: 0x908b2427
98: 0x918b2427
99: 0x928b2427
100: 0xe000eacc -- 0xE is end of fifo data, counter 0xeacc must match the counter in the 0xC word.
ReadDataThread read 344 -- next packet
...
</pre>

= TODO =

* DONE July 2022. add FwRev to the UDP data output
* RJ45 SFP: PROBLEM, D.A. CABLE: GOOD, Fiber SFP: ???. fix "write did not happen" (send udp write command, there is no reply, read returns old data as if write never happened). suspect udp "write" packet is lost?
* PROBLEM GONE Aug 2021. fix reply to wrong socket - udp packets should reply to same socket as they came from, udp data packets should be sent to same socket as requested them, not same socket as last command.
* DONE 2021jul30. add fixes from Chris P. for the auto-negotiation and dhcp (see email from him).
* DONE flash chip connected to FPGA. Aug 2021. implement ethernet flash programmer
* DONE Aug 2021. updated maxv firmware. implement FPGA reboot
* speed up programming the MLU by writing more than 1 bit at a time
* DONE Nov 2021. add 64-bit bitmap of BSC trigger bits
* DONE. add chronobox code
* DONE. add avalon mux for alphag and chronobox packets
* DONE. add chronobox fifo to udp packet sequencer
* check that TxReadyOut is correct and it is safe to send an avalon packet while previous packet is still transmitting.
* DONE. test fiber SFP is working
* complete the UDP flash programmer (parallel flash erase and write)

= End =

//KO

TRG

2022-07-25T16:59:49Z

Olchansk: /* firmware 0x618b790b (Nov 2021) */

= TRG, the trigger control board for the ALPHA-g detector =

= Links =

* xxx
* https://bitbucket.org/expalpha/trg_firmware - firmware sources on bitbucket

= General characteristics =

== Photos ==

== Board schematics ==

* https://bitbucket.org/expalpha/trg_firmware/src/master/3xFMC_VME_Motherboard.pdf

== Available hardware ==

* Altera Stratix IV - main FPGA
* Altera Max V - boot FPGA
* boot flash: PC28F512M29EW - 512 Mbit parallel NOR flash.

= TRG front panel connections =

From top to bottom:

<pre>
|
| minisas-C - links 8-11
| minisas-D - links 12-15
|
| ethernet sfp - use copper sfp only
| minisas - not used, do not connect
| esata - clock in, trigger out
|
| minisas-A - links 0-3
| minisas-B - links 4-7
|
| LEDs
|
</pre>

MiniSAS and SATA flail cable connections:

<pre>
P1 <--> link 3
P2 <--> link 2
P3 <--> link 1
P4 <--> link 0
</pre>

LEDs:

<pre>
--PCB-- (left)
LED[0] - trigger out - ag_trig_out
LED[1] - network packet received - sfp_rx_data_valid
LED[2] - Xilinx FPGA boot ok - FMC1_CFG_DONE
LED[3] - not used
(right)
</pre>

= TRG onboard jumpers and switches =

* rotary switches: select IP address: 00=192.168.1.50, 11=.51, 22=.52, 33=.53, 44=.54, otherwire=.251

= Firmware update procedure =

* use quartus to generate the grifc.pof file (use grifc.cof)
* open quartus programmer
* attach grifc.pof to the 1st CFI_512 flash
* mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
* check that "initiate configuration after programming" is set in tools->options
* say "start"
* should take about 5 minutes
* grifc should reboot into the new firmware

If CFI_512 flash is not visible to the quartus programmer, load correct
code into the MaxV CPLD:

* open quartus programmer,
* say "auto detect"
* change file for the 5M2210 device
* use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
* say "program", it should finish in 10-15 seconds
* say "auto detect"
* CFI_512 flash should be visible now.

= Firmware revisions =

* 0x5bc8f90f - original firmware used for all data
* 0x6147c0f9 - added cbtrg, etc. installed at CERN on 20 Sep 2021.
* 0x618376ae - bigger cbtrg fifo, data rate tested up to 30 Mbytes/sec
* 0x6189c7f3 - fix loss of trigger packets. (missing fifo between alphag block and ethernet mux)
* 0x618b790b - fix loss of timestamps. (cbtrg inputs stretched to 100 ns long). installed at CERN 10 Nov 2021.
* 0x62d32d95 - updated cbtrg, switched to edge-triggered cbtrg inputs, improved BSC multiplicity trigger, improved coinc trigger, added burst pulser. installed at CERN 19 Jul 2022.

= Firmware build =

* use quartus 20.1
* see Makefile in the trg_firmware project

= Jtag remote connection =

* ssh agmini@daq16
* /opt/intelFPGA/16.1/quartus/bin/jtagd --config /home/agmini/.jtagd.conf
* netstat -an | grep 1309 ### note listen address is "0.0.0.0", NOT "127.0.0.1"
<pre>
tcp 0 0 0.0.0.0:1309 0.0.0.0:* LISTEN
</pre>
* opt/intelFPGA/16.1/quartus/bin/jtagconfig ### should work
* ssh olchansk@daq01
* cd git/trg_firmware
* /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
* jtagconfig ### should work
<pre>
daq01:trg_firmware$ jtagconfig
1) DE-SoC on daq16 [2-1.2.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) USB-Blaster on daq16 [2-1.3]
024090DD EP4SGX230(.|ES)
020A40DD 5M(1270ZF324|2210Z)/EPM2210

daq01:trg_firmware$
</pre>

= ALPHA-g trigger functions =

Trigger options:
* software trigger
* pulser trigger
* trigger on GRIF16 ADC NIM and ESATA inputs ("external trigger")
* adc16 grand-or
* adc32 grand-or
* adc16 wire multiplicity
* TPC anode wire per-preamp trigger (aw16 section)
** trigger on coincidences of preamps (removed fw 0x62c77f0b)
** trigger on multiplicity of preamps (removed fw 0x62c77f0b)
** trigger on specific topology of preamps (multiplicity of preamp clusters, etc) via the aw16_mlu trigger
* BSC trigger
** BSC grand_or
** BSC bar multiplicity
* coincidence trigger - select coincidence of external trigger, TPC AW grand-or, TPC AW MLU, BSC grand-or and BSC bar multiplicity triggers

== software trigger ==

to programmatically fire the trigger, one should:
* set the conf_enable_sw_trigger bit in conf_trig_enable, this will permit the software trigger to fire the trigger
* write value 0x4 to register 0x2B, this will cause the software trigger to fire

== pulser trigger ==

To use the pulser trigger, one should program:
* pulser period (in clocks)
* pulser width (in clocks, use value 5, the pulser no longer goes outside of the trigger board, so changing the width does not do anything)
* set the run_pulser bit in conf_trig_enable, this will cause the pulser to run
* set the enable_pulser bit in conf_trig_enable, this will cause the pulser to fire the trigger
* set the output_pulser bit in conf_trig_enable, this will cause the pulser to be output from the alphag firmware block (the pulser no longer goes outside of the trigger board, so changing the bit does not do anything)

== timeout trigger ==

The event builder uses event timestamps to assemble physics events. The timestamps
are usually 32 bit wide and run at 125 MHz (8 ns) or 62.5 MHz (16 ns). If
triggers are generated often (1 per second or more), timestamp wrap around
is easily detected by the event builder. If triggers come infrequently,
timestamp wrap around may occur while there are no triggers, not be seen
by the event builder causing loss of event synchronization.

To avoid this problem in the event builder, a timeout trigger should be generated
if no triggers were generated inside a 10 second interval.

The guaranties that even if all physics triggers temporarily stop for any reason,
the event builder will stay synchronized. (0.1 Hz timeout trigger frequency).

To enable the timeout trigger:
* program timeout trigger timeout in reg 0x43 in units of 8 ns clock
* enable it in bit 23 of [[#conf_trig_enable bits]]

== adc16 multiplicity trigger ==

This trigger is intended for use with the barrel scintillator signals connected to adc16 digitizers. It does not work well with TPC AW signals.

The 16 adc16 trigger bits (16x16=256) are added together to form the hit multiplicity value (adc16_mult, 16 bits, actual range 0 to 256).

Four threshold signals are computed: adc16_mult_1ormore = adc16_mult>=1, 2ormore, 3ormore, 4ormore.

There is a counter for each of these four signals.

Each of these four signals can fire the trigger, see [[#conf_trig_enable bits]].

== TPC anode wire triggers ==

=== aw16 bus ===

TPC Anode Wire trigger is based on the aw16[15:0] (xaw16) bus.

Each bit corresponds to one AW preamp. 16 preamps, 16 bits.

The aw16[15:0] bus can be fed by
* adc16_or16[15:0] - or16 of 100 MHz ADCs, 16 ADC sas links
* adc32_or16[15:0] - or16 of 62.5 MHz ADCs, FMC-ADC32 has 32 channels, so 2 bits per ADC: low 16 channels and high 16 channels, sas links 7..0
* adc32_or16[31:16] - or16 of 62.5 MHz ADCs, ditto, sas links 15..8
as selected by conf_enable_aw_adc16, conf_enable_aw_adc32a, conf_enable_aw_adc32b in [[#conf_control bits]]

<pre>
///////////////////////////////////////////////////////////
// TPC Anode Wire trigger logic (aw16)
///////////////////////////////////////////////////////////

// map adc signals into aw16

wire [15:0] aw16 = ({16{conf_enable_aw_adc16}} & adc16_or16[15:0]) |
({16{conf_enable_aw_adc32a}} & adc32_or16[15:0]) |
({16{conf_enable_aw_adc32b}} & adc32_or16[31:16]);
...
ag_conditioner cond_adc16_or16_0(.clk(clk), .in(aw16[0]), .out(xxaw16[0]));
...
xaw16 <= xxaw16;
</pre>

=== aw16_grand_or ===

TPC AW "grand or" trigger: use aw16_mult_1ormore (before fw 0x62c77f0b)

(256 anode wires, 16 wires per preamp, 16 preamps, 16 aw16 signals)

=== aw16_mlu ===

TPC AW preamp MLU trigger: the MLU (memory lookup
table) implements an arbitrary logical function
to map the 16 aw16 preamp signals into 1 aw16_mlu_trig trigger output.

Description of the aw16 mlu trigger.

In words:

* any aw16 signal starts the aw16_prompt_run gate
* aw16 signals are collected for the duration of conf_mlu_prompt (125MHz/8ns clock)
* this corresponds to time spread of TPC AW signals due to the drift time in the AW drift cell and to the variation in signal transmission time from the ADC to the TRG (digital trigger data link).
* when this prompt time expires, the MLU looks at the accumulated aw16_prompt bit pattern and makes the "yes/no" trigger decision
* after the trigger decision is made, we wait for the TPC to become quiet:
* we wait until all aw16 signals are empty (no timeout)
* we run the aw16_prompt_wait gate, length conf_mlu_wait (8ns clock), if any aw16 signals arrive, we wait for aw16 empty again, rinse, repeat.
* now, after TPC aw16 have been empty for conf_mlu_wait clocks (8ns clock), MLU trigger is ready for the next event.

In logic: (see alphag.v)

* aw16_or <= grand-or of 16 aw16 signals
* "aw16_or" starts the "aw16_prompt_cnt" counter, opens the aw16_prompt_run gate
* during the aw16_prompt_run gate, aw16_prompt collects (latches) the aw16 bits (aw16_prompt <= aw16_prompt | aw16)
* this is the time when we wait for all "prompt" signals from the TPC to arrive into the trigger
* at the end of the aw16_prompt_run gate, the signal aw16_prompt_out is pulsed, latching the output of the MLU into aw16_mlu_trig
* this is the MLU trigger "yes/no" trigger decision.
* after the MLU trigger decision is made, we wait for the arrival and passing of all TPC drift signals
* the aw16_prompt_wait_cnt and aw_prompt_wait gate opens
* if any new aw16 signals arrive (they are TPC drift signals at this time), the aw16_prompt_wait gate is restarted
* if no aw16 signals arrive during the full run of the aw16_prompt_wait gate ("TPC quiet time")
* the aw16_prompt_wait and aw16_prompt gates are cleared and the MLU trigger is ready for the next event.

Good settings are:
* conf_mlu_prompt: 64 (512 ns)
* conf_mlu_wait: 128 (1024 ns)

== BSC trigger ==

=== bsc_adc16 bus ===

The BSC trigger is based on the [15:0]bsc_adc16[7:0] bus: 16 trigger discriminator bits from 8 ADC sas links. (8*16 = 64+64 bars, top and bottom).

The bsc_adc16 bus can be fed from sas links 0..7 or 8..15, controlled by conf_bsc_adc16_a and conf_bsc_adc16_b bits on [[#conf_bsc_control bits]].

bsc_adc16 can be fed only from GRIF-16 100 MHz ADC trigger discriminators.

=== bsc64_top and bsc64_bot buses ===

* firmware 0x5bc8f90f: bsc_adc16 is remapped into 64 bits of top (bsc64_top) and bottom (bsc64_bot):
<pre>
ag_bsc_remap bsc_remap_a(.adc(bsc_adc16[0]), .bsc_bot(bsc64_bot[7:0]), .bsc_top(bsc64_top[7:0]));
ag_bsc_remap bsc_remap_b(.adc(bsc_adc16[1]), .bsc_bot(bsc64_bot[8+7:8+0]), .bsc_top(bsc64_top[8+7:8+0]));
ag_bsc_remap bsc_remap_c(.adc(bsc_adc16[2]), .bsc_bot(bsc64_bot[2*8+7:2*8+0]), .bsc_top(bsc64_top[2*8+7:2*8+0]));
ag_bsc_remap bsc_remap_d(.adc(bsc_adc16[3]), .bsc_bot(bsc64_bot[3*8+7:3*8+0]), .bsc_top(bsc64_top[3*8+7:3*8+0]));

ag_bsc_remap bsc_remap_e(.adc(bsc_adc16[4]), .bsc_bot(bsc64_bot[4*8+7:4*8+0]), .bsc_top(bsc64_top[4*8+7:4*8+0]));
ag_bsc_remap bsc_remap_f(.adc(bsc_adc16[5]), .bsc_bot(bsc64_bot[5*8+7:5*8+0]), .bsc_top(bsc64_top[5*8+7:5*8+0]));
ag_bsc_remap bsc_remap_g(.adc(bsc_adc16[6]), .bsc_bot(bsc64_bot[6*8+7:6*8+0]), .bsc_top(bsc64_top[6*8+7:6*8+0]));
ag_bsc_remap bsc_remap_h(.adc(bsc_adc16[7]), .bsc_bot(bsc64_bot[7*8+7:7*8+0]), .bsc_top(bsc64_top[7*8+7:7*8+0]));

module ag_bsc_remap
(
input wire [15:0] adc,
output wire [7:0] bsc_bot,
output wire [7:0] bsc_top
);

assign bsc_top[3] = adc[0];
assign bsc_top[2] = adc[1];
assign bsc_top[1] = adc[2];
assign bsc_top[0] = adc[3];

assign bsc_top[7] = adc[4];
assign bsc_top[6] = adc[5];
assign bsc_top[5] = adc[6];
assign bsc_top[4] = adc[7];

assign bsc_bot[0] = adc[8];
assign bsc_bot[1] = adc[9];
assign bsc_bot[2] = adc[10];
assign bsc_bot[3] = adc[11];

assign bsc_bot[4] = adc[12];
assign bsc_bot[5] = adc[13];
assign bsc_bot[6] = adc[14];
assign bsc_bot[7] = adc[15];

endmodule
</pre>

=== bsc64 bus ===

the bsc64 bus is the 64 bars used by the trigger, formed from bsc64_top and bsc64_bot:
<pre>
if (conf_bsc64_bot_only) begin
bsc64 <= bsc64_bot;
end else if (conf_bsc64_top_only) begin
bsc64 <= bsc64_top;
end else if (conf_bsc64_bot_top_or) begin
bsc64 <= bsc64_bot | bsc64_top;
end else if (conf_bsc64_bot_top_and) begin
bsc64 <= bsc64_bot & bsc64_top;
end else begin
bsc64 <= 64'b0;
end
</pre>

=== bsc_grand_or_trig ===

bsc_grand_or_trig is the grand-or of 64 bits of the bsc64 bus

to enable triggering on bsc_grand_or_trig, set corresponding bit in [[#conf_trig_enable bits]]

=== old bsc_mult_trig ===

(from fw 0x62c77f0b, old bsc_mult_trig was replaced by new bsc64 multiplicity trigger)

* bsc64_mult is computed as multiplicity of the bsc64 bus (number of 64 bsc64 bits that fired)
* bsc_mult_trig is computed:
<pre>
if (bsc64_mult >= conf_bsc64_mult) begin
bsc_mult_trig <= 1;
end else begin
bsc_mult_trig <= 0;
end
</pre>

to enable the bsc multiplicity trigger, set the multiplicity value conf_bsc64_mult in [[#conf_bsc_control bits]] and enable the corresponding bit in [[#conf_trig_enable bits]].

=== bsc64 multiplicity trigger ===

bsc64 BSC bar multiplicity trigger uses a time window. this time window is started by bsc64_grand_or and runs for conf_bsc64_mult_window clocks (8 nc clock). During this time, hits in bsc64_bus are accumulated (latched) and their multiplicity is computed. If multiplicity condition is satisfied (bigger or equal to conf_bsc64_mult_min), bsc64_mult_trig is fired and the bsc64 bit pattern is saved to the UDP packet. Then trigger waits for the bsc64_bus to be empty. Then trigger waits for conf_bsc64_empty_window clocks, if there is any bsc64 hits, we wait for empty again. So after bsc64 has been empty for conf_bsc64_empty_window clocks, multiplicity trigger is ready for the next event. This scheme cannot implement max multiplicity.

recommended values:
* conf_bsc64_mult_window (8 bits): slightly longer than 3 cycles of SAS link: 3*18 = 54 clocks, good value is 80 (640 ns).
* conf_bsc64_mult_min (8 bits): 2
* conf_bsc64_empty_window (8 bits): 80 (640 ns)

== Coincidence trigger ==

Coincidence trigger provides a combination of TPC, BSC and external scintillator (esata_nim_grand_or) signals:

<pre>
assign coinc_input[0] = aw16_grand_or; // was aw16_mult_1ormore;
assign coinc_input[1] = aw16_mlu_trig;
assign coinc_input[2] = bsc_grand_or_trig;
assign coinc_input[3] = bsc_mult_trig;
assign coinc_input[4] = esata_nim_grand_or;
assign coinc_input[5] = 0;
assign coinc_input[6] = 0;
assign coinc_input[7] = 0;
</pre>

Coincidence trigger "start" mask selects which of the inputs can start the coincidence window.

Coincidence trigger "require" mask selects which inputs must have a hits for the coincidence to be satisfied.

Input hits are collected for the duration of the coincidence window, if all required inputs have hits, coinc_trig is fired.

Example settings:

* coincidence of external scintillator, BSC and TPC AW "grand or" signals: start 0x10, required 0x15
* coincidence of BSC grand-or and TPC AW grand-or signals: start 0x5, required 0x5
* coincidence of BSC multiplicity and TPC AW grand-or triggers: start 0x9, required 0x9

= Control registers =

== Register addresses ==

Note: all registers are 32 bits unless otherwise noted.

Note: RW means read-write register, RO means read-only, ROL means read-only, contents is latched by the "latch_out" bit

{| cellpadding="10" cellspacing="0" border="1"
! Address || Quartus Name || Access || FwRev || Description
|-
| 0x08 || num_sample || RW || GRIF-C || magic 16-bit register to control UDP packet size
|-
| 0x08 || scratch_reg || RW || 0x618b790b || 32-bit scratch register
|-
| 0x1F || compilation_time || RO || || Firmware revision
|-
| 0x20 || conf_trig_width || RW || || Trigger signal width, 16 ns clock
|-
| 0x21 || conf_busy_width || RW || || Busy signal width, 16 ns clock (not used)
|-
| 0x22 || conf_pulser_width || RW || || Pulser signal width, 16 ns clock
|-
| 0x23 || conf_pulser_period || RW || || Pulser signal period, 16 ns clock
|-
| 0x24 || conf_pulser_burst_ctrl || RW || 0x62d1c47e || Generate bursts of pulses: 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses, 16 ns clocks
|-
| 0x25 || conf_trig_enable || RW || || see [[#conf_trig_enable bits]]
|-
| 0x26 || || || not used
|-
| 0x27 || || || not used
|-
| 0x28 || || || not used
|-
| 0x29 || conf_nim_mask || RW || || enable bits for ADC NIM inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2A || conf_esata_mask || RW || || enable bits for ADC eSATA inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2B || reset_out, latch_out, trigger_out || W || || see [[#reg 0x2B bits]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x5bc8f90f || configure AW coincidence trigger, see [[#aw16_coinc]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x62c77f0b || removed
|-
| 0x2D || conf_aw16_coinc_b || RW || 0x5bc8f90f ||
|-
| 0x2E || conf_aw16_coinc_c || RW || 0x5bc8f90f ||
|-
| 0x2F || conf_aw16_coinc_d || RW || 0x5bc8f90f ||
|-
| 0x30 || sas_sd[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect for each link
|-
| 0x31 || pll_625_status || ROL || 0x5b2057f5 (12Jun18_16:32) || 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter
|-
| 0x32 || clk_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the system 125 MHz clock
|-
| 0x33 || clk_625_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625)
|-
| 0x34 || conf_control || RW || 0x5b398983 (01Jul18_19:10) || see [[#conf_control bits]] below
|-
| 0x35 || conf_drift_width || RW || 0x5b398983 (01Jul18_19:10) || width of drift time blank-out in 16 ns clocks
|-
| 0x36 || conf_scaledown || RW || 0x5b398983 (01Jul18_19:10) || trigger scaledown, 0=no scaledown, 1=divide-by-2, 2=divide-by-3, etc
|-
| 0x37 || conf_mlu || RW || 0x5b398983 (01Jul18_19:10) || AW MLU control bits, see [[#conf_mlu bits]]
|-
| 0x38 || conf_trig_delay || RW || 0x5baedfca (28Sep18_19:13) || delay the trigger pulse, 16 ns clock
|-
| 0x39 || esata_clk_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the TRG 125 MHz clock
|-
| 0x3A || esata_clk_esata_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the external clock (eSATA 62.5 MHz clock)
|-
| 0x3B || conf_counter_adc_select || RW || 0x5bb7f6ae (05Oct18_16:41) || select which 16 ADCs are connected to the selected adc counters, 0..15 - connect the adc16 signals, 16..47 connect the adc32 signals
|-
| 0x3C || sysreset_ts || RO || 0x5bb7f6ae (05Oct18_16:41) || 125MHz counter of VME-SYSRESET
|-
| 0x3C || || || 0x618b790b || not used
|-
| 0x3D || GRIF-C csr || RW || GRIF-C || <= csr & ~par_value; // Selective clear
|-
| 0x3E || GRIF-C csr || RW || GRIF-C || <= csr | par_value; // Selective set
|-
| 0x3F || GRIF-C csr || RW || GRIF-C || <= par_value; // write
|-
| 0x3D || || || 0x618b790b || not used
|-
| 0x3E || || || 0x618b790b || not used
|-
| 0x3F || || || 0x618b790b || not used
|-
| 0x40 || conf_bsc_control || RW || 0x5bc13541 (12Oct18_16:58) || Barrel Scintillator trigger control, see [[#conf_bsc_control bits]]
|-
| 0x41 || conf_coinc_control || RW || 0x5bc13541 (12Oct18_16:58) || Coincidence trigger control, see [[#conf_coinc_control bits]]
|-
| 0x42 || reconfig_out || WO || 0x5bc13541 (12Oct18_16:58) || reserved for rebooting the FPGA (does not work)
|-
| 0x43 || conf_trigger_timeout || RW || 0x5bc8f90f (18Oct18_14:20) || Generate timeout trigger if there is no other trigger after given timeout, in 8 ns clocks, must be enabled by bit conf_enable_timeout_trig in [[#conf_trig_enable bits]]
|-
| 0x44 || eth_clk_counter || ROL || 0x618b790b ||
|-
| 0x45 || eth_clk_eth_counter || ROL || 0x618b790b ||
|-
| 0x100 || ts_625 || ROL || || latched timestamp
|-
| 0x101 || counter_trig_out || ROL || || counter of issued triggers
|-
| 0x102 || counter_trig_in || ROL || || counter of triggers
|-
| 0x103 || counter_pulser || ROL || || counter of pulser
|-
| 0x104 || counter_adc16_grand_or || ROL ||
|-
| 0x105 || counter_adc32_grand_or || ROL ||
|-
| 0x106 || counter_adc_grand_or || ROL ||
|-
| 0x107 || counter_esata_nim_grand_or || ROL ||
|-
| 0x108 || counter_adc16_mult_1ormore || ROL ||
|-
| 0x109 || counter_adc16_mult_2ormore || ROL ||
|-
| 0x10A || counter_adc16_mult_3ormore || ROL ||
|-
| 0x10B || counter_adc16_mult_4ormore || ROL ||
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x5bc8f90f || counter of AW coincidence triggers
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x62c77f0b || removed
|-
| 0x10D || counter_aw16_coinc_b || ROL || 0x5bc8f90f ||
|-
| 0x10E || counter_aw16_coinc_c || ROL || 0x5bc8f90f ||
|-
| 0x10F || counter_aw16_coinc_d || ROL || 0x5bc8f90f ||
|-
| 0x110 || counter_drift || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the drift time blank-out
|-
| 0x111 || counter_scaledown || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the scaledown
|-
| 0x112 || counter_aw16_coinc || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW coincidence triggers
|-
| 0x113 || counter_aw16_mlu || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW MLU triggers
|-
| 0x114 || counter_aw16_grand_or || ROL || 0x62c77f0b || counter of AW grand-or triggers
|-
| 0x114 || counter_aw16_mult_1ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 1ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 2ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x62c77f0b || removed
|-
| 0x116 || counter_aw16_mult_3ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 3ormore triggers
|-
| 0x117 || counter_aw16_mult_4ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 4ormore triggers
|-
| 0x118 || counter_bsc_grand_or || ROL || 0x5bc13541 (12Oct18_16:58) || counter of BSC grand-or triggers
|-
| 0x119 || counter_bsc_mult || ROL || 0x5bc13541 (12Oct18_16:58) || counter of old BSC multiplicity triggers
|-
| 0x11A || counter_coinc || ROL || 0x5bc13541 (12Oct18_16:58) || counter of coincidence triggers
|-
| 0x11B || counter_timeout || ROL || 0x618b790b || counter of timeout triggers
|-
| 0x11C || counter_bsc_mult_start || ROL || 0x62c77f0b || counter of BSC multiplicity windows
|-
| 0x11D || counter_bsc_mult_trig || ROL || 0x62c77f0b || counter of BSC multiplicity triggers
|-
| 0x11E || counter_coinc_start || ROL || 0x62d1b152 || counter of coincidence windows
|-
| 0x11F || counter_aw16_mlu_start || ROL || 0x62d1b152 || counter of TPC AW MLU windows
|-
| 0x200..0x207 || conf_adc16_masks || RW || all || adc16 enable bits
|-
| 0x300..0x30F || conf_adc32_masks || RW || all || adc32 enable bits
|-
| 0x400..0x41F || sas_bits[15:0][63:0] || ROL || all || sas data bits for each link
|-
| 0x420..0x42F || sas_sd_counters[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect counter for each link
|-
| 0x430..0x43F || counters_adc16_or16[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 16 counters of adc16 ORes
|-
| 0x440..0x45F || counters_adc32_or16[31:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 32 counters of adc32 ORes
|-
| 0x460..0x46F || counters_adc_selected[15:0] || ROL || 0x5bb7f6ae (05Oct18_16:41) || 16 counters for selected group of adcs, see conf_counter_adc_select
|-
| 0x470..0x4AF || counters_bsc64[63:0] || ROL || 0x5bc13541 (12Oct18_16:58) || 64 counters for the BSC bars
|-
|}

== additional registers ==

<pre>
reg | rw/ro/rol | quartus name | firmware | description
-----------------------------------------------------------------
0x60 | rw | cb_control_out | 0x618b790b | chronobox control
0x61 | rw | cb_status | 0x618b790b | chronobox status
0x62 | rw | cb_invert_a_out | 0x618b790b | chronobox input invert
0x63 | rw | cb_invert_b_out | 0x618b790b |
0x64 | rw | cb_enable_le_a_out | 0x618b790b | timestamp enable leading edge
0x65 | rw | cb_enable_le_b_out | 0x618b790b |
0x66 | rw | cb_enable_te_a_out | 0x618b790b | timestamp enable traiing edge
0x67 | rw | cb_enable_te_b_out | 0x618b790b |
0x6A | ro | cb_input_num | 0x618b790b | chronobox number of inputs
0x6B | rw | cb_sync_mask_a_out | 0x618b790b | chronobox sync signal source
0x6C | rw | cb_sync_mask_b_out | 0x618b790b |
0x6D | rw | cb_sync_reg_out | 0x618b790b | chronobox sync register
0x6E | ro | cb_sync_status | 0x618b790b | chronobox sync status
0x6F | rw | cb_latch_period_out | 0x618b790b | chronobox scalers latch period
0x70 | ro | cb_fifo_status | 0x618b790b | chronobox data fifo status
0x71 | ro | cb_fifo_data | 0x618b790b | read chronobox data fifo (cb_fifo_rdack_out <= 1)
0x72 | rw | cb_udp_period_out | 0x618b790b | period for flushing fifo to UDP
0x73 | rw | cb_udp_threshold_out | 0x618b790b | byte threshold for flushing fifo to UDP
</pre>

== conf_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_clock_select || 0x5b3aa19f (02Jul18_15:05) || select 0=internal 62.5 MHz clock or 1=esata 62.5 MHz clock
|-
| 1 || conf_enable_aw_adc16 || 0x5baedfca (28Sep18_19:13) || select source of TPC AW aw16 bus, see [[#aw16 bus]]
|-
| 2 || conf_enable_aw_adc32a || 0x5baedfca (28Sep18_19:13) ||
|-
| 3 || conf_enable_aw_adc32b || 0x5baedfca (28Sep18_19:13) ||
|-
| 15..4 || || ||
|-
| 23..16 || conf_mlu_prompt || 0x5b3aa19f (02Jul18_15:05) || MLU trigger prompt window, see [[#aw16_mlu]]
|-
| 31..24 || conf_mlu_wait || 0x5b3aa19f (02Jul18_15:05) || MLU trigger wait window, see [[#aw16_mlu]]
|-
|}

== conf_mlu bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 31 || mlu_reset || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 30 || mlu_write || 0x5b3aa19f (02Jul18_15:05) || 1=write data bit into given address
|-
| 16 || mlu_data || 0x5b3aa19f (02Jul18_15:05) || data bit for writing to MLU RAM
|-
| 15..0 || mlu_write_addr || 0x5b3aa19f (02Jul18_15:05) || MLU RAM write address for writing the data bit
|-
|}

== conf_bsc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_bsc_adc_a || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 0..7
|-
| 1 || conf_bsc_adc_b || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 8..15
|-
| 2 || conf_bsc64_bot_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses bottom channels only
|-
| 3 || conf_bsc64_top_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses top channels only
|-
| 4 || conf_bsc64_bot_top_or || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "or" of top and bottom
|-
| 5 || conf_bsc64_bot_top_and || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "and" of top and bottom
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_bsc64_mult_min || 0x5bc13541 (12Oct18_16:58) || minimum bsc64 multiplicity
|-
| 23..16 || conf_bsc64_empty_wondow || 0x62d1c47e || bsc64 empty window length, 8 ns clocks
|-
| 31..24 || conf_bsc64_mult_window || 0x62c77f0b || bsc64 multiplicity window length, 8 ns clocks
|-
|}

== conf_coinc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_coinc_required[0] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mult_1ormore
|-
| 0 || conf_coinc_required[0] || 0x62c77f0b || enable aw16_grand_or
|-
| 1 || conf_coinc_required[1] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mlu_trig
|-
| 2 || conf_coinc_required[2] || 0x5bc13541 (12Oct18_16:58) || enable bsc_grand_or_trig
|-
| 3 || conf_coinc_required[3] || 0x5bc13541 (12Oct18_16:58) || enable bsc_mult_trig
|-
| 3 || conf_coinc_required[3] || 0x62c77f0b || enable bsc64_mult_trig
|-
| 4 || conf_coinc_required[4] || 0x5bc13541 (12Oct18_16:58) || enable esata_nim_grand_or
|-
| 5 || conf_coinc_required[5]
|-
| 6 || conf_coinc_required[6]
|-
| 7 || conf_coinc_required[7]
|-
| 15..8 || conf_coinc_window[7:0] || 0x5bc13541 (12Oct18_16:58) || coincidence window length in units of 125MHz clock (8 ns)
|-
| 23..16 || conf_coinc_start[7:0] || 0x5bc13541 (12Oct18_16:58) || start the coincidence window, same bits as "required"
|-
| 31..24 ||
|-
|}

== conf_trig_enable bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_enable_sw_trigger || || trigger on software trigger (how generated???)
|-
| 1 || conf_enable_pulser || || trigger on pulser
|-
| 2 || - || 0x5b120c9f (01Jun18_20:18) || not used
|-
| 3 || conf_pulser_run || || allow the pulser to run (frequency has to be set beforehand)
|-
| 4 || conf_output_pulser || 0x5bc8f90f || does nothing (top level ag_pulser_out is disconnected)
|-
| 4 || || 0x618b790b || not used
|-
| 5 || conf_enable_esata_nim || || trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand)
|-
| 6 || conf_enable_adc16 || || trigger on adc16_grand_or
|-
| 7 || conf_enable_adc32 || || trigger on adc32_grand_or
|-
| 8 || conf_enable_adc16_1ormore || || trigger on adc16_mult_1ormore "1 or more"
|-
| 9 || conf_enable_adc16_2ormore || || same, "2 or more"
|-
| 10 || conf_enable_adc16_3ormore || || same, "3 or more"
|-
| 11 || conf_enable_adc16_4ormore || || same, "4 or more"
|-
| 12 || - || 0x5b08938c (25May18_15:51) || not used
|-
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
|-
| 14 || - || 0x5bc8f90f || not used
|-
| 15 || conf_enable_adc || 0x5b120c9f (01Jun18_20:18) || trigger on adc_grand_or
|-
| 16 || conf_enable_aw16_coinc_a || 0x5bc8f90f || enable AW coincidence trigger, see [[#aw16_coinc]]
|-
| 16 || - || 0x62c77f0b || aw16_coinc_x removed
|-
| 17 || conf_enable_aw16_coinc_b || 0x5bc8f90f ||
|-
| 18 || conf_enable_aw16_coinc_c || 0x5bc8f90f ||
|-
| 19 || conf_enable_aw16_coinc_d || 0x5bc8f90f ||
|-
| 20 || - || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 20 || conf_enable_aw16_grand_or || 0x618b790b || enable trigger on aw16_grand_or
|-
| 21 || conf_enable_aw16_coinc || 0x5b3aa19f (02Jul18_15:05) || enable trigger on aw16_coinc_trig
|-
| 22 || conf_enable_aw16_mlu || 0x5b3aa19f (02Jul18_15:05) || enable AW MLU trigger
|-
| 23 || conf_enable_timeout_trig || 0x5bc8f90f (18Oct18_14:20) || enable trigger timeout trigger
|-
| 24 || conf_enable_aw16_1ormore || 0x5b3aa19f (02Jul18_15:05) || trigger on aw16_mult_1ormore "1 or more"
|-
| 24 || - || 0x62c77f0b || aw16_mult_xxx removed
|-
| 25 || conf_enable_aw16_2ormore || 0x5b3aa19f (02Jul18_15:05) || same, "2 or more"
|-
| 26 || conf_enable_aw16_3ormore || 0x5b3aa19f (02Jul18_15:05) || same, "3 or more"
|-
| 27 || conf_enable_aw16_4ormore || 0x5b3aa19f (02Jul18_15:05) || same, "4 or more"
|-
| 28 || conf_enable_bsc_grand_or || 0x5bc13541 (12Oct18_16:58) || trigger on BSC grand-or
|-
| 29 || conf_enable_bsc_mult || 0x5bc13541 (12Oct18_16:58) || trigger on BSC multiplicity
|-
| 30 || conf_enable_coinc || 0x5bc13541 (12Oct18_16:58) || trigger on TPC/BSC/ext coincidence trigger
|-
| 31 || - || || not used
|-
|}

== reg 0x2B bits ==

Write to this register will pulse corresponding fpga signals:

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || reset_out || 0x5b120c9f (01Jun18_20:18) || reset counters, etc
|-
| 1 || latch_out || 0x5b120c9f (01Jun18_20:18) || latch counters, sas bits, etc
|-
| 2 || trigger_out || 0x5b120c9f (01Jun18_20:18) || generate a software trigger
|-
|}

= UDP data format =

== general format ==

<pre>
trigger packet:

[0] udp packet counter
[1] 0x8ccccccc
...
[N] 0xEccccccc

different versions of trigger packets should be decoded according to packet length:
40 bytes: initial firmware
76 bytes: firmware 0x618b790b (Nov 2021)
80 bytes: firmware 0x62d1c47e (Jul 2022)

chronobox fifo packet, firmware 0x618b790b (Nov 2021)

[0] udp packet counter
[1] 0xCccccccc
[2] fifo status
[3] fifo data
...
[N] 0xEccccccc

0x0ccccccc is the 28 bit fifo packet counter

chronobox fifo packet, firmware 0x618b790b (Nov 2021)

[0] udp packet counter
[1] 0xDccccccc
[2] 0xDEADBEEF
[3] fifo status
[4] fifo data
...
[N] 0xEccccccc

0x0ccccccc is the 28 bit fifo packet counter
</pre>

== firmware 0x5bc8f90f ==

{| cellpadding="10" cellspacing="0" border="1"
! Offset || Name || Quartus name || FwRev || Description
|-
| 0 || packet counter || none || all || 31-bit UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
|-
| 1 || 0x8 packet header || || all || 28 bits of counter_trig_out
|-
| 2 || trigger timestamp || trig_ts || all || 62.5MHz trigger timestamp
|-
| 3 || accepted triggers || counter_trig_out || all || counter of accepted triggers
|-
| 4 || input triggers || counter_trig_in || all || counter of trigger input
|-
| 5 || pulser triggers || counter_pulser || all || counter of pulser triggers
|-
| 6 || trigger bitmap || udp_trig_bits || 0x5a48448d (30Dec17_17:59) || bitmap of trigger information, see below
|-
| 7 || nim bits || udp_nim_bits_masked || ??? || 32 bits of ADC NIM inputs (2 bits per ADC)
|-
| 8 || esata bits || udp_esata_bits_masked || ??? || 32 bits of ADC ESATA inputs (2 bits per ADC)
|-
| 9 || mlu bits || aw16_prompt || 0x5b398983 (01Jul18_19:10) || 16 bits of MLU input, 1 bit per preamp
|-
| 10 || drift-blank-off counter || udp_drift_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the drift blank-off
|-
| 11 || scaledown counter || udp_scaledown_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the scaledown
|-
| X || || || ||
|-
| 12 || 0xE packet footer || || all || 28 bits of counter_trig_out
|-
|}

== firmware 0x618b790b (Nov 2021) ==

packet size 76 bytes

<pre>
0 udp packet counter
1 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
2 udp_data_out <= udp_trig_ts_625;
3 udp_data_out <= udp_counter_trig_out;
4 udp_data_out <= udp_counter_trig_in;
5 udp_data_out <= udp_counter_pulser;
6 udp_data_out <= udp_trig_bits;
7 udp_data_out <= udp_nim_bits;
8 udp_data_out <= udp_esata_bits;
9 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
10 udp_data_out <= udp_counter_drift;
11 udp_data_out <= udp_counter_scaledown;
12 udp_data_out <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
13 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
14 udp_data_out <= { udp_bsc64_bus[31:0]};
15 udp_data_out <= { udp_bsc64_bus[63:32]};
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
17 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
18 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

== firmware 0x62d1c47e (Jul 2022) ==

packet size 80 bytes

<pre>
0 udp packet counter
1 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
2 udp_data_out <= udp_trig_ts_625;
3 udp_data_out <= udp_counter_trig_out;
4 udp_data_out <= udp_counter_trig_in;
5 udp_data_out <= udp_counter_pulser;
6 udp_data_out <= udp_trig_bits;
7 udp_data_out <= udp_nim_bits;
8 udp_data_out <= udp_esata_bits;
9 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
10 udp_data_out <= udp_counter_drift;
11 udp_data_out <= udp_counter_scaledown;
12 udp_data_out <= { 8'h00, 8'h00, 16'h0000 };
13 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
14 udp_data_out <= { udp_bsc64_bus[31:0]};
15 udp_data_out <= { udp_bsc64_bus[63:32]};
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
17 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
18 udp_data_out <= conf_fw_rev;
19 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

Values of udp_coinc_latch[7:0]:
* aaa

Values of udp_aw16_mult[7:0] and udp_aw16_bus[15:0]:
* aaa

Values of udp_bsc64_mult[7:0] and udp_bsc64_bus[63:0]
* aaa

== trigger bitmap ==

Firmware ??? (one of the very early revisions)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= adc16_coinc_top;
udp_trig_bits[5] <= adc16_coinc_bot;
udp_trig_bits[6] <= adc16_coinc;
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
udp_trig_bits[31:24] <= mult16[7:0];

</pre>

Firmware 0x5b08938c (25May18_15:51)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= 0; // not used
udp_trig_bits[31:24] <= mult16[7:0];
</pre>

Firmware 0x5b217dc4 (13Jun18_13:25)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5b3aa19f (02Jul18_15:05)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= udp_mlu_out;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5bc8f90f (18Oct18_14:20)

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_run_pulser
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = 0; // not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x618b790b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x62c77f0b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = 0; // aw16_coinc_a;
assign trig32_in[17] = 0; // aw16_coinc_b;
assign trig32_in[18] = 0; // aw16_coinc_c;
assign trig32_in[19] = 0; // aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = 0; // aw16_mult_1ormore;
assign trig32_in[25] = 0; // aw16_mult_2ormore;
assign trig32_in[26] = 0; // aw16_mult_3ormore;
assign trig32_in[27] = 0; // aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc64_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

= TRG chronobox inputs =

from trg_firmware/toplevel/grifc.v

<pre>
localparam CB_N = 23;
localparam CB_N1 = CB_N-1;

wire [CB_N1:0] cb_xinputs_async;

assign cb_xinputs_async[0] = ag_trig_out;
assign cb_xinputs_async[1] = ag_trig_scaledown_out;
assign cb_xinputs_async[2] = ag_trig_drift_out;
assign cb_xinputs_async[3] = ag_trig_received_out;

assign cb_xinputs_async[4] = ag_cb_sw_trig;
assign cb_xinputs_async[5] = ag_cb_pulser_trig;
assign cb_xinputs_async[6] = ag_cb_esata_nim_trig;
assign cb_xinputs_async[7] = ag_cb_adc16_grand_or_trig;
assign cb_xinputs_async[8] = ag_cb_adc32_grand_or_trig;

assign cb_xinputs_async[9] = ag_cb_aw16_grand_or_trig;
assign cb_xinputs_async[10] = ag_cb_aw16_mult_1ormore;
assign cb_xinputs_async[11] = ag_cb_aw16_mult_2ormore;
assign cb_xinputs_async[12] = ag_cb_aw16_mult_3ormore;
assign cb_xinputs_async[13] = ag_cb_aw16_mult_4ormore;
assign cb_xinputs_async[14] = ag_cb_aw16_mlu_trig;

assign cb_xinputs_async[15] = ag_cb_bsc64_grand_or_trig;
assign cb_xinputs_async[16] = ag_cb_bsc64_mult_1ormore;
assign cb_xinputs_async[17] = ag_cb_bsc64_mult_2ormore;
assign cb_xinputs_async[18] = ag_cb_bsc64_mult_3ormore;
assign cb_xinputs_async[19] = ag_cb_bsc64_mult_4ormore;
assign cb_xinputs_async[20] = ag_cb_bsc64_mult_trig;

assign cb_xinputs_async[21] = ag_cb_coinc_trig;

assign cb_xinputs_async[22] = ag_cb_timeout_trig;
</pre>

= Example UDP packets =

* trigger data, marker words 0x8

<pre>
ReadDataThread read 76
0: 0x003666ed -- UDP packet counter from UDP transmitter
1: 0x80000bf8 -- 0x8 is trigger data packet, 0xbf8 is the trigger counter from alphag.v
2: 0x2edf8b41 -- trigger data
3: 0x00000bf8
4: 0x00000bf8
5: 0x00000bee
6: 0x00000001
7: 0x00000000
8: 0x00000000
9: 0x00000003
10: 0x00000bf8
11: 0x00000bf8
12: 0x00000000
13: 0x00000000
14: 0x00000000
15: 0x00000000
16: 0x00000000
17: 0x00000000
18: 0xe0000bf8 -- 0xE is end of trigger data, counter 0xbf8 must match the counter in the 0x8 word.
ReadDataThread read 76 -- next packet
0: 0x003666ee -- UDP packet counter from UDP transmitter
...
</pre>

* chronobox fifo data, marker word 0xC, see [[Chronobox#FIFO_data_format]]

<pre>
ReadDataThread read 404
0: 0x003658ed -- UDP packet counter from UDP transmitter
1: 0xc000eacc -- 0xC is FIFO data, fifo packet counter 0xeacc from fifo_to_udp.v
2: 0x00000061 -- FIFO status, low bits the the word counter, so up to 0x61 fifo words are to follow
3: 0x87fb3d72 -- tsc hits
4: 0x8ffb3d74
5: 0x90fb3d74
6: 0x91fb3d74
7: 0x92fb3d74
8: 0x93fb3d74
9: 0x93fb3d75
10: 0x94fb3d74
11: 0x94fb3d77
12: 0x87fb3d77
13: 0x8ffb3d77
14: 0x90fb3d77
15: 0x91fb3d77
16: 0x92fb3d77
17: 0xfe000018 -- 0xFE scaler data starts, 0x18 words to follow
18: 0x00000000
19: 0x00000000
20: 0x00000000
21: 0x00000000
22: 0x00000000
23: 0x00000000
24: 0x00000000
25: 0x00000108
26: 0x00000000
27: 0x00000000
28: 0x00000000
29: 0x00000000
30: 0x00000000
31: 0x00000000
32: 0x00000000
33: 0x00000108
34: 0x00000108
35: 0x00000108
36: 0x00000108
37: 0x00000108
38: 0x00000108
39: 0x00000000
40: 0x00000000
41: 0xce56fa93 -- last word of scaler data is the sysclock counter (125 MHz)
42: 0xff800048 -- timestamp wraparound
43: 0x8f1f36e4 -- tsc hits
44: 0x901f36e4
45: 0x911f36e4
46: 0x921f36e4
47: 0x931f36e4
48: 0x941f36e4
49: 0x871f36e4
50: 0x871f36e7
51: 0x8f1f36e7
52: 0x901f36e9
53: 0x911f36e7
54: 0x921f36e9
55: 0x931f36e7
56: 0x941f36e9
57: 0x904330ac
58: 0x914330ac
59: 0x924330ac
60: 0x934330ac
61: 0x934330ad
62: 0x944330ac
63: 0x944330ad
64: 0x874330ac
65: 0x874330ad
66: 0x8f4330ac
67: 0x8f4330ad
68: 0x904330ad
69: 0x914330ad
70: 0x924330ad
71: 0x8f672a62
72: 0x90672a62
73: 0x91672a62
74: 0x92672a62
75: 0x93672a62
76: 0x94672a62
77: 0x87672a62
78: 0x87672a65
79: 0x8f672a65
80: 0x90672a65
81: 0x91672a65
82: 0x92672a65
83: 0x93672a65
84: 0x94672a65
85: 0xff000049
86: 0x878b2422
87: 0x8f8b2424
88: 0x908b2424
89: 0x918b2424
90: 0x928b2424
91: 0x938b2424
92: 0x938b2425
93: 0x948b2424
94: 0x948b2427
95: 0x878b2427
96: 0x8f8b2427
97: 0x908b2427
98: 0x918b2427
99: 0x928b2427
100: 0xe000eacc -- 0xE is end of fifo data, counter 0xeacc must match the counter in the 0xC word.
ReadDataThread read 344 -- next packet
...
</pre>

= TODO =

* DONE July 2022. add FwRev to the UDP data output
* RJ45 SFP: PROBLEM, D.A. CABLE: GOOD, Fiber SFP: ???. fix "write did not happen" (send udp write command, there is no reply, read returns old data as if write never happened). suspect udp "write" packet is lost?
* PROBLEM GONE Aug 2021. fix reply to wrong socket - udp packets should reply to same socket as they came from, udp data packets should be sent to same socket as requested them, not same socket as last command.
* DONE 2021jul30. add fixes from Chris P. for the auto-negotiation and dhcp (see email from him).
* DONE flash chip connected to FPGA. Aug 2021. implement ethernet flash programmer
* DONE Aug 2021. updated maxv firmware. implement FPGA reboot
* speed up programming the MLU by writing more than 1 bit at a time
* DONE Nov 2021. add 64-bit bitmap of BSC trigger bits
* DONE. add chronobox code
* DONE. add avalon mux for alphag and chronobox packets
* DONE. add chronobox fifo to udp packet sequencer
* check that TxReadyOut is correct and it is safe to send an avalon packet while previous packet is still transmitting.
* DONE. test fiber SFP is working
* complete the UDP flash programmer (parallel flash erase and write)

= End =

//KO

TRG

2022-07-25T16:59:19Z

Olchansk: /* firmware 0x62d1c47e (Jul 2022) */

= TRG, the trigger control board for the ALPHA-g detector =

= Links =

* xxx
* https://bitbucket.org/expalpha/trg_firmware - firmware sources on bitbucket

= General characteristics =

== Photos ==

== Board schematics ==

* https://bitbucket.org/expalpha/trg_firmware/src/master/3xFMC_VME_Motherboard.pdf

== Available hardware ==

* Altera Stratix IV - main FPGA
* Altera Max V - boot FPGA
* boot flash: PC28F512M29EW - 512 Mbit parallel NOR flash.

= TRG front panel connections =

From top to bottom:

<pre>
|
| minisas-C - links 8-11
| minisas-D - links 12-15
|
| ethernet sfp - use copper sfp only
| minisas - not used, do not connect
| esata - clock in, trigger out
|
| minisas-A - links 0-3
| minisas-B - links 4-7
|
| LEDs
|
</pre>

MiniSAS and SATA flail cable connections:

<pre>
P1 <--> link 3
P2 <--> link 2
P3 <--> link 1
P4 <--> link 0
</pre>

LEDs:

<pre>
--PCB-- (left)
LED[0] - trigger out - ag_trig_out
LED[1] - network packet received - sfp_rx_data_valid
LED[2] - Xilinx FPGA boot ok - FMC1_CFG_DONE
LED[3] - not used
(right)
</pre>

= TRG onboard jumpers and switches =

* rotary switches: select IP address: 00=192.168.1.50, 11=.51, 22=.52, 33=.53, 44=.54, otherwire=.251

= Firmware update procedure =

* use quartus to generate the grifc.pof file (use grifc.cof)
* open quartus programmer
* attach grifc.pof to the 1st CFI_512 flash
* mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
* check that "initiate configuration after programming" is set in tools->options
* say "start"
* should take about 5 minutes
* grifc should reboot into the new firmware

If CFI_512 flash is not visible to the quartus programmer, load correct
code into the MaxV CPLD:

* open quartus programmer,
* say "auto detect"
* change file for the 5M2210 device
* use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
* say "program", it should finish in 10-15 seconds
* say "auto detect"
* CFI_512 flash should be visible now.

= Firmware revisions =

* 0x5bc8f90f - original firmware used for all data
* 0x6147c0f9 - added cbtrg, etc. installed at CERN on 20 Sep 2021.
* 0x618376ae - bigger cbtrg fifo, data rate tested up to 30 Mbytes/sec
* 0x6189c7f3 - fix loss of trigger packets. (missing fifo between alphag block and ethernet mux)
* 0x618b790b - fix loss of timestamps. (cbtrg inputs stretched to 100 ns long). installed at CERN 10 Nov 2021.
* 0x62d32d95 - updated cbtrg, switched to edge-triggered cbtrg inputs, improved BSC multiplicity trigger, improved coinc trigger, added burst pulser. installed at CERN 19 Jul 2022.

= Firmware build =

* use quartus 20.1
* see Makefile in the trg_firmware project

= Jtag remote connection =

* ssh agmini@daq16
* /opt/intelFPGA/16.1/quartus/bin/jtagd --config /home/agmini/.jtagd.conf
* netstat -an | grep 1309 ### note listen address is "0.0.0.0", NOT "127.0.0.1"
<pre>
tcp 0 0 0.0.0.0:1309 0.0.0.0:* LISTEN
</pre>
* opt/intelFPGA/16.1/quartus/bin/jtagconfig ### should work
* ssh olchansk@daq01
* cd git/trg_firmware
* /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
* jtagconfig ### should work
<pre>
daq01:trg_firmware$ jtagconfig
1) DE-SoC on daq16 [2-1.2.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) USB-Blaster on daq16 [2-1.3]
024090DD EP4SGX230(.|ES)
020A40DD 5M(1270ZF324|2210Z)/EPM2210

daq01:trg_firmware$
</pre>

= ALPHA-g trigger functions =

Trigger options:
* software trigger
* pulser trigger
* trigger on GRIF16 ADC NIM and ESATA inputs ("external trigger")
* adc16 grand-or
* adc32 grand-or
* adc16 wire multiplicity
* TPC anode wire per-preamp trigger (aw16 section)
** trigger on coincidences of preamps (removed fw 0x62c77f0b)
** trigger on multiplicity of preamps (removed fw 0x62c77f0b)
** trigger on specific topology of preamps (multiplicity of preamp clusters, etc) via the aw16_mlu trigger
* BSC trigger
** BSC grand_or
** BSC bar multiplicity
* coincidence trigger - select coincidence of external trigger, TPC AW grand-or, TPC AW MLU, BSC grand-or and BSC bar multiplicity triggers

== software trigger ==

to programmatically fire the trigger, one should:
* set the conf_enable_sw_trigger bit in conf_trig_enable, this will permit the software trigger to fire the trigger
* write value 0x4 to register 0x2B, this will cause the software trigger to fire

== pulser trigger ==

To use the pulser trigger, one should program:
* pulser period (in clocks)
* pulser width (in clocks, use value 5, the pulser no longer goes outside of the trigger board, so changing the width does not do anything)
* set the run_pulser bit in conf_trig_enable, this will cause the pulser to run
* set the enable_pulser bit in conf_trig_enable, this will cause the pulser to fire the trigger
* set the output_pulser bit in conf_trig_enable, this will cause the pulser to be output from the alphag firmware block (the pulser no longer goes outside of the trigger board, so changing the bit does not do anything)

== timeout trigger ==

The event builder uses event timestamps to assemble physics events. The timestamps
are usually 32 bit wide and run at 125 MHz (8 ns) or 62.5 MHz (16 ns). If
triggers are generated often (1 per second or more), timestamp wrap around
is easily detected by the event builder. If triggers come infrequently,
timestamp wrap around may occur while there are no triggers, not be seen
by the event builder causing loss of event synchronization.

To avoid this problem in the event builder, a timeout trigger should be generated
if no triggers were generated inside a 10 second interval.

The guaranties that even if all physics triggers temporarily stop for any reason,
the event builder will stay synchronized. (0.1 Hz timeout trigger frequency).

To enable the timeout trigger:
* program timeout trigger timeout in reg 0x43 in units of 8 ns clock
* enable it in bit 23 of [[#conf_trig_enable bits]]

== adc16 multiplicity trigger ==

This trigger is intended for use with the barrel scintillator signals connected to adc16 digitizers. It does not work well with TPC AW signals.

The 16 adc16 trigger bits (16x16=256) are added together to form the hit multiplicity value (adc16_mult, 16 bits, actual range 0 to 256).

Four threshold signals are computed: adc16_mult_1ormore = adc16_mult>=1, 2ormore, 3ormore, 4ormore.

There is a counter for each of these four signals.

Each of these four signals can fire the trigger, see [[#conf_trig_enable bits]].

== TPC anode wire triggers ==

=== aw16 bus ===

TPC Anode Wire trigger is based on the aw16[15:0] (xaw16) bus.

Each bit corresponds to one AW preamp. 16 preamps, 16 bits.

The aw16[15:0] bus can be fed by
* adc16_or16[15:0] - or16 of 100 MHz ADCs, 16 ADC sas links
* adc32_or16[15:0] - or16 of 62.5 MHz ADCs, FMC-ADC32 has 32 channels, so 2 bits per ADC: low 16 channels and high 16 channels, sas links 7..0
* adc32_or16[31:16] - or16 of 62.5 MHz ADCs, ditto, sas links 15..8
as selected by conf_enable_aw_adc16, conf_enable_aw_adc32a, conf_enable_aw_adc32b in [[#conf_control bits]]

<pre>
///////////////////////////////////////////////////////////
// TPC Anode Wire trigger logic (aw16)
///////////////////////////////////////////////////////////

// map adc signals into aw16

wire [15:0] aw16 = ({16{conf_enable_aw_adc16}} & adc16_or16[15:0]) |
({16{conf_enable_aw_adc32a}} & adc32_or16[15:0]) |
({16{conf_enable_aw_adc32b}} & adc32_or16[31:16]);
...
ag_conditioner cond_adc16_or16_0(.clk(clk), .in(aw16[0]), .out(xxaw16[0]));
...
xaw16 <= xxaw16;
</pre>

=== aw16_grand_or ===

TPC AW "grand or" trigger: use aw16_mult_1ormore (before fw 0x62c77f0b)

(256 anode wires, 16 wires per preamp, 16 preamps, 16 aw16 signals)

=== aw16_mlu ===

TPC AW preamp MLU trigger: the MLU (memory lookup
table) implements an arbitrary logical function
to map the 16 aw16 preamp signals into 1 aw16_mlu_trig trigger output.

Description of the aw16 mlu trigger.

In words:

* any aw16 signal starts the aw16_prompt_run gate
* aw16 signals are collected for the duration of conf_mlu_prompt (125MHz/8ns clock)
* this corresponds to time spread of TPC AW signals due to the drift time in the AW drift cell and to the variation in signal transmission time from the ADC to the TRG (digital trigger data link).
* when this prompt time expires, the MLU looks at the accumulated aw16_prompt bit pattern and makes the "yes/no" trigger decision
* after the trigger decision is made, we wait for the TPC to become quiet:
* we wait until all aw16 signals are empty (no timeout)
* we run the aw16_prompt_wait gate, length conf_mlu_wait (8ns clock), if any aw16 signals arrive, we wait for aw16 empty again, rinse, repeat.
* now, after TPC aw16 have been empty for conf_mlu_wait clocks (8ns clock), MLU trigger is ready for the next event.

In logic: (see alphag.v)

* aw16_or <= grand-or of 16 aw16 signals
* "aw16_or" starts the "aw16_prompt_cnt" counter, opens the aw16_prompt_run gate
* during the aw16_prompt_run gate, aw16_prompt collects (latches) the aw16 bits (aw16_prompt <= aw16_prompt | aw16)
* this is the time when we wait for all "prompt" signals from the TPC to arrive into the trigger
* at the end of the aw16_prompt_run gate, the signal aw16_prompt_out is pulsed, latching the output of the MLU into aw16_mlu_trig
* this is the MLU trigger "yes/no" trigger decision.
* after the MLU trigger decision is made, we wait for the arrival and passing of all TPC drift signals
* the aw16_prompt_wait_cnt and aw_prompt_wait gate opens
* if any new aw16 signals arrive (they are TPC drift signals at this time), the aw16_prompt_wait gate is restarted
* if no aw16 signals arrive during the full run of the aw16_prompt_wait gate ("TPC quiet time")
* the aw16_prompt_wait and aw16_prompt gates are cleared and the MLU trigger is ready for the next event.

Good settings are:
* conf_mlu_prompt: 64 (512 ns)
* conf_mlu_wait: 128 (1024 ns)

== BSC trigger ==

=== bsc_adc16 bus ===

The BSC trigger is based on the [15:0]bsc_adc16[7:0] bus: 16 trigger discriminator bits from 8 ADC sas links. (8*16 = 64+64 bars, top and bottom).

The bsc_adc16 bus can be fed from sas links 0..7 or 8..15, controlled by conf_bsc_adc16_a and conf_bsc_adc16_b bits on [[#conf_bsc_control bits]].

bsc_adc16 can be fed only from GRIF-16 100 MHz ADC trigger discriminators.

=== bsc64_top and bsc64_bot buses ===

* firmware 0x5bc8f90f: bsc_adc16 is remapped into 64 bits of top (bsc64_top) and bottom (bsc64_bot):
<pre>
ag_bsc_remap bsc_remap_a(.adc(bsc_adc16[0]), .bsc_bot(bsc64_bot[7:0]), .bsc_top(bsc64_top[7:0]));
ag_bsc_remap bsc_remap_b(.adc(bsc_adc16[1]), .bsc_bot(bsc64_bot[8+7:8+0]), .bsc_top(bsc64_top[8+7:8+0]));
ag_bsc_remap bsc_remap_c(.adc(bsc_adc16[2]), .bsc_bot(bsc64_bot[2*8+7:2*8+0]), .bsc_top(bsc64_top[2*8+7:2*8+0]));
ag_bsc_remap bsc_remap_d(.adc(bsc_adc16[3]), .bsc_bot(bsc64_bot[3*8+7:3*8+0]), .bsc_top(bsc64_top[3*8+7:3*8+0]));

ag_bsc_remap bsc_remap_e(.adc(bsc_adc16[4]), .bsc_bot(bsc64_bot[4*8+7:4*8+0]), .bsc_top(bsc64_top[4*8+7:4*8+0]));
ag_bsc_remap bsc_remap_f(.adc(bsc_adc16[5]), .bsc_bot(bsc64_bot[5*8+7:5*8+0]), .bsc_top(bsc64_top[5*8+7:5*8+0]));
ag_bsc_remap bsc_remap_g(.adc(bsc_adc16[6]), .bsc_bot(bsc64_bot[6*8+7:6*8+0]), .bsc_top(bsc64_top[6*8+7:6*8+0]));
ag_bsc_remap bsc_remap_h(.adc(bsc_adc16[7]), .bsc_bot(bsc64_bot[7*8+7:7*8+0]), .bsc_top(bsc64_top[7*8+7:7*8+0]));

module ag_bsc_remap
(
input wire [15:0] adc,
output wire [7:0] bsc_bot,
output wire [7:0] bsc_top
);

assign bsc_top[3] = adc[0];
assign bsc_top[2] = adc[1];
assign bsc_top[1] = adc[2];
assign bsc_top[0] = adc[3];

assign bsc_top[7] = adc[4];
assign bsc_top[6] = adc[5];
assign bsc_top[5] = adc[6];
assign bsc_top[4] = adc[7];

assign bsc_bot[0] = adc[8];
assign bsc_bot[1] = adc[9];
assign bsc_bot[2] = adc[10];
assign bsc_bot[3] = adc[11];

assign bsc_bot[4] = adc[12];
assign bsc_bot[5] = adc[13];
assign bsc_bot[6] = adc[14];
assign bsc_bot[7] = adc[15];

endmodule
</pre>

=== bsc64 bus ===

the bsc64 bus is the 64 bars used by the trigger, formed from bsc64_top and bsc64_bot:
<pre>
if (conf_bsc64_bot_only) begin
bsc64 <= bsc64_bot;
end else if (conf_bsc64_top_only) begin
bsc64 <= bsc64_top;
end else if (conf_bsc64_bot_top_or) begin
bsc64 <= bsc64_bot | bsc64_top;
end else if (conf_bsc64_bot_top_and) begin
bsc64 <= bsc64_bot & bsc64_top;
end else begin
bsc64 <= 64'b0;
end
</pre>

=== bsc_grand_or_trig ===

bsc_grand_or_trig is the grand-or of 64 bits of the bsc64 bus

to enable triggering on bsc_grand_or_trig, set corresponding bit in [[#conf_trig_enable bits]]

=== old bsc_mult_trig ===

(from fw 0x62c77f0b, old bsc_mult_trig was replaced by new bsc64 multiplicity trigger)

* bsc64_mult is computed as multiplicity of the bsc64 bus (number of 64 bsc64 bits that fired)
* bsc_mult_trig is computed:
<pre>
if (bsc64_mult >= conf_bsc64_mult) begin
bsc_mult_trig <= 1;
end else begin
bsc_mult_trig <= 0;
end
</pre>

to enable the bsc multiplicity trigger, set the multiplicity value conf_bsc64_mult in [[#conf_bsc_control bits]] and enable the corresponding bit in [[#conf_trig_enable bits]].

=== bsc64 multiplicity trigger ===

bsc64 BSC bar multiplicity trigger uses a time window. this time window is started by bsc64_grand_or and runs for conf_bsc64_mult_window clocks (8 nc clock). During this time, hits in bsc64_bus are accumulated (latched) and their multiplicity is computed. If multiplicity condition is satisfied (bigger or equal to conf_bsc64_mult_min), bsc64_mult_trig is fired and the bsc64 bit pattern is saved to the UDP packet. Then trigger waits for the bsc64_bus to be empty. Then trigger waits for conf_bsc64_empty_window clocks, if there is any bsc64 hits, we wait for empty again. So after bsc64 has been empty for conf_bsc64_empty_window clocks, multiplicity trigger is ready for the next event. This scheme cannot implement max multiplicity.

recommended values:
* conf_bsc64_mult_window (8 bits): slightly longer than 3 cycles of SAS link: 3*18 = 54 clocks, good value is 80 (640 ns).
* conf_bsc64_mult_min (8 bits): 2
* conf_bsc64_empty_window (8 bits): 80 (640 ns)

== Coincidence trigger ==

Coincidence trigger provides a combination of TPC, BSC and external scintillator (esata_nim_grand_or) signals:

<pre>
assign coinc_input[0] = aw16_grand_or; // was aw16_mult_1ormore;
assign coinc_input[1] = aw16_mlu_trig;
assign coinc_input[2] = bsc_grand_or_trig;
assign coinc_input[3] = bsc_mult_trig;
assign coinc_input[4] = esata_nim_grand_or;
assign coinc_input[5] = 0;
assign coinc_input[6] = 0;
assign coinc_input[7] = 0;
</pre>

Coincidence trigger "start" mask selects which of the inputs can start the coincidence window.

Coincidence trigger "require" mask selects which inputs must have a hits for the coincidence to be satisfied.

Input hits are collected for the duration of the coincidence window, if all required inputs have hits, coinc_trig is fired.

Example settings:

* coincidence of external scintillator, BSC and TPC AW "grand or" signals: start 0x10, required 0x15
* coincidence of BSC grand-or and TPC AW grand-or signals: start 0x5, required 0x5
* coincidence of BSC multiplicity and TPC AW grand-or triggers: start 0x9, required 0x9

= Control registers =

== Register addresses ==

Note: all registers are 32 bits unless otherwise noted.

Note: RW means read-write register, RO means read-only, ROL means read-only, contents is latched by the "latch_out" bit

{| cellpadding="10" cellspacing="0" border="1"
! Address || Quartus Name || Access || FwRev || Description
|-
| 0x08 || num_sample || RW || GRIF-C || magic 16-bit register to control UDP packet size
|-
| 0x08 || scratch_reg || RW || 0x618b790b || 32-bit scratch register
|-
| 0x1F || compilation_time || RO || || Firmware revision
|-
| 0x20 || conf_trig_width || RW || || Trigger signal width, 16 ns clock
|-
| 0x21 || conf_busy_width || RW || || Busy signal width, 16 ns clock (not used)
|-
| 0x22 || conf_pulser_width || RW || || Pulser signal width, 16 ns clock
|-
| 0x23 || conf_pulser_period || RW || || Pulser signal period, 16 ns clock
|-
| 0x24 || conf_pulser_burst_ctrl || RW || 0x62d1c47e || Generate bursts of pulses: 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses, 16 ns clocks
|-
| 0x25 || conf_trig_enable || RW || || see [[#conf_trig_enable bits]]
|-
| 0x26 || || || not used
|-
| 0x27 || || || not used
|-
| 0x28 || || || not used
|-
| 0x29 || conf_nim_mask || RW || || enable bits for ADC NIM inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2A || conf_esata_mask || RW || || enable bits for ADC eSATA inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2B || reset_out, latch_out, trigger_out || W || || see [[#reg 0x2B bits]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x5bc8f90f || configure AW coincidence trigger, see [[#aw16_coinc]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x62c77f0b || removed
|-
| 0x2D || conf_aw16_coinc_b || RW || 0x5bc8f90f ||
|-
| 0x2E || conf_aw16_coinc_c || RW || 0x5bc8f90f ||
|-
| 0x2F || conf_aw16_coinc_d || RW || 0x5bc8f90f ||
|-
| 0x30 || sas_sd[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect for each link
|-
| 0x31 || pll_625_status || ROL || 0x5b2057f5 (12Jun18_16:32) || 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter
|-
| 0x32 || clk_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the system 125 MHz clock
|-
| 0x33 || clk_625_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625)
|-
| 0x34 || conf_control || RW || 0x5b398983 (01Jul18_19:10) || see [[#conf_control bits]] below
|-
| 0x35 || conf_drift_width || RW || 0x5b398983 (01Jul18_19:10) || width of drift time blank-out in 16 ns clocks
|-
| 0x36 || conf_scaledown || RW || 0x5b398983 (01Jul18_19:10) || trigger scaledown, 0=no scaledown, 1=divide-by-2, 2=divide-by-3, etc
|-
| 0x37 || conf_mlu || RW || 0x5b398983 (01Jul18_19:10) || AW MLU control bits, see [[#conf_mlu bits]]
|-
| 0x38 || conf_trig_delay || RW || 0x5baedfca (28Sep18_19:13) || delay the trigger pulse, 16 ns clock
|-
| 0x39 || esata_clk_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the TRG 125 MHz clock
|-
| 0x3A || esata_clk_esata_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the external clock (eSATA 62.5 MHz clock)
|-
| 0x3B || conf_counter_adc_select || RW || 0x5bb7f6ae (05Oct18_16:41) || select which 16 ADCs are connected to the selected adc counters, 0..15 - connect the adc16 signals, 16..47 connect the adc32 signals
|-
| 0x3C || sysreset_ts || RO || 0x5bb7f6ae (05Oct18_16:41) || 125MHz counter of VME-SYSRESET
|-
| 0x3C || || || 0x618b790b || not used
|-
| 0x3D || GRIF-C csr || RW || GRIF-C || <= csr & ~par_value; // Selective clear
|-
| 0x3E || GRIF-C csr || RW || GRIF-C || <= csr | par_value; // Selective set
|-
| 0x3F || GRIF-C csr || RW || GRIF-C || <= par_value; // write
|-
| 0x3D || || || 0x618b790b || not used
|-
| 0x3E || || || 0x618b790b || not used
|-
| 0x3F || || || 0x618b790b || not used
|-
| 0x40 || conf_bsc_control || RW || 0x5bc13541 (12Oct18_16:58) || Barrel Scintillator trigger control, see [[#conf_bsc_control bits]]
|-
| 0x41 || conf_coinc_control || RW || 0x5bc13541 (12Oct18_16:58) || Coincidence trigger control, see [[#conf_coinc_control bits]]
|-
| 0x42 || reconfig_out || WO || 0x5bc13541 (12Oct18_16:58) || reserved for rebooting the FPGA (does not work)
|-
| 0x43 || conf_trigger_timeout || RW || 0x5bc8f90f (18Oct18_14:20) || Generate timeout trigger if there is no other trigger after given timeout, in 8 ns clocks, must be enabled by bit conf_enable_timeout_trig in [[#conf_trig_enable bits]]
|-
| 0x44 || eth_clk_counter || ROL || 0x618b790b ||
|-
| 0x45 || eth_clk_eth_counter || ROL || 0x618b790b ||
|-
| 0x100 || ts_625 || ROL || || latched timestamp
|-
| 0x101 || counter_trig_out || ROL || || counter of issued triggers
|-
| 0x102 || counter_trig_in || ROL || || counter of triggers
|-
| 0x103 || counter_pulser || ROL || || counter of pulser
|-
| 0x104 || counter_adc16_grand_or || ROL ||
|-
| 0x105 || counter_adc32_grand_or || ROL ||
|-
| 0x106 || counter_adc_grand_or || ROL ||
|-
| 0x107 || counter_esata_nim_grand_or || ROL ||
|-
| 0x108 || counter_adc16_mult_1ormore || ROL ||
|-
| 0x109 || counter_adc16_mult_2ormore || ROL ||
|-
| 0x10A || counter_adc16_mult_3ormore || ROL ||
|-
| 0x10B || counter_adc16_mult_4ormore || ROL ||
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x5bc8f90f || counter of AW coincidence triggers
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x62c77f0b || removed
|-
| 0x10D || counter_aw16_coinc_b || ROL || 0x5bc8f90f ||
|-
| 0x10E || counter_aw16_coinc_c || ROL || 0x5bc8f90f ||
|-
| 0x10F || counter_aw16_coinc_d || ROL || 0x5bc8f90f ||
|-
| 0x110 || counter_drift || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the drift time blank-out
|-
| 0x111 || counter_scaledown || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the scaledown
|-
| 0x112 || counter_aw16_coinc || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW coincidence triggers
|-
| 0x113 || counter_aw16_mlu || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW MLU triggers
|-
| 0x114 || counter_aw16_grand_or || ROL || 0x62c77f0b || counter of AW grand-or triggers
|-
| 0x114 || counter_aw16_mult_1ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 1ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 2ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x62c77f0b || removed
|-
| 0x116 || counter_aw16_mult_3ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 3ormore triggers
|-
| 0x117 || counter_aw16_mult_4ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 4ormore triggers
|-
| 0x118 || counter_bsc_grand_or || ROL || 0x5bc13541 (12Oct18_16:58) || counter of BSC grand-or triggers
|-
| 0x119 || counter_bsc_mult || ROL || 0x5bc13541 (12Oct18_16:58) || counter of old BSC multiplicity triggers
|-
| 0x11A || counter_coinc || ROL || 0x5bc13541 (12Oct18_16:58) || counter of coincidence triggers
|-
| 0x11B || counter_timeout || ROL || 0x618b790b || counter of timeout triggers
|-
| 0x11C || counter_bsc_mult_start || ROL || 0x62c77f0b || counter of BSC multiplicity windows
|-
| 0x11D || counter_bsc_mult_trig || ROL || 0x62c77f0b || counter of BSC multiplicity triggers
|-
| 0x11E || counter_coinc_start || ROL || 0x62d1b152 || counter of coincidence windows
|-
| 0x11F || counter_aw16_mlu_start || ROL || 0x62d1b152 || counter of TPC AW MLU windows
|-
| 0x200..0x207 || conf_adc16_masks || RW || all || adc16 enable bits
|-
| 0x300..0x30F || conf_adc32_masks || RW || all || adc32 enable bits
|-
| 0x400..0x41F || sas_bits[15:0][63:0] || ROL || all || sas data bits for each link
|-
| 0x420..0x42F || sas_sd_counters[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect counter for each link
|-
| 0x430..0x43F || counters_adc16_or16[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 16 counters of adc16 ORes
|-
| 0x440..0x45F || counters_adc32_or16[31:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 32 counters of adc32 ORes
|-
| 0x460..0x46F || counters_adc_selected[15:0] || ROL || 0x5bb7f6ae (05Oct18_16:41) || 16 counters for selected group of adcs, see conf_counter_adc_select
|-
| 0x470..0x4AF || counters_bsc64[63:0] || ROL || 0x5bc13541 (12Oct18_16:58) || 64 counters for the BSC bars
|-
|}

== additional registers ==

<pre>
reg | rw/ro/rol | quartus name | firmware | description
-----------------------------------------------------------------
0x60 | rw | cb_control_out | 0x618b790b | chronobox control
0x61 | rw | cb_status | 0x618b790b | chronobox status
0x62 | rw | cb_invert_a_out | 0x618b790b | chronobox input invert
0x63 | rw | cb_invert_b_out | 0x618b790b |
0x64 | rw | cb_enable_le_a_out | 0x618b790b | timestamp enable leading edge
0x65 | rw | cb_enable_le_b_out | 0x618b790b |
0x66 | rw | cb_enable_te_a_out | 0x618b790b | timestamp enable traiing edge
0x67 | rw | cb_enable_te_b_out | 0x618b790b |
0x6A | ro | cb_input_num | 0x618b790b | chronobox number of inputs
0x6B | rw | cb_sync_mask_a_out | 0x618b790b | chronobox sync signal source
0x6C | rw | cb_sync_mask_b_out | 0x618b790b |
0x6D | rw | cb_sync_reg_out | 0x618b790b | chronobox sync register
0x6E | ro | cb_sync_status | 0x618b790b | chronobox sync status
0x6F | rw | cb_latch_period_out | 0x618b790b | chronobox scalers latch period
0x70 | ro | cb_fifo_status | 0x618b790b | chronobox data fifo status
0x71 | ro | cb_fifo_data | 0x618b790b | read chronobox data fifo (cb_fifo_rdack_out <= 1)
0x72 | rw | cb_udp_period_out | 0x618b790b | period for flushing fifo to UDP
0x73 | rw | cb_udp_threshold_out | 0x618b790b | byte threshold for flushing fifo to UDP
</pre>

== conf_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_clock_select || 0x5b3aa19f (02Jul18_15:05) || select 0=internal 62.5 MHz clock or 1=esata 62.5 MHz clock
|-
| 1 || conf_enable_aw_adc16 || 0x5baedfca (28Sep18_19:13) || select source of TPC AW aw16 bus, see [[#aw16 bus]]
|-
| 2 || conf_enable_aw_adc32a || 0x5baedfca (28Sep18_19:13) ||
|-
| 3 || conf_enable_aw_adc32b || 0x5baedfca (28Sep18_19:13) ||
|-
| 15..4 || || ||
|-
| 23..16 || conf_mlu_prompt || 0x5b3aa19f (02Jul18_15:05) || MLU trigger prompt window, see [[#aw16_mlu]]
|-
| 31..24 || conf_mlu_wait || 0x5b3aa19f (02Jul18_15:05) || MLU trigger wait window, see [[#aw16_mlu]]
|-
|}

== conf_mlu bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 31 || mlu_reset || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 30 || mlu_write || 0x5b3aa19f (02Jul18_15:05) || 1=write data bit into given address
|-
| 16 || mlu_data || 0x5b3aa19f (02Jul18_15:05) || data bit for writing to MLU RAM
|-
| 15..0 || mlu_write_addr || 0x5b3aa19f (02Jul18_15:05) || MLU RAM write address for writing the data bit
|-
|}

== conf_bsc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_bsc_adc_a || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 0..7
|-
| 1 || conf_bsc_adc_b || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 8..15
|-
| 2 || conf_bsc64_bot_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses bottom channels only
|-
| 3 || conf_bsc64_top_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses top channels only
|-
| 4 || conf_bsc64_bot_top_or || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "or" of top and bottom
|-
| 5 || conf_bsc64_bot_top_and || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "and" of top and bottom
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_bsc64_mult_min || 0x5bc13541 (12Oct18_16:58) || minimum bsc64 multiplicity
|-
| 23..16 || conf_bsc64_empty_wondow || 0x62d1c47e || bsc64 empty window length, 8 ns clocks
|-
| 31..24 || conf_bsc64_mult_window || 0x62c77f0b || bsc64 multiplicity window length, 8 ns clocks
|-
|}

== conf_coinc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_coinc_required[0] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mult_1ormore
|-
| 0 || conf_coinc_required[0] || 0x62c77f0b || enable aw16_grand_or
|-
| 1 || conf_coinc_required[1] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mlu_trig
|-
| 2 || conf_coinc_required[2] || 0x5bc13541 (12Oct18_16:58) || enable bsc_grand_or_trig
|-
| 3 || conf_coinc_required[3] || 0x5bc13541 (12Oct18_16:58) || enable bsc_mult_trig
|-
| 3 || conf_coinc_required[3] || 0x62c77f0b || enable bsc64_mult_trig
|-
| 4 || conf_coinc_required[4] || 0x5bc13541 (12Oct18_16:58) || enable esata_nim_grand_or
|-
| 5 || conf_coinc_required[5]
|-
| 6 || conf_coinc_required[6]
|-
| 7 || conf_coinc_required[7]
|-
| 15..8 || conf_coinc_window[7:0] || 0x5bc13541 (12Oct18_16:58) || coincidence window length in units of 125MHz clock (8 ns)
|-
| 23..16 || conf_coinc_start[7:0] || 0x5bc13541 (12Oct18_16:58) || start the coincidence window, same bits as "required"
|-
| 31..24 ||
|-
|}

== conf_trig_enable bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_enable_sw_trigger || || trigger on software trigger (how generated???)
|-
| 1 || conf_enable_pulser || || trigger on pulser
|-
| 2 || - || 0x5b120c9f (01Jun18_20:18) || not used
|-
| 3 || conf_pulser_run || || allow the pulser to run (frequency has to be set beforehand)
|-
| 4 || conf_output_pulser || 0x5bc8f90f || does nothing (top level ag_pulser_out is disconnected)
|-
| 4 || || 0x618b790b || not used
|-
| 5 || conf_enable_esata_nim || || trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand)
|-
| 6 || conf_enable_adc16 || || trigger on adc16_grand_or
|-
| 7 || conf_enable_adc32 || || trigger on adc32_grand_or
|-
| 8 || conf_enable_adc16_1ormore || || trigger on adc16_mult_1ormore "1 or more"
|-
| 9 || conf_enable_adc16_2ormore || || same, "2 or more"
|-
| 10 || conf_enable_adc16_3ormore || || same, "3 or more"
|-
| 11 || conf_enable_adc16_4ormore || || same, "4 or more"
|-
| 12 || - || 0x5b08938c (25May18_15:51) || not used
|-
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
|-
| 14 || - || 0x5bc8f90f || not used
|-
| 15 || conf_enable_adc || 0x5b120c9f (01Jun18_20:18) || trigger on adc_grand_or
|-
| 16 || conf_enable_aw16_coinc_a || 0x5bc8f90f || enable AW coincidence trigger, see [[#aw16_coinc]]
|-
| 16 || - || 0x62c77f0b || aw16_coinc_x removed
|-
| 17 || conf_enable_aw16_coinc_b || 0x5bc8f90f ||
|-
| 18 || conf_enable_aw16_coinc_c || 0x5bc8f90f ||
|-
| 19 || conf_enable_aw16_coinc_d || 0x5bc8f90f ||
|-
| 20 || - || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 20 || conf_enable_aw16_grand_or || 0x618b790b || enable trigger on aw16_grand_or
|-
| 21 || conf_enable_aw16_coinc || 0x5b3aa19f (02Jul18_15:05) || enable trigger on aw16_coinc_trig
|-
| 22 || conf_enable_aw16_mlu || 0x5b3aa19f (02Jul18_15:05) || enable AW MLU trigger
|-
| 23 || conf_enable_timeout_trig || 0x5bc8f90f (18Oct18_14:20) || enable trigger timeout trigger
|-
| 24 || conf_enable_aw16_1ormore || 0x5b3aa19f (02Jul18_15:05) || trigger on aw16_mult_1ormore "1 or more"
|-
| 24 || - || 0x62c77f0b || aw16_mult_xxx removed
|-
| 25 || conf_enable_aw16_2ormore || 0x5b3aa19f (02Jul18_15:05) || same, "2 or more"
|-
| 26 || conf_enable_aw16_3ormore || 0x5b3aa19f (02Jul18_15:05) || same, "3 or more"
|-
| 27 || conf_enable_aw16_4ormore || 0x5b3aa19f (02Jul18_15:05) || same, "4 or more"
|-
| 28 || conf_enable_bsc_grand_or || 0x5bc13541 (12Oct18_16:58) || trigger on BSC grand-or
|-
| 29 || conf_enable_bsc_mult || 0x5bc13541 (12Oct18_16:58) || trigger on BSC multiplicity
|-
| 30 || conf_enable_coinc || 0x5bc13541 (12Oct18_16:58) || trigger on TPC/BSC/ext coincidence trigger
|-
| 31 || - || || not used
|-
|}

== reg 0x2B bits ==

Write to this register will pulse corresponding fpga signals:

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || reset_out || 0x5b120c9f (01Jun18_20:18) || reset counters, etc
|-
| 1 || latch_out || 0x5b120c9f (01Jun18_20:18) || latch counters, sas bits, etc
|-
| 2 || trigger_out || 0x5b120c9f (01Jun18_20:18) || generate a software trigger
|-
|}

= UDP data format =

== general format ==

<pre>
trigger packet:

[0] udp packet counter
[1] 0x8ccccccc
...
[N] 0xEccccccc

different versions of trigger packets should be decoded according to packet length:
40 bytes: initial firmware
76 bytes: firmware 0x618b790b (Nov 2021)
80 bytes: firmware 0x62d1c47e (Jul 2022)

chronobox fifo packet, firmware 0x618b790b (Nov 2021)

[0] udp packet counter
[1] 0xCccccccc
[2] fifo status
[3] fifo data
...
[N] 0xEccccccc

0x0ccccccc is the 28 bit fifo packet counter

chronobox fifo packet, firmware 0x618b790b (Nov 2021)

[0] udp packet counter
[1] 0xDccccccc
[2] 0xDEADBEEF
[3] fifo status
[4] fifo data
...
[N] 0xEccccccc

0x0ccccccc is the 28 bit fifo packet counter
</pre>

== firmware 0x5bc8f90f ==

{| cellpadding="10" cellspacing="0" border="1"
! Offset || Name || Quartus name || FwRev || Description
|-
| 0 || packet counter || none || all || 31-bit UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
|-
| 1 || 0x8 packet header || || all || 28 bits of counter_trig_out
|-
| 2 || trigger timestamp || trig_ts || all || 62.5MHz trigger timestamp
|-
| 3 || accepted triggers || counter_trig_out || all || counter of accepted triggers
|-
| 4 || input triggers || counter_trig_in || all || counter of trigger input
|-
| 5 || pulser triggers || counter_pulser || all || counter of pulser triggers
|-
| 6 || trigger bitmap || udp_trig_bits || 0x5a48448d (30Dec17_17:59) || bitmap of trigger information, see below
|-
| 7 || nim bits || udp_nim_bits_masked || ??? || 32 bits of ADC NIM inputs (2 bits per ADC)
|-
| 8 || esata bits || udp_esata_bits_masked || ??? || 32 bits of ADC ESATA inputs (2 bits per ADC)
|-
| 9 || mlu bits || aw16_prompt || 0x5b398983 (01Jul18_19:10) || 16 bits of MLU input, 1 bit per preamp
|-
| 10 || drift-blank-off counter || udp_drift_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the drift blank-off
|-
| 11 || scaledown counter || udp_scaledown_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the scaledown
|-
| X || || || ||
|-
| 12 || 0xE packet footer || || all || 28 bits of counter_trig_out
|-
|}

== firmware 0x618b790b (Nov 2021) ==

packet size 80 bytes

<pre>
0 udp packet counter
1 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
2 udp_data_out <= udp_trig_ts_625;
3 udp_data_out <= udp_counter_trig_out;
4 udp_data_out <= udp_counter_trig_in;
5 udp_data_out <= udp_counter_pulser;
6 udp_data_out <= udp_trig_bits;
7 udp_data_out <= udp_nim_bits;
8 udp_data_out <= udp_esata_bits;
9 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
10 udp_data_out <= udp_counter_drift;
11 udp_data_out <= udp_counter_scaledown;
12 udp_data_out <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
13 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
14 udp_data_out <= { udp_bsc64_bus[31:0]};
15 udp_data_out <= { udp_bsc64_bus[63:32]};
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
17 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
19 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

== firmware 0x62d1c47e (Jul 2022) ==

packet size 80 bytes

<pre>
0 udp packet counter
1 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
2 udp_data_out <= udp_trig_ts_625;
3 udp_data_out <= udp_counter_trig_out;
4 udp_data_out <= udp_counter_trig_in;
5 udp_data_out <= udp_counter_pulser;
6 udp_data_out <= udp_trig_bits;
7 udp_data_out <= udp_nim_bits;
8 udp_data_out <= udp_esata_bits;
9 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
10 udp_data_out <= udp_counter_drift;
11 udp_data_out <= udp_counter_scaledown;
12 udp_data_out <= { 8'h00, 8'h00, 16'h0000 };
13 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
14 udp_data_out <= { udp_bsc64_bus[31:0]};
15 udp_data_out <= { udp_bsc64_bus[63:32]};
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
17 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
18 udp_data_out <= conf_fw_rev;
19 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

Values of udp_coinc_latch[7:0]:
* aaa

Values of udp_aw16_mult[7:0] and udp_aw16_bus[15:0]:
* aaa

Values of udp_bsc64_mult[7:0] and udp_bsc64_bus[63:0]
* aaa

== trigger bitmap ==

Firmware ??? (one of the very early revisions)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= adc16_coinc_top;
udp_trig_bits[5] <= adc16_coinc_bot;
udp_trig_bits[6] <= adc16_coinc;
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
udp_trig_bits[31:24] <= mult16[7:0];

</pre>

Firmware 0x5b08938c (25May18_15:51)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= 0; // not used
udp_trig_bits[31:24] <= mult16[7:0];
</pre>

Firmware 0x5b217dc4 (13Jun18_13:25)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5b3aa19f (02Jul18_15:05)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= udp_mlu_out;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5bc8f90f (18Oct18_14:20)

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_run_pulser
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = 0; // not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x618b790b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x62c77f0b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = 0; // aw16_coinc_a;
assign trig32_in[17] = 0; // aw16_coinc_b;
assign trig32_in[18] = 0; // aw16_coinc_c;
assign trig32_in[19] = 0; // aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = 0; // aw16_mult_1ormore;
assign trig32_in[25] = 0; // aw16_mult_2ormore;
assign trig32_in[26] = 0; // aw16_mult_3ormore;
assign trig32_in[27] = 0; // aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc64_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

= TRG chronobox inputs =

from trg_firmware/toplevel/grifc.v

<pre>
localparam CB_N = 23;
localparam CB_N1 = CB_N-1;

wire [CB_N1:0] cb_xinputs_async;

assign cb_xinputs_async[0] = ag_trig_out;
assign cb_xinputs_async[1] = ag_trig_scaledown_out;
assign cb_xinputs_async[2] = ag_trig_drift_out;
assign cb_xinputs_async[3] = ag_trig_received_out;

assign cb_xinputs_async[4] = ag_cb_sw_trig;
assign cb_xinputs_async[5] = ag_cb_pulser_trig;
assign cb_xinputs_async[6] = ag_cb_esata_nim_trig;
assign cb_xinputs_async[7] = ag_cb_adc16_grand_or_trig;
assign cb_xinputs_async[8] = ag_cb_adc32_grand_or_trig;

assign cb_xinputs_async[9] = ag_cb_aw16_grand_or_trig;
assign cb_xinputs_async[10] = ag_cb_aw16_mult_1ormore;
assign cb_xinputs_async[11] = ag_cb_aw16_mult_2ormore;
assign cb_xinputs_async[12] = ag_cb_aw16_mult_3ormore;
assign cb_xinputs_async[13] = ag_cb_aw16_mult_4ormore;
assign cb_xinputs_async[14] = ag_cb_aw16_mlu_trig;

assign cb_xinputs_async[15] = ag_cb_bsc64_grand_or_trig;
assign cb_xinputs_async[16] = ag_cb_bsc64_mult_1ormore;
assign cb_xinputs_async[17] = ag_cb_bsc64_mult_2ormore;
assign cb_xinputs_async[18] = ag_cb_bsc64_mult_3ormore;
assign cb_xinputs_async[19] = ag_cb_bsc64_mult_4ormore;
assign cb_xinputs_async[20] = ag_cb_bsc64_mult_trig;

assign cb_xinputs_async[21] = ag_cb_coinc_trig;

assign cb_xinputs_async[22] = ag_cb_timeout_trig;
</pre>

= Example UDP packets =

* trigger data, marker words 0x8

<pre>
ReadDataThread read 76
0: 0x003666ed -- UDP packet counter from UDP transmitter
1: 0x80000bf8 -- 0x8 is trigger data packet, 0xbf8 is the trigger counter from alphag.v
2: 0x2edf8b41 -- trigger data
3: 0x00000bf8
4: 0x00000bf8
5: 0x00000bee
6: 0x00000001
7: 0x00000000
8: 0x00000000
9: 0x00000003
10: 0x00000bf8
11: 0x00000bf8
12: 0x00000000
13: 0x00000000
14: 0x00000000
15: 0x00000000
16: 0x00000000
17: 0x00000000
18: 0xe0000bf8 -- 0xE is end of trigger data, counter 0xbf8 must match the counter in the 0x8 word.
ReadDataThread read 76 -- next packet
0: 0x003666ee -- UDP packet counter from UDP transmitter
...
</pre>

* chronobox fifo data, marker word 0xC, see [[Chronobox#FIFO_data_format]]

<pre>
ReadDataThread read 404
0: 0x003658ed -- UDP packet counter from UDP transmitter
1: 0xc000eacc -- 0xC is FIFO data, fifo packet counter 0xeacc from fifo_to_udp.v
2: 0x00000061 -- FIFO status, low bits the the word counter, so up to 0x61 fifo words are to follow
3: 0x87fb3d72 -- tsc hits
4: 0x8ffb3d74
5: 0x90fb3d74
6: 0x91fb3d74
7: 0x92fb3d74
8: 0x93fb3d74
9: 0x93fb3d75
10: 0x94fb3d74
11: 0x94fb3d77
12: 0x87fb3d77
13: 0x8ffb3d77
14: 0x90fb3d77
15: 0x91fb3d77
16: 0x92fb3d77
17: 0xfe000018 -- 0xFE scaler data starts, 0x18 words to follow
18: 0x00000000
19: 0x00000000
20: 0x00000000
21: 0x00000000
22: 0x00000000
23: 0x00000000
24: 0x00000000
25: 0x00000108
26: 0x00000000
27: 0x00000000
28: 0x00000000
29: 0x00000000
30: 0x00000000
31: 0x00000000
32: 0x00000000
33: 0x00000108
34: 0x00000108
35: 0x00000108
36: 0x00000108
37: 0x00000108
38: 0x00000108
39: 0x00000000
40: 0x00000000
41: 0xce56fa93 -- last word of scaler data is the sysclock counter (125 MHz)
42: 0xff800048 -- timestamp wraparound
43: 0x8f1f36e4 -- tsc hits
44: 0x901f36e4
45: 0x911f36e4
46: 0x921f36e4
47: 0x931f36e4
48: 0x941f36e4
49: 0x871f36e4
50: 0x871f36e7
51: 0x8f1f36e7
52: 0x901f36e9
53: 0x911f36e7
54: 0x921f36e9
55: 0x931f36e7
56: 0x941f36e9
57: 0x904330ac
58: 0x914330ac
59: 0x924330ac
60: 0x934330ac
61: 0x934330ad
62: 0x944330ac
63: 0x944330ad
64: 0x874330ac
65: 0x874330ad
66: 0x8f4330ac
67: 0x8f4330ad
68: 0x904330ad
69: 0x914330ad
70: 0x924330ad
71: 0x8f672a62
72: 0x90672a62
73: 0x91672a62
74: 0x92672a62
75: 0x93672a62
76: 0x94672a62
77: 0x87672a62
78: 0x87672a65
79: 0x8f672a65
80: 0x90672a65
81: 0x91672a65
82: 0x92672a65
83: 0x93672a65
84: 0x94672a65
85: 0xff000049
86: 0x878b2422
87: 0x8f8b2424
88: 0x908b2424
89: 0x918b2424
90: 0x928b2424
91: 0x938b2424
92: 0x938b2425
93: 0x948b2424
94: 0x948b2427
95: 0x878b2427
96: 0x8f8b2427
97: 0x908b2427
98: 0x918b2427
99: 0x928b2427
100: 0xe000eacc -- 0xE is end of fifo data, counter 0xeacc must match the counter in the 0xC word.
ReadDataThread read 344 -- next packet
...
</pre>

= TODO =

* DONE July 2022. add FwRev to the UDP data output
* RJ45 SFP: PROBLEM, D.A. CABLE: GOOD, Fiber SFP: ???. fix "write did not happen" (send udp write command, there is no reply, read returns old data as if write never happened). suspect udp "write" packet is lost?
* PROBLEM GONE Aug 2021. fix reply to wrong socket - udp packets should reply to same socket as they came from, udp data packets should be sent to same socket as requested them, not same socket as last command.
* DONE 2021jul30. add fixes from Chris P. for the auto-negotiation and dhcp (see email from him).
* DONE flash chip connected to FPGA. Aug 2021. implement ethernet flash programmer
* DONE Aug 2021. updated maxv firmware. implement FPGA reboot
* speed up programming the MLU by writing more than 1 bit at a time
* DONE Nov 2021. add 64-bit bitmap of BSC trigger bits
* DONE. add chronobox code
* DONE. add avalon mux for alphag and chronobox packets
* DONE. add chronobox fifo to udp packet sequencer
* check that TxReadyOut is correct and it is safe to send an avalon packet while previous packet is still transmitting.
* DONE. test fiber SFP is working
* complete the UDP flash programmer (parallel flash erase and write)

= End =

//KO

TRG

2022-07-25T16:58:29Z

Olchansk: /* firmware 0x618b790b (Nov 2021) */

= TRG, the trigger control board for the ALPHA-g detector =

= Links =

* xxx
* https://bitbucket.org/expalpha/trg_firmware - firmware sources on bitbucket

= General characteristics =

== Photos ==

== Board schematics ==

* https://bitbucket.org/expalpha/trg_firmware/src/master/3xFMC_VME_Motherboard.pdf

== Available hardware ==

* Altera Stratix IV - main FPGA
* Altera Max V - boot FPGA
* boot flash: PC28F512M29EW - 512 Mbit parallel NOR flash.

= TRG front panel connections =

From top to bottom:

<pre>
|
| minisas-C - links 8-11
| minisas-D - links 12-15
|
| ethernet sfp - use copper sfp only
| minisas - not used, do not connect
| esata - clock in, trigger out
|
| minisas-A - links 0-3
| minisas-B - links 4-7
|
| LEDs
|
</pre>

MiniSAS and SATA flail cable connections:

<pre>
P1 <--> link 3
P2 <--> link 2
P3 <--> link 1
P4 <--> link 0
</pre>

LEDs:

<pre>
--PCB-- (left)
LED[0] - trigger out - ag_trig_out
LED[1] - network packet received - sfp_rx_data_valid
LED[2] - Xilinx FPGA boot ok - FMC1_CFG_DONE
LED[3] - not used
(right)
</pre>

= TRG onboard jumpers and switches =

* rotary switches: select IP address: 00=192.168.1.50, 11=.51, 22=.52, 33=.53, 44=.54, otherwire=.251

= Firmware update procedure =

* use quartus to generate the grifc.pof file (use grifc.cof)
* open quartus programmer
* attach grifc.pof to the 1st CFI_512 flash
* mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
* check that "initiate configuration after programming" is set in tools->options
* say "start"
* should take about 5 minutes
* grifc should reboot into the new firmware

If CFI_512 flash is not visible to the quartus programmer, load correct
code into the MaxV CPLD:

* open quartus programmer,
* say "auto detect"
* change file for the 5M2210 device
* use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
* say "program", it should finish in 10-15 seconds
* say "auto detect"
* CFI_512 flash should be visible now.

= Firmware revisions =

* 0x5bc8f90f - original firmware used for all data
* 0x6147c0f9 - added cbtrg, etc. installed at CERN on 20 Sep 2021.
* 0x618376ae - bigger cbtrg fifo, data rate tested up to 30 Mbytes/sec
* 0x6189c7f3 - fix loss of trigger packets. (missing fifo between alphag block and ethernet mux)
* 0x618b790b - fix loss of timestamps. (cbtrg inputs stretched to 100 ns long). installed at CERN 10 Nov 2021.
* 0x62d32d95 - updated cbtrg, switched to edge-triggered cbtrg inputs, improved BSC multiplicity trigger, improved coinc trigger, added burst pulser. installed at CERN 19 Jul 2022.

= Firmware build =

* use quartus 20.1
* see Makefile in the trg_firmware project

= Jtag remote connection =

* ssh agmini@daq16
* /opt/intelFPGA/16.1/quartus/bin/jtagd --config /home/agmini/.jtagd.conf
* netstat -an | grep 1309 ### note listen address is "0.0.0.0", NOT "127.0.0.1"
<pre>
tcp 0 0 0.0.0.0:1309 0.0.0.0:* LISTEN
</pre>
* opt/intelFPGA/16.1/quartus/bin/jtagconfig ### should work
* ssh olchansk@daq01
* cd git/trg_firmware
* /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
* jtagconfig ### should work
<pre>
daq01:trg_firmware$ jtagconfig
1) DE-SoC on daq16 [2-1.2.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) USB-Blaster on daq16 [2-1.3]
024090DD EP4SGX230(.|ES)
020A40DD 5M(1270ZF324|2210Z)/EPM2210

daq01:trg_firmware$
</pre>

= ALPHA-g trigger functions =

Trigger options:
* software trigger
* pulser trigger
* trigger on GRIF16 ADC NIM and ESATA inputs ("external trigger")
* adc16 grand-or
* adc32 grand-or
* adc16 wire multiplicity
* TPC anode wire per-preamp trigger (aw16 section)
** trigger on coincidences of preamps (removed fw 0x62c77f0b)
** trigger on multiplicity of preamps (removed fw 0x62c77f0b)
** trigger on specific topology of preamps (multiplicity of preamp clusters, etc) via the aw16_mlu trigger
* BSC trigger
** BSC grand_or
** BSC bar multiplicity
* coincidence trigger - select coincidence of external trigger, TPC AW grand-or, TPC AW MLU, BSC grand-or and BSC bar multiplicity triggers

== software trigger ==

to programmatically fire the trigger, one should:
* set the conf_enable_sw_trigger bit in conf_trig_enable, this will permit the software trigger to fire the trigger
* write value 0x4 to register 0x2B, this will cause the software trigger to fire

== pulser trigger ==

To use the pulser trigger, one should program:
* pulser period (in clocks)
* pulser width (in clocks, use value 5, the pulser no longer goes outside of the trigger board, so changing the width does not do anything)
* set the run_pulser bit in conf_trig_enable, this will cause the pulser to run
* set the enable_pulser bit in conf_trig_enable, this will cause the pulser to fire the trigger
* set the output_pulser bit in conf_trig_enable, this will cause the pulser to be output from the alphag firmware block (the pulser no longer goes outside of the trigger board, so changing the bit does not do anything)

== timeout trigger ==

The event builder uses event timestamps to assemble physics events. The timestamps
are usually 32 bit wide and run at 125 MHz (8 ns) or 62.5 MHz (16 ns). If
triggers are generated often (1 per second or more), timestamp wrap around
is easily detected by the event builder. If triggers come infrequently,
timestamp wrap around may occur while there are no triggers, not be seen
by the event builder causing loss of event synchronization.

To avoid this problem in the event builder, a timeout trigger should be generated
if no triggers were generated inside a 10 second interval.

The guaranties that even if all physics triggers temporarily stop for any reason,
the event builder will stay synchronized. (0.1 Hz timeout trigger frequency).

To enable the timeout trigger:
* program timeout trigger timeout in reg 0x43 in units of 8 ns clock
* enable it in bit 23 of [[#conf_trig_enable bits]]

== adc16 multiplicity trigger ==

This trigger is intended for use with the barrel scintillator signals connected to adc16 digitizers. It does not work well with TPC AW signals.

The 16 adc16 trigger bits (16x16=256) are added together to form the hit multiplicity value (adc16_mult, 16 bits, actual range 0 to 256).

Four threshold signals are computed: adc16_mult_1ormore = adc16_mult>=1, 2ormore, 3ormore, 4ormore.

There is a counter for each of these four signals.

Each of these four signals can fire the trigger, see [[#conf_trig_enable bits]].

== TPC anode wire triggers ==

=== aw16 bus ===

TPC Anode Wire trigger is based on the aw16[15:0] (xaw16) bus.

Each bit corresponds to one AW preamp. 16 preamps, 16 bits.

The aw16[15:0] bus can be fed by
* adc16_or16[15:0] - or16 of 100 MHz ADCs, 16 ADC sas links
* adc32_or16[15:0] - or16 of 62.5 MHz ADCs, FMC-ADC32 has 32 channels, so 2 bits per ADC: low 16 channels and high 16 channels, sas links 7..0
* adc32_or16[31:16] - or16 of 62.5 MHz ADCs, ditto, sas links 15..8
as selected by conf_enable_aw_adc16, conf_enable_aw_adc32a, conf_enable_aw_adc32b in [[#conf_control bits]]

<pre>
///////////////////////////////////////////////////////////
// TPC Anode Wire trigger logic (aw16)
///////////////////////////////////////////////////////////

// map adc signals into aw16

wire [15:0] aw16 = ({16{conf_enable_aw_adc16}} & adc16_or16[15:0]) |
({16{conf_enable_aw_adc32a}} & adc32_or16[15:0]) |
({16{conf_enable_aw_adc32b}} & adc32_or16[31:16]);
...
ag_conditioner cond_adc16_or16_0(.clk(clk), .in(aw16[0]), .out(xxaw16[0]));
...
xaw16 <= xxaw16;
</pre>

=== aw16_grand_or ===

TPC AW "grand or" trigger: use aw16_mult_1ormore (before fw 0x62c77f0b)

(256 anode wires, 16 wires per preamp, 16 preamps, 16 aw16 signals)

=== aw16_mlu ===

TPC AW preamp MLU trigger: the MLU (memory lookup
table) implements an arbitrary logical function
to map the 16 aw16 preamp signals into 1 aw16_mlu_trig trigger output.

Description of the aw16 mlu trigger.

In words:

* any aw16 signal starts the aw16_prompt_run gate
* aw16 signals are collected for the duration of conf_mlu_prompt (125MHz/8ns clock)
* this corresponds to time spread of TPC AW signals due to the drift time in the AW drift cell and to the variation in signal transmission time from the ADC to the TRG (digital trigger data link).
* when this prompt time expires, the MLU looks at the accumulated aw16_prompt bit pattern and makes the "yes/no" trigger decision
* after the trigger decision is made, we wait for the TPC to become quiet:
* we wait until all aw16 signals are empty (no timeout)
* we run the aw16_prompt_wait gate, length conf_mlu_wait (8ns clock), if any aw16 signals arrive, we wait for aw16 empty again, rinse, repeat.
* now, after TPC aw16 have been empty for conf_mlu_wait clocks (8ns clock), MLU trigger is ready for the next event.

In logic: (see alphag.v)

* aw16_or <= grand-or of 16 aw16 signals
* "aw16_or" starts the "aw16_prompt_cnt" counter, opens the aw16_prompt_run gate
* during the aw16_prompt_run gate, aw16_prompt collects (latches) the aw16 bits (aw16_prompt <= aw16_prompt | aw16)
* this is the time when we wait for all "prompt" signals from the TPC to arrive into the trigger
* at the end of the aw16_prompt_run gate, the signal aw16_prompt_out is pulsed, latching the output of the MLU into aw16_mlu_trig
* this is the MLU trigger "yes/no" trigger decision.
* after the MLU trigger decision is made, we wait for the arrival and passing of all TPC drift signals
* the aw16_prompt_wait_cnt and aw_prompt_wait gate opens
* if any new aw16 signals arrive (they are TPC drift signals at this time), the aw16_prompt_wait gate is restarted
* if no aw16 signals arrive during the full run of the aw16_prompt_wait gate ("TPC quiet time")
* the aw16_prompt_wait and aw16_prompt gates are cleared and the MLU trigger is ready for the next event.

Good settings are:
* conf_mlu_prompt: 64 (512 ns)
* conf_mlu_wait: 128 (1024 ns)

== BSC trigger ==

=== bsc_adc16 bus ===

The BSC trigger is based on the [15:0]bsc_adc16[7:0] bus: 16 trigger discriminator bits from 8 ADC sas links. (8*16 = 64+64 bars, top and bottom).

The bsc_adc16 bus can be fed from sas links 0..7 or 8..15, controlled by conf_bsc_adc16_a and conf_bsc_adc16_b bits on [[#conf_bsc_control bits]].

bsc_adc16 can be fed only from GRIF-16 100 MHz ADC trigger discriminators.

=== bsc64_top and bsc64_bot buses ===

* firmware 0x5bc8f90f: bsc_adc16 is remapped into 64 bits of top (bsc64_top) and bottom (bsc64_bot):
<pre>
ag_bsc_remap bsc_remap_a(.adc(bsc_adc16[0]), .bsc_bot(bsc64_bot[7:0]), .bsc_top(bsc64_top[7:0]));
ag_bsc_remap bsc_remap_b(.adc(bsc_adc16[1]), .bsc_bot(bsc64_bot[8+7:8+0]), .bsc_top(bsc64_top[8+7:8+0]));
ag_bsc_remap bsc_remap_c(.adc(bsc_adc16[2]), .bsc_bot(bsc64_bot[2*8+7:2*8+0]), .bsc_top(bsc64_top[2*8+7:2*8+0]));
ag_bsc_remap bsc_remap_d(.adc(bsc_adc16[3]), .bsc_bot(bsc64_bot[3*8+7:3*8+0]), .bsc_top(bsc64_top[3*8+7:3*8+0]));

ag_bsc_remap bsc_remap_e(.adc(bsc_adc16[4]), .bsc_bot(bsc64_bot[4*8+7:4*8+0]), .bsc_top(bsc64_top[4*8+7:4*8+0]));
ag_bsc_remap bsc_remap_f(.adc(bsc_adc16[5]), .bsc_bot(bsc64_bot[5*8+7:5*8+0]), .bsc_top(bsc64_top[5*8+7:5*8+0]));
ag_bsc_remap bsc_remap_g(.adc(bsc_adc16[6]), .bsc_bot(bsc64_bot[6*8+7:6*8+0]), .bsc_top(bsc64_top[6*8+7:6*8+0]));
ag_bsc_remap bsc_remap_h(.adc(bsc_adc16[7]), .bsc_bot(bsc64_bot[7*8+7:7*8+0]), .bsc_top(bsc64_top[7*8+7:7*8+0]));

module ag_bsc_remap
(
input wire [15:0] adc,
output wire [7:0] bsc_bot,
output wire [7:0] bsc_top
);

assign bsc_top[3] = adc[0];
assign bsc_top[2] = adc[1];
assign bsc_top[1] = adc[2];
assign bsc_top[0] = adc[3];

assign bsc_top[7] = adc[4];
assign bsc_top[6] = adc[5];
assign bsc_top[5] = adc[6];
assign bsc_top[4] = adc[7];

assign bsc_bot[0] = adc[8];
assign bsc_bot[1] = adc[9];
assign bsc_bot[2] = adc[10];
assign bsc_bot[3] = adc[11];

assign bsc_bot[4] = adc[12];
assign bsc_bot[5] = adc[13];
assign bsc_bot[6] = adc[14];
assign bsc_bot[7] = adc[15];

endmodule
</pre>

=== bsc64 bus ===

the bsc64 bus is the 64 bars used by the trigger, formed from bsc64_top and bsc64_bot:
<pre>
if (conf_bsc64_bot_only) begin
bsc64 <= bsc64_bot;
end else if (conf_bsc64_top_only) begin
bsc64 <= bsc64_top;
end else if (conf_bsc64_bot_top_or) begin
bsc64 <= bsc64_bot | bsc64_top;
end else if (conf_bsc64_bot_top_and) begin
bsc64 <= bsc64_bot & bsc64_top;
end else begin
bsc64 <= 64'b0;
end
</pre>

=== bsc_grand_or_trig ===

bsc_grand_or_trig is the grand-or of 64 bits of the bsc64 bus

to enable triggering on bsc_grand_or_trig, set corresponding bit in [[#conf_trig_enable bits]]

=== old bsc_mult_trig ===

(from fw 0x62c77f0b, old bsc_mult_trig was replaced by new bsc64 multiplicity trigger)

* bsc64_mult is computed as multiplicity of the bsc64 bus (number of 64 bsc64 bits that fired)
* bsc_mult_trig is computed:
<pre>
if (bsc64_mult >= conf_bsc64_mult) begin
bsc_mult_trig <= 1;
end else begin
bsc_mult_trig <= 0;
end
</pre>

to enable the bsc multiplicity trigger, set the multiplicity value conf_bsc64_mult in [[#conf_bsc_control bits]] and enable the corresponding bit in [[#conf_trig_enable bits]].

=== bsc64 multiplicity trigger ===

bsc64 BSC bar multiplicity trigger uses a time window. this time window is started by bsc64_grand_or and runs for conf_bsc64_mult_window clocks (8 nc clock). During this time, hits in bsc64_bus are accumulated (latched) and their multiplicity is computed. If multiplicity condition is satisfied (bigger or equal to conf_bsc64_mult_min), bsc64_mult_trig is fired and the bsc64 bit pattern is saved to the UDP packet. Then trigger waits for the bsc64_bus to be empty. Then trigger waits for conf_bsc64_empty_window clocks, if there is any bsc64 hits, we wait for empty again. So after bsc64 has been empty for conf_bsc64_empty_window clocks, multiplicity trigger is ready for the next event. This scheme cannot implement max multiplicity.

recommended values:
* conf_bsc64_mult_window (8 bits): slightly longer than 3 cycles of SAS link: 3*18 = 54 clocks, good value is 80 (640 ns).
* conf_bsc64_mult_min (8 bits): 2
* conf_bsc64_empty_window (8 bits): 80 (640 ns)

== Coincidence trigger ==

Coincidence trigger provides a combination of TPC, BSC and external scintillator (esata_nim_grand_or) signals:

<pre>
assign coinc_input[0] = aw16_grand_or; // was aw16_mult_1ormore;
assign coinc_input[1] = aw16_mlu_trig;
assign coinc_input[2] = bsc_grand_or_trig;
assign coinc_input[3] = bsc_mult_trig;
assign coinc_input[4] = esata_nim_grand_or;
assign coinc_input[5] = 0;
assign coinc_input[6] = 0;
assign coinc_input[7] = 0;
</pre>

Coincidence trigger "start" mask selects which of the inputs can start the coincidence window.

Coincidence trigger "require" mask selects which inputs must have a hits for the coincidence to be satisfied.

Input hits are collected for the duration of the coincidence window, if all required inputs have hits, coinc_trig is fired.

Example settings:

* coincidence of external scintillator, BSC and TPC AW "grand or" signals: start 0x10, required 0x15
* coincidence of BSC grand-or and TPC AW grand-or signals: start 0x5, required 0x5
* coincidence of BSC multiplicity and TPC AW grand-or triggers: start 0x9, required 0x9

= Control registers =

== Register addresses ==

Note: all registers are 32 bits unless otherwise noted.

Note: RW means read-write register, RO means read-only, ROL means read-only, contents is latched by the "latch_out" bit

{| cellpadding="10" cellspacing="0" border="1"
! Address || Quartus Name || Access || FwRev || Description
|-
| 0x08 || num_sample || RW || GRIF-C || magic 16-bit register to control UDP packet size
|-
| 0x08 || scratch_reg || RW || 0x618b790b || 32-bit scratch register
|-
| 0x1F || compilation_time || RO || || Firmware revision
|-
| 0x20 || conf_trig_width || RW || || Trigger signal width, 16 ns clock
|-
| 0x21 || conf_busy_width || RW || || Busy signal width, 16 ns clock (not used)
|-
| 0x22 || conf_pulser_width || RW || || Pulser signal width, 16 ns clock
|-
| 0x23 || conf_pulser_period || RW || || Pulser signal period, 16 ns clock
|-
| 0x24 || conf_pulser_burst_ctrl || RW || 0x62d1c47e || Generate bursts of pulses: 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses, 16 ns clocks
|-
| 0x25 || conf_trig_enable || RW || || see [[#conf_trig_enable bits]]
|-
| 0x26 || || || not used
|-
| 0x27 || || || not used
|-
| 0x28 || || || not used
|-
| 0x29 || conf_nim_mask || RW || || enable bits for ADC NIM inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2A || conf_esata_mask || RW || || enable bits for ADC eSATA inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2B || reset_out, latch_out, trigger_out || W || || see [[#reg 0x2B bits]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x5bc8f90f || configure AW coincidence trigger, see [[#aw16_coinc]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x62c77f0b || removed
|-
| 0x2D || conf_aw16_coinc_b || RW || 0x5bc8f90f ||
|-
| 0x2E || conf_aw16_coinc_c || RW || 0x5bc8f90f ||
|-
| 0x2F || conf_aw16_coinc_d || RW || 0x5bc8f90f ||
|-
| 0x30 || sas_sd[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect for each link
|-
| 0x31 || pll_625_status || ROL || 0x5b2057f5 (12Jun18_16:32) || 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter
|-
| 0x32 || clk_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the system 125 MHz clock
|-
| 0x33 || clk_625_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625)
|-
| 0x34 || conf_control || RW || 0x5b398983 (01Jul18_19:10) || see [[#conf_control bits]] below
|-
| 0x35 || conf_drift_width || RW || 0x5b398983 (01Jul18_19:10) || width of drift time blank-out in 16 ns clocks
|-
| 0x36 || conf_scaledown || RW || 0x5b398983 (01Jul18_19:10) || trigger scaledown, 0=no scaledown, 1=divide-by-2, 2=divide-by-3, etc
|-
| 0x37 || conf_mlu || RW || 0x5b398983 (01Jul18_19:10) || AW MLU control bits, see [[#conf_mlu bits]]
|-
| 0x38 || conf_trig_delay || RW || 0x5baedfca (28Sep18_19:13) || delay the trigger pulse, 16 ns clock
|-
| 0x39 || esata_clk_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the TRG 125 MHz clock
|-
| 0x3A || esata_clk_esata_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the external clock (eSATA 62.5 MHz clock)
|-
| 0x3B || conf_counter_adc_select || RW || 0x5bb7f6ae (05Oct18_16:41) || select which 16 ADCs are connected to the selected adc counters, 0..15 - connect the adc16 signals, 16..47 connect the adc32 signals
|-
| 0x3C || sysreset_ts || RO || 0x5bb7f6ae (05Oct18_16:41) || 125MHz counter of VME-SYSRESET
|-
| 0x3C || || || 0x618b790b || not used
|-
| 0x3D || GRIF-C csr || RW || GRIF-C || <= csr & ~par_value; // Selective clear
|-
| 0x3E || GRIF-C csr || RW || GRIF-C || <= csr | par_value; // Selective set
|-
| 0x3F || GRIF-C csr || RW || GRIF-C || <= par_value; // write
|-
| 0x3D || || || 0x618b790b || not used
|-
| 0x3E || || || 0x618b790b || not used
|-
| 0x3F || || || 0x618b790b || not used
|-
| 0x40 || conf_bsc_control || RW || 0x5bc13541 (12Oct18_16:58) || Barrel Scintillator trigger control, see [[#conf_bsc_control bits]]
|-
| 0x41 || conf_coinc_control || RW || 0x5bc13541 (12Oct18_16:58) || Coincidence trigger control, see [[#conf_coinc_control bits]]
|-
| 0x42 || reconfig_out || WO || 0x5bc13541 (12Oct18_16:58) || reserved for rebooting the FPGA (does not work)
|-
| 0x43 || conf_trigger_timeout || RW || 0x5bc8f90f (18Oct18_14:20) || Generate timeout trigger if there is no other trigger after given timeout, in 8 ns clocks, must be enabled by bit conf_enable_timeout_trig in [[#conf_trig_enable bits]]
|-
| 0x44 || eth_clk_counter || ROL || 0x618b790b ||
|-
| 0x45 || eth_clk_eth_counter || ROL || 0x618b790b ||
|-
| 0x100 || ts_625 || ROL || || latched timestamp
|-
| 0x101 || counter_trig_out || ROL || || counter of issued triggers
|-
| 0x102 || counter_trig_in || ROL || || counter of triggers
|-
| 0x103 || counter_pulser || ROL || || counter of pulser
|-
| 0x104 || counter_adc16_grand_or || ROL ||
|-
| 0x105 || counter_adc32_grand_or || ROL ||
|-
| 0x106 || counter_adc_grand_or || ROL ||
|-
| 0x107 || counter_esata_nim_grand_or || ROL ||
|-
| 0x108 || counter_adc16_mult_1ormore || ROL ||
|-
| 0x109 || counter_adc16_mult_2ormore || ROL ||
|-
| 0x10A || counter_adc16_mult_3ormore || ROL ||
|-
| 0x10B || counter_adc16_mult_4ormore || ROL ||
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x5bc8f90f || counter of AW coincidence triggers
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x62c77f0b || removed
|-
| 0x10D || counter_aw16_coinc_b || ROL || 0x5bc8f90f ||
|-
| 0x10E || counter_aw16_coinc_c || ROL || 0x5bc8f90f ||
|-
| 0x10F || counter_aw16_coinc_d || ROL || 0x5bc8f90f ||
|-
| 0x110 || counter_drift || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the drift time blank-out
|-
| 0x111 || counter_scaledown || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the scaledown
|-
| 0x112 || counter_aw16_coinc || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW coincidence triggers
|-
| 0x113 || counter_aw16_mlu || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW MLU triggers
|-
| 0x114 || counter_aw16_grand_or || ROL || 0x62c77f0b || counter of AW grand-or triggers
|-
| 0x114 || counter_aw16_mult_1ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 1ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 2ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x62c77f0b || removed
|-
| 0x116 || counter_aw16_mult_3ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 3ormore triggers
|-
| 0x117 || counter_aw16_mult_4ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 4ormore triggers
|-
| 0x118 || counter_bsc_grand_or || ROL || 0x5bc13541 (12Oct18_16:58) || counter of BSC grand-or triggers
|-
| 0x119 || counter_bsc_mult || ROL || 0x5bc13541 (12Oct18_16:58) || counter of old BSC multiplicity triggers
|-
| 0x11A || counter_coinc || ROL || 0x5bc13541 (12Oct18_16:58) || counter of coincidence triggers
|-
| 0x11B || counter_timeout || ROL || 0x618b790b || counter of timeout triggers
|-
| 0x11C || counter_bsc_mult_start || ROL || 0x62c77f0b || counter of BSC multiplicity windows
|-
| 0x11D || counter_bsc_mult_trig || ROL || 0x62c77f0b || counter of BSC multiplicity triggers
|-
| 0x11E || counter_coinc_start || ROL || 0x62d1b152 || counter of coincidence windows
|-
| 0x11F || counter_aw16_mlu_start || ROL || 0x62d1b152 || counter of TPC AW MLU windows
|-
| 0x200..0x207 || conf_adc16_masks || RW || all || adc16 enable bits
|-
| 0x300..0x30F || conf_adc32_masks || RW || all || adc32 enable bits
|-
| 0x400..0x41F || sas_bits[15:0][63:0] || ROL || all || sas data bits for each link
|-
| 0x420..0x42F || sas_sd_counters[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect counter for each link
|-
| 0x430..0x43F || counters_adc16_or16[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 16 counters of adc16 ORes
|-
| 0x440..0x45F || counters_adc32_or16[31:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 32 counters of adc32 ORes
|-
| 0x460..0x46F || counters_adc_selected[15:0] || ROL || 0x5bb7f6ae (05Oct18_16:41) || 16 counters for selected group of adcs, see conf_counter_adc_select
|-
| 0x470..0x4AF || counters_bsc64[63:0] || ROL || 0x5bc13541 (12Oct18_16:58) || 64 counters for the BSC bars
|-
|}

== additional registers ==

<pre>
reg | rw/ro/rol | quartus name | firmware | description
-----------------------------------------------------------------
0x60 | rw | cb_control_out | 0x618b790b | chronobox control
0x61 | rw | cb_status | 0x618b790b | chronobox status
0x62 | rw | cb_invert_a_out | 0x618b790b | chronobox input invert
0x63 | rw | cb_invert_b_out | 0x618b790b |
0x64 | rw | cb_enable_le_a_out | 0x618b790b | timestamp enable leading edge
0x65 | rw | cb_enable_le_b_out | 0x618b790b |
0x66 | rw | cb_enable_te_a_out | 0x618b790b | timestamp enable traiing edge
0x67 | rw | cb_enable_te_b_out | 0x618b790b |
0x6A | ro | cb_input_num | 0x618b790b | chronobox number of inputs
0x6B | rw | cb_sync_mask_a_out | 0x618b790b | chronobox sync signal source
0x6C | rw | cb_sync_mask_b_out | 0x618b790b |
0x6D | rw | cb_sync_reg_out | 0x618b790b | chronobox sync register
0x6E | ro | cb_sync_status | 0x618b790b | chronobox sync status
0x6F | rw | cb_latch_period_out | 0x618b790b | chronobox scalers latch period
0x70 | ro | cb_fifo_status | 0x618b790b | chronobox data fifo status
0x71 | ro | cb_fifo_data | 0x618b790b | read chronobox data fifo (cb_fifo_rdack_out <= 1)
0x72 | rw | cb_udp_period_out | 0x618b790b | period for flushing fifo to UDP
0x73 | rw | cb_udp_threshold_out | 0x618b790b | byte threshold for flushing fifo to UDP
</pre>

== conf_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_clock_select || 0x5b3aa19f (02Jul18_15:05) || select 0=internal 62.5 MHz clock or 1=esata 62.5 MHz clock
|-
| 1 || conf_enable_aw_adc16 || 0x5baedfca (28Sep18_19:13) || select source of TPC AW aw16 bus, see [[#aw16 bus]]
|-
| 2 || conf_enable_aw_adc32a || 0x5baedfca (28Sep18_19:13) ||
|-
| 3 || conf_enable_aw_adc32b || 0x5baedfca (28Sep18_19:13) ||
|-
| 15..4 || || ||
|-
| 23..16 || conf_mlu_prompt || 0x5b3aa19f (02Jul18_15:05) || MLU trigger prompt window, see [[#aw16_mlu]]
|-
| 31..24 || conf_mlu_wait || 0x5b3aa19f (02Jul18_15:05) || MLU trigger wait window, see [[#aw16_mlu]]
|-
|}

== conf_mlu bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 31 || mlu_reset || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 30 || mlu_write || 0x5b3aa19f (02Jul18_15:05) || 1=write data bit into given address
|-
| 16 || mlu_data || 0x5b3aa19f (02Jul18_15:05) || data bit for writing to MLU RAM
|-
| 15..0 || mlu_write_addr || 0x5b3aa19f (02Jul18_15:05) || MLU RAM write address for writing the data bit
|-
|}

== conf_bsc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_bsc_adc_a || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 0..7
|-
| 1 || conf_bsc_adc_b || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 8..15
|-
| 2 || conf_bsc64_bot_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses bottom channels only
|-
| 3 || conf_bsc64_top_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses top channels only
|-
| 4 || conf_bsc64_bot_top_or || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "or" of top and bottom
|-
| 5 || conf_bsc64_bot_top_and || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "and" of top and bottom
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_bsc64_mult_min || 0x5bc13541 (12Oct18_16:58) || minimum bsc64 multiplicity
|-
| 23..16 || conf_bsc64_empty_wondow || 0x62d1c47e || bsc64 empty window length, 8 ns clocks
|-
| 31..24 || conf_bsc64_mult_window || 0x62c77f0b || bsc64 multiplicity window length, 8 ns clocks
|-
|}

== conf_coinc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_coinc_required[0] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mult_1ormore
|-
| 0 || conf_coinc_required[0] || 0x62c77f0b || enable aw16_grand_or
|-
| 1 || conf_coinc_required[1] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mlu_trig
|-
| 2 || conf_coinc_required[2] || 0x5bc13541 (12Oct18_16:58) || enable bsc_grand_or_trig
|-
| 3 || conf_coinc_required[3] || 0x5bc13541 (12Oct18_16:58) || enable bsc_mult_trig
|-
| 3 || conf_coinc_required[3] || 0x62c77f0b || enable bsc64_mult_trig
|-
| 4 || conf_coinc_required[4] || 0x5bc13541 (12Oct18_16:58) || enable esata_nim_grand_or
|-
| 5 || conf_coinc_required[5]
|-
| 6 || conf_coinc_required[6]
|-
| 7 || conf_coinc_required[7]
|-
| 15..8 || conf_coinc_window[7:0] || 0x5bc13541 (12Oct18_16:58) || coincidence window length in units of 125MHz clock (8 ns)
|-
| 23..16 || conf_coinc_start[7:0] || 0x5bc13541 (12Oct18_16:58) || start the coincidence window, same bits as "required"
|-
| 31..24 ||
|-
|}

== conf_trig_enable bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_enable_sw_trigger || || trigger on software trigger (how generated???)
|-
| 1 || conf_enable_pulser || || trigger on pulser
|-
| 2 || - || 0x5b120c9f (01Jun18_20:18) || not used
|-
| 3 || conf_pulser_run || || allow the pulser to run (frequency has to be set beforehand)
|-
| 4 || conf_output_pulser || 0x5bc8f90f || does nothing (top level ag_pulser_out is disconnected)
|-
| 4 || || 0x618b790b || not used
|-
| 5 || conf_enable_esata_nim || || trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand)
|-
| 6 || conf_enable_adc16 || || trigger on adc16_grand_or
|-
| 7 || conf_enable_adc32 || || trigger on adc32_grand_or
|-
| 8 || conf_enable_adc16_1ormore || || trigger on adc16_mult_1ormore "1 or more"
|-
| 9 || conf_enable_adc16_2ormore || || same, "2 or more"
|-
| 10 || conf_enable_adc16_3ormore || || same, "3 or more"
|-
| 11 || conf_enable_adc16_4ormore || || same, "4 or more"
|-
| 12 || - || 0x5b08938c (25May18_15:51) || not used
|-
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
|-
| 14 || - || 0x5bc8f90f || not used
|-
| 15 || conf_enable_adc || 0x5b120c9f (01Jun18_20:18) || trigger on adc_grand_or
|-
| 16 || conf_enable_aw16_coinc_a || 0x5bc8f90f || enable AW coincidence trigger, see [[#aw16_coinc]]
|-
| 16 || - || 0x62c77f0b || aw16_coinc_x removed
|-
| 17 || conf_enable_aw16_coinc_b || 0x5bc8f90f ||
|-
| 18 || conf_enable_aw16_coinc_c || 0x5bc8f90f ||
|-
| 19 || conf_enable_aw16_coinc_d || 0x5bc8f90f ||
|-
| 20 || - || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 20 || conf_enable_aw16_grand_or || 0x618b790b || enable trigger on aw16_grand_or
|-
| 21 || conf_enable_aw16_coinc || 0x5b3aa19f (02Jul18_15:05) || enable trigger on aw16_coinc_trig
|-
| 22 || conf_enable_aw16_mlu || 0x5b3aa19f (02Jul18_15:05) || enable AW MLU trigger
|-
| 23 || conf_enable_timeout_trig || 0x5bc8f90f (18Oct18_14:20) || enable trigger timeout trigger
|-
| 24 || conf_enable_aw16_1ormore || 0x5b3aa19f (02Jul18_15:05) || trigger on aw16_mult_1ormore "1 or more"
|-
| 24 || - || 0x62c77f0b || aw16_mult_xxx removed
|-
| 25 || conf_enable_aw16_2ormore || 0x5b3aa19f (02Jul18_15:05) || same, "2 or more"
|-
| 26 || conf_enable_aw16_3ormore || 0x5b3aa19f (02Jul18_15:05) || same, "3 or more"
|-
| 27 || conf_enable_aw16_4ormore || 0x5b3aa19f (02Jul18_15:05) || same, "4 or more"
|-
| 28 || conf_enable_bsc_grand_or || 0x5bc13541 (12Oct18_16:58) || trigger on BSC grand-or
|-
| 29 || conf_enable_bsc_mult || 0x5bc13541 (12Oct18_16:58) || trigger on BSC multiplicity
|-
| 30 || conf_enable_coinc || 0x5bc13541 (12Oct18_16:58) || trigger on TPC/BSC/ext coincidence trigger
|-
| 31 || - || || not used
|-
|}

== reg 0x2B bits ==

Write to this register will pulse corresponding fpga signals:

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || reset_out || 0x5b120c9f (01Jun18_20:18) || reset counters, etc
|-
| 1 || latch_out || 0x5b120c9f (01Jun18_20:18) || latch counters, sas bits, etc
|-
| 2 || trigger_out || 0x5b120c9f (01Jun18_20:18) || generate a software trigger
|-
|}

= UDP data format =

== general format ==

<pre>
trigger packet:

[0] udp packet counter
[1] 0x8ccccccc
...
[N] 0xEccccccc

different versions of trigger packets should be decoded according to packet length:
40 bytes: initial firmware
76 bytes: firmware 0x618b790b (Nov 2021)
80 bytes: firmware 0x62d1c47e (Jul 2022)

chronobox fifo packet, firmware 0x618b790b (Nov 2021)

[0] udp packet counter
[1] 0xCccccccc
[2] fifo status
[3] fifo data
...
[N] 0xEccccccc

0x0ccccccc is the 28 bit fifo packet counter

chronobox fifo packet, firmware 0x618b790b (Nov 2021)

[0] udp packet counter
[1] 0xDccccccc
[2] 0xDEADBEEF
[3] fifo status
[4] fifo data
...
[N] 0xEccccccc

0x0ccccccc is the 28 bit fifo packet counter
</pre>

== firmware 0x5bc8f90f ==

{| cellpadding="10" cellspacing="0" border="1"
! Offset || Name || Quartus name || FwRev || Description
|-
| 0 || packet counter || none || all || 31-bit UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
|-
| 1 || 0x8 packet header || || all || 28 bits of counter_trig_out
|-
| 2 || trigger timestamp || trig_ts || all || 62.5MHz trigger timestamp
|-
| 3 || accepted triggers || counter_trig_out || all || counter of accepted triggers
|-
| 4 || input triggers || counter_trig_in || all || counter of trigger input
|-
| 5 || pulser triggers || counter_pulser || all || counter of pulser triggers
|-
| 6 || trigger bitmap || udp_trig_bits || 0x5a48448d (30Dec17_17:59) || bitmap of trigger information, see below
|-
| 7 || nim bits || udp_nim_bits_masked || ??? || 32 bits of ADC NIM inputs (2 bits per ADC)
|-
| 8 || esata bits || udp_esata_bits_masked || ??? || 32 bits of ADC ESATA inputs (2 bits per ADC)
|-
| 9 || mlu bits || aw16_prompt || 0x5b398983 (01Jul18_19:10) || 16 bits of MLU input, 1 bit per preamp
|-
| 10 || drift-blank-off counter || udp_drift_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the drift blank-off
|-
| 11 || scaledown counter || udp_scaledown_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the scaledown
|-
| X || || || ||
|-
| 12 || 0xE packet footer || || all || 28 bits of counter_trig_out
|-
|}

== firmware 0x618b790b (Nov 2021) ==

packet size 80 bytes

<pre>
0 udp packet counter
1 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
2 udp_data_out <= udp_trig_ts_625;
3 udp_data_out <= udp_counter_trig_out;
4 udp_data_out <= udp_counter_trig_in;
5 udp_data_out <= udp_counter_pulser;
6 udp_data_out <= udp_trig_bits;
7 udp_data_out <= udp_nim_bits;
8 udp_data_out <= udp_esata_bits;
9 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
10 udp_data_out <= udp_counter_drift;
11 udp_data_out <= udp_counter_scaledown;
12 udp_data_out <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
13 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
14 udp_data_out <= { udp_bsc64_bus[31:0]};
15 udp_data_out <= { udp_bsc64_bus[63:32]};
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
17 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
19 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

== firmware 0x62d1c47e (Jul 2022) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, 8'h00, 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= conf_fw_rev;
18 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

Values of udp_coinc_latch[7:0]:
* aaa

Values of udp_aw16_mult[7:0] and udp_aw16_bus[15:0]:
* aaa

Values of udp_bsc64_mult[7:0] and udp_bsc64_bus[63:0]
* aaa

== trigger bitmap ==

Firmware ??? (one of the very early revisions)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= adc16_coinc_top;
udp_trig_bits[5] <= adc16_coinc_bot;
udp_trig_bits[6] <= adc16_coinc;
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
udp_trig_bits[31:24] <= mult16[7:0];

</pre>

Firmware 0x5b08938c (25May18_15:51)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= 0; // not used
udp_trig_bits[31:24] <= mult16[7:0];
</pre>

Firmware 0x5b217dc4 (13Jun18_13:25)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5b3aa19f (02Jul18_15:05)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= udp_mlu_out;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5bc8f90f (18Oct18_14:20)

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_run_pulser
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = 0; // not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x618b790b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x62c77f0b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = 0; // aw16_coinc_a;
assign trig32_in[17] = 0; // aw16_coinc_b;
assign trig32_in[18] = 0; // aw16_coinc_c;
assign trig32_in[19] = 0; // aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = 0; // aw16_mult_1ormore;
assign trig32_in[25] = 0; // aw16_mult_2ormore;
assign trig32_in[26] = 0; // aw16_mult_3ormore;
assign trig32_in[27] = 0; // aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc64_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

= TRG chronobox inputs =

from trg_firmware/toplevel/grifc.v

<pre>
localparam CB_N = 23;
localparam CB_N1 = CB_N-1;

wire [CB_N1:0] cb_xinputs_async;

assign cb_xinputs_async[0] = ag_trig_out;
assign cb_xinputs_async[1] = ag_trig_scaledown_out;
assign cb_xinputs_async[2] = ag_trig_drift_out;
assign cb_xinputs_async[3] = ag_trig_received_out;

assign cb_xinputs_async[4] = ag_cb_sw_trig;
assign cb_xinputs_async[5] = ag_cb_pulser_trig;
assign cb_xinputs_async[6] = ag_cb_esata_nim_trig;
assign cb_xinputs_async[7] = ag_cb_adc16_grand_or_trig;
assign cb_xinputs_async[8] = ag_cb_adc32_grand_or_trig;

assign cb_xinputs_async[9] = ag_cb_aw16_grand_or_trig;
assign cb_xinputs_async[10] = ag_cb_aw16_mult_1ormore;
assign cb_xinputs_async[11] = ag_cb_aw16_mult_2ormore;
assign cb_xinputs_async[12] = ag_cb_aw16_mult_3ormore;
assign cb_xinputs_async[13] = ag_cb_aw16_mult_4ormore;
assign cb_xinputs_async[14] = ag_cb_aw16_mlu_trig;

assign cb_xinputs_async[15] = ag_cb_bsc64_grand_or_trig;
assign cb_xinputs_async[16] = ag_cb_bsc64_mult_1ormore;
assign cb_xinputs_async[17] = ag_cb_bsc64_mult_2ormore;
assign cb_xinputs_async[18] = ag_cb_bsc64_mult_3ormore;
assign cb_xinputs_async[19] = ag_cb_bsc64_mult_4ormore;
assign cb_xinputs_async[20] = ag_cb_bsc64_mult_trig;

assign cb_xinputs_async[21] = ag_cb_coinc_trig;

assign cb_xinputs_async[22] = ag_cb_timeout_trig;
</pre>

= Example UDP packets =

* trigger data, marker words 0x8

<pre>
ReadDataThread read 76
0: 0x003666ed -- UDP packet counter from UDP transmitter
1: 0x80000bf8 -- 0x8 is trigger data packet, 0xbf8 is the trigger counter from alphag.v
2: 0x2edf8b41 -- trigger data
3: 0x00000bf8
4: 0x00000bf8
5: 0x00000bee
6: 0x00000001
7: 0x00000000
8: 0x00000000
9: 0x00000003
10: 0x00000bf8
11: 0x00000bf8
12: 0x00000000
13: 0x00000000
14: 0x00000000
15: 0x00000000
16: 0x00000000
17: 0x00000000
18: 0xe0000bf8 -- 0xE is end of trigger data, counter 0xbf8 must match the counter in the 0x8 word.
ReadDataThread read 76 -- next packet
0: 0x003666ee -- UDP packet counter from UDP transmitter
...
</pre>

* chronobox fifo data, marker word 0xC, see [[Chronobox#FIFO_data_format]]

<pre>
ReadDataThread read 404
0: 0x003658ed -- UDP packet counter from UDP transmitter
1: 0xc000eacc -- 0xC is FIFO data, fifo packet counter 0xeacc from fifo_to_udp.v
2: 0x00000061 -- FIFO status, low bits the the word counter, so up to 0x61 fifo words are to follow
3: 0x87fb3d72 -- tsc hits
4: 0x8ffb3d74
5: 0x90fb3d74
6: 0x91fb3d74
7: 0x92fb3d74
8: 0x93fb3d74
9: 0x93fb3d75
10: 0x94fb3d74
11: 0x94fb3d77
12: 0x87fb3d77
13: 0x8ffb3d77
14: 0x90fb3d77
15: 0x91fb3d77
16: 0x92fb3d77
17: 0xfe000018 -- 0xFE scaler data starts, 0x18 words to follow
18: 0x00000000
19: 0x00000000
20: 0x00000000
21: 0x00000000
22: 0x00000000
23: 0x00000000
24: 0x00000000
25: 0x00000108
26: 0x00000000
27: 0x00000000
28: 0x00000000
29: 0x00000000
30: 0x00000000
31: 0x00000000
32: 0x00000000
33: 0x00000108
34: 0x00000108
35: 0x00000108
36: 0x00000108
37: 0x00000108
38: 0x00000108
39: 0x00000000
40: 0x00000000
41: 0xce56fa93 -- last word of scaler data is the sysclock counter (125 MHz)
42: 0xff800048 -- timestamp wraparound
43: 0x8f1f36e4 -- tsc hits
44: 0x901f36e4
45: 0x911f36e4
46: 0x921f36e4
47: 0x931f36e4
48: 0x941f36e4
49: 0x871f36e4
50: 0x871f36e7
51: 0x8f1f36e7
52: 0x901f36e9
53: 0x911f36e7
54: 0x921f36e9
55: 0x931f36e7
56: 0x941f36e9
57: 0x904330ac
58: 0x914330ac
59: 0x924330ac
60: 0x934330ac
61: 0x934330ad
62: 0x944330ac
63: 0x944330ad
64: 0x874330ac
65: 0x874330ad
66: 0x8f4330ac
67: 0x8f4330ad
68: 0x904330ad
69: 0x914330ad
70: 0x924330ad
71: 0x8f672a62
72: 0x90672a62
73: 0x91672a62
74: 0x92672a62
75: 0x93672a62
76: 0x94672a62
77: 0x87672a62
78: 0x87672a65
79: 0x8f672a65
80: 0x90672a65
81: 0x91672a65
82: 0x92672a65
83: 0x93672a65
84: 0x94672a65
85: 0xff000049
86: 0x878b2422
87: 0x8f8b2424
88: 0x908b2424
89: 0x918b2424
90: 0x928b2424
91: 0x938b2424
92: 0x938b2425
93: 0x948b2424
94: 0x948b2427
95: 0x878b2427
96: 0x8f8b2427
97: 0x908b2427
98: 0x918b2427
99: 0x928b2427
100: 0xe000eacc -- 0xE is end of fifo data, counter 0xeacc must match the counter in the 0xC word.
ReadDataThread read 344 -- next packet
...
</pre>

= TODO =

* DONE July 2022. add FwRev to the UDP data output
* RJ45 SFP: PROBLEM, D.A. CABLE: GOOD, Fiber SFP: ???. fix "write did not happen" (send udp write command, there is no reply, read returns old data as if write never happened). suspect udp "write" packet is lost?
* PROBLEM GONE Aug 2021. fix reply to wrong socket - udp packets should reply to same socket as they came from, udp data packets should be sent to same socket as requested them, not same socket as last command.
* DONE 2021jul30. add fixes from Chris P. for the auto-negotiation and dhcp (see email from him).
* DONE flash chip connected to FPGA. Aug 2021. implement ethernet flash programmer
* DONE Aug 2021. updated maxv firmware. implement FPGA reboot
* speed up programming the MLU by writing more than 1 bit at a time
* DONE Nov 2021. add 64-bit bitmap of BSC trigger bits
* DONE. add chronobox code
* DONE. add avalon mux for alphag and chronobox packets
* DONE. add chronobox fifo to udp packet sequencer
* check that TxReadyOut is correct and it is safe to send an avalon packet while previous packet is still transmitting.
* DONE. test fiber SFP is working
* complete the UDP flash programmer (parallel flash erase and write)

= End =

//KO

TRG

2022-07-25T16:57:32Z

Olchansk: /* general format */

= TRG, the trigger control board for the ALPHA-g detector =

= Links =

* xxx
* https://bitbucket.org/expalpha/trg_firmware - firmware sources on bitbucket

= General characteristics =

== Photos ==

== Board schematics ==

* https://bitbucket.org/expalpha/trg_firmware/src/master/3xFMC_VME_Motherboard.pdf

== Available hardware ==

* Altera Stratix IV - main FPGA
* Altera Max V - boot FPGA
* boot flash: PC28F512M29EW - 512 Mbit parallel NOR flash.

= TRG front panel connections =

From top to bottom:

<pre>
|
| minisas-C - links 8-11
| minisas-D - links 12-15
|
| ethernet sfp - use copper sfp only
| minisas - not used, do not connect
| esata - clock in, trigger out
|
| minisas-A - links 0-3
| minisas-B - links 4-7
|
| LEDs
|
</pre>

MiniSAS and SATA flail cable connections:

<pre>
P1 <--> link 3
P2 <--> link 2
P3 <--> link 1
P4 <--> link 0
</pre>

LEDs:

<pre>
--PCB-- (left)
LED[0] - trigger out - ag_trig_out
LED[1] - network packet received - sfp_rx_data_valid
LED[2] - Xilinx FPGA boot ok - FMC1_CFG_DONE
LED[3] - not used
(right)
</pre>

= TRG onboard jumpers and switches =

* rotary switches: select IP address: 00=192.168.1.50, 11=.51, 22=.52, 33=.53, 44=.54, otherwire=.251

= Firmware update procedure =

* use quartus to generate the grifc.pof file (use grifc.cof)
* open quartus programmer
* attach grifc.pof to the 1st CFI_512 flash
* mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
* check that "initiate configuration after programming" is set in tools->options
* say "start"
* should take about 5 minutes
* grifc should reboot into the new firmware

If CFI_512 flash is not visible to the quartus programmer, load correct
code into the MaxV CPLD:

* open quartus programmer,
* say "auto detect"
* change file for the 5M2210 device
* use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
* say "program", it should finish in 10-15 seconds
* say "auto detect"
* CFI_512 flash should be visible now.

= Firmware revisions =

* 0x5bc8f90f - original firmware used for all data
* 0x6147c0f9 - added cbtrg, etc. installed at CERN on 20 Sep 2021.
* 0x618376ae - bigger cbtrg fifo, data rate tested up to 30 Mbytes/sec
* 0x6189c7f3 - fix loss of trigger packets. (missing fifo between alphag block and ethernet mux)
* 0x618b790b - fix loss of timestamps. (cbtrg inputs stretched to 100 ns long). installed at CERN 10 Nov 2021.
* 0x62d32d95 - updated cbtrg, switched to edge-triggered cbtrg inputs, improved BSC multiplicity trigger, improved coinc trigger, added burst pulser. installed at CERN 19 Jul 2022.

= Firmware build =

* use quartus 20.1
* see Makefile in the trg_firmware project

= Jtag remote connection =

* ssh agmini@daq16
* /opt/intelFPGA/16.1/quartus/bin/jtagd --config /home/agmini/.jtagd.conf
* netstat -an | grep 1309 ### note listen address is "0.0.0.0", NOT "127.0.0.1"
<pre>
tcp 0 0 0.0.0.0:1309 0.0.0.0:* LISTEN
</pre>
* opt/intelFPGA/16.1/quartus/bin/jtagconfig ### should work
* ssh olchansk@daq01
* cd git/trg_firmware
* /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
* jtagconfig ### should work
<pre>
daq01:trg_firmware$ jtagconfig
1) DE-SoC on daq16 [2-1.2.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) USB-Blaster on daq16 [2-1.3]
024090DD EP4SGX230(.|ES)
020A40DD 5M(1270ZF324|2210Z)/EPM2210

daq01:trg_firmware$
</pre>

= ALPHA-g trigger functions =

Trigger options:
* software trigger
* pulser trigger
* trigger on GRIF16 ADC NIM and ESATA inputs ("external trigger")
* adc16 grand-or
* adc32 grand-or
* adc16 wire multiplicity
* TPC anode wire per-preamp trigger (aw16 section)
** trigger on coincidences of preamps (removed fw 0x62c77f0b)
** trigger on multiplicity of preamps (removed fw 0x62c77f0b)
** trigger on specific topology of preamps (multiplicity of preamp clusters, etc) via the aw16_mlu trigger
* BSC trigger
** BSC grand_or
** BSC bar multiplicity
* coincidence trigger - select coincidence of external trigger, TPC AW grand-or, TPC AW MLU, BSC grand-or and BSC bar multiplicity triggers

== software trigger ==

to programmatically fire the trigger, one should:
* set the conf_enable_sw_trigger bit in conf_trig_enable, this will permit the software trigger to fire the trigger
* write value 0x4 to register 0x2B, this will cause the software trigger to fire

== pulser trigger ==

To use the pulser trigger, one should program:
* pulser period (in clocks)
* pulser width (in clocks, use value 5, the pulser no longer goes outside of the trigger board, so changing the width does not do anything)
* set the run_pulser bit in conf_trig_enable, this will cause the pulser to run
* set the enable_pulser bit in conf_trig_enable, this will cause the pulser to fire the trigger
* set the output_pulser bit in conf_trig_enable, this will cause the pulser to be output from the alphag firmware block (the pulser no longer goes outside of the trigger board, so changing the bit does not do anything)

== timeout trigger ==

The event builder uses event timestamps to assemble physics events. The timestamps
are usually 32 bit wide and run at 125 MHz (8 ns) or 62.5 MHz (16 ns). If
triggers are generated often (1 per second or more), timestamp wrap around
is easily detected by the event builder. If triggers come infrequently,
timestamp wrap around may occur while there are no triggers, not be seen
by the event builder causing loss of event synchronization.

To avoid this problem in the event builder, a timeout trigger should be generated
if no triggers were generated inside a 10 second interval.

The guaranties that even if all physics triggers temporarily stop for any reason,
the event builder will stay synchronized. (0.1 Hz timeout trigger frequency).

To enable the timeout trigger:
* program timeout trigger timeout in reg 0x43 in units of 8 ns clock
* enable it in bit 23 of [[#conf_trig_enable bits]]

== adc16 multiplicity trigger ==

This trigger is intended for use with the barrel scintillator signals connected to adc16 digitizers. It does not work well with TPC AW signals.

The 16 adc16 trigger bits (16x16=256) are added together to form the hit multiplicity value (adc16_mult, 16 bits, actual range 0 to 256).

Four threshold signals are computed: adc16_mult_1ormore = adc16_mult>=1, 2ormore, 3ormore, 4ormore.

There is a counter for each of these four signals.

Each of these four signals can fire the trigger, see [[#conf_trig_enable bits]].

== TPC anode wire triggers ==

=== aw16 bus ===

TPC Anode Wire trigger is based on the aw16[15:0] (xaw16) bus.

Each bit corresponds to one AW preamp. 16 preamps, 16 bits.

The aw16[15:0] bus can be fed by
* adc16_or16[15:0] - or16 of 100 MHz ADCs, 16 ADC sas links
* adc32_or16[15:0] - or16 of 62.5 MHz ADCs, FMC-ADC32 has 32 channels, so 2 bits per ADC: low 16 channels and high 16 channels, sas links 7..0
* adc32_or16[31:16] - or16 of 62.5 MHz ADCs, ditto, sas links 15..8
as selected by conf_enable_aw_adc16, conf_enable_aw_adc32a, conf_enable_aw_adc32b in [[#conf_control bits]]

<pre>
///////////////////////////////////////////////////////////
// TPC Anode Wire trigger logic (aw16)
///////////////////////////////////////////////////////////

// map adc signals into aw16

wire [15:0] aw16 = ({16{conf_enable_aw_adc16}} & adc16_or16[15:0]) |
({16{conf_enable_aw_adc32a}} & adc32_or16[15:0]) |
({16{conf_enable_aw_adc32b}} & adc32_or16[31:16]);
...
ag_conditioner cond_adc16_or16_0(.clk(clk), .in(aw16[0]), .out(xxaw16[0]));
...
xaw16 <= xxaw16;
</pre>

=== aw16_grand_or ===

TPC AW "grand or" trigger: use aw16_mult_1ormore (before fw 0x62c77f0b)

(256 anode wires, 16 wires per preamp, 16 preamps, 16 aw16 signals)

=== aw16_mlu ===

TPC AW preamp MLU trigger: the MLU (memory lookup
table) implements an arbitrary logical function
to map the 16 aw16 preamp signals into 1 aw16_mlu_trig trigger output.

Description of the aw16 mlu trigger.

In words:

* any aw16 signal starts the aw16_prompt_run gate
* aw16 signals are collected for the duration of conf_mlu_prompt (125MHz/8ns clock)
* this corresponds to time spread of TPC AW signals due to the drift time in the AW drift cell and to the variation in signal transmission time from the ADC to the TRG (digital trigger data link).
* when this prompt time expires, the MLU looks at the accumulated aw16_prompt bit pattern and makes the "yes/no" trigger decision
* after the trigger decision is made, we wait for the TPC to become quiet:
* we wait until all aw16 signals are empty (no timeout)
* we run the aw16_prompt_wait gate, length conf_mlu_wait (8ns clock), if any aw16 signals arrive, we wait for aw16 empty again, rinse, repeat.
* now, after TPC aw16 have been empty for conf_mlu_wait clocks (8ns clock), MLU trigger is ready for the next event.

In logic: (see alphag.v)

* aw16_or <= grand-or of 16 aw16 signals
* "aw16_or" starts the "aw16_prompt_cnt" counter, opens the aw16_prompt_run gate
* during the aw16_prompt_run gate, aw16_prompt collects (latches) the aw16 bits (aw16_prompt <= aw16_prompt | aw16)
* this is the time when we wait for all "prompt" signals from the TPC to arrive into the trigger
* at the end of the aw16_prompt_run gate, the signal aw16_prompt_out is pulsed, latching the output of the MLU into aw16_mlu_trig
* this is the MLU trigger "yes/no" trigger decision.
* after the MLU trigger decision is made, we wait for the arrival and passing of all TPC drift signals
* the aw16_prompt_wait_cnt and aw_prompt_wait gate opens
* if any new aw16 signals arrive (they are TPC drift signals at this time), the aw16_prompt_wait gate is restarted
* if no aw16 signals arrive during the full run of the aw16_prompt_wait gate ("TPC quiet time")
* the aw16_prompt_wait and aw16_prompt gates are cleared and the MLU trigger is ready for the next event.

Good settings are:
* conf_mlu_prompt: 64 (512 ns)
* conf_mlu_wait: 128 (1024 ns)

== BSC trigger ==

=== bsc_adc16 bus ===

The BSC trigger is based on the [15:0]bsc_adc16[7:0] bus: 16 trigger discriminator bits from 8 ADC sas links. (8*16 = 64+64 bars, top and bottom).

The bsc_adc16 bus can be fed from sas links 0..7 or 8..15, controlled by conf_bsc_adc16_a and conf_bsc_adc16_b bits on [[#conf_bsc_control bits]].

bsc_adc16 can be fed only from GRIF-16 100 MHz ADC trigger discriminators.

=== bsc64_top and bsc64_bot buses ===

* firmware 0x5bc8f90f: bsc_adc16 is remapped into 64 bits of top (bsc64_top) and bottom (bsc64_bot):
<pre>
ag_bsc_remap bsc_remap_a(.adc(bsc_adc16[0]), .bsc_bot(bsc64_bot[7:0]), .bsc_top(bsc64_top[7:0]));
ag_bsc_remap bsc_remap_b(.adc(bsc_adc16[1]), .bsc_bot(bsc64_bot[8+7:8+0]), .bsc_top(bsc64_top[8+7:8+0]));
ag_bsc_remap bsc_remap_c(.adc(bsc_adc16[2]), .bsc_bot(bsc64_bot[2*8+7:2*8+0]), .bsc_top(bsc64_top[2*8+7:2*8+0]));
ag_bsc_remap bsc_remap_d(.adc(bsc_adc16[3]), .bsc_bot(bsc64_bot[3*8+7:3*8+0]), .bsc_top(bsc64_top[3*8+7:3*8+0]));

ag_bsc_remap bsc_remap_e(.adc(bsc_adc16[4]), .bsc_bot(bsc64_bot[4*8+7:4*8+0]), .bsc_top(bsc64_top[4*8+7:4*8+0]));
ag_bsc_remap bsc_remap_f(.adc(bsc_adc16[5]), .bsc_bot(bsc64_bot[5*8+7:5*8+0]), .bsc_top(bsc64_top[5*8+7:5*8+0]));
ag_bsc_remap bsc_remap_g(.adc(bsc_adc16[6]), .bsc_bot(bsc64_bot[6*8+7:6*8+0]), .bsc_top(bsc64_top[6*8+7:6*8+0]));
ag_bsc_remap bsc_remap_h(.adc(bsc_adc16[7]), .bsc_bot(bsc64_bot[7*8+7:7*8+0]), .bsc_top(bsc64_top[7*8+7:7*8+0]));

module ag_bsc_remap
(
input wire [15:0] adc,
output wire [7:0] bsc_bot,
output wire [7:0] bsc_top
);

assign bsc_top[3] = adc[0];
assign bsc_top[2] = adc[1];
assign bsc_top[1] = adc[2];
assign bsc_top[0] = adc[3];

assign bsc_top[7] = adc[4];
assign bsc_top[6] = adc[5];
assign bsc_top[5] = adc[6];
assign bsc_top[4] = adc[7];

assign bsc_bot[0] = adc[8];
assign bsc_bot[1] = adc[9];
assign bsc_bot[2] = adc[10];
assign bsc_bot[3] = adc[11];

assign bsc_bot[4] = adc[12];
assign bsc_bot[5] = adc[13];
assign bsc_bot[6] = adc[14];
assign bsc_bot[7] = adc[15];

endmodule
</pre>

=== bsc64 bus ===

the bsc64 bus is the 64 bars used by the trigger, formed from bsc64_top and bsc64_bot:
<pre>
if (conf_bsc64_bot_only) begin
bsc64 <= bsc64_bot;
end else if (conf_bsc64_top_only) begin
bsc64 <= bsc64_top;
end else if (conf_bsc64_bot_top_or) begin
bsc64 <= bsc64_bot | bsc64_top;
end else if (conf_bsc64_bot_top_and) begin
bsc64 <= bsc64_bot & bsc64_top;
end else begin
bsc64 <= 64'b0;
end
</pre>

=== bsc_grand_or_trig ===

bsc_grand_or_trig is the grand-or of 64 bits of the bsc64 bus

to enable triggering on bsc_grand_or_trig, set corresponding bit in [[#conf_trig_enable bits]]

=== old bsc_mult_trig ===

(from fw 0x62c77f0b, old bsc_mult_trig was replaced by new bsc64 multiplicity trigger)

* bsc64_mult is computed as multiplicity of the bsc64 bus (number of 64 bsc64 bits that fired)
* bsc_mult_trig is computed:
<pre>
if (bsc64_mult >= conf_bsc64_mult) begin
bsc_mult_trig <= 1;
end else begin
bsc_mult_trig <= 0;
end
</pre>

to enable the bsc multiplicity trigger, set the multiplicity value conf_bsc64_mult in [[#conf_bsc_control bits]] and enable the corresponding bit in [[#conf_trig_enable bits]].

=== bsc64 multiplicity trigger ===

bsc64 BSC bar multiplicity trigger uses a time window. this time window is started by bsc64_grand_or and runs for conf_bsc64_mult_window clocks (8 nc clock). During this time, hits in bsc64_bus are accumulated (latched) and their multiplicity is computed. If multiplicity condition is satisfied (bigger or equal to conf_bsc64_mult_min), bsc64_mult_trig is fired and the bsc64 bit pattern is saved to the UDP packet. Then trigger waits for the bsc64_bus to be empty. Then trigger waits for conf_bsc64_empty_window clocks, if there is any bsc64 hits, we wait for empty again. So after bsc64 has been empty for conf_bsc64_empty_window clocks, multiplicity trigger is ready for the next event. This scheme cannot implement max multiplicity.

recommended values:
* conf_bsc64_mult_window (8 bits): slightly longer than 3 cycles of SAS link: 3*18 = 54 clocks, good value is 80 (640 ns).
* conf_bsc64_mult_min (8 bits): 2
* conf_bsc64_empty_window (8 bits): 80 (640 ns)

== Coincidence trigger ==

Coincidence trigger provides a combination of TPC, BSC and external scintillator (esata_nim_grand_or) signals:

<pre>
assign coinc_input[0] = aw16_grand_or; // was aw16_mult_1ormore;
assign coinc_input[1] = aw16_mlu_trig;
assign coinc_input[2] = bsc_grand_or_trig;
assign coinc_input[3] = bsc_mult_trig;
assign coinc_input[4] = esata_nim_grand_or;
assign coinc_input[5] = 0;
assign coinc_input[6] = 0;
assign coinc_input[7] = 0;
</pre>

Coincidence trigger "start" mask selects which of the inputs can start the coincidence window.

Coincidence trigger "require" mask selects which inputs must have a hits for the coincidence to be satisfied.

Input hits are collected for the duration of the coincidence window, if all required inputs have hits, coinc_trig is fired.

Example settings:

* coincidence of external scintillator, BSC and TPC AW "grand or" signals: start 0x10, required 0x15
* coincidence of BSC grand-or and TPC AW grand-or signals: start 0x5, required 0x5
* coincidence of BSC multiplicity and TPC AW grand-or triggers: start 0x9, required 0x9

= Control registers =

== Register addresses ==

Note: all registers are 32 bits unless otherwise noted.

Note: RW means read-write register, RO means read-only, ROL means read-only, contents is latched by the "latch_out" bit

{| cellpadding="10" cellspacing="0" border="1"
! Address || Quartus Name || Access || FwRev || Description
|-
| 0x08 || num_sample || RW || GRIF-C || magic 16-bit register to control UDP packet size
|-
| 0x08 || scratch_reg || RW || 0x618b790b || 32-bit scratch register
|-
| 0x1F || compilation_time || RO || || Firmware revision
|-
| 0x20 || conf_trig_width || RW || || Trigger signal width, 16 ns clock
|-
| 0x21 || conf_busy_width || RW || || Busy signal width, 16 ns clock (not used)
|-
| 0x22 || conf_pulser_width || RW || || Pulser signal width, 16 ns clock
|-
| 0x23 || conf_pulser_period || RW || || Pulser signal period, 16 ns clock
|-
| 0x24 || conf_pulser_burst_ctrl || RW || 0x62d1c47e || Generate bursts of pulses: 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses, 16 ns clocks
|-
| 0x25 || conf_trig_enable || RW || || see [[#conf_trig_enable bits]]
|-
| 0x26 || || || not used
|-
| 0x27 || || || not used
|-
| 0x28 || || || not used
|-
| 0x29 || conf_nim_mask || RW || || enable bits for ADC NIM inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2A || conf_esata_mask || RW || || enable bits for ADC eSATA inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2B || reset_out, latch_out, trigger_out || W || || see [[#reg 0x2B bits]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x5bc8f90f || configure AW coincidence trigger, see [[#aw16_coinc]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x62c77f0b || removed
|-
| 0x2D || conf_aw16_coinc_b || RW || 0x5bc8f90f ||
|-
| 0x2E || conf_aw16_coinc_c || RW || 0x5bc8f90f ||
|-
| 0x2F || conf_aw16_coinc_d || RW || 0x5bc8f90f ||
|-
| 0x30 || sas_sd[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect for each link
|-
| 0x31 || pll_625_status || ROL || 0x5b2057f5 (12Jun18_16:32) || 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter
|-
| 0x32 || clk_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the system 125 MHz clock
|-
| 0x33 || clk_625_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625)
|-
| 0x34 || conf_control || RW || 0x5b398983 (01Jul18_19:10) || see [[#conf_control bits]] below
|-
| 0x35 || conf_drift_width || RW || 0x5b398983 (01Jul18_19:10) || width of drift time blank-out in 16 ns clocks
|-
| 0x36 || conf_scaledown || RW || 0x5b398983 (01Jul18_19:10) || trigger scaledown, 0=no scaledown, 1=divide-by-2, 2=divide-by-3, etc
|-
| 0x37 || conf_mlu || RW || 0x5b398983 (01Jul18_19:10) || AW MLU control bits, see [[#conf_mlu bits]]
|-
| 0x38 || conf_trig_delay || RW || 0x5baedfca (28Sep18_19:13) || delay the trigger pulse, 16 ns clock
|-
| 0x39 || esata_clk_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the TRG 125 MHz clock
|-
| 0x3A || esata_clk_esata_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the external clock (eSATA 62.5 MHz clock)
|-
| 0x3B || conf_counter_adc_select || RW || 0x5bb7f6ae (05Oct18_16:41) || select which 16 ADCs are connected to the selected adc counters, 0..15 - connect the adc16 signals, 16..47 connect the adc32 signals
|-
| 0x3C || sysreset_ts || RO || 0x5bb7f6ae (05Oct18_16:41) || 125MHz counter of VME-SYSRESET
|-
| 0x3C || || || 0x618b790b || not used
|-
| 0x3D || GRIF-C csr || RW || GRIF-C || <= csr & ~par_value; // Selective clear
|-
| 0x3E || GRIF-C csr || RW || GRIF-C || <= csr | par_value; // Selective set
|-
| 0x3F || GRIF-C csr || RW || GRIF-C || <= par_value; // write
|-
| 0x3D || || || 0x618b790b || not used
|-
| 0x3E || || || 0x618b790b || not used
|-
| 0x3F || || || 0x618b790b || not used
|-
| 0x40 || conf_bsc_control || RW || 0x5bc13541 (12Oct18_16:58) || Barrel Scintillator trigger control, see [[#conf_bsc_control bits]]
|-
| 0x41 || conf_coinc_control || RW || 0x5bc13541 (12Oct18_16:58) || Coincidence trigger control, see [[#conf_coinc_control bits]]
|-
| 0x42 || reconfig_out || WO || 0x5bc13541 (12Oct18_16:58) || reserved for rebooting the FPGA (does not work)
|-
| 0x43 || conf_trigger_timeout || RW || 0x5bc8f90f (18Oct18_14:20) || Generate timeout trigger if there is no other trigger after given timeout, in 8 ns clocks, must be enabled by bit conf_enable_timeout_trig in [[#conf_trig_enable bits]]
|-
| 0x44 || eth_clk_counter || ROL || 0x618b790b ||
|-
| 0x45 || eth_clk_eth_counter || ROL || 0x618b790b ||
|-
| 0x100 || ts_625 || ROL || || latched timestamp
|-
| 0x101 || counter_trig_out || ROL || || counter of issued triggers
|-
| 0x102 || counter_trig_in || ROL || || counter of triggers
|-
| 0x103 || counter_pulser || ROL || || counter of pulser
|-
| 0x104 || counter_adc16_grand_or || ROL ||
|-
| 0x105 || counter_adc32_grand_or || ROL ||
|-
| 0x106 || counter_adc_grand_or || ROL ||
|-
| 0x107 || counter_esata_nim_grand_or || ROL ||
|-
| 0x108 || counter_adc16_mult_1ormore || ROL ||
|-
| 0x109 || counter_adc16_mult_2ormore || ROL ||
|-
| 0x10A || counter_adc16_mult_3ormore || ROL ||
|-
| 0x10B || counter_adc16_mult_4ormore || ROL ||
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x5bc8f90f || counter of AW coincidence triggers
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x62c77f0b || removed
|-
| 0x10D || counter_aw16_coinc_b || ROL || 0x5bc8f90f ||
|-
| 0x10E || counter_aw16_coinc_c || ROL || 0x5bc8f90f ||
|-
| 0x10F || counter_aw16_coinc_d || ROL || 0x5bc8f90f ||
|-
| 0x110 || counter_drift || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the drift time blank-out
|-
| 0x111 || counter_scaledown || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the scaledown
|-
| 0x112 || counter_aw16_coinc || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW coincidence triggers
|-
| 0x113 || counter_aw16_mlu || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW MLU triggers
|-
| 0x114 || counter_aw16_grand_or || ROL || 0x62c77f0b || counter of AW grand-or triggers
|-
| 0x114 || counter_aw16_mult_1ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 1ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 2ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x62c77f0b || removed
|-
| 0x116 || counter_aw16_mult_3ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 3ormore triggers
|-
| 0x117 || counter_aw16_mult_4ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 4ormore triggers
|-
| 0x118 || counter_bsc_grand_or || ROL || 0x5bc13541 (12Oct18_16:58) || counter of BSC grand-or triggers
|-
| 0x119 || counter_bsc_mult || ROL || 0x5bc13541 (12Oct18_16:58) || counter of old BSC multiplicity triggers
|-
| 0x11A || counter_coinc || ROL || 0x5bc13541 (12Oct18_16:58) || counter of coincidence triggers
|-
| 0x11B || counter_timeout || ROL || 0x618b790b || counter of timeout triggers
|-
| 0x11C || counter_bsc_mult_start || ROL || 0x62c77f0b || counter of BSC multiplicity windows
|-
| 0x11D || counter_bsc_mult_trig || ROL || 0x62c77f0b || counter of BSC multiplicity triggers
|-
| 0x11E || counter_coinc_start || ROL || 0x62d1b152 || counter of coincidence windows
|-
| 0x11F || counter_aw16_mlu_start || ROL || 0x62d1b152 || counter of TPC AW MLU windows
|-
| 0x200..0x207 || conf_adc16_masks || RW || all || adc16 enable bits
|-
| 0x300..0x30F || conf_adc32_masks || RW || all || adc32 enable bits
|-
| 0x400..0x41F || sas_bits[15:0][63:0] || ROL || all || sas data bits for each link
|-
| 0x420..0x42F || sas_sd_counters[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect counter for each link
|-
| 0x430..0x43F || counters_adc16_or16[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 16 counters of adc16 ORes
|-
| 0x440..0x45F || counters_adc32_or16[31:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 32 counters of adc32 ORes
|-
| 0x460..0x46F || counters_adc_selected[15:0] || ROL || 0x5bb7f6ae (05Oct18_16:41) || 16 counters for selected group of adcs, see conf_counter_adc_select
|-
| 0x470..0x4AF || counters_bsc64[63:0] || ROL || 0x5bc13541 (12Oct18_16:58) || 64 counters for the BSC bars
|-
|}

== additional registers ==

<pre>
reg | rw/ro/rol | quartus name | firmware | description
-----------------------------------------------------------------
0x60 | rw | cb_control_out | 0x618b790b | chronobox control
0x61 | rw | cb_status | 0x618b790b | chronobox status
0x62 | rw | cb_invert_a_out | 0x618b790b | chronobox input invert
0x63 | rw | cb_invert_b_out | 0x618b790b |
0x64 | rw | cb_enable_le_a_out | 0x618b790b | timestamp enable leading edge
0x65 | rw | cb_enable_le_b_out | 0x618b790b |
0x66 | rw | cb_enable_te_a_out | 0x618b790b | timestamp enable traiing edge
0x67 | rw | cb_enable_te_b_out | 0x618b790b |
0x6A | ro | cb_input_num | 0x618b790b | chronobox number of inputs
0x6B | rw | cb_sync_mask_a_out | 0x618b790b | chronobox sync signal source
0x6C | rw | cb_sync_mask_b_out | 0x618b790b |
0x6D | rw | cb_sync_reg_out | 0x618b790b | chronobox sync register
0x6E | ro | cb_sync_status | 0x618b790b | chronobox sync status
0x6F | rw | cb_latch_period_out | 0x618b790b | chronobox scalers latch period
0x70 | ro | cb_fifo_status | 0x618b790b | chronobox data fifo status
0x71 | ro | cb_fifo_data | 0x618b790b | read chronobox data fifo (cb_fifo_rdack_out <= 1)
0x72 | rw | cb_udp_period_out | 0x618b790b | period for flushing fifo to UDP
0x73 | rw | cb_udp_threshold_out | 0x618b790b | byte threshold for flushing fifo to UDP
</pre>

== conf_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_clock_select || 0x5b3aa19f (02Jul18_15:05) || select 0=internal 62.5 MHz clock or 1=esata 62.5 MHz clock
|-
| 1 || conf_enable_aw_adc16 || 0x5baedfca (28Sep18_19:13) || select source of TPC AW aw16 bus, see [[#aw16 bus]]
|-
| 2 || conf_enable_aw_adc32a || 0x5baedfca (28Sep18_19:13) ||
|-
| 3 || conf_enable_aw_adc32b || 0x5baedfca (28Sep18_19:13) ||
|-
| 15..4 || || ||
|-
| 23..16 || conf_mlu_prompt || 0x5b3aa19f (02Jul18_15:05) || MLU trigger prompt window, see [[#aw16_mlu]]
|-
| 31..24 || conf_mlu_wait || 0x5b3aa19f (02Jul18_15:05) || MLU trigger wait window, see [[#aw16_mlu]]
|-
|}

== conf_mlu bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 31 || mlu_reset || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 30 || mlu_write || 0x5b3aa19f (02Jul18_15:05) || 1=write data bit into given address
|-
| 16 || mlu_data || 0x5b3aa19f (02Jul18_15:05) || data bit for writing to MLU RAM
|-
| 15..0 || mlu_write_addr || 0x5b3aa19f (02Jul18_15:05) || MLU RAM write address for writing the data bit
|-
|}

== conf_bsc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_bsc_adc_a || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 0..7
|-
| 1 || conf_bsc_adc_b || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 8..15
|-
| 2 || conf_bsc64_bot_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses bottom channels only
|-
| 3 || conf_bsc64_top_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses top channels only
|-
| 4 || conf_bsc64_bot_top_or || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "or" of top and bottom
|-
| 5 || conf_bsc64_bot_top_and || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "and" of top and bottom
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_bsc64_mult_min || 0x5bc13541 (12Oct18_16:58) || minimum bsc64 multiplicity
|-
| 23..16 || conf_bsc64_empty_wondow || 0x62d1c47e || bsc64 empty window length, 8 ns clocks
|-
| 31..24 || conf_bsc64_mult_window || 0x62c77f0b || bsc64 multiplicity window length, 8 ns clocks
|-
|}

== conf_coinc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_coinc_required[0] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mult_1ormore
|-
| 0 || conf_coinc_required[0] || 0x62c77f0b || enable aw16_grand_or
|-
| 1 || conf_coinc_required[1] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mlu_trig
|-
| 2 || conf_coinc_required[2] || 0x5bc13541 (12Oct18_16:58) || enable bsc_grand_or_trig
|-
| 3 || conf_coinc_required[3] || 0x5bc13541 (12Oct18_16:58) || enable bsc_mult_trig
|-
| 3 || conf_coinc_required[3] || 0x62c77f0b || enable bsc64_mult_trig
|-
| 4 || conf_coinc_required[4] || 0x5bc13541 (12Oct18_16:58) || enable esata_nim_grand_or
|-
| 5 || conf_coinc_required[5]
|-
| 6 || conf_coinc_required[6]
|-
| 7 || conf_coinc_required[7]
|-
| 15..8 || conf_coinc_window[7:0] || 0x5bc13541 (12Oct18_16:58) || coincidence window length in units of 125MHz clock (8 ns)
|-
| 23..16 || conf_coinc_start[7:0] || 0x5bc13541 (12Oct18_16:58) || start the coincidence window, same bits as "required"
|-
| 31..24 ||
|-
|}

== conf_trig_enable bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_enable_sw_trigger || || trigger on software trigger (how generated???)
|-
| 1 || conf_enable_pulser || || trigger on pulser
|-
| 2 || - || 0x5b120c9f (01Jun18_20:18) || not used
|-
| 3 || conf_pulser_run || || allow the pulser to run (frequency has to be set beforehand)
|-
| 4 || conf_output_pulser || 0x5bc8f90f || does nothing (top level ag_pulser_out is disconnected)
|-
| 4 || || 0x618b790b || not used
|-
| 5 || conf_enable_esata_nim || || trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand)
|-
| 6 || conf_enable_adc16 || || trigger on adc16_grand_or
|-
| 7 || conf_enable_adc32 || || trigger on adc32_grand_or
|-
| 8 || conf_enable_adc16_1ormore || || trigger on adc16_mult_1ormore "1 or more"
|-
| 9 || conf_enable_adc16_2ormore || || same, "2 or more"
|-
| 10 || conf_enable_adc16_3ormore || || same, "3 or more"
|-
| 11 || conf_enable_adc16_4ormore || || same, "4 or more"
|-
| 12 || - || 0x5b08938c (25May18_15:51) || not used
|-
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
|-
| 14 || - || 0x5bc8f90f || not used
|-
| 15 || conf_enable_adc || 0x5b120c9f (01Jun18_20:18) || trigger on adc_grand_or
|-
| 16 || conf_enable_aw16_coinc_a || 0x5bc8f90f || enable AW coincidence trigger, see [[#aw16_coinc]]
|-
| 16 || - || 0x62c77f0b || aw16_coinc_x removed
|-
| 17 || conf_enable_aw16_coinc_b || 0x5bc8f90f ||
|-
| 18 || conf_enable_aw16_coinc_c || 0x5bc8f90f ||
|-
| 19 || conf_enable_aw16_coinc_d || 0x5bc8f90f ||
|-
| 20 || - || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 20 || conf_enable_aw16_grand_or || 0x618b790b || enable trigger on aw16_grand_or
|-
| 21 || conf_enable_aw16_coinc || 0x5b3aa19f (02Jul18_15:05) || enable trigger on aw16_coinc_trig
|-
| 22 || conf_enable_aw16_mlu || 0x5b3aa19f (02Jul18_15:05) || enable AW MLU trigger
|-
| 23 || conf_enable_timeout_trig || 0x5bc8f90f (18Oct18_14:20) || enable trigger timeout trigger
|-
| 24 || conf_enable_aw16_1ormore || 0x5b3aa19f (02Jul18_15:05) || trigger on aw16_mult_1ormore "1 or more"
|-
| 24 || - || 0x62c77f0b || aw16_mult_xxx removed
|-
| 25 || conf_enable_aw16_2ormore || 0x5b3aa19f (02Jul18_15:05) || same, "2 or more"
|-
| 26 || conf_enable_aw16_3ormore || 0x5b3aa19f (02Jul18_15:05) || same, "3 or more"
|-
| 27 || conf_enable_aw16_4ormore || 0x5b3aa19f (02Jul18_15:05) || same, "4 or more"
|-
| 28 || conf_enable_bsc_grand_or || 0x5bc13541 (12Oct18_16:58) || trigger on BSC grand-or
|-
| 29 || conf_enable_bsc_mult || 0x5bc13541 (12Oct18_16:58) || trigger on BSC multiplicity
|-
| 30 || conf_enable_coinc || 0x5bc13541 (12Oct18_16:58) || trigger on TPC/BSC/ext coincidence trigger
|-
| 31 || - || || not used
|-
|}

== reg 0x2B bits ==

Write to this register will pulse corresponding fpga signals:

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || reset_out || 0x5b120c9f (01Jun18_20:18) || reset counters, etc
|-
| 1 || latch_out || 0x5b120c9f (01Jun18_20:18) || latch counters, sas bits, etc
|-
| 2 || trigger_out || 0x5b120c9f (01Jun18_20:18) || generate a software trigger
|-
|}

= UDP data format =

== general format ==

<pre>
trigger packet:

[0] udp packet counter
[1] 0x8ccccccc
...
[N] 0xEccccccc

different versions of trigger packets should be decoded according to packet length:
40 bytes: initial firmware
76 bytes: firmware 0x618b790b (Nov 2021)
80 bytes: firmware 0x62d1c47e (Jul 2022)

chronobox fifo packet, firmware 0x618b790b (Nov 2021)

[0] udp packet counter
[1] 0xCccccccc
[2] fifo status
[3] fifo data
...
[N] 0xEccccccc

0x0ccccccc is the 28 bit fifo packet counter

chronobox fifo packet, firmware 0x618b790b (Nov 2021)

[0] udp packet counter
[1] 0xDccccccc
[2] 0xDEADBEEF
[3] fifo status
[4] fifo data
...
[N] 0xEccccccc

0x0ccccccc is the 28 bit fifo packet counter
</pre>

== firmware 0x5bc8f90f ==

{| cellpadding="10" cellspacing="0" border="1"
! Offset || Name || Quartus name || FwRev || Description
|-
| 0 || packet counter || none || all || 31-bit UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
|-
| 1 || 0x8 packet header || || all || 28 bits of counter_trig_out
|-
| 2 || trigger timestamp || trig_ts || all || 62.5MHz trigger timestamp
|-
| 3 || accepted triggers || counter_trig_out || all || counter of accepted triggers
|-
| 4 || input triggers || counter_trig_in || all || counter of trigger input
|-
| 5 || pulser triggers || counter_pulser || all || counter of pulser triggers
|-
| 6 || trigger bitmap || udp_trig_bits || 0x5a48448d (30Dec17_17:59) || bitmap of trigger information, see below
|-
| 7 || nim bits || udp_nim_bits_masked || ??? || 32 bits of ADC NIM inputs (2 bits per ADC)
|-
| 8 || esata bits || udp_esata_bits_masked || ??? || 32 bits of ADC ESATA inputs (2 bits per ADC)
|-
| 9 || mlu bits || aw16_prompt || 0x5b398983 (01Jul18_19:10) || 16 bits of MLU input, 1 bit per preamp
|-
| 10 || drift-blank-off counter || udp_drift_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the drift blank-off
|-
| 11 || scaledown counter || udp_scaledown_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the scaledown
|-
| X || || || ||
|-
| 12 || 0xE packet footer || || all || 28 bits of counter_trig_out
|-
|}

== firmware 0x618b790b (Nov 2021) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

== firmware 0x62d1c47e (Jul 2022) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, 8'h00, 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= conf_fw_rev;
18 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

Values of udp_coinc_latch[7:0]:
* aaa

Values of udp_aw16_mult[7:0] and udp_aw16_bus[15:0]:
* aaa

Values of udp_bsc64_mult[7:0] and udp_bsc64_bus[63:0]
* aaa

== trigger bitmap ==

Firmware ??? (one of the very early revisions)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= adc16_coinc_top;
udp_trig_bits[5] <= adc16_coinc_bot;
udp_trig_bits[6] <= adc16_coinc;
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
udp_trig_bits[31:24] <= mult16[7:0];

</pre>

Firmware 0x5b08938c (25May18_15:51)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= 0; // not used
udp_trig_bits[31:24] <= mult16[7:0];
</pre>

Firmware 0x5b217dc4 (13Jun18_13:25)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5b3aa19f (02Jul18_15:05)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= udp_mlu_out;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5bc8f90f (18Oct18_14:20)

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_run_pulser
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = 0; // not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x618b790b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x62c77f0b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = 0; // aw16_coinc_a;
assign trig32_in[17] = 0; // aw16_coinc_b;
assign trig32_in[18] = 0; // aw16_coinc_c;
assign trig32_in[19] = 0; // aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = 0; // aw16_mult_1ormore;
assign trig32_in[25] = 0; // aw16_mult_2ormore;
assign trig32_in[26] = 0; // aw16_mult_3ormore;
assign trig32_in[27] = 0; // aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc64_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

= TRG chronobox inputs =

from trg_firmware/toplevel/grifc.v

<pre>
localparam CB_N = 23;
localparam CB_N1 = CB_N-1;

wire [CB_N1:0] cb_xinputs_async;

assign cb_xinputs_async[0] = ag_trig_out;
assign cb_xinputs_async[1] = ag_trig_scaledown_out;
assign cb_xinputs_async[2] = ag_trig_drift_out;
assign cb_xinputs_async[3] = ag_trig_received_out;

assign cb_xinputs_async[4] = ag_cb_sw_trig;
assign cb_xinputs_async[5] = ag_cb_pulser_trig;
assign cb_xinputs_async[6] = ag_cb_esata_nim_trig;
assign cb_xinputs_async[7] = ag_cb_adc16_grand_or_trig;
assign cb_xinputs_async[8] = ag_cb_adc32_grand_or_trig;

assign cb_xinputs_async[9] = ag_cb_aw16_grand_or_trig;
assign cb_xinputs_async[10] = ag_cb_aw16_mult_1ormore;
assign cb_xinputs_async[11] = ag_cb_aw16_mult_2ormore;
assign cb_xinputs_async[12] = ag_cb_aw16_mult_3ormore;
assign cb_xinputs_async[13] = ag_cb_aw16_mult_4ormore;
assign cb_xinputs_async[14] = ag_cb_aw16_mlu_trig;

assign cb_xinputs_async[15] = ag_cb_bsc64_grand_or_trig;
assign cb_xinputs_async[16] = ag_cb_bsc64_mult_1ormore;
assign cb_xinputs_async[17] = ag_cb_bsc64_mult_2ormore;
assign cb_xinputs_async[18] = ag_cb_bsc64_mult_3ormore;
assign cb_xinputs_async[19] = ag_cb_bsc64_mult_4ormore;
assign cb_xinputs_async[20] = ag_cb_bsc64_mult_trig;

assign cb_xinputs_async[21] = ag_cb_coinc_trig;

assign cb_xinputs_async[22] = ag_cb_timeout_trig;
</pre>

= Example UDP packets =

* trigger data, marker words 0x8

<pre>
ReadDataThread read 76
0: 0x003666ed -- UDP packet counter from UDP transmitter
1: 0x80000bf8 -- 0x8 is trigger data packet, 0xbf8 is the trigger counter from alphag.v
2: 0x2edf8b41 -- trigger data
3: 0x00000bf8
4: 0x00000bf8
5: 0x00000bee
6: 0x00000001
7: 0x00000000
8: 0x00000000
9: 0x00000003
10: 0x00000bf8
11: 0x00000bf8
12: 0x00000000
13: 0x00000000
14: 0x00000000
15: 0x00000000
16: 0x00000000
17: 0x00000000
18: 0xe0000bf8 -- 0xE is end of trigger data, counter 0xbf8 must match the counter in the 0x8 word.
ReadDataThread read 76 -- next packet
0: 0x003666ee -- UDP packet counter from UDP transmitter
...
</pre>

* chronobox fifo data, marker word 0xC, see [[Chronobox#FIFO_data_format]]

<pre>
ReadDataThread read 404
0: 0x003658ed -- UDP packet counter from UDP transmitter
1: 0xc000eacc -- 0xC is FIFO data, fifo packet counter 0xeacc from fifo_to_udp.v
2: 0x00000061 -- FIFO status, low bits the the word counter, so up to 0x61 fifo words are to follow
3: 0x87fb3d72 -- tsc hits
4: 0x8ffb3d74
5: 0x90fb3d74
6: 0x91fb3d74
7: 0x92fb3d74
8: 0x93fb3d74
9: 0x93fb3d75
10: 0x94fb3d74
11: 0x94fb3d77
12: 0x87fb3d77
13: 0x8ffb3d77
14: 0x90fb3d77
15: 0x91fb3d77
16: 0x92fb3d77
17: 0xfe000018 -- 0xFE scaler data starts, 0x18 words to follow
18: 0x00000000
19: 0x00000000
20: 0x00000000
21: 0x00000000
22: 0x00000000
23: 0x00000000
24: 0x00000000
25: 0x00000108
26: 0x00000000
27: 0x00000000
28: 0x00000000
29: 0x00000000
30: 0x00000000
31: 0x00000000
32: 0x00000000
33: 0x00000108
34: 0x00000108
35: 0x00000108
36: 0x00000108
37: 0x00000108
38: 0x00000108
39: 0x00000000
40: 0x00000000
41: 0xce56fa93 -- last word of scaler data is the sysclock counter (125 MHz)
42: 0xff800048 -- timestamp wraparound
43: 0x8f1f36e4 -- tsc hits
44: 0x901f36e4
45: 0x911f36e4
46: 0x921f36e4
47: 0x931f36e4
48: 0x941f36e4
49: 0x871f36e4
50: 0x871f36e7
51: 0x8f1f36e7
52: 0x901f36e9
53: 0x911f36e7
54: 0x921f36e9
55: 0x931f36e7
56: 0x941f36e9
57: 0x904330ac
58: 0x914330ac
59: 0x924330ac
60: 0x934330ac
61: 0x934330ad
62: 0x944330ac
63: 0x944330ad
64: 0x874330ac
65: 0x874330ad
66: 0x8f4330ac
67: 0x8f4330ad
68: 0x904330ad
69: 0x914330ad
70: 0x924330ad
71: 0x8f672a62
72: 0x90672a62
73: 0x91672a62
74: 0x92672a62
75: 0x93672a62
76: 0x94672a62
77: 0x87672a62
78: 0x87672a65
79: 0x8f672a65
80: 0x90672a65
81: 0x91672a65
82: 0x92672a65
83: 0x93672a65
84: 0x94672a65
85: 0xff000049
86: 0x878b2422
87: 0x8f8b2424
88: 0x908b2424
89: 0x918b2424
90: 0x928b2424
91: 0x938b2424
92: 0x938b2425
93: 0x948b2424
94: 0x948b2427
95: 0x878b2427
96: 0x8f8b2427
97: 0x908b2427
98: 0x918b2427
99: 0x928b2427
100: 0xe000eacc -- 0xE is end of fifo data, counter 0xeacc must match the counter in the 0xC word.
ReadDataThread read 344 -- next packet
...
</pre>

= TODO =

* DONE July 2022. add FwRev to the UDP data output
* RJ45 SFP: PROBLEM, D.A. CABLE: GOOD, Fiber SFP: ???. fix "write did not happen" (send udp write command, there is no reply, read returns old data as if write never happened). suspect udp "write" packet is lost?
* PROBLEM GONE Aug 2021. fix reply to wrong socket - udp packets should reply to same socket as they came from, udp data packets should be sent to same socket as requested them, not same socket as last command.
* DONE 2021jul30. add fixes from Chris P. for the auto-negotiation and dhcp (see email from him).
* DONE flash chip connected to FPGA. Aug 2021. implement ethernet flash programmer
* DONE Aug 2021. updated maxv firmware. implement FPGA reboot
* speed up programming the MLU by writing more than 1 bit at a time
* DONE Nov 2021. add 64-bit bitmap of BSC trigger bits
* DONE. add chronobox code
* DONE. add avalon mux for alphag and chronobox packets
* DONE. add chronobox fifo to udp packet sequencer
* check that TxReadyOut is correct and it is safe to send an avalon packet while previous packet is still transmitting.
* DONE. test fiber SFP is working
* complete the UDP flash programmer (parallel flash erase and write)

= End =

//KO

TRG

2022-07-25T16:46:23Z

Olchansk: /* general format */

= TRG, the trigger control board for the ALPHA-g detector =

= Links =

* xxx
* https://bitbucket.org/expalpha/trg_firmware - firmware sources on bitbucket

= General characteristics =

== Photos ==

== Board schematics ==

* https://bitbucket.org/expalpha/trg_firmware/src/master/3xFMC_VME_Motherboard.pdf

== Available hardware ==

* Altera Stratix IV - main FPGA
* Altera Max V - boot FPGA
* boot flash: PC28F512M29EW - 512 Mbit parallel NOR flash.

= TRG front panel connections =

From top to bottom:

<pre>
|
| minisas-C - links 8-11
| minisas-D - links 12-15
|
| ethernet sfp - use copper sfp only
| minisas - not used, do not connect
| esata - clock in, trigger out
|
| minisas-A - links 0-3
| minisas-B - links 4-7
|
| LEDs
|
</pre>

MiniSAS and SATA flail cable connections:

<pre>
P1 <--> link 3
P2 <--> link 2
P3 <--> link 1
P4 <--> link 0
</pre>

LEDs:

<pre>
--PCB-- (left)
LED[0] - trigger out - ag_trig_out
LED[1] - network packet received - sfp_rx_data_valid
LED[2] - Xilinx FPGA boot ok - FMC1_CFG_DONE
LED[3] - not used
(right)
</pre>

= TRG onboard jumpers and switches =

* rotary switches: select IP address: 00=192.168.1.50, 11=.51, 22=.52, 33=.53, 44=.54, otherwire=.251

= Firmware update procedure =

* use quartus to generate the grifc.pof file (use grifc.cof)
* open quartus programmer
* attach grifc.pof to the 1st CFI_512 flash
* mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
* check that "initiate configuration after programming" is set in tools->options
* say "start"
* should take about 5 minutes
* grifc should reboot into the new firmware

If CFI_512 flash is not visible to the quartus programmer, load correct
code into the MaxV CPLD:

* open quartus programmer,
* say "auto detect"
* change file for the 5M2210 device
* use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
* say "program", it should finish in 10-15 seconds
* say "auto detect"
* CFI_512 flash should be visible now.

= Firmware revisions =

* 0x5bc8f90f - original firmware used for all data
* 0x6147c0f9 - added cbtrg, etc. installed at CERN on 20 Sep 2021.
* 0x618376ae - bigger cbtrg fifo, data rate tested up to 30 Mbytes/sec
* 0x6189c7f3 - fix loss of trigger packets. (missing fifo between alphag block and ethernet mux)
* 0x618b790b - fix loss of timestamps. (cbtrg inputs stretched to 100 ns long). installed at CERN 10 Nov 2021.
* 0x62d32d95 - updated cbtrg, switched to edge-triggered cbtrg inputs, improved BSC multiplicity trigger, improved coinc trigger, added burst pulser. installed at CERN 19 Jul 2022.

= Firmware build =

* use quartus 20.1
* see Makefile in the trg_firmware project

= Jtag remote connection =

* ssh agmini@daq16
* /opt/intelFPGA/16.1/quartus/bin/jtagd --config /home/agmini/.jtagd.conf
* netstat -an | grep 1309 ### note listen address is "0.0.0.0", NOT "127.0.0.1"
<pre>
tcp 0 0 0.0.0.0:1309 0.0.0.0:* LISTEN
</pre>
* opt/intelFPGA/16.1/quartus/bin/jtagconfig ### should work
* ssh olchansk@daq01
* cd git/trg_firmware
* /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
* jtagconfig ### should work
<pre>
daq01:trg_firmware$ jtagconfig
1) DE-SoC on daq16 [2-1.2.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) USB-Blaster on daq16 [2-1.3]
024090DD EP4SGX230(.|ES)
020A40DD 5M(1270ZF324|2210Z)/EPM2210

daq01:trg_firmware$
</pre>

= ALPHA-g trigger functions =

Trigger options:
* software trigger
* pulser trigger
* trigger on GRIF16 ADC NIM and ESATA inputs ("external trigger")
* adc16 grand-or
* adc32 grand-or
* adc16 wire multiplicity
* TPC anode wire per-preamp trigger (aw16 section)
** trigger on coincidences of preamps (removed fw 0x62c77f0b)
** trigger on multiplicity of preamps (removed fw 0x62c77f0b)
** trigger on specific topology of preamps (multiplicity of preamp clusters, etc) via the aw16_mlu trigger
* BSC trigger
** BSC grand_or
** BSC bar multiplicity
* coincidence trigger - select coincidence of external trigger, TPC AW grand-or, TPC AW MLU, BSC grand-or and BSC bar multiplicity triggers

== software trigger ==

to programmatically fire the trigger, one should:
* set the conf_enable_sw_trigger bit in conf_trig_enable, this will permit the software trigger to fire the trigger
* write value 0x4 to register 0x2B, this will cause the software trigger to fire

== pulser trigger ==

To use the pulser trigger, one should program:
* pulser period (in clocks)
* pulser width (in clocks, use value 5, the pulser no longer goes outside of the trigger board, so changing the width does not do anything)
* set the run_pulser bit in conf_trig_enable, this will cause the pulser to run
* set the enable_pulser bit in conf_trig_enable, this will cause the pulser to fire the trigger
* set the output_pulser bit in conf_trig_enable, this will cause the pulser to be output from the alphag firmware block (the pulser no longer goes outside of the trigger board, so changing the bit does not do anything)

== timeout trigger ==

The event builder uses event timestamps to assemble physics events. The timestamps
are usually 32 bit wide and run at 125 MHz (8 ns) or 62.5 MHz (16 ns). If
triggers are generated often (1 per second or more), timestamp wrap around
is easily detected by the event builder. If triggers come infrequently,
timestamp wrap around may occur while there are no triggers, not be seen
by the event builder causing loss of event synchronization.

To avoid this problem in the event builder, a timeout trigger should be generated
if no triggers were generated inside a 10 second interval.

The guaranties that even if all physics triggers temporarily stop for any reason,
the event builder will stay synchronized. (0.1 Hz timeout trigger frequency).

To enable the timeout trigger:
* program timeout trigger timeout in reg 0x43 in units of 8 ns clock
* enable it in bit 23 of [[#conf_trig_enable bits]]

== adc16 multiplicity trigger ==

This trigger is intended for use with the barrel scintillator signals connected to adc16 digitizers. It does not work well with TPC AW signals.

The 16 adc16 trigger bits (16x16=256) are added together to form the hit multiplicity value (adc16_mult, 16 bits, actual range 0 to 256).

Four threshold signals are computed: adc16_mult_1ormore = adc16_mult>=1, 2ormore, 3ormore, 4ormore.

There is a counter for each of these four signals.

Each of these four signals can fire the trigger, see [[#conf_trig_enable bits]].

== TPC anode wire triggers ==

=== aw16 bus ===

TPC Anode Wire trigger is based on the aw16[15:0] (xaw16) bus.

Each bit corresponds to one AW preamp. 16 preamps, 16 bits.

The aw16[15:0] bus can be fed by
* adc16_or16[15:0] - or16 of 100 MHz ADCs, 16 ADC sas links
* adc32_or16[15:0] - or16 of 62.5 MHz ADCs, FMC-ADC32 has 32 channels, so 2 bits per ADC: low 16 channels and high 16 channels, sas links 7..0
* adc32_or16[31:16] - or16 of 62.5 MHz ADCs, ditto, sas links 15..8
as selected by conf_enable_aw_adc16, conf_enable_aw_adc32a, conf_enable_aw_adc32b in [[#conf_control bits]]

<pre>
///////////////////////////////////////////////////////////
// TPC Anode Wire trigger logic (aw16)
///////////////////////////////////////////////////////////

// map adc signals into aw16

wire [15:0] aw16 = ({16{conf_enable_aw_adc16}} & adc16_or16[15:0]) |
({16{conf_enable_aw_adc32a}} & adc32_or16[15:0]) |
({16{conf_enable_aw_adc32b}} & adc32_or16[31:16]);
...
ag_conditioner cond_adc16_or16_0(.clk(clk), .in(aw16[0]), .out(xxaw16[0]));
...
xaw16 <= xxaw16;
</pre>

=== aw16_grand_or ===

TPC AW "grand or" trigger: use aw16_mult_1ormore (before fw 0x62c77f0b)

(256 anode wires, 16 wires per preamp, 16 preamps, 16 aw16 signals)

=== aw16_mlu ===

TPC AW preamp MLU trigger: the MLU (memory lookup
table) implements an arbitrary logical function
to map the 16 aw16 preamp signals into 1 aw16_mlu_trig trigger output.

Description of the aw16 mlu trigger.

In words:

* any aw16 signal starts the aw16_prompt_run gate
* aw16 signals are collected for the duration of conf_mlu_prompt (125MHz/8ns clock)
* this corresponds to time spread of TPC AW signals due to the drift time in the AW drift cell and to the variation in signal transmission time from the ADC to the TRG (digital trigger data link).
* when this prompt time expires, the MLU looks at the accumulated aw16_prompt bit pattern and makes the "yes/no" trigger decision
* after the trigger decision is made, we wait for the TPC to become quiet:
* we wait until all aw16 signals are empty (no timeout)
* we run the aw16_prompt_wait gate, length conf_mlu_wait (8ns clock), if any aw16 signals arrive, we wait for aw16 empty again, rinse, repeat.
* now, after TPC aw16 have been empty for conf_mlu_wait clocks (8ns clock), MLU trigger is ready for the next event.

In logic: (see alphag.v)

* aw16_or <= grand-or of 16 aw16 signals
* "aw16_or" starts the "aw16_prompt_cnt" counter, opens the aw16_prompt_run gate
* during the aw16_prompt_run gate, aw16_prompt collects (latches) the aw16 bits (aw16_prompt <= aw16_prompt | aw16)
* this is the time when we wait for all "prompt" signals from the TPC to arrive into the trigger
* at the end of the aw16_prompt_run gate, the signal aw16_prompt_out is pulsed, latching the output of the MLU into aw16_mlu_trig
* this is the MLU trigger "yes/no" trigger decision.
* after the MLU trigger decision is made, we wait for the arrival and passing of all TPC drift signals
* the aw16_prompt_wait_cnt and aw_prompt_wait gate opens
* if any new aw16 signals arrive (they are TPC drift signals at this time), the aw16_prompt_wait gate is restarted
* if no aw16 signals arrive during the full run of the aw16_prompt_wait gate ("TPC quiet time")
* the aw16_prompt_wait and aw16_prompt gates are cleared and the MLU trigger is ready for the next event.

Good settings are:
* conf_mlu_prompt: 64 (512 ns)
* conf_mlu_wait: 128 (1024 ns)

== BSC trigger ==

=== bsc_adc16 bus ===

The BSC trigger is based on the [15:0]bsc_adc16[7:0] bus: 16 trigger discriminator bits from 8 ADC sas links. (8*16 = 64+64 bars, top and bottom).

The bsc_adc16 bus can be fed from sas links 0..7 or 8..15, controlled by conf_bsc_adc16_a and conf_bsc_adc16_b bits on [[#conf_bsc_control bits]].

bsc_adc16 can be fed only from GRIF-16 100 MHz ADC trigger discriminators.

=== bsc64_top and bsc64_bot buses ===

* firmware 0x5bc8f90f: bsc_adc16 is remapped into 64 bits of top (bsc64_top) and bottom (bsc64_bot):
<pre>
ag_bsc_remap bsc_remap_a(.adc(bsc_adc16[0]), .bsc_bot(bsc64_bot[7:0]), .bsc_top(bsc64_top[7:0]));
ag_bsc_remap bsc_remap_b(.adc(bsc_adc16[1]), .bsc_bot(bsc64_bot[8+7:8+0]), .bsc_top(bsc64_top[8+7:8+0]));
ag_bsc_remap bsc_remap_c(.adc(bsc_adc16[2]), .bsc_bot(bsc64_bot[2*8+7:2*8+0]), .bsc_top(bsc64_top[2*8+7:2*8+0]));
ag_bsc_remap bsc_remap_d(.adc(bsc_adc16[3]), .bsc_bot(bsc64_bot[3*8+7:3*8+0]), .bsc_top(bsc64_top[3*8+7:3*8+0]));

ag_bsc_remap bsc_remap_e(.adc(bsc_adc16[4]), .bsc_bot(bsc64_bot[4*8+7:4*8+0]), .bsc_top(bsc64_top[4*8+7:4*8+0]));
ag_bsc_remap bsc_remap_f(.adc(bsc_adc16[5]), .bsc_bot(bsc64_bot[5*8+7:5*8+0]), .bsc_top(bsc64_top[5*8+7:5*8+0]));
ag_bsc_remap bsc_remap_g(.adc(bsc_adc16[6]), .bsc_bot(bsc64_bot[6*8+7:6*8+0]), .bsc_top(bsc64_top[6*8+7:6*8+0]));
ag_bsc_remap bsc_remap_h(.adc(bsc_adc16[7]), .bsc_bot(bsc64_bot[7*8+7:7*8+0]), .bsc_top(bsc64_top[7*8+7:7*8+0]));

module ag_bsc_remap
(
input wire [15:0] adc,
output wire [7:0] bsc_bot,
output wire [7:0] bsc_top
);

assign bsc_top[3] = adc[0];
assign bsc_top[2] = adc[1];
assign bsc_top[1] = adc[2];
assign bsc_top[0] = adc[3];

assign bsc_top[7] = adc[4];
assign bsc_top[6] = adc[5];
assign bsc_top[5] = adc[6];
assign bsc_top[4] = adc[7];

assign bsc_bot[0] = adc[8];
assign bsc_bot[1] = adc[9];
assign bsc_bot[2] = adc[10];
assign bsc_bot[3] = adc[11];

assign bsc_bot[4] = adc[12];
assign bsc_bot[5] = adc[13];
assign bsc_bot[6] = adc[14];
assign bsc_bot[7] = adc[15];

endmodule
</pre>

=== bsc64 bus ===

the bsc64 bus is the 64 bars used by the trigger, formed from bsc64_top and bsc64_bot:
<pre>
if (conf_bsc64_bot_only) begin
bsc64 <= bsc64_bot;
end else if (conf_bsc64_top_only) begin
bsc64 <= bsc64_top;
end else if (conf_bsc64_bot_top_or) begin
bsc64 <= bsc64_bot | bsc64_top;
end else if (conf_bsc64_bot_top_and) begin
bsc64 <= bsc64_bot & bsc64_top;
end else begin
bsc64 <= 64'b0;
end
</pre>

=== bsc_grand_or_trig ===

bsc_grand_or_trig is the grand-or of 64 bits of the bsc64 bus

to enable triggering on bsc_grand_or_trig, set corresponding bit in [[#conf_trig_enable bits]]

=== old bsc_mult_trig ===

(from fw 0x62c77f0b, old bsc_mult_trig was replaced by new bsc64 multiplicity trigger)

* bsc64_mult is computed as multiplicity of the bsc64 bus (number of 64 bsc64 bits that fired)
* bsc_mult_trig is computed:
<pre>
if (bsc64_mult >= conf_bsc64_mult) begin
bsc_mult_trig <= 1;
end else begin
bsc_mult_trig <= 0;
end
</pre>

to enable the bsc multiplicity trigger, set the multiplicity value conf_bsc64_mult in [[#conf_bsc_control bits]] and enable the corresponding bit in [[#conf_trig_enable bits]].

=== bsc64 multiplicity trigger ===

bsc64 BSC bar multiplicity trigger uses a time window. this time window is started by bsc64_grand_or and runs for conf_bsc64_mult_window clocks (8 nc clock). During this time, hits in bsc64_bus are accumulated (latched) and their multiplicity is computed. If multiplicity condition is satisfied (bigger or equal to conf_bsc64_mult_min), bsc64_mult_trig is fired and the bsc64 bit pattern is saved to the UDP packet. Then trigger waits for the bsc64_bus to be empty. Then trigger waits for conf_bsc64_empty_window clocks, if there is any bsc64 hits, we wait for empty again. So after bsc64 has been empty for conf_bsc64_empty_window clocks, multiplicity trigger is ready for the next event. This scheme cannot implement max multiplicity.

recommended values:
* conf_bsc64_mult_window (8 bits): slightly longer than 3 cycles of SAS link: 3*18 = 54 clocks, good value is 80 (640 ns).
* conf_bsc64_mult_min (8 bits): 2
* conf_bsc64_empty_window (8 bits): 80 (640 ns)

== Coincidence trigger ==

Coincidence trigger provides a combination of TPC, BSC and external scintillator (esata_nim_grand_or) signals:

<pre>
assign coinc_input[0] = aw16_grand_or; // was aw16_mult_1ormore;
assign coinc_input[1] = aw16_mlu_trig;
assign coinc_input[2] = bsc_grand_or_trig;
assign coinc_input[3] = bsc_mult_trig;
assign coinc_input[4] = esata_nim_grand_or;
assign coinc_input[5] = 0;
assign coinc_input[6] = 0;
assign coinc_input[7] = 0;
</pre>

Coincidence trigger "start" mask selects which of the inputs can start the coincidence window.

Coincidence trigger "require" mask selects which inputs must have a hits for the coincidence to be satisfied.

Input hits are collected for the duration of the coincidence window, if all required inputs have hits, coinc_trig is fired.

Example settings:

* coincidence of external scintillator, BSC and TPC AW "grand or" signals: start 0x10, required 0x15
* coincidence of BSC grand-or and TPC AW grand-or signals: start 0x5, required 0x5
* coincidence of BSC multiplicity and TPC AW grand-or triggers: start 0x9, required 0x9

= Control registers =

== Register addresses ==

Note: all registers are 32 bits unless otherwise noted.

Note: RW means read-write register, RO means read-only, ROL means read-only, contents is latched by the "latch_out" bit

{| cellpadding="10" cellspacing="0" border="1"
! Address || Quartus Name || Access || FwRev || Description
|-
| 0x08 || num_sample || RW || GRIF-C || magic 16-bit register to control UDP packet size
|-
| 0x08 || scratch_reg || RW || 0x618b790b || 32-bit scratch register
|-
| 0x1F || compilation_time || RO || || Firmware revision
|-
| 0x20 || conf_trig_width || RW || || Trigger signal width, 16 ns clock
|-
| 0x21 || conf_busy_width || RW || || Busy signal width, 16 ns clock (not used)
|-
| 0x22 || conf_pulser_width || RW || || Pulser signal width, 16 ns clock
|-
| 0x23 || conf_pulser_period || RW || || Pulser signal period, 16 ns clock
|-
| 0x24 || conf_pulser_burst_ctrl || RW || 0x62d1c47e || Generate bursts of pulses: 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses, 16 ns clocks
|-
| 0x25 || conf_trig_enable || RW || || see [[#conf_trig_enable bits]]
|-
| 0x26 || || || not used
|-
| 0x27 || || || not used
|-
| 0x28 || || || not used
|-
| 0x29 || conf_nim_mask || RW || || enable bits for ADC NIM inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2A || conf_esata_mask || RW || || enable bits for ADC eSATA inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2B || reset_out, latch_out, trigger_out || W || || see [[#reg 0x2B bits]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x5bc8f90f || configure AW coincidence trigger, see [[#aw16_coinc]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x62c77f0b || removed
|-
| 0x2D || conf_aw16_coinc_b || RW || 0x5bc8f90f ||
|-
| 0x2E || conf_aw16_coinc_c || RW || 0x5bc8f90f ||
|-
| 0x2F || conf_aw16_coinc_d || RW || 0x5bc8f90f ||
|-
| 0x30 || sas_sd[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect for each link
|-
| 0x31 || pll_625_status || ROL || 0x5b2057f5 (12Jun18_16:32) || 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter
|-
| 0x32 || clk_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the system 125 MHz clock
|-
| 0x33 || clk_625_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625)
|-
| 0x34 || conf_control || RW || 0x5b398983 (01Jul18_19:10) || see [[#conf_control bits]] below
|-
| 0x35 || conf_drift_width || RW || 0x5b398983 (01Jul18_19:10) || width of drift time blank-out in 16 ns clocks
|-
| 0x36 || conf_scaledown || RW || 0x5b398983 (01Jul18_19:10) || trigger scaledown, 0=no scaledown, 1=divide-by-2, 2=divide-by-3, etc
|-
| 0x37 || conf_mlu || RW || 0x5b398983 (01Jul18_19:10) || AW MLU control bits, see [[#conf_mlu bits]]
|-
| 0x38 || conf_trig_delay || RW || 0x5baedfca (28Sep18_19:13) || delay the trigger pulse, 16 ns clock
|-
| 0x39 || esata_clk_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the TRG 125 MHz clock
|-
| 0x3A || esata_clk_esata_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the external clock (eSATA 62.5 MHz clock)
|-
| 0x3B || conf_counter_adc_select || RW || 0x5bb7f6ae (05Oct18_16:41) || select which 16 ADCs are connected to the selected adc counters, 0..15 - connect the adc16 signals, 16..47 connect the adc32 signals
|-
| 0x3C || sysreset_ts || RO || 0x5bb7f6ae (05Oct18_16:41) || 125MHz counter of VME-SYSRESET
|-
| 0x3C || || || 0x618b790b || not used
|-
| 0x3D || GRIF-C csr || RW || GRIF-C || <= csr & ~par_value; // Selective clear
|-
| 0x3E || GRIF-C csr || RW || GRIF-C || <= csr | par_value; // Selective set
|-
| 0x3F || GRIF-C csr || RW || GRIF-C || <= par_value; // write
|-
| 0x3D || || || 0x618b790b || not used
|-
| 0x3E || || || 0x618b790b || not used
|-
| 0x3F || || || 0x618b790b || not used
|-
| 0x40 || conf_bsc_control || RW || 0x5bc13541 (12Oct18_16:58) || Barrel Scintillator trigger control, see [[#conf_bsc_control bits]]
|-
| 0x41 || conf_coinc_control || RW || 0x5bc13541 (12Oct18_16:58) || Coincidence trigger control, see [[#conf_coinc_control bits]]
|-
| 0x42 || reconfig_out || WO || 0x5bc13541 (12Oct18_16:58) || reserved for rebooting the FPGA (does not work)
|-
| 0x43 || conf_trigger_timeout || RW || 0x5bc8f90f (18Oct18_14:20) || Generate timeout trigger if there is no other trigger after given timeout, in 8 ns clocks, must be enabled by bit conf_enable_timeout_trig in [[#conf_trig_enable bits]]
|-
| 0x44 || eth_clk_counter || ROL || 0x618b790b ||
|-
| 0x45 || eth_clk_eth_counter || ROL || 0x618b790b ||
|-
| 0x100 || ts_625 || ROL || || latched timestamp
|-
| 0x101 || counter_trig_out || ROL || || counter of issued triggers
|-
| 0x102 || counter_trig_in || ROL || || counter of triggers
|-
| 0x103 || counter_pulser || ROL || || counter of pulser
|-
| 0x104 || counter_adc16_grand_or || ROL ||
|-
| 0x105 || counter_adc32_grand_or || ROL ||
|-
| 0x106 || counter_adc_grand_or || ROL ||
|-
| 0x107 || counter_esata_nim_grand_or || ROL ||
|-
| 0x108 || counter_adc16_mult_1ormore || ROL ||
|-
| 0x109 || counter_adc16_mult_2ormore || ROL ||
|-
| 0x10A || counter_adc16_mult_3ormore || ROL ||
|-
| 0x10B || counter_adc16_mult_4ormore || ROL ||
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x5bc8f90f || counter of AW coincidence triggers
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x62c77f0b || removed
|-
| 0x10D || counter_aw16_coinc_b || ROL || 0x5bc8f90f ||
|-
| 0x10E || counter_aw16_coinc_c || ROL || 0x5bc8f90f ||
|-
| 0x10F || counter_aw16_coinc_d || ROL || 0x5bc8f90f ||
|-
| 0x110 || counter_drift || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the drift time blank-out
|-
| 0x111 || counter_scaledown || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the scaledown
|-
| 0x112 || counter_aw16_coinc || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW coincidence triggers
|-
| 0x113 || counter_aw16_mlu || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW MLU triggers
|-
| 0x114 || counter_aw16_grand_or || ROL || 0x62c77f0b || counter of AW grand-or triggers
|-
| 0x114 || counter_aw16_mult_1ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 1ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 2ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x62c77f0b || removed
|-
| 0x116 || counter_aw16_mult_3ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 3ormore triggers
|-
| 0x117 || counter_aw16_mult_4ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 4ormore triggers
|-
| 0x118 || counter_bsc_grand_or || ROL || 0x5bc13541 (12Oct18_16:58) || counter of BSC grand-or triggers
|-
| 0x119 || counter_bsc_mult || ROL || 0x5bc13541 (12Oct18_16:58) || counter of old BSC multiplicity triggers
|-
| 0x11A || counter_coinc || ROL || 0x5bc13541 (12Oct18_16:58) || counter of coincidence triggers
|-
| 0x11B || counter_timeout || ROL || 0x618b790b || counter of timeout triggers
|-
| 0x11C || counter_bsc_mult_start || ROL || 0x62c77f0b || counter of BSC multiplicity windows
|-
| 0x11D || counter_bsc_mult_trig || ROL || 0x62c77f0b || counter of BSC multiplicity triggers
|-
| 0x11E || counter_coinc_start || ROL || 0x62d1b152 || counter of coincidence windows
|-
| 0x11F || counter_aw16_mlu_start || ROL || 0x62d1b152 || counter of TPC AW MLU windows
|-
| 0x200..0x207 || conf_adc16_masks || RW || all || adc16 enable bits
|-
| 0x300..0x30F || conf_adc32_masks || RW || all || adc32 enable bits
|-
| 0x400..0x41F || sas_bits[15:0][63:0] || ROL || all || sas data bits for each link
|-
| 0x420..0x42F || sas_sd_counters[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect counter for each link
|-
| 0x430..0x43F || counters_adc16_or16[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 16 counters of adc16 ORes
|-
| 0x440..0x45F || counters_adc32_or16[31:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 32 counters of adc32 ORes
|-
| 0x460..0x46F || counters_adc_selected[15:0] || ROL || 0x5bb7f6ae (05Oct18_16:41) || 16 counters for selected group of adcs, see conf_counter_adc_select
|-
| 0x470..0x4AF || counters_bsc64[63:0] || ROL || 0x5bc13541 (12Oct18_16:58) || 64 counters for the BSC bars
|-
|}

== additional registers ==

<pre>
reg | rw/ro/rol | quartus name | firmware | description
-----------------------------------------------------------------
0x60 | rw | cb_control_out | 0x618b790b | chronobox control
0x61 | rw | cb_status | 0x618b790b | chronobox status
0x62 | rw | cb_invert_a_out | 0x618b790b | chronobox input invert
0x63 | rw | cb_invert_b_out | 0x618b790b |
0x64 | rw | cb_enable_le_a_out | 0x618b790b | timestamp enable leading edge
0x65 | rw | cb_enable_le_b_out | 0x618b790b |
0x66 | rw | cb_enable_te_a_out | 0x618b790b | timestamp enable traiing edge
0x67 | rw | cb_enable_te_b_out | 0x618b790b |
0x6A | ro | cb_input_num | 0x618b790b | chronobox number of inputs
0x6B | rw | cb_sync_mask_a_out | 0x618b790b | chronobox sync signal source
0x6C | rw | cb_sync_mask_b_out | 0x618b790b |
0x6D | rw | cb_sync_reg_out | 0x618b790b | chronobox sync register
0x6E | ro | cb_sync_status | 0x618b790b | chronobox sync status
0x6F | rw | cb_latch_period_out | 0x618b790b | chronobox scalers latch period
0x70 | ro | cb_fifo_status | 0x618b790b | chronobox data fifo status
0x71 | ro | cb_fifo_data | 0x618b790b | read chronobox data fifo (cb_fifo_rdack_out <= 1)
0x72 | rw | cb_udp_period_out | 0x618b790b | period for flushing fifo to UDP
0x73 | rw | cb_udp_threshold_out | 0x618b790b | byte threshold for flushing fifo to UDP
</pre>

== conf_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_clock_select || 0x5b3aa19f (02Jul18_15:05) || select 0=internal 62.5 MHz clock or 1=esata 62.5 MHz clock
|-
| 1 || conf_enable_aw_adc16 || 0x5baedfca (28Sep18_19:13) || select source of TPC AW aw16 bus, see [[#aw16 bus]]
|-
| 2 || conf_enable_aw_adc32a || 0x5baedfca (28Sep18_19:13) ||
|-
| 3 || conf_enable_aw_adc32b || 0x5baedfca (28Sep18_19:13) ||
|-
| 15..4 || || ||
|-
| 23..16 || conf_mlu_prompt || 0x5b3aa19f (02Jul18_15:05) || MLU trigger prompt window, see [[#aw16_mlu]]
|-
| 31..24 || conf_mlu_wait || 0x5b3aa19f (02Jul18_15:05) || MLU trigger wait window, see [[#aw16_mlu]]
|-
|}

== conf_mlu bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 31 || mlu_reset || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 30 || mlu_write || 0x5b3aa19f (02Jul18_15:05) || 1=write data bit into given address
|-
| 16 || mlu_data || 0x5b3aa19f (02Jul18_15:05) || data bit for writing to MLU RAM
|-
| 15..0 || mlu_write_addr || 0x5b3aa19f (02Jul18_15:05) || MLU RAM write address for writing the data bit
|-
|}

== conf_bsc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_bsc_adc_a || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 0..7
|-
| 1 || conf_bsc_adc_b || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 8..15
|-
| 2 || conf_bsc64_bot_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses bottom channels only
|-
| 3 || conf_bsc64_top_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses top channels only
|-
| 4 || conf_bsc64_bot_top_or || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "or" of top and bottom
|-
| 5 || conf_bsc64_bot_top_and || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "and" of top and bottom
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_bsc64_mult_min || 0x5bc13541 (12Oct18_16:58) || minimum bsc64 multiplicity
|-
| 23..16 || conf_bsc64_empty_wondow || 0x62d1c47e || bsc64 empty window length, 8 ns clocks
|-
| 31..24 || conf_bsc64_mult_window || 0x62c77f0b || bsc64 multiplicity window length, 8 ns clocks
|-
|}

== conf_coinc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_coinc_required[0] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mult_1ormore
|-
| 0 || conf_coinc_required[0] || 0x62c77f0b || enable aw16_grand_or
|-
| 1 || conf_coinc_required[1] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mlu_trig
|-
| 2 || conf_coinc_required[2] || 0x5bc13541 (12Oct18_16:58) || enable bsc_grand_or_trig
|-
| 3 || conf_coinc_required[3] || 0x5bc13541 (12Oct18_16:58) || enable bsc_mult_trig
|-
| 3 || conf_coinc_required[3] || 0x62c77f0b || enable bsc64_mult_trig
|-
| 4 || conf_coinc_required[4] || 0x5bc13541 (12Oct18_16:58) || enable esata_nim_grand_or
|-
| 5 || conf_coinc_required[5]
|-
| 6 || conf_coinc_required[6]
|-
| 7 || conf_coinc_required[7]
|-
| 15..8 || conf_coinc_window[7:0] || 0x5bc13541 (12Oct18_16:58) || coincidence window length in units of 125MHz clock (8 ns)
|-
| 23..16 || conf_coinc_start[7:0] || 0x5bc13541 (12Oct18_16:58) || start the coincidence window, same bits as "required"
|-
| 31..24 ||
|-
|}

== conf_trig_enable bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_enable_sw_trigger || || trigger on software trigger (how generated???)
|-
| 1 || conf_enable_pulser || || trigger on pulser
|-
| 2 || - || 0x5b120c9f (01Jun18_20:18) || not used
|-
| 3 || conf_pulser_run || || allow the pulser to run (frequency has to be set beforehand)
|-
| 4 || conf_output_pulser || 0x5bc8f90f || does nothing (top level ag_pulser_out is disconnected)
|-
| 4 || || 0x618b790b || not used
|-
| 5 || conf_enable_esata_nim || || trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand)
|-
| 6 || conf_enable_adc16 || || trigger on adc16_grand_or
|-
| 7 || conf_enable_adc32 || || trigger on adc32_grand_or
|-
| 8 || conf_enable_adc16_1ormore || || trigger on adc16_mult_1ormore "1 or more"
|-
| 9 || conf_enable_adc16_2ormore || || same, "2 or more"
|-
| 10 || conf_enable_adc16_3ormore || || same, "3 or more"
|-
| 11 || conf_enable_adc16_4ormore || || same, "4 or more"
|-
| 12 || - || 0x5b08938c (25May18_15:51) || not used
|-
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
|-
| 14 || - || 0x5bc8f90f || not used
|-
| 15 || conf_enable_adc || 0x5b120c9f (01Jun18_20:18) || trigger on adc_grand_or
|-
| 16 || conf_enable_aw16_coinc_a || 0x5bc8f90f || enable AW coincidence trigger, see [[#aw16_coinc]]
|-
| 16 || - || 0x62c77f0b || aw16_coinc_x removed
|-
| 17 || conf_enable_aw16_coinc_b || 0x5bc8f90f ||
|-
| 18 || conf_enable_aw16_coinc_c || 0x5bc8f90f ||
|-
| 19 || conf_enable_aw16_coinc_d || 0x5bc8f90f ||
|-
| 20 || - || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 20 || conf_enable_aw16_grand_or || 0x618b790b || enable trigger on aw16_grand_or
|-
| 21 || conf_enable_aw16_coinc || 0x5b3aa19f (02Jul18_15:05) || enable trigger on aw16_coinc_trig
|-
| 22 || conf_enable_aw16_mlu || 0x5b3aa19f (02Jul18_15:05) || enable AW MLU trigger
|-
| 23 || conf_enable_timeout_trig || 0x5bc8f90f (18Oct18_14:20) || enable trigger timeout trigger
|-
| 24 || conf_enable_aw16_1ormore || 0x5b3aa19f (02Jul18_15:05) || trigger on aw16_mult_1ormore "1 or more"
|-
| 24 || - || 0x62c77f0b || aw16_mult_xxx removed
|-
| 25 || conf_enable_aw16_2ormore || 0x5b3aa19f (02Jul18_15:05) || same, "2 or more"
|-
| 26 || conf_enable_aw16_3ormore || 0x5b3aa19f (02Jul18_15:05) || same, "3 or more"
|-
| 27 || conf_enable_aw16_4ormore || 0x5b3aa19f (02Jul18_15:05) || same, "4 or more"
|-
| 28 || conf_enable_bsc_grand_or || 0x5bc13541 (12Oct18_16:58) || trigger on BSC grand-or
|-
| 29 || conf_enable_bsc_mult || 0x5bc13541 (12Oct18_16:58) || trigger on BSC multiplicity
|-
| 30 || conf_enable_coinc || 0x5bc13541 (12Oct18_16:58) || trigger on TPC/BSC/ext coincidence trigger
|-
| 31 || - || || not used
|-
|}

== reg 0x2B bits ==

Write to this register will pulse corresponding fpga signals:

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || reset_out || 0x5b120c9f (01Jun18_20:18) || reset counters, etc
|-
| 1 || latch_out || 0x5b120c9f (01Jun18_20:18) || latch counters, sas bits, etc
|-
| 2 || trigger_out || 0x5b120c9f (01Jun18_20:18) || generate a software trigger
|-
|}

= UDP data format =

== general format ==

<pre>
trigger packet:

[0] udp packet counter
[1] 0x8ccccccc
...
[N] 0xEccccccc

chronobox fifo packet:

[0] udp packet counter
[1] 0xCccccccc
[2] fifo status
[3] fifo data
...
[N] 0xEccccccc

chronobox fifo packet:

[0] udp packet counter
[1] 0xDccccccc
[2] 0xDEADBEEF
[3] fifo status
[4] fifo data
...
[N] 0xEccccccc
</pre>

== firmware 0x5bc8f90f ==

{| cellpadding="10" cellspacing="0" border="1"
! Offset || Name || Quartus name || FwRev || Description
|-
| 0 || packet counter || none || all || 31-bit UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
|-
| 1 || 0x8 packet header || || all || 28 bits of counter_trig_out
|-
| 2 || trigger timestamp || trig_ts || all || 62.5MHz trigger timestamp
|-
| 3 || accepted triggers || counter_trig_out || all || counter of accepted triggers
|-
| 4 || input triggers || counter_trig_in || all || counter of trigger input
|-
| 5 || pulser triggers || counter_pulser || all || counter of pulser triggers
|-
| 6 || trigger bitmap || udp_trig_bits || 0x5a48448d (30Dec17_17:59) || bitmap of trigger information, see below
|-
| 7 || nim bits || udp_nim_bits_masked || ??? || 32 bits of ADC NIM inputs (2 bits per ADC)
|-
| 8 || esata bits || udp_esata_bits_masked || ??? || 32 bits of ADC ESATA inputs (2 bits per ADC)
|-
| 9 || mlu bits || aw16_prompt || 0x5b398983 (01Jul18_19:10) || 16 bits of MLU input, 1 bit per preamp
|-
| 10 || drift-blank-off counter || udp_drift_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the drift blank-off
|-
| 11 || scaledown counter || udp_scaledown_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the scaledown
|-
| X || || || ||
|-
| 12 || 0xE packet footer || || all || 28 bits of counter_trig_out
|-
|}

== firmware 0x618b790b (Nov 2021) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

== firmware 0x62d1c47e (Jul 2022) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, 8'h00, 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= conf_fw_rev;
18 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

Values of udp_coinc_latch[7:0]:
* aaa

Values of udp_aw16_mult[7:0] and udp_aw16_bus[15:0]:
* aaa

Values of udp_bsc64_mult[7:0] and udp_bsc64_bus[63:0]
* aaa

== trigger bitmap ==

Firmware ??? (one of the very early revisions)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= adc16_coinc_top;
udp_trig_bits[5] <= adc16_coinc_bot;
udp_trig_bits[6] <= adc16_coinc;
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
udp_trig_bits[31:24] <= mult16[7:0];

</pre>

Firmware 0x5b08938c (25May18_15:51)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= 0; // not used
udp_trig_bits[31:24] <= mult16[7:0];
</pre>

Firmware 0x5b217dc4 (13Jun18_13:25)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5b3aa19f (02Jul18_15:05)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= udp_mlu_out;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5bc8f90f (18Oct18_14:20)

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_run_pulser
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = 0; // not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x618b790b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x62c77f0b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = 0; // aw16_coinc_a;
assign trig32_in[17] = 0; // aw16_coinc_b;
assign trig32_in[18] = 0; // aw16_coinc_c;
assign trig32_in[19] = 0; // aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = 0; // aw16_mult_1ormore;
assign trig32_in[25] = 0; // aw16_mult_2ormore;
assign trig32_in[26] = 0; // aw16_mult_3ormore;
assign trig32_in[27] = 0; // aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc64_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

= TRG chronobox inputs =

from trg_firmware/toplevel/grifc.v

<pre>
localparam CB_N = 23;
localparam CB_N1 = CB_N-1;

wire [CB_N1:0] cb_xinputs_async;

assign cb_xinputs_async[0] = ag_trig_out;
assign cb_xinputs_async[1] = ag_trig_scaledown_out;
assign cb_xinputs_async[2] = ag_trig_drift_out;
assign cb_xinputs_async[3] = ag_trig_received_out;

assign cb_xinputs_async[4] = ag_cb_sw_trig;
assign cb_xinputs_async[5] = ag_cb_pulser_trig;
assign cb_xinputs_async[6] = ag_cb_esata_nim_trig;
assign cb_xinputs_async[7] = ag_cb_adc16_grand_or_trig;
assign cb_xinputs_async[8] = ag_cb_adc32_grand_or_trig;

assign cb_xinputs_async[9] = ag_cb_aw16_grand_or_trig;
assign cb_xinputs_async[10] = ag_cb_aw16_mult_1ormore;
assign cb_xinputs_async[11] = ag_cb_aw16_mult_2ormore;
assign cb_xinputs_async[12] = ag_cb_aw16_mult_3ormore;
assign cb_xinputs_async[13] = ag_cb_aw16_mult_4ormore;
assign cb_xinputs_async[14] = ag_cb_aw16_mlu_trig;

assign cb_xinputs_async[15] = ag_cb_bsc64_grand_or_trig;
assign cb_xinputs_async[16] = ag_cb_bsc64_mult_1ormore;
assign cb_xinputs_async[17] = ag_cb_bsc64_mult_2ormore;
assign cb_xinputs_async[18] = ag_cb_bsc64_mult_3ormore;
assign cb_xinputs_async[19] = ag_cb_bsc64_mult_4ormore;
assign cb_xinputs_async[20] = ag_cb_bsc64_mult_trig;

assign cb_xinputs_async[21] = ag_cb_coinc_trig;

assign cb_xinputs_async[22] = ag_cb_timeout_trig;
</pre>

= Example UDP packets =

* trigger data, marker words 0x8

<pre>
ReadDataThread read 76
0: 0x003666ed -- UDP packet counter from UDP transmitter
1: 0x80000bf8 -- 0x8 is trigger data packet, 0xbf8 is the trigger counter from alphag.v
2: 0x2edf8b41 -- trigger data
3: 0x00000bf8
4: 0x00000bf8
5: 0x00000bee
6: 0x00000001
7: 0x00000000
8: 0x00000000
9: 0x00000003
10: 0x00000bf8
11: 0x00000bf8
12: 0x00000000
13: 0x00000000
14: 0x00000000
15: 0x00000000
16: 0x00000000
17: 0x00000000
18: 0xe0000bf8 -- 0xE is end of trigger data, counter 0xbf8 must match the counter in the 0x8 word.
ReadDataThread read 76 -- next packet
0: 0x003666ee -- UDP packet counter from UDP transmitter
...
</pre>

* chronobox fifo data, marker word 0xC, see [[Chronobox#FIFO_data_format]]

<pre>
ReadDataThread read 404
0: 0x003658ed -- UDP packet counter from UDP transmitter
1: 0xc000eacc -- 0xC is FIFO data, fifo packet counter 0xeacc from fifo_to_udp.v
2: 0x00000061 -- FIFO status, low bits the the word counter, so up to 0x61 fifo words are to follow
3: 0x87fb3d72 -- tsc hits
4: 0x8ffb3d74
5: 0x90fb3d74
6: 0x91fb3d74
7: 0x92fb3d74
8: 0x93fb3d74
9: 0x93fb3d75
10: 0x94fb3d74
11: 0x94fb3d77
12: 0x87fb3d77
13: 0x8ffb3d77
14: 0x90fb3d77
15: 0x91fb3d77
16: 0x92fb3d77
17: 0xfe000018 -- 0xFE scaler data starts, 0x18 words to follow
18: 0x00000000
19: 0x00000000
20: 0x00000000
21: 0x00000000
22: 0x00000000
23: 0x00000000
24: 0x00000000
25: 0x00000108
26: 0x00000000
27: 0x00000000
28: 0x00000000
29: 0x00000000
30: 0x00000000
31: 0x00000000
32: 0x00000000
33: 0x00000108
34: 0x00000108
35: 0x00000108
36: 0x00000108
37: 0x00000108
38: 0x00000108
39: 0x00000000
40: 0x00000000
41: 0xce56fa93 -- last word of scaler data is the sysclock counter (125 MHz)
42: 0xff800048 -- timestamp wraparound
43: 0x8f1f36e4 -- tsc hits
44: 0x901f36e4
45: 0x911f36e4
46: 0x921f36e4
47: 0x931f36e4
48: 0x941f36e4
49: 0x871f36e4
50: 0x871f36e7
51: 0x8f1f36e7
52: 0x901f36e9
53: 0x911f36e7
54: 0x921f36e9
55: 0x931f36e7
56: 0x941f36e9
57: 0x904330ac
58: 0x914330ac
59: 0x924330ac
60: 0x934330ac
61: 0x934330ad
62: 0x944330ac
63: 0x944330ad
64: 0x874330ac
65: 0x874330ad
66: 0x8f4330ac
67: 0x8f4330ad
68: 0x904330ad
69: 0x914330ad
70: 0x924330ad
71: 0x8f672a62
72: 0x90672a62
73: 0x91672a62
74: 0x92672a62
75: 0x93672a62
76: 0x94672a62
77: 0x87672a62
78: 0x87672a65
79: 0x8f672a65
80: 0x90672a65
81: 0x91672a65
82: 0x92672a65
83: 0x93672a65
84: 0x94672a65
85: 0xff000049
86: 0x878b2422
87: 0x8f8b2424
88: 0x908b2424
89: 0x918b2424
90: 0x928b2424
91: 0x938b2424
92: 0x938b2425
93: 0x948b2424
94: 0x948b2427
95: 0x878b2427
96: 0x8f8b2427
97: 0x908b2427
98: 0x918b2427
99: 0x928b2427
100: 0xe000eacc -- 0xE is end of fifo data, counter 0xeacc must match the counter in the 0xC word.
ReadDataThread read 344 -- next packet
...
</pre>

= TODO =

* DONE July 2022. add FwRev to the UDP data output
* RJ45 SFP: PROBLEM, D.A. CABLE: GOOD, Fiber SFP: ???. fix "write did not happen" (send udp write command, there is no reply, read returns old data as if write never happened). suspect udp "write" packet is lost?
* PROBLEM GONE Aug 2021. fix reply to wrong socket - udp packets should reply to same socket as they came from, udp data packets should be sent to same socket as requested them, not same socket as last command.
* DONE 2021jul30. add fixes from Chris P. for the auto-negotiation and dhcp (see email from him).
* DONE flash chip connected to FPGA. Aug 2021. implement ethernet flash programmer
* DONE Aug 2021. updated maxv firmware. implement FPGA reboot
* speed up programming the MLU by writing more than 1 bit at a time
* DONE Nov 2021. add 64-bit bitmap of BSC trigger bits
* DONE. add chronobox code
* DONE. add avalon mux for alphag and chronobox packets
* DONE. add chronobox fifo to udp packet sequencer
* check that TxReadyOut is correct and it is safe to send an avalon packet while previous packet is still transmitting.
* DONE. test fiber SFP is working
* complete the UDP flash programmer (parallel flash erase and write)

= End =

//KO

TRG

2022-07-25T16:42:53Z

Olchansk: /* UDP data format */

= TRG, the trigger control board for the ALPHA-g detector =

= Links =

* xxx
* https://bitbucket.org/expalpha/trg_firmware - firmware sources on bitbucket

= General characteristics =

== Photos ==

== Board schematics ==

* https://bitbucket.org/expalpha/trg_firmware/src/master/3xFMC_VME_Motherboard.pdf

== Available hardware ==

* Altera Stratix IV - main FPGA
* Altera Max V - boot FPGA
* boot flash: PC28F512M29EW - 512 Mbit parallel NOR flash.

= TRG front panel connections =

From top to bottom:

<pre>
|
| minisas-C - links 8-11
| minisas-D - links 12-15
|
| ethernet sfp - use copper sfp only
| minisas - not used, do not connect
| esata - clock in, trigger out
|
| minisas-A - links 0-3
| minisas-B - links 4-7
|
| LEDs
|
</pre>

MiniSAS and SATA flail cable connections:

<pre>
P1 <--> link 3
P2 <--> link 2
P3 <--> link 1
P4 <--> link 0
</pre>

LEDs:

<pre>
--PCB-- (left)
LED[0] - trigger out - ag_trig_out
LED[1] - network packet received - sfp_rx_data_valid
LED[2] - Xilinx FPGA boot ok - FMC1_CFG_DONE
LED[3] - not used
(right)
</pre>

= TRG onboard jumpers and switches =

* rotary switches: select IP address: 00=192.168.1.50, 11=.51, 22=.52, 33=.53, 44=.54, otherwire=.251

= Firmware update procedure =

* use quartus to generate the grifc.pof file (use grifc.cof)
* open quartus programmer
* attach grifc.pof to the 1st CFI_512 flash
* mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
* check that "initiate configuration after programming" is set in tools->options
* say "start"
* should take about 5 minutes
* grifc should reboot into the new firmware

If CFI_512 flash is not visible to the quartus programmer, load correct
code into the MaxV CPLD:

* open quartus programmer,
* say "auto detect"
* change file for the 5M2210 device
* use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
* say "program", it should finish in 10-15 seconds
* say "auto detect"
* CFI_512 flash should be visible now.

= Firmware revisions =

* 0x5bc8f90f - original firmware used for all data
* 0x6147c0f9 - added cbtrg, etc. installed at CERN on 20 Sep 2021.
* 0x618376ae - bigger cbtrg fifo, data rate tested up to 30 Mbytes/sec
* 0x6189c7f3 - fix loss of trigger packets. (missing fifo between alphag block and ethernet mux)
* 0x618b790b - fix loss of timestamps. (cbtrg inputs stretched to 100 ns long). installed at CERN 10 Nov 2021.
* 0x62d32d95 - updated cbtrg, switched to edge-triggered cbtrg inputs, improved BSC multiplicity trigger, improved coinc trigger, added burst pulser. installed at CERN 19 Jul 2022.

= Firmware build =

* use quartus 20.1
* see Makefile in the trg_firmware project

= Jtag remote connection =

* ssh agmini@daq16
* /opt/intelFPGA/16.1/quartus/bin/jtagd --config /home/agmini/.jtagd.conf
* netstat -an | grep 1309 ### note listen address is "0.0.0.0", NOT "127.0.0.1"
<pre>
tcp 0 0 0.0.0.0:1309 0.0.0.0:* LISTEN
</pre>
* opt/intelFPGA/16.1/quartus/bin/jtagconfig ### should work
* ssh olchansk@daq01
* cd git/trg_firmware
* /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
* jtagconfig ### should work
<pre>
daq01:trg_firmware$ jtagconfig
1) DE-SoC on daq16 [2-1.2.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) USB-Blaster on daq16 [2-1.3]
024090DD EP4SGX230(.|ES)
020A40DD 5M(1270ZF324|2210Z)/EPM2210

daq01:trg_firmware$
</pre>

= ALPHA-g trigger functions =

Trigger options:
* software trigger
* pulser trigger
* trigger on GRIF16 ADC NIM and ESATA inputs ("external trigger")
* adc16 grand-or
* adc32 grand-or
* adc16 wire multiplicity
* TPC anode wire per-preamp trigger (aw16 section)
** trigger on coincidences of preamps (removed fw 0x62c77f0b)
** trigger on multiplicity of preamps (removed fw 0x62c77f0b)
** trigger on specific topology of preamps (multiplicity of preamp clusters, etc) via the aw16_mlu trigger
* BSC trigger
** BSC grand_or
** BSC bar multiplicity
* coincidence trigger - select coincidence of external trigger, TPC AW grand-or, TPC AW MLU, BSC grand-or and BSC bar multiplicity triggers

== software trigger ==

to programmatically fire the trigger, one should:
* set the conf_enable_sw_trigger bit in conf_trig_enable, this will permit the software trigger to fire the trigger
* write value 0x4 to register 0x2B, this will cause the software trigger to fire

== pulser trigger ==

To use the pulser trigger, one should program:
* pulser period (in clocks)
* pulser width (in clocks, use value 5, the pulser no longer goes outside of the trigger board, so changing the width does not do anything)
* set the run_pulser bit in conf_trig_enable, this will cause the pulser to run
* set the enable_pulser bit in conf_trig_enable, this will cause the pulser to fire the trigger
* set the output_pulser bit in conf_trig_enable, this will cause the pulser to be output from the alphag firmware block (the pulser no longer goes outside of the trigger board, so changing the bit does not do anything)

== timeout trigger ==

The event builder uses event timestamps to assemble physics events. The timestamps
are usually 32 bit wide and run at 125 MHz (8 ns) or 62.5 MHz (16 ns). If
triggers are generated often (1 per second or more), timestamp wrap around
is easily detected by the event builder. If triggers come infrequently,
timestamp wrap around may occur while there are no triggers, not be seen
by the event builder causing loss of event synchronization.

To avoid this problem in the event builder, a timeout trigger should be generated
if no triggers were generated inside a 10 second interval.

The guaranties that even if all physics triggers temporarily stop for any reason,
the event builder will stay synchronized. (0.1 Hz timeout trigger frequency).

To enable the timeout trigger:
* program timeout trigger timeout in reg 0x43 in units of 8 ns clock
* enable it in bit 23 of [[#conf_trig_enable bits]]

== adc16 multiplicity trigger ==

This trigger is intended for use with the barrel scintillator signals connected to adc16 digitizers. It does not work well with TPC AW signals.

The 16 adc16 trigger bits (16x16=256) are added together to form the hit multiplicity value (adc16_mult, 16 bits, actual range 0 to 256).

Four threshold signals are computed: adc16_mult_1ormore = adc16_mult>=1, 2ormore, 3ormore, 4ormore.

There is a counter for each of these four signals.

Each of these four signals can fire the trigger, see [[#conf_trig_enable bits]].

== TPC anode wire triggers ==

=== aw16 bus ===

TPC Anode Wire trigger is based on the aw16[15:0] (xaw16) bus.

Each bit corresponds to one AW preamp. 16 preamps, 16 bits.

The aw16[15:0] bus can be fed by
* adc16_or16[15:0] - or16 of 100 MHz ADCs, 16 ADC sas links
* adc32_or16[15:0] - or16 of 62.5 MHz ADCs, FMC-ADC32 has 32 channels, so 2 bits per ADC: low 16 channels and high 16 channels, sas links 7..0
* adc32_or16[31:16] - or16 of 62.5 MHz ADCs, ditto, sas links 15..8
as selected by conf_enable_aw_adc16, conf_enable_aw_adc32a, conf_enable_aw_adc32b in [[#conf_control bits]]

<pre>
///////////////////////////////////////////////////////////
// TPC Anode Wire trigger logic (aw16)
///////////////////////////////////////////////////////////

// map adc signals into aw16

wire [15:0] aw16 = ({16{conf_enable_aw_adc16}} & adc16_or16[15:0]) |
({16{conf_enable_aw_adc32a}} & adc32_or16[15:0]) |
({16{conf_enable_aw_adc32b}} & adc32_or16[31:16]);
...
ag_conditioner cond_adc16_or16_0(.clk(clk), .in(aw16[0]), .out(xxaw16[0]));
...
xaw16 <= xxaw16;
</pre>

=== aw16_grand_or ===

TPC AW "grand or" trigger: use aw16_mult_1ormore (before fw 0x62c77f0b)

(256 anode wires, 16 wires per preamp, 16 preamps, 16 aw16 signals)

=== aw16_mlu ===

TPC AW preamp MLU trigger: the MLU (memory lookup
table) implements an arbitrary logical function
to map the 16 aw16 preamp signals into 1 aw16_mlu_trig trigger output.

Description of the aw16 mlu trigger.

In words:

* any aw16 signal starts the aw16_prompt_run gate
* aw16 signals are collected for the duration of conf_mlu_prompt (125MHz/8ns clock)
* this corresponds to time spread of TPC AW signals due to the drift time in the AW drift cell and to the variation in signal transmission time from the ADC to the TRG (digital trigger data link).
* when this prompt time expires, the MLU looks at the accumulated aw16_prompt bit pattern and makes the "yes/no" trigger decision
* after the trigger decision is made, we wait for the TPC to become quiet:
* we wait until all aw16 signals are empty (no timeout)
* we run the aw16_prompt_wait gate, length conf_mlu_wait (8ns clock), if any aw16 signals arrive, we wait for aw16 empty again, rinse, repeat.
* now, after TPC aw16 have been empty for conf_mlu_wait clocks (8ns clock), MLU trigger is ready for the next event.

In logic: (see alphag.v)

* aw16_or <= grand-or of 16 aw16 signals
* "aw16_or" starts the "aw16_prompt_cnt" counter, opens the aw16_prompt_run gate
* during the aw16_prompt_run gate, aw16_prompt collects (latches) the aw16 bits (aw16_prompt <= aw16_prompt | aw16)
* this is the time when we wait for all "prompt" signals from the TPC to arrive into the trigger
* at the end of the aw16_prompt_run gate, the signal aw16_prompt_out is pulsed, latching the output of the MLU into aw16_mlu_trig
* this is the MLU trigger "yes/no" trigger decision.
* after the MLU trigger decision is made, we wait for the arrival and passing of all TPC drift signals
* the aw16_prompt_wait_cnt and aw_prompt_wait gate opens
* if any new aw16 signals arrive (they are TPC drift signals at this time), the aw16_prompt_wait gate is restarted
* if no aw16 signals arrive during the full run of the aw16_prompt_wait gate ("TPC quiet time")
* the aw16_prompt_wait and aw16_prompt gates are cleared and the MLU trigger is ready for the next event.

Good settings are:
* conf_mlu_prompt: 64 (512 ns)
* conf_mlu_wait: 128 (1024 ns)

== BSC trigger ==

=== bsc_adc16 bus ===

The BSC trigger is based on the [15:0]bsc_adc16[7:0] bus: 16 trigger discriminator bits from 8 ADC sas links. (8*16 = 64+64 bars, top and bottom).

The bsc_adc16 bus can be fed from sas links 0..7 or 8..15, controlled by conf_bsc_adc16_a and conf_bsc_adc16_b bits on [[#conf_bsc_control bits]].

bsc_adc16 can be fed only from GRIF-16 100 MHz ADC trigger discriminators.

=== bsc64_top and bsc64_bot buses ===

* firmware 0x5bc8f90f: bsc_adc16 is remapped into 64 bits of top (bsc64_top) and bottom (bsc64_bot):
<pre>
ag_bsc_remap bsc_remap_a(.adc(bsc_adc16[0]), .bsc_bot(bsc64_bot[7:0]), .bsc_top(bsc64_top[7:0]));
ag_bsc_remap bsc_remap_b(.adc(bsc_adc16[1]), .bsc_bot(bsc64_bot[8+7:8+0]), .bsc_top(bsc64_top[8+7:8+0]));
ag_bsc_remap bsc_remap_c(.adc(bsc_adc16[2]), .bsc_bot(bsc64_bot[2*8+7:2*8+0]), .bsc_top(bsc64_top[2*8+7:2*8+0]));
ag_bsc_remap bsc_remap_d(.adc(bsc_adc16[3]), .bsc_bot(bsc64_bot[3*8+7:3*8+0]), .bsc_top(bsc64_top[3*8+7:3*8+0]));

ag_bsc_remap bsc_remap_e(.adc(bsc_adc16[4]), .bsc_bot(bsc64_bot[4*8+7:4*8+0]), .bsc_top(bsc64_top[4*8+7:4*8+0]));
ag_bsc_remap bsc_remap_f(.adc(bsc_adc16[5]), .bsc_bot(bsc64_bot[5*8+7:5*8+0]), .bsc_top(bsc64_top[5*8+7:5*8+0]));
ag_bsc_remap bsc_remap_g(.adc(bsc_adc16[6]), .bsc_bot(bsc64_bot[6*8+7:6*8+0]), .bsc_top(bsc64_top[6*8+7:6*8+0]));
ag_bsc_remap bsc_remap_h(.adc(bsc_adc16[7]), .bsc_bot(bsc64_bot[7*8+7:7*8+0]), .bsc_top(bsc64_top[7*8+7:7*8+0]));

module ag_bsc_remap
(
input wire [15:0] adc,
output wire [7:0] bsc_bot,
output wire [7:0] bsc_top
);

assign bsc_top[3] = adc[0];
assign bsc_top[2] = adc[1];
assign bsc_top[1] = adc[2];
assign bsc_top[0] = adc[3];

assign bsc_top[7] = adc[4];
assign bsc_top[6] = adc[5];
assign bsc_top[5] = adc[6];
assign bsc_top[4] = adc[7];

assign bsc_bot[0] = adc[8];
assign bsc_bot[1] = adc[9];
assign bsc_bot[2] = adc[10];
assign bsc_bot[3] = adc[11];

assign bsc_bot[4] = adc[12];
assign bsc_bot[5] = adc[13];
assign bsc_bot[6] = adc[14];
assign bsc_bot[7] = adc[15];

endmodule
</pre>

=== bsc64 bus ===

the bsc64 bus is the 64 bars used by the trigger, formed from bsc64_top and bsc64_bot:
<pre>
if (conf_bsc64_bot_only) begin
bsc64 <= bsc64_bot;
end else if (conf_bsc64_top_only) begin
bsc64 <= bsc64_top;
end else if (conf_bsc64_bot_top_or) begin
bsc64 <= bsc64_bot | bsc64_top;
end else if (conf_bsc64_bot_top_and) begin
bsc64 <= bsc64_bot & bsc64_top;
end else begin
bsc64 <= 64'b0;
end
</pre>

=== bsc_grand_or_trig ===

bsc_grand_or_trig is the grand-or of 64 bits of the bsc64 bus

to enable triggering on bsc_grand_or_trig, set corresponding bit in [[#conf_trig_enable bits]]

=== old bsc_mult_trig ===

(from fw 0x62c77f0b, old bsc_mult_trig was replaced by new bsc64 multiplicity trigger)

* bsc64_mult is computed as multiplicity of the bsc64 bus (number of 64 bsc64 bits that fired)
* bsc_mult_trig is computed:
<pre>
if (bsc64_mult >= conf_bsc64_mult) begin
bsc_mult_trig <= 1;
end else begin
bsc_mult_trig <= 0;
end
</pre>

to enable the bsc multiplicity trigger, set the multiplicity value conf_bsc64_mult in [[#conf_bsc_control bits]] and enable the corresponding bit in [[#conf_trig_enable bits]].

=== bsc64 multiplicity trigger ===

bsc64 BSC bar multiplicity trigger uses a time window. this time window is started by bsc64_grand_or and runs for conf_bsc64_mult_window clocks (8 nc clock). During this time, hits in bsc64_bus are accumulated (latched) and their multiplicity is computed. If multiplicity condition is satisfied (bigger or equal to conf_bsc64_mult_min), bsc64_mult_trig is fired and the bsc64 bit pattern is saved to the UDP packet. Then trigger waits for the bsc64_bus to be empty. Then trigger waits for conf_bsc64_empty_window clocks, if there is any bsc64 hits, we wait for empty again. So after bsc64 has been empty for conf_bsc64_empty_window clocks, multiplicity trigger is ready for the next event. This scheme cannot implement max multiplicity.

recommended values:
* conf_bsc64_mult_window (8 bits): slightly longer than 3 cycles of SAS link: 3*18 = 54 clocks, good value is 80 (640 ns).
* conf_bsc64_mult_min (8 bits): 2
* conf_bsc64_empty_window (8 bits): 80 (640 ns)

== Coincidence trigger ==

Coincidence trigger provides a combination of TPC, BSC and external scintillator (esata_nim_grand_or) signals:

<pre>
assign coinc_input[0] = aw16_grand_or; // was aw16_mult_1ormore;
assign coinc_input[1] = aw16_mlu_trig;
assign coinc_input[2] = bsc_grand_or_trig;
assign coinc_input[3] = bsc_mult_trig;
assign coinc_input[4] = esata_nim_grand_or;
assign coinc_input[5] = 0;
assign coinc_input[6] = 0;
assign coinc_input[7] = 0;
</pre>

Coincidence trigger "start" mask selects which of the inputs can start the coincidence window.

Coincidence trigger "require" mask selects which inputs must have a hits for the coincidence to be satisfied.

Input hits are collected for the duration of the coincidence window, if all required inputs have hits, coinc_trig is fired.

Example settings:

* coincidence of external scintillator, BSC and TPC AW "grand or" signals: start 0x10, required 0x15
* coincidence of BSC grand-or and TPC AW grand-or signals: start 0x5, required 0x5
* coincidence of BSC multiplicity and TPC AW grand-or triggers: start 0x9, required 0x9

= Control registers =

== Register addresses ==

Note: all registers are 32 bits unless otherwise noted.

Note: RW means read-write register, RO means read-only, ROL means read-only, contents is latched by the "latch_out" bit

{| cellpadding="10" cellspacing="0" border="1"
! Address || Quartus Name || Access || FwRev || Description
|-
| 0x08 || num_sample || RW || GRIF-C || magic 16-bit register to control UDP packet size
|-
| 0x08 || scratch_reg || RW || 0x618b790b || 32-bit scratch register
|-
| 0x1F || compilation_time || RO || || Firmware revision
|-
| 0x20 || conf_trig_width || RW || || Trigger signal width, 16 ns clock
|-
| 0x21 || conf_busy_width || RW || || Busy signal width, 16 ns clock (not used)
|-
| 0x22 || conf_pulser_width || RW || || Pulser signal width, 16 ns clock
|-
| 0x23 || conf_pulser_period || RW || || Pulser signal period, 16 ns clock
|-
| 0x24 || conf_pulser_burst_ctrl || RW || 0x62d1c47e || Generate bursts of pulses: 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses, 16 ns clocks
|-
| 0x25 || conf_trig_enable || RW || || see [[#conf_trig_enable bits]]
|-
| 0x26 || || || not used
|-
| 0x27 || || || not used
|-
| 0x28 || || || not used
|-
| 0x29 || conf_nim_mask || RW || || enable bits for ADC NIM inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2A || conf_esata_mask || RW || || enable bits for ADC eSATA inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2B || reset_out, latch_out, trigger_out || W || || see [[#reg 0x2B bits]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x5bc8f90f || configure AW coincidence trigger, see [[#aw16_coinc]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x62c77f0b || removed
|-
| 0x2D || conf_aw16_coinc_b || RW || 0x5bc8f90f ||
|-
| 0x2E || conf_aw16_coinc_c || RW || 0x5bc8f90f ||
|-
| 0x2F || conf_aw16_coinc_d || RW || 0x5bc8f90f ||
|-
| 0x30 || sas_sd[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect for each link
|-
| 0x31 || pll_625_status || ROL || 0x5b2057f5 (12Jun18_16:32) || 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter
|-
| 0x32 || clk_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the system 125 MHz clock
|-
| 0x33 || clk_625_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625)
|-
| 0x34 || conf_control || RW || 0x5b398983 (01Jul18_19:10) || see [[#conf_control bits]] below
|-
| 0x35 || conf_drift_width || RW || 0x5b398983 (01Jul18_19:10) || width of drift time blank-out in 16 ns clocks
|-
| 0x36 || conf_scaledown || RW || 0x5b398983 (01Jul18_19:10) || trigger scaledown, 0=no scaledown, 1=divide-by-2, 2=divide-by-3, etc
|-
| 0x37 || conf_mlu || RW || 0x5b398983 (01Jul18_19:10) || AW MLU control bits, see [[#conf_mlu bits]]
|-
| 0x38 || conf_trig_delay || RW || 0x5baedfca (28Sep18_19:13) || delay the trigger pulse, 16 ns clock
|-
| 0x39 || esata_clk_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the TRG 125 MHz clock
|-
| 0x3A || esata_clk_esata_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the external clock (eSATA 62.5 MHz clock)
|-
| 0x3B || conf_counter_adc_select || RW || 0x5bb7f6ae (05Oct18_16:41) || select which 16 ADCs are connected to the selected adc counters, 0..15 - connect the adc16 signals, 16..47 connect the adc32 signals
|-
| 0x3C || sysreset_ts || RO || 0x5bb7f6ae (05Oct18_16:41) || 125MHz counter of VME-SYSRESET
|-
| 0x3C || || || 0x618b790b || not used
|-
| 0x3D || GRIF-C csr || RW || GRIF-C || <= csr & ~par_value; // Selective clear
|-
| 0x3E || GRIF-C csr || RW || GRIF-C || <= csr | par_value; // Selective set
|-
| 0x3F || GRIF-C csr || RW || GRIF-C || <= par_value; // write
|-
| 0x3D || || || 0x618b790b || not used
|-
| 0x3E || || || 0x618b790b || not used
|-
| 0x3F || || || 0x618b790b || not used
|-
| 0x40 || conf_bsc_control || RW || 0x5bc13541 (12Oct18_16:58) || Barrel Scintillator trigger control, see [[#conf_bsc_control bits]]
|-
| 0x41 || conf_coinc_control || RW || 0x5bc13541 (12Oct18_16:58) || Coincidence trigger control, see [[#conf_coinc_control bits]]
|-
| 0x42 || reconfig_out || WO || 0x5bc13541 (12Oct18_16:58) || reserved for rebooting the FPGA (does not work)
|-
| 0x43 || conf_trigger_timeout || RW || 0x5bc8f90f (18Oct18_14:20) || Generate timeout trigger if there is no other trigger after given timeout, in 8 ns clocks, must be enabled by bit conf_enable_timeout_trig in [[#conf_trig_enable bits]]
|-
| 0x44 || eth_clk_counter || ROL || 0x618b790b ||
|-
| 0x45 || eth_clk_eth_counter || ROL || 0x618b790b ||
|-
| 0x100 || ts_625 || ROL || || latched timestamp
|-
| 0x101 || counter_trig_out || ROL || || counter of issued triggers
|-
| 0x102 || counter_trig_in || ROL || || counter of triggers
|-
| 0x103 || counter_pulser || ROL || || counter of pulser
|-
| 0x104 || counter_adc16_grand_or || ROL ||
|-
| 0x105 || counter_adc32_grand_or || ROL ||
|-
| 0x106 || counter_adc_grand_or || ROL ||
|-
| 0x107 || counter_esata_nim_grand_or || ROL ||
|-
| 0x108 || counter_adc16_mult_1ormore || ROL ||
|-
| 0x109 || counter_adc16_mult_2ormore || ROL ||
|-
| 0x10A || counter_adc16_mult_3ormore || ROL ||
|-
| 0x10B || counter_adc16_mult_4ormore || ROL ||
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x5bc8f90f || counter of AW coincidence triggers
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x62c77f0b || removed
|-
| 0x10D || counter_aw16_coinc_b || ROL || 0x5bc8f90f ||
|-
| 0x10E || counter_aw16_coinc_c || ROL || 0x5bc8f90f ||
|-
| 0x10F || counter_aw16_coinc_d || ROL || 0x5bc8f90f ||
|-
| 0x110 || counter_drift || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the drift time blank-out
|-
| 0x111 || counter_scaledown || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the scaledown
|-
| 0x112 || counter_aw16_coinc || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW coincidence triggers
|-
| 0x113 || counter_aw16_mlu || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW MLU triggers
|-
| 0x114 || counter_aw16_grand_or || ROL || 0x62c77f0b || counter of AW grand-or triggers
|-
| 0x114 || counter_aw16_mult_1ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 1ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 2ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x62c77f0b || removed
|-
| 0x116 || counter_aw16_mult_3ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 3ormore triggers
|-
| 0x117 || counter_aw16_mult_4ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 4ormore triggers
|-
| 0x118 || counter_bsc_grand_or || ROL || 0x5bc13541 (12Oct18_16:58) || counter of BSC grand-or triggers
|-
| 0x119 || counter_bsc_mult || ROL || 0x5bc13541 (12Oct18_16:58) || counter of old BSC multiplicity triggers
|-
| 0x11A || counter_coinc || ROL || 0x5bc13541 (12Oct18_16:58) || counter of coincidence triggers
|-
| 0x11B || counter_timeout || ROL || 0x618b790b || counter of timeout triggers
|-
| 0x11C || counter_bsc_mult_start || ROL || 0x62c77f0b || counter of BSC multiplicity windows
|-
| 0x11D || counter_bsc_mult_trig || ROL || 0x62c77f0b || counter of BSC multiplicity triggers
|-
| 0x11E || counter_coinc_start || ROL || 0x62d1b152 || counter of coincidence windows
|-
| 0x11F || counter_aw16_mlu_start || ROL || 0x62d1b152 || counter of TPC AW MLU windows
|-
| 0x200..0x207 || conf_adc16_masks || RW || all || adc16 enable bits
|-
| 0x300..0x30F || conf_adc32_masks || RW || all || adc32 enable bits
|-
| 0x400..0x41F || sas_bits[15:0][63:0] || ROL || all || sas data bits for each link
|-
| 0x420..0x42F || sas_sd_counters[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect counter for each link
|-
| 0x430..0x43F || counters_adc16_or16[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 16 counters of adc16 ORes
|-
| 0x440..0x45F || counters_adc32_or16[31:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 32 counters of adc32 ORes
|-
| 0x460..0x46F || counters_adc_selected[15:0] || ROL || 0x5bb7f6ae (05Oct18_16:41) || 16 counters for selected group of adcs, see conf_counter_adc_select
|-
| 0x470..0x4AF || counters_bsc64[63:0] || ROL || 0x5bc13541 (12Oct18_16:58) || 64 counters for the BSC bars
|-
|}

== additional registers ==

<pre>
reg | rw/ro/rol | quartus name | firmware | description
-----------------------------------------------------------------
0x60 | rw | cb_control_out | 0x618b790b | chronobox control
0x61 | rw | cb_status | 0x618b790b | chronobox status
0x62 | rw | cb_invert_a_out | 0x618b790b | chronobox input invert
0x63 | rw | cb_invert_b_out | 0x618b790b |
0x64 | rw | cb_enable_le_a_out | 0x618b790b | timestamp enable leading edge
0x65 | rw | cb_enable_le_b_out | 0x618b790b |
0x66 | rw | cb_enable_te_a_out | 0x618b790b | timestamp enable traiing edge
0x67 | rw | cb_enable_te_b_out | 0x618b790b |
0x6A | ro | cb_input_num | 0x618b790b | chronobox number of inputs
0x6B | rw | cb_sync_mask_a_out | 0x618b790b | chronobox sync signal source
0x6C | rw | cb_sync_mask_b_out | 0x618b790b |
0x6D | rw | cb_sync_reg_out | 0x618b790b | chronobox sync register
0x6E | ro | cb_sync_status | 0x618b790b | chronobox sync status
0x6F | rw | cb_latch_period_out | 0x618b790b | chronobox scalers latch period
0x70 | ro | cb_fifo_status | 0x618b790b | chronobox data fifo status
0x71 | ro | cb_fifo_data | 0x618b790b | read chronobox data fifo (cb_fifo_rdack_out <= 1)
0x72 | rw | cb_udp_period_out | 0x618b790b | period for flushing fifo to UDP
0x73 | rw | cb_udp_threshold_out | 0x618b790b | byte threshold for flushing fifo to UDP
</pre>

== conf_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_clock_select || 0x5b3aa19f (02Jul18_15:05) || select 0=internal 62.5 MHz clock or 1=esata 62.5 MHz clock
|-
| 1 || conf_enable_aw_adc16 || 0x5baedfca (28Sep18_19:13) || select source of TPC AW aw16 bus, see [[#aw16 bus]]
|-
| 2 || conf_enable_aw_adc32a || 0x5baedfca (28Sep18_19:13) ||
|-
| 3 || conf_enable_aw_adc32b || 0x5baedfca (28Sep18_19:13) ||
|-
| 15..4 || || ||
|-
| 23..16 || conf_mlu_prompt || 0x5b3aa19f (02Jul18_15:05) || MLU trigger prompt window, see [[#aw16_mlu]]
|-
| 31..24 || conf_mlu_wait || 0x5b3aa19f (02Jul18_15:05) || MLU trigger wait window, see [[#aw16_mlu]]
|-
|}

== conf_mlu bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 31 || mlu_reset || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 30 || mlu_write || 0x5b3aa19f (02Jul18_15:05) || 1=write data bit into given address
|-
| 16 || mlu_data || 0x5b3aa19f (02Jul18_15:05) || data bit for writing to MLU RAM
|-
| 15..0 || mlu_write_addr || 0x5b3aa19f (02Jul18_15:05) || MLU RAM write address for writing the data bit
|-
|}

== conf_bsc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_bsc_adc_a || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 0..7
|-
| 1 || conf_bsc_adc_b || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 8..15
|-
| 2 || conf_bsc64_bot_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses bottom channels only
|-
| 3 || conf_bsc64_top_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses top channels only
|-
| 4 || conf_bsc64_bot_top_or || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "or" of top and bottom
|-
| 5 || conf_bsc64_bot_top_and || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "and" of top and bottom
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_bsc64_mult_min || 0x5bc13541 (12Oct18_16:58) || minimum bsc64 multiplicity
|-
| 23..16 || conf_bsc64_empty_wondow || 0x62d1c47e || bsc64 empty window length, 8 ns clocks
|-
| 31..24 || conf_bsc64_mult_window || 0x62c77f0b || bsc64 multiplicity window length, 8 ns clocks
|-
|}

== conf_coinc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_coinc_required[0] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mult_1ormore
|-
| 0 || conf_coinc_required[0] || 0x62c77f0b || enable aw16_grand_or
|-
| 1 || conf_coinc_required[1] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mlu_trig
|-
| 2 || conf_coinc_required[2] || 0x5bc13541 (12Oct18_16:58) || enable bsc_grand_or_trig
|-
| 3 || conf_coinc_required[3] || 0x5bc13541 (12Oct18_16:58) || enable bsc_mult_trig
|-
| 3 || conf_coinc_required[3] || 0x62c77f0b || enable bsc64_mult_trig
|-
| 4 || conf_coinc_required[4] || 0x5bc13541 (12Oct18_16:58) || enable esata_nim_grand_or
|-
| 5 || conf_coinc_required[5]
|-
| 6 || conf_coinc_required[6]
|-
| 7 || conf_coinc_required[7]
|-
| 15..8 || conf_coinc_window[7:0] || 0x5bc13541 (12Oct18_16:58) || coincidence window length in units of 125MHz clock (8 ns)
|-
| 23..16 || conf_coinc_start[7:0] || 0x5bc13541 (12Oct18_16:58) || start the coincidence window, same bits as "required"
|-
| 31..24 ||
|-
|}

== conf_trig_enable bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_enable_sw_trigger || || trigger on software trigger (how generated???)
|-
| 1 || conf_enable_pulser || || trigger on pulser
|-
| 2 || - || 0x5b120c9f (01Jun18_20:18) || not used
|-
| 3 || conf_pulser_run || || allow the pulser to run (frequency has to be set beforehand)
|-
| 4 || conf_output_pulser || 0x5bc8f90f || does nothing (top level ag_pulser_out is disconnected)
|-
| 4 || || 0x618b790b || not used
|-
| 5 || conf_enable_esata_nim || || trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand)
|-
| 6 || conf_enable_adc16 || || trigger on adc16_grand_or
|-
| 7 || conf_enable_adc32 || || trigger on adc32_grand_or
|-
| 8 || conf_enable_adc16_1ormore || || trigger on adc16_mult_1ormore "1 or more"
|-
| 9 || conf_enable_adc16_2ormore || || same, "2 or more"
|-
| 10 || conf_enable_adc16_3ormore || || same, "3 or more"
|-
| 11 || conf_enable_adc16_4ormore || || same, "4 or more"
|-
| 12 || - || 0x5b08938c (25May18_15:51) || not used
|-
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
|-
| 14 || - || 0x5bc8f90f || not used
|-
| 15 || conf_enable_adc || 0x5b120c9f (01Jun18_20:18) || trigger on adc_grand_or
|-
| 16 || conf_enable_aw16_coinc_a || 0x5bc8f90f || enable AW coincidence trigger, see [[#aw16_coinc]]
|-
| 16 || - || 0x62c77f0b || aw16_coinc_x removed
|-
| 17 || conf_enable_aw16_coinc_b || 0x5bc8f90f ||
|-
| 18 || conf_enable_aw16_coinc_c || 0x5bc8f90f ||
|-
| 19 || conf_enable_aw16_coinc_d || 0x5bc8f90f ||
|-
| 20 || - || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 20 || conf_enable_aw16_grand_or || 0x618b790b || enable trigger on aw16_grand_or
|-
| 21 || conf_enable_aw16_coinc || 0x5b3aa19f (02Jul18_15:05) || enable trigger on aw16_coinc_trig
|-
| 22 || conf_enable_aw16_mlu || 0x5b3aa19f (02Jul18_15:05) || enable AW MLU trigger
|-
| 23 || conf_enable_timeout_trig || 0x5bc8f90f (18Oct18_14:20) || enable trigger timeout trigger
|-
| 24 || conf_enable_aw16_1ormore || 0x5b3aa19f (02Jul18_15:05) || trigger on aw16_mult_1ormore "1 or more"
|-
| 24 || - || 0x62c77f0b || aw16_mult_xxx removed
|-
| 25 || conf_enable_aw16_2ormore || 0x5b3aa19f (02Jul18_15:05) || same, "2 or more"
|-
| 26 || conf_enable_aw16_3ormore || 0x5b3aa19f (02Jul18_15:05) || same, "3 or more"
|-
| 27 || conf_enable_aw16_4ormore || 0x5b3aa19f (02Jul18_15:05) || same, "4 or more"
|-
| 28 || conf_enable_bsc_grand_or || 0x5bc13541 (12Oct18_16:58) || trigger on BSC grand-or
|-
| 29 || conf_enable_bsc_mult || 0x5bc13541 (12Oct18_16:58) || trigger on BSC multiplicity
|-
| 30 || conf_enable_coinc || 0x5bc13541 (12Oct18_16:58) || trigger on TPC/BSC/ext coincidence trigger
|-
| 31 || - || || not used
|-
|}

== reg 0x2B bits ==

Write to this register will pulse corresponding fpga signals:

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || reset_out || 0x5b120c9f (01Jun18_20:18) || reset counters, etc
|-
| 1 || latch_out || 0x5b120c9f (01Jun18_20:18) || latch counters, sas bits, etc
|-
| 2 || trigger_out || 0x5b120c9f (01Jun18_20:18) || generate a software trigger
|-
|}

= UDP data format =

== general format ==

AAA

== firmware 0x5bc8f90f ==

{| cellpadding="10" cellspacing="0" border="1"
! Offset || Name || Quartus name || FwRev || Description
|-
| 0 || packet counter || none || all || 31-bit UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
|-
| 1 || 0x8 packet header || || all || 28 bits of counter_trig_out
|-
| 2 || trigger timestamp || trig_ts || all || 62.5MHz trigger timestamp
|-
| 3 || accepted triggers || counter_trig_out || all || counter of accepted triggers
|-
| 4 || input triggers || counter_trig_in || all || counter of trigger input
|-
| 5 || pulser triggers || counter_pulser || all || counter of pulser triggers
|-
| 6 || trigger bitmap || udp_trig_bits || 0x5a48448d (30Dec17_17:59) || bitmap of trigger information, see below
|-
| 7 || nim bits || udp_nim_bits_masked || ??? || 32 bits of ADC NIM inputs (2 bits per ADC)
|-
| 8 || esata bits || udp_esata_bits_masked || ??? || 32 bits of ADC ESATA inputs (2 bits per ADC)
|-
| 9 || mlu bits || aw16_prompt || 0x5b398983 (01Jul18_19:10) || 16 bits of MLU input, 1 bit per preamp
|-
| 10 || drift-blank-off counter || udp_drift_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the drift blank-off
|-
| 11 || scaledown counter || udp_scaledown_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the scaledown
|-
| X || || || ||
|-
| 12 || 0xE packet footer || || all || 28 bits of counter_trig_out
|-
|}

== firmware 0x618b790b (Nov 2021) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

== firmware 0x62d1c47e (Jul 2022) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, 8'h00, 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= conf_fw_rev;
18 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

Values of udp_coinc_latch[7:0]:
* aaa

Values of udp_aw16_mult[7:0] and udp_aw16_bus[15:0]:
* aaa

Values of udp_bsc64_mult[7:0] and udp_bsc64_bus[63:0]
* aaa

== trigger bitmap ==

Firmware ??? (one of the very early revisions)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= adc16_coinc_top;
udp_trig_bits[5] <= adc16_coinc_bot;
udp_trig_bits[6] <= adc16_coinc;
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
udp_trig_bits[31:24] <= mult16[7:0];

</pre>

Firmware 0x5b08938c (25May18_15:51)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= 0; // not used
udp_trig_bits[31:24] <= mult16[7:0];
</pre>

Firmware 0x5b217dc4 (13Jun18_13:25)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5b3aa19f (02Jul18_15:05)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= udp_mlu_out;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5bc8f90f (18Oct18_14:20)

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_run_pulser
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = 0; // not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x618b790b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x62c77f0b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = 0; // aw16_coinc_a;
assign trig32_in[17] = 0; // aw16_coinc_b;
assign trig32_in[18] = 0; // aw16_coinc_c;
assign trig32_in[19] = 0; // aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = 0; // aw16_mult_1ormore;
assign trig32_in[25] = 0; // aw16_mult_2ormore;
assign trig32_in[26] = 0; // aw16_mult_3ormore;
assign trig32_in[27] = 0; // aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc64_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

= TRG chronobox inputs =

from trg_firmware/toplevel/grifc.v

<pre>
localparam CB_N = 23;
localparam CB_N1 = CB_N-1;

wire [CB_N1:0] cb_xinputs_async;

assign cb_xinputs_async[0] = ag_trig_out;
assign cb_xinputs_async[1] = ag_trig_scaledown_out;
assign cb_xinputs_async[2] = ag_trig_drift_out;
assign cb_xinputs_async[3] = ag_trig_received_out;

assign cb_xinputs_async[4] = ag_cb_sw_trig;
assign cb_xinputs_async[5] = ag_cb_pulser_trig;
assign cb_xinputs_async[6] = ag_cb_esata_nim_trig;
assign cb_xinputs_async[7] = ag_cb_adc16_grand_or_trig;
assign cb_xinputs_async[8] = ag_cb_adc32_grand_or_trig;

assign cb_xinputs_async[9] = ag_cb_aw16_grand_or_trig;
assign cb_xinputs_async[10] = ag_cb_aw16_mult_1ormore;
assign cb_xinputs_async[11] = ag_cb_aw16_mult_2ormore;
assign cb_xinputs_async[12] = ag_cb_aw16_mult_3ormore;
assign cb_xinputs_async[13] = ag_cb_aw16_mult_4ormore;
assign cb_xinputs_async[14] = ag_cb_aw16_mlu_trig;

assign cb_xinputs_async[15] = ag_cb_bsc64_grand_or_trig;
assign cb_xinputs_async[16] = ag_cb_bsc64_mult_1ormore;
assign cb_xinputs_async[17] = ag_cb_bsc64_mult_2ormore;
assign cb_xinputs_async[18] = ag_cb_bsc64_mult_3ormore;
assign cb_xinputs_async[19] = ag_cb_bsc64_mult_4ormore;
assign cb_xinputs_async[20] = ag_cb_bsc64_mult_trig;

assign cb_xinputs_async[21] = ag_cb_coinc_trig;

assign cb_xinputs_async[22] = ag_cb_timeout_trig;
</pre>

= Example UDP packets =

* trigger data, marker words 0x8

<pre>
ReadDataThread read 76
0: 0x003666ed -- UDP packet counter from UDP transmitter
1: 0x80000bf8 -- 0x8 is trigger data packet, 0xbf8 is the trigger counter from alphag.v
2: 0x2edf8b41 -- trigger data
3: 0x00000bf8
4: 0x00000bf8
5: 0x00000bee
6: 0x00000001
7: 0x00000000
8: 0x00000000
9: 0x00000003
10: 0x00000bf8
11: 0x00000bf8
12: 0x00000000
13: 0x00000000
14: 0x00000000
15: 0x00000000
16: 0x00000000
17: 0x00000000
18: 0xe0000bf8 -- 0xE is end of trigger data, counter 0xbf8 must match the counter in the 0x8 word.
ReadDataThread read 76 -- next packet
0: 0x003666ee -- UDP packet counter from UDP transmitter
...
</pre>

* chronobox fifo data, marker word 0xC, see [[Chronobox#FIFO_data_format]]

<pre>
ReadDataThread read 404
0: 0x003658ed -- UDP packet counter from UDP transmitter
1: 0xc000eacc -- 0xC is FIFO data, fifo packet counter 0xeacc from fifo_to_udp.v
2: 0x00000061 -- FIFO status, low bits the the word counter, so up to 0x61 fifo words are to follow
3: 0x87fb3d72 -- tsc hits
4: 0x8ffb3d74
5: 0x90fb3d74
6: 0x91fb3d74
7: 0x92fb3d74
8: 0x93fb3d74
9: 0x93fb3d75
10: 0x94fb3d74
11: 0x94fb3d77
12: 0x87fb3d77
13: 0x8ffb3d77
14: 0x90fb3d77
15: 0x91fb3d77
16: 0x92fb3d77
17: 0xfe000018 -- 0xFE scaler data starts, 0x18 words to follow
18: 0x00000000
19: 0x00000000
20: 0x00000000
21: 0x00000000
22: 0x00000000
23: 0x00000000
24: 0x00000000
25: 0x00000108
26: 0x00000000
27: 0x00000000
28: 0x00000000
29: 0x00000000
30: 0x00000000
31: 0x00000000
32: 0x00000000
33: 0x00000108
34: 0x00000108
35: 0x00000108
36: 0x00000108
37: 0x00000108
38: 0x00000108
39: 0x00000000
40: 0x00000000
41: 0xce56fa93 -- last word of scaler data is the sysclock counter (125 MHz)
42: 0xff800048 -- timestamp wraparound
43: 0x8f1f36e4 -- tsc hits
44: 0x901f36e4
45: 0x911f36e4
46: 0x921f36e4
47: 0x931f36e4
48: 0x941f36e4
49: 0x871f36e4
50: 0x871f36e7
51: 0x8f1f36e7
52: 0x901f36e9
53: 0x911f36e7
54: 0x921f36e9
55: 0x931f36e7
56: 0x941f36e9
57: 0x904330ac
58: 0x914330ac
59: 0x924330ac
60: 0x934330ac
61: 0x934330ad
62: 0x944330ac
63: 0x944330ad
64: 0x874330ac
65: 0x874330ad
66: 0x8f4330ac
67: 0x8f4330ad
68: 0x904330ad
69: 0x914330ad
70: 0x924330ad
71: 0x8f672a62
72: 0x90672a62
73: 0x91672a62
74: 0x92672a62
75: 0x93672a62
76: 0x94672a62
77: 0x87672a62
78: 0x87672a65
79: 0x8f672a65
80: 0x90672a65
81: 0x91672a65
82: 0x92672a65
83: 0x93672a65
84: 0x94672a65
85: 0xff000049
86: 0x878b2422
87: 0x8f8b2424
88: 0x908b2424
89: 0x918b2424
90: 0x928b2424
91: 0x938b2424
92: 0x938b2425
93: 0x948b2424
94: 0x948b2427
95: 0x878b2427
96: 0x8f8b2427
97: 0x908b2427
98: 0x918b2427
99: 0x928b2427
100: 0xe000eacc -- 0xE is end of fifo data, counter 0xeacc must match the counter in the 0xC word.
ReadDataThread read 344 -- next packet
...
</pre>

= TODO =

* DONE July 2022. add FwRev to the UDP data output
* RJ45 SFP: PROBLEM, D.A. CABLE: GOOD, Fiber SFP: ???. fix "write did not happen" (send udp write command, there is no reply, read returns old data as if write never happened). suspect udp "write" packet is lost?
* PROBLEM GONE Aug 2021. fix reply to wrong socket - udp packets should reply to same socket as they came from, udp data packets should be sent to same socket as requested them, not same socket as last command.
* DONE 2021jul30. add fixes from Chris P. for the auto-negotiation and dhcp (see email from him).
* DONE flash chip connected to FPGA. Aug 2021. implement ethernet flash programmer
* DONE Aug 2021. updated maxv firmware. implement FPGA reboot
* speed up programming the MLU by writing more than 1 bit at a time
* DONE Nov 2021. add 64-bit bitmap of BSC trigger bits
* DONE. add chronobox code
* DONE. add avalon mux for alphag and chronobox packets
* DONE. add chronobox fifo to udp packet sequencer
* check that TxReadyOut is correct and it is safe to send an avalon packet while previous packet is still transmitting.
* DONE. test fiber SFP is working
* complete the UDP flash programmer (parallel flash erase and write)

= End =

//KO

TRG

2022-07-24T22:44:00Z

Olchansk: /* Firmware revisions */

= TRG, the trigger control board for the ALPHA-g detector =

= Links =

* xxx
* https://bitbucket.org/expalpha/trg_firmware - firmware sources on bitbucket

= General characteristics =

== Photos ==

== Board schematics ==

* https://bitbucket.org/expalpha/trg_firmware/src/master/3xFMC_VME_Motherboard.pdf

== Available hardware ==

* Altera Stratix IV - main FPGA
* Altera Max V - boot FPGA
* boot flash: PC28F512M29EW - 512 Mbit parallel NOR flash.

= TRG front panel connections =

From top to bottom:

<pre>
|
| minisas-C - links 8-11
| minisas-D - links 12-15
|
| ethernet sfp - use copper sfp only
| minisas - not used, do not connect
| esata - clock in, trigger out
|
| minisas-A - links 0-3
| minisas-B - links 4-7
|
| LEDs
|
</pre>

MiniSAS and SATA flail cable connections:

<pre>
P1 <--> link 3
P2 <--> link 2
P3 <--> link 1
P4 <--> link 0
</pre>

LEDs:

<pre>
--PCB-- (left)
LED[0] - trigger out - ag_trig_out
LED[1] - network packet received - sfp_rx_data_valid
LED[2] - Xilinx FPGA boot ok - FMC1_CFG_DONE
LED[3] - not used
(right)
</pre>

= TRG onboard jumpers and switches =

* rotary switches: select IP address: 00=192.168.1.50, 11=.51, 22=.52, 33=.53, 44=.54, otherwire=.251

= Firmware update procedure =

* use quartus to generate the grifc.pof file (use grifc.cof)
* open quartus programmer
* attach grifc.pof to the 1st CFI_512 flash
* mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
* check that "initiate configuration after programming" is set in tools->options
* say "start"
* should take about 5 minutes
* grifc should reboot into the new firmware

If CFI_512 flash is not visible to the quartus programmer, load correct
code into the MaxV CPLD:

* open quartus programmer,
* say "auto detect"
* change file for the 5M2210 device
* use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
* say "program", it should finish in 10-15 seconds
* say "auto detect"
* CFI_512 flash should be visible now.

= Firmware revisions =

* 0x5bc8f90f - original firmware used for all data
* 0x6147c0f9 - added cbtrg, etc. installed at CERN on 20 Sep 2021.
* 0x618376ae - bigger cbtrg fifo, data rate tested up to 30 Mbytes/sec
* 0x6189c7f3 - fix loss of trigger packets. (missing fifo between alphag block and ethernet mux)
* 0x618b790b - fix loss of timestamps. (cbtrg inputs stretched to 100 ns long). installed at CERN 10 Nov 2021.
* 0x62d32d95 - updated cbtrg, switched to edge-triggered cbtrg inputs, improved BSC multiplicity trigger, improved coinc trigger, added burst pulser. installed at CERN 19 Jul 2022.

= Firmware build =

* use quartus 20.1
* see Makefile in the trg_firmware project

= Jtag remote connection =

* ssh agmini@daq16
* /opt/intelFPGA/16.1/quartus/bin/jtagd --config /home/agmini/.jtagd.conf
* netstat -an | grep 1309 ### note listen address is "0.0.0.0", NOT "127.0.0.1"
<pre>
tcp 0 0 0.0.0.0:1309 0.0.0.0:* LISTEN
</pre>
* opt/intelFPGA/16.1/quartus/bin/jtagconfig ### should work
* ssh olchansk@daq01
* cd git/trg_firmware
* /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
* jtagconfig ### should work
<pre>
daq01:trg_firmware$ jtagconfig
1) DE-SoC on daq16 [2-1.2.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) USB-Blaster on daq16 [2-1.3]
024090DD EP4SGX230(.|ES)
020A40DD 5M(1270ZF324|2210Z)/EPM2210

daq01:trg_firmware$
</pre>

= ALPHA-g trigger functions =

Trigger options:
* software trigger
* pulser trigger
* trigger on GRIF16 ADC NIM and ESATA inputs ("external trigger")
* adc16 grand-or
* adc32 grand-or
* adc16 wire multiplicity
* TPC anode wire per-preamp trigger (aw16 section)
** trigger on coincidences of preamps (removed fw 0x62c77f0b)
** trigger on multiplicity of preamps (removed fw 0x62c77f0b)
** trigger on specific topology of preamps (multiplicity of preamp clusters, etc) via the aw16_mlu trigger
* BSC trigger
** BSC grand_or
** BSC bar multiplicity
* coincidence trigger - select coincidence of external trigger, TPC AW grand-or, TPC AW MLU, BSC grand-or and BSC bar multiplicity triggers

== software trigger ==

to programmatically fire the trigger, one should:
* set the conf_enable_sw_trigger bit in conf_trig_enable, this will permit the software trigger to fire the trigger
* write value 0x4 to register 0x2B, this will cause the software trigger to fire

== pulser trigger ==

To use the pulser trigger, one should program:
* pulser period (in clocks)
* pulser width (in clocks, use value 5, the pulser no longer goes outside of the trigger board, so changing the width does not do anything)
* set the run_pulser bit in conf_trig_enable, this will cause the pulser to run
* set the enable_pulser bit in conf_trig_enable, this will cause the pulser to fire the trigger
* set the output_pulser bit in conf_trig_enable, this will cause the pulser to be output from the alphag firmware block (the pulser no longer goes outside of the trigger board, so changing the bit does not do anything)

== timeout trigger ==

The event builder uses event timestamps to assemble physics events. The timestamps
are usually 32 bit wide and run at 125 MHz (8 ns) or 62.5 MHz (16 ns). If
triggers are generated often (1 per second or more), timestamp wrap around
is easily detected by the event builder. If triggers come infrequently,
timestamp wrap around may occur while there are no triggers, not be seen
by the event builder causing loss of event synchronization.

To avoid this problem in the event builder, a timeout trigger should be generated
if no triggers were generated inside a 10 second interval.

The guaranties that even if all physics triggers temporarily stop for any reason,
the event builder will stay synchronized. (0.1 Hz timeout trigger frequency).

To enable the timeout trigger:
* program timeout trigger timeout in reg 0x43 in units of 8 ns clock
* enable it in bit 23 of [[#conf_trig_enable bits]]

== adc16 multiplicity trigger ==

This trigger is intended for use with the barrel scintillator signals connected to adc16 digitizers. It does not work well with TPC AW signals.

The 16 adc16 trigger bits (16x16=256) are added together to form the hit multiplicity value (adc16_mult, 16 bits, actual range 0 to 256).

Four threshold signals are computed: adc16_mult_1ormore = adc16_mult>=1, 2ormore, 3ormore, 4ormore.

There is a counter for each of these four signals.

Each of these four signals can fire the trigger, see [[#conf_trig_enable bits]].

== TPC anode wire triggers ==

=== aw16 bus ===

TPC Anode Wire trigger is based on the aw16[15:0] (xaw16) bus.

Each bit corresponds to one AW preamp. 16 preamps, 16 bits.

The aw16[15:0] bus can be fed by
* adc16_or16[15:0] - or16 of 100 MHz ADCs, 16 ADC sas links
* adc32_or16[15:0] - or16 of 62.5 MHz ADCs, FMC-ADC32 has 32 channels, so 2 bits per ADC: low 16 channels and high 16 channels, sas links 7..0
* adc32_or16[31:16] - or16 of 62.5 MHz ADCs, ditto, sas links 15..8
as selected by conf_enable_aw_adc16, conf_enable_aw_adc32a, conf_enable_aw_adc32b in [[#conf_control bits]]

<pre>
///////////////////////////////////////////////////////////
// TPC Anode Wire trigger logic (aw16)
///////////////////////////////////////////////////////////

// map adc signals into aw16

wire [15:0] aw16 = ({16{conf_enable_aw_adc16}} & adc16_or16[15:0]) |
({16{conf_enable_aw_adc32a}} & adc32_or16[15:0]) |
({16{conf_enable_aw_adc32b}} & adc32_or16[31:16]);
...
ag_conditioner cond_adc16_or16_0(.clk(clk), .in(aw16[0]), .out(xxaw16[0]));
...
xaw16 <= xxaw16;
</pre>

=== aw16_grand_or ===

TPC AW "grand or" trigger: use aw16_mult_1ormore (before fw 0x62c77f0b)

(256 anode wires, 16 wires per preamp, 16 preamps, 16 aw16 signals)

=== aw16_mlu ===

TPC AW preamp MLU trigger: the MLU (memory lookup
table) implements an arbitrary logical function
to map the 16 aw16 preamp signals into 1 aw16_mlu_trig trigger output.

Description of the aw16 mlu trigger.

In words:

* any aw16 signal starts the aw16_prompt_run gate
* aw16 signals are collected for the duration of conf_mlu_prompt (125MHz/8ns clock)
* this corresponds to time spread of TPC AW signals due to the drift time in the AW drift cell and to the variation in signal transmission time from the ADC to the TRG (digital trigger data link).
* when this prompt time expires, the MLU looks at the accumulated aw16_prompt bit pattern and makes the "yes/no" trigger decision
* after the trigger decision is made, we wait for the TPC to become quiet:
* we wait until all aw16 signals are empty (no timeout)
* we run the aw16_prompt_wait gate, length conf_mlu_wait (8ns clock), if any aw16 signals arrive, we wait for aw16 empty again, rinse, repeat.
* now, after TPC aw16 have been empty for conf_mlu_wait clocks (8ns clock), MLU trigger is ready for the next event.

In logic: (see alphag.v)

* aw16_or <= grand-or of 16 aw16 signals
* "aw16_or" starts the "aw16_prompt_cnt" counter, opens the aw16_prompt_run gate
* during the aw16_prompt_run gate, aw16_prompt collects (latches) the aw16 bits (aw16_prompt <= aw16_prompt | aw16)
* this is the time when we wait for all "prompt" signals from the TPC to arrive into the trigger
* at the end of the aw16_prompt_run gate, the signal aw16_prompt_out is pulsed, latching the output of the MLU into aw16_mlu_trig
* this is the MLU trigger "yes/no" trigger decision.
* after the MLU trigger decision is made, we wait for the arrival and passing of all TPC drift signals
* the aw16_prompt_wait_cnt and aw_prompt_wait gate opens
* if any new aw16 signals arrive (they are TPC drift signals at this time), the aw16_prompt_wait gate is restarted
* if no aw16 signals arrive during the full run of the aw16_prompt_wait gate ("TPC quiet time")
* the aw16_prompt_wait and aw16_prompt gates are cleared and the MLU trigger is ready for the next event.

Good settings are:
* conf_mlu_prompt: 64 (512 ns)
* conf_mlu_wait: 128 (1024 ns)

== BSC trigger ==

=== bsc_adc16 bus ===

The BSC trigger is based on the [15:0]bsc_adc16[7:0] bus: 16 trigger discriminator bits from 8 ADC sas links. (8*16 = 64+64 bars, top and bottom).

The bsc_adc16 bus can be fed from sas links 0..7 or 8..15, controlled by conf_bsc_adc16_a and conf_bsc_adc16_b bits on [[#conf_bsc_control bits]].

bsc_adc16 can be fed only from GRIF-16 100 MHz ADC trigger discriminators.

=== bsc64_top and bsc64_bot buses ===

* firmware 0x5bc8f90f: bsc_adc16 is remapped into 64 bits of top (bsc64_top) and bottom (bsc64_bot):
<pre>
ag_bsc_remap bsc_remap_a(.adc(bsc_adc16[0]), .bsc_bot(bsc64_bot[7:0]), .bsc_top(bsc64_top[7:0]));
ag_bsc_remap bsc_remap_b(.adc(bsc_adc16[1]), .bsc_bot(bsc64_bot[8+7:8+0]), .bsc_top(bsc64_top[8+7:8+0]));
ag_bsc_remap bsc_remap_c(.adc(bsc_adc16[2]), .bsc_bot(bsc64_bot[2*8+7:2*8+0]), .bsc_top(bsc64_top[2*8+7:2*8+0]));
ag_bsc_remap bsc_remap_d(.adc(bsc_adc16[3]), .bsc_bot(bsc64_bot[3*8+7:3*8+0]), .bsc_top(bsc64_top[3*8+7:3*8+0]));

ag_bsc_remap bsc_remap_e(.adc(bsc_adc16[4]), .bsc_bot(bsc64_bot[4*8+7:4*8+0]), .bsc_top(bsc64_top[4*8+7:4*8+0]));
ag_bsc_remap bsc_remap_f(.adc(bsc_adc16[5]), .bsc_bot(bsc64_bot[5*8+7:5*8+0]), .bsc_top(bsc64_top[5*8+7:5*8+0]));
ag_bsc_remap bsc_remap_g(.adc(bsc_adc16[6]), .bsc_bot(bsc64_bot[6*8+7:6*8+0]), .bsc_top(bsc64_top[6*8+7:6*8+0]));
ag_bsc_remap bsc_remap_h(.adc(bsc_adc16[7]), .bsc_bot(bsc64_bot[7*8+7:7*8+0]), .bsc_top(bsc64_top[7*8+7:7*8+0]));

module ag_bsc_remap
(
input wire [15:0] adc,
output wire [7:0] bsc_bot,
output wire [7:0] bsc_top
);

assign bsc_top[3] = adc[0];
assign bsc_top[2] = adc[1];
assign bsc_top[1] = adc[2];
assign bsc_top[0] = adc[3];

assign bsc_top[7] = adc[4];
assign bsc_top[6] = adc[5];
assign bsc_top[5] = adc[6];
assign bsc_top[4] = adc[7];

assign bsc_bot[0] = adc[8];
assign bsc_bot[1] = adc[9];
assign bsc_bot[2] = adc[10];
assign bsc_bot[3] = adc[11];

assign bsc_bot[4] = adc[12];
assign bsc_bot[5] = adc[13];
assign bsc_bot[6] = adc[14];
assign bsc_bot[7] = adc[15];

endmodule
</pre>

=== bsc64 bus ===

the bsc64 bus is the 64 bars used by the trigger, formed from bsc64_top and bsc64_bot:
<pre>
if (conf_bsc64_bot_only) begin
bsc64 <= bsc64_bot;
end else if (conf_bsc64_top_only) begin
bsc64 <= bsc64_top;
end else if (conf_bsc64_bot_top_or) begin
bsc64 <= bsc64_bot | bsc64_top;
end else if (conf_bsc64_bot_top_and) begin
bsc64 <= bsc64_bot & bsc64_top;
end else begin
bsc64 <= 64'b0;
end
</pre>

=== bsc_grand_or_trig ===

bsc_grand_or_trig is the grand-or of 64 bits of the bsc64 bus

to enable triggering on bsc_grand_or_trig, set corresponding bit in [[#conf_trig_enable bits]]

=== old bsc_mult_trig ===

(from fw 0x62c77f0b, old bsc_mult_trig was replaced by new bsc64 multiplicity trigger)

* bsc64_mult is computed as multiplicity of the bsc64 bus (number of 64 bsc64 bits that fired)
* bsc_mult_trig is computed:
<pre>
if (bsc64_mult >= conf_bsc64_mult) begin
bsc_mult_trig <= 1;
end else begin
bsc_mult_trig <= 0;
end
</pre>

to enable the bsc multiplicity trigger, set the multiplicity value conf_bsc64_mult in [[#conf_bsc_control bits]] and enable the corresponding bit in [[#conf_trig_enable bits]].

=== bsc64 multiplicity trigger ===

bsc64 BSC bar multiplicity trigger uses a time window. this time window is started by bsc64_grand_or and runs for conf_bsc64_mult_window clocks (8 nc clock). During this time, hits in bsc64_bus are accumulated (latched) and their multiplicity is computed. If multiplicity condition is satisfied (bigger or equal to conf_bsc64_mult_min), bsc64_mult_trig is fired and the bsc64 bit pattern is saved to the UDP packet. Then trigger waits for the bsc64_bus to be empty. Then trigger waits for conf_bsc64_empty_window clocks, if there is any bsc64 hits, we wait for empty again. So after bsc64 has been empty for conf_bsc64_empty_window clocks, multiplicity trigger is ready for the next event. This scheme cannot implement max multiplicity.

recommended values:
* conf_bsc64_mult_window (8 bits): slightly longer than 3 cycles of SAS link: 3*18 = 54 clocks, good value is 80 (640 ns).
* conf_bsc64_mult_min (8 bits): 2
* conf_bsc64_empty_window (8 bits): 80 (640 ns)

== Coincidence trigger ==

Coincidence trigger provides a combination of TPC, BSC and external scintillator (esata_nim_grand_or) signals:

<pre>
assign coinc_input[0] = aw16_grand_or; // was aw16_mult_1ormore;
assign coinc_input[1] = aw16_mlu_trig;
assign coinc_input[2] = bsc_grand_or_trig;
assign coinc_input[3] = bsc_mult_trig;
assign coinc_input[4] = esata_nim_grand_or;
assign coinc_input[5] = 0;
assign coinc_input[6] = 0;
assign coinc_input[7] = 0;
</pre>

Coincidence trigger "start" mask selects which of the inputs can start the coincidence window.

Coincidence trigger "require" mask selects which inputs must have a hits for the coincidence to be satisfied.

Input hits are collected for the duration of the coincidence window, if all required inputs have hits, coinc_trig is fired.

Example settings:

* coincidence of external scintillator, BSC and TPC AW "grand or" signals: start 0x10, required 0x15
* coincidence of BSC grand-or and TPC AW grand-or signals: start 0x5, required 0x5
* coincidence of BSC multiplicity and TPC AW grand-or triggers: start 0x9, required 0x9

= Control registers =

== Register addresses ==

Note: all registers are 32 bits unless otherwise noted.

Note: RW means read-write register, RO means read-only, ROL means read-only, contents is latched by the "latch_out" bit

{| cellpadding="10" cellspacing="0" border="1"
! Address || Quartus Name || Access || FwRev || Description
|-
| 0x08 || num_sample || RW || GRIF-C || magic 16-bit register to control UDP packet size
|-
| 0x08 || scratch_reg || RW || 0x618b790b || 32-bit scratch register
|-
| 0x1F || compilation_time || RO || || Firmware revision
|-
| 0x20 || conf_trig_width || RW || || Trigger signal width, 16 ns clock
|-
| 0x21 || conf_busy_width || RW || || Busy signal width, 16 ns clock (not used)
|-
| 0x22 || conf_pulser_width || RW || || Pulser signal width, 16 ns clock
|-
| 0x23 || conf_pulser_period || RW || || Pulser signal period, 16 ns clock
|-
| 0x24 || conf_pulser_burst_ctrl || RW || 0x62d1c47e || Generate bursts of pulses: 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses, 16 ns clocks
|-
| 0x25 || conf_trig_enable || RW || || see [[#conf_trig_enable bits]]
|-
| 0x26 || || || not used
|-
| 0x27 || || || not used
|-
| 0x28 || || || not used
|-
| 0x29 || conf_nim_mask || RW || || enable bits for ADC NIM inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2A || conf_esata_mask || RW || || enable bits for ADC eSATA inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2B || reset_out, latch_out, trigger_out || W || || see [[#reg 0x2B bits]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x5bc8f90f || configure AW coincidence trigger, see [[#aw16_coinc]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x62c77f0b || removed
|-
| 0x2D || conf_aw16_coinc_b || RW || 0x5bc8f90f ||
|-
| 0x2E || conf_aw16_coinc_c || RW || 0x5bc8f90f ||
|-
| 0x2F || conf_aw16_coinc_d || RW || 0x5bc8f90f ||
|-
| 0x30 || sas_sd[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect for each link
|-
| 0x31 || pll_625_status || ROL || 0x5b2057f5 (12Jun18_16:32) || 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter
|-
| 0x32 || clk_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the system 125 MHz clock
|-
| 0x33 || clk_625_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625)
|-
| 0x34 || conf_control || RW || 0x5b398983 (01Jul18_19:10) || see [[#conf_control bits]] below
|-
| 0x35 || conf_drift_width || RW || 0x5b398983 (01Jul18_19:10) || width of drift time blank-out in 16 ns clocks
|-
| 0x36 || conf_scaledown || RW || 0x5b398983 (01Jul18_19:10) || trigger scaledown, 0=no scaledown, 1=divide-by-2, 2=divide-by-3, etc
|-
| 0x37 || conf_mlu || RW || 0x5b398983 (01Jul18_19:10) || AW MLU control bits, see [[#conf_mlu bits]]
|-
| 0x38 || conf_trig_delay || RW || 0x5baedfca (28Sep18_19:13) || delay the trigger pulse, 16 ns clock
|-
| 0x39 || esata_clk_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the TRG 125 MHz clock
|-
| 0x3A || esata_clk_esata_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the external clock (eSATA 62.5 MHz clock)
|-
| 0x3B || conf_counter_adc_select || RW || 0x5bb7f6ae (05Oct18_16:41) || select which 16 ADCs are connected to the selected adc counters, 0..15 - connect the adc16 signals, 16..47 connect the adc32 signals
|-
| 0x3C || sysreset_ts || RO || 0x5bb7f6ae (05Oct18_16:41) || 125MHz counter of VME-SYSRESET
|-
| 0x3C || || || 0x618b790b || not used
|-
| 0x3D || GRIF-C csr || RW || GRIF-C || <= csr & ~par_value; // Selective clear
|-
| 0x3E || GRIF-C csr || RW || GRIF-C || <= csr | par_value; // Selective set
|-
| 0x3F || GRIF-C csr || RW || GRIF-C || <= par_value; // write
|-
| 0x3D || || || 0x618b790b || not used
|-
| 0x3E || || || 0x618b790b || not used
|-
| 0x3F || || || 0x618b790b || not used
|-
| 0x40 || conf_bsc_control || RW || 0x5bc13541 (12Oct18_16:58) || Barrel Scintillator trigger control, see [[#conf_bsc_control bits]]
|-
| 0x41 || conf_coinc_control || RW || 0x5bc13541 (12Oct18_16:58) || Coincidence trigger control, see [[#conf_coinc_control bits]]
|-
| 0x42 || reconfig_out || WO || 0x5bc13541 (12Oct18_16:58) || reserved for rebooting the FPGA (does not work)
|-
| 0x43 || conf_trigger_timeout || RW || 0x5bc8f90f (18Oct18_14:20) || Generate timeout trigger if there is no other trigger after given timeout, in 8 ns clocks, must be enabled by bit conf_enable_timeout_trig in [[#conf_trig_enable bits]]
|-
| 0x44 || eth_clk_counter || ROL || 0x618b790b ||
|-
| 0x45 || eth_clk_eth_counter || ROL || 0x618b790b ||
|-
| 0x100 || ts_625 || ROL || || latched timestamp
|-
| 0x101 || counter_trig_out || ROL || || counter of issued triggers
|-
| 0x102 || counter_trig_in || ROL || || counter of triggers
|-
| 0x103 || counter_pulser || ROL || || counter of pulser
|-
| 0x104 || counter_adc16_grand_or || ROL ||
|-
| 0x105 || counter_adc32_grand_or || ROL ||
|-
| 0x106 || counter_adc_grand_or || ROL ||
|-
| 0x107 || counter_esata_nim_grand_or || ROL ||
|-
| 0x108 || counter_adc16_mult_1ormore || ROL ||
|-
| 0x109 || counter_adc16_mult_2ormore || ROL ||
|-
| 0x10A || counter_adc16_mult_3ormore || ROL ||
|-
| 0x10B || counter_adc16_mult_4ormore || ROL ||
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x5bc8f90f || counter of AW coincidence triggers
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x62c77f0b || removed
|-
| 0x10D || counter_aw16_coinc_b || ROL || 0x5bc8f90f ||
|-
| 0x10E || counter_aw16_coinc_c || ROL || 0x5bc8f90f ||
|-
| 0x10F || counter_aw16_coinc_d || ROL || 0x5bc8f90f ||
|-
| 0x110 || counter_drift || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the drift time blank-out
|-
| 0x111 || counter_scaledown || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the scaledown
|-
| 0x112 || counter_aw16_coinc || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW coincidence triggers
|-
| 0x113 || counter_aw16_mlu || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW MLU triggers
|-
| 0x114 || counter_aw16_grand_or || ROL || 0x62c77f0b || counter of AW grand-or triggers
|-
| 0x114 || counter_aw16_mult_1ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 1ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 2ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x62c77f0b || removed
|-
| 0x116 || counter_aw16_mult_3ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 3ormore triggers
|-
| 0x117 || counter_aw16_mult_4ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 4ormore triggers
|-
| 0x118 || counter_bsc_grand_or || ROL || 0x5bc13541 (12Oct18_16:58) || counter of BSC grand-or triggers
|-
| 0x119 || counter_bsc_mult || ROL || 0x5bc13541 (12Oct18_16:58) || counter of old BSC multiplicity triggers
|-
| 0x11A || counter_coinc || ROL || 0x5bc13541 (12Oct18_16:58) || counter of coincidence triggers
|-
| 0x11B || counter_timeout || ROL || 0x618b790b || counter of timeout triggers
|-
| 0x11C || counter_bsc_mult_start || ROL || 0x62c77f0b || counter of BSC multiplicity windows
|-
| 0x11D || counter_bsc_mult_trig || ROL || 0x62c77f0b || counter of BSC multiplicity triggers
|-
| 0x11E || counter_coinc_start || ROL || 0x62d1b152 || counter of coincidence windows
|-
| 0x11F || counter_aw16_mlu_start || ROL || 0x62d1b152 || counter of TPC AW MLU windows
|-
| 0x200..0x207 || conf_adc16_masks || RW || all || adc16 enable bits
|-
| 0x300..0x30F || conf_adc32_masks || RW || all || adc32 enable bits
|-
| 0x400..0x41F || sas_bits[15:0][63:0] || ROL || all || sas data bits for each link
|-
| 0x420..0x42F || sas_sd_counters[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect counter for each link
|-
| 0x430..0x43F || counters_adc16_or16[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 16 counters of adc16 ORes
|-
| 0x440..0x45F || counters_adc32_or16[31:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 32 counters of adc32 ORes
|-
| 0x460..0x46F || counters_adc_selected[15:0] || ROL || 0x5bb7f6ae (05Oct18_16:41) || 16 counters for selected group of adcs, see conf_counter_adc_select
|-
| 0x470..0x4AF || counters_bsc64[63:0] || ROL || 0x5bc13541 (12Oct18_16:58) || 64 counters for the BSC bars
|-
|}

== additional registers ==

<pre>
reg | rw/ro/rol | quartus name | firmware | description
-----------------------------------------------------------------
0x60 | rw | cb_control_out | 0x618b790b | chronobox control
0x61 | rw | cb_status | 0x618b790b | chronobox status
0x62 | rw | cb_invert_a_out | 0x618b790b | chronobox input invert
0x63 | rw | cb_invert_b_out | 0x618b790b |
0x64 | rw | cb_enable_le_a_out | 0x618b790b | timestamp enable leading edge
0x65 | rw | cb_enable_le_b_out | 0x618b790b |
0x66 | rw | cb_enable_te_a_out | 0x618b790b | timestamp enable traiing edge
0x67 | rw | cb_enable_te_b_out | 0x618b790b |
0x6A | ro | cb_input_num | 0x618b790b | chronobox number of inputs
0x6B | rw | cb_sync_mask_a_out | 0x618b790b | chronobox sync signal source
0x6C | rw | cb_sync_mask_b_out | 0x618b790b |
0x6D | rw | cb_sync_reg_out | 0x618b790b | chronobox sync register
0x6E | ro | cb_sync_status | 0x618b790b | chronobox sync status
0x6F | rw | cb_latch_period_out | 0x618b790b | chronobox scalers latch period
0x70 | ro | cb_fifo_status | 0x618b790b | chronobox data fifo status
0x71 | ro | cb_fifo_data | 0x618b790b | read chronobox data fifo (cb_fifo_rdack_out <= 1)
0x72 | rw | cb_udp_period_out | 0x618b790b | period for flushing fifo to UDP
0x73 | rw | cb_udp_threshold_out | 0x618b790b | byte threshold for flushing fifo to UDP
</pre>

== conf_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_clock_select || 0x5b3aa19f (02Jul18_15:05) || select 0=internal 62.5 MHz clock or 1=esata 62.5 MHz clock
|-
| 1 || conf_enable_aw_adc16 || 0x5baedfca (28Sep18_19:13) || select source of TPC AW aw16 bus, see [[#aw16 bus]]
|-
| 2 || conf_enable_aw_adc32a || 0x5baedfca (28Sep18_19:13) ||
|-
| 3 || conf_enable_aw_adc32b || 0x5baedfca (28Sep18_19:13) ||
|-
| 15..4 || || ||
|-
| 23..16 || conf_mlu_prompt || 0x5b3aa19f (02Jul18_15:05) || MLU trigger prompt window, see [[#aw16_mlu]]
|-
| 31..24 || conf_mlu_wait || 0x5b3aa19f (02Jul18_15:05) || MLU trigger wait window, see [[#aw16_mlu]]
|-
|}

== conf_mlu bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 31 || mlu_reset || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 30 || mlu_write || 0x5b3aa19f (02Jul18_15:05) || 1=write data bit into given address
|-
| 16 || mlu_data || 0x5b3aa19f (02Jul18_15:05) || data bit for writing to MLU RAM
|-
| 15..0 || mlu_write_addr || 0x5b3aa19f (02Jul18_15:05) || MLU RAM write address for writing the data bit
|-
|}

== conf_bsc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_bsc_adc_a || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 0..7
|-
| 1 || conf_bsc_adc_b || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 8..15
|-
| 2 || conf_bsc64_bot_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses bottom channels only
|-
| 3 || conf_bsc64_top_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses top channels only
|-
| 4 || conf_bsc64_bot_top_or || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "or" of top and bottom
|-
| 5 || conf_bsc64_bot_top_and || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "and" of top and bottom
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_bsc64_mult_min || 0x5bc13541 (12Oct18_16:58) || minimum bsc64 multiplicity
|-
| 23..16 || conf_bsc64_empty_wondow || 0x62d1c47e || bsc64 empty window length, 8 ns clocks
|-
| 31..24 || conf_bsc64_mult_window || 0x62c77f0b || bsc64 multiplicity window length, 8 ns clocks
|-
|}

== conf_coinc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_coinc_required[0] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mult_1ormore
|-
| 0 || conf_coinc_required[0] || 0x62c77f0b || enable aw16_grand_or
|-
| 1 || conf_coinc_required[1] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mlu_trig
|-
| 2 || conf_coinc_required[2] || 0x5bc13541 (12Oct18_16:58) || enable bsc_grand_or_trig
|-
| 3 || conf_coinc_required[3] || 0x5bc13541 (12Oct18_16:58) || enable bsc_mult_trig
|-
| 3 || conf_coinc_required[3] || 0x62c77f0b || enable bsc64_mult_trig
|-
| 4 || conf_coinc_required[4] || 0x5bc13541 (12Oct18_16:58) || enable esata_nim_grand_or
|-
| 5 || conf_coinc_required[5]
|-
| 6 || conf_coinc_required[6]
|-
| 7 || conf_coinc_required[7]
|-
| 15..8 || conf_coinc_window[7:0] || 0x5bc13541 (12Oct18_16:58) || coincidence window length in units of 125MHz clock (8 ns)
|-
| 23..16 || conf_coinc_start[7:0] || 0x5bc13541 (12Oct18_16:58) || start the coincidence window, same bits as "required"
|-
| 31..24 ||
|-
|}

== conf_trig_enable bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_enable_sw_trigger || || trigger on software trigger (how generated???)
|-
| 1 || conf_enable_pulser || || trigger on pulser
|-
| 2 || - || 0x5b120c9f (01Jun18_20:18) || not used
|-
| 3 || conf_pulser_run || || allow the pulser to run (frequency has to be set beforehand)
|-
| 4 || conf_output_pulser || 0x5bc8f90f || does nothing (top level ag_pulser_out is disconnected)
|-
| 4 || || 0x618b790b || not used
|-
| 5 || conf_enable_esata_nim || || trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand)
|-
| 6 || conf_enable_adc16 || || trigger on adc16_grand_or
|-
| 7 || conf_enable_adc32 || || trigger on adc32_grand_or
|-
| 8 || conf_enable_adc16_1ormore || || trigger on adc16_mult_1ormore "1 or more"
|-
| 9 || conf_enable_adc16_2ormore || || same, "2 or more"
|-
| 10 || conf_enable_adc16_3ormore || || same, "3 or more"
|-
| 11 || conf_enable_adc16_4ormore || || same, "4 or more"
|-
| 12 || - || 0x5b08938c (25May18_15:51) || not used
|-
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
|-
| 14 || - || 0x5bc8f90f || not used
|-
| 15 || conf_enable_adc || 0x5b120c9f (01Jun18_20:18) || trigger on adc_grand_or
|-
| 16 || conf_enable_aw16_coinc_a || 0x5bc8f90f || enable AW coincidence trigger, see [[#aw16_coinc]]
|-
| 16 || - || 0x62c77f0b || aw16_coinc_x removed
|-
| 17 || conf_enable_aw16_coinc_b || 0x5bc8f90f ||
|-
| 18 || conf_enable_aw16_coinc_c || 0x5bc8f90f ||
|-
| 19 || conf_enable_aw16_coinc_d || 0x5bc8f90f ||
|-
| 20 || - || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 20 || conf_enable_aw16_grand_or || 0x618b790b || enable trigger on aw16_grand_or
|-
| 21 || conf_enable_aw16_coinc || 0x5b3aa19f (02Jul18_15:05) || enable trigger on aw16_coinc_trig
|-
| 22 || conf_enable_aw16_mlu || 0x5b3aa19f (02Jul18_15:05) || enable AW MLU trigger
|-
| 23 || conf_enable_timeout_trig || 0x5bc8f90f (18Oct18_14:20) || enable trigger timeout trigger
|-
| 24 || conf_enable_aw16_1ormore || 0x5b3aa19f (02Jul18_15:05) || trigger on aw16_mult_1ormore "1 or more"
|-
| 24 || - || 0x62c77f0b || aw16_mult_xxx removed
|-
| 25 || conf_enable_aw16_2ormore || 0x5b3aa19f (02Jul18_15:05) || same, "2 or more"
|-
| 26 || conf_enable_aw16_3ormore || 0x5b3aa19f (02Jul18_15:05) || same, "3 or more"
|-
| 27 || conf_enable_aw16_4ormore || 0x5b3aa19f (02Jul18_15:05) || same, "4 or more"
|-
| 28 || conf_enable_bsc_grand_or || 0x5bc13541 (12Oct18_16:58) || trigger on BSC grand-or
|-
| 29 || conf_enable_bsc_mult || 0x5bc13541 (12Oct18_16:58) || trigger on BSC multiplicity
|-
| 30 || conf_enable_coinc || 0x5bc13541 (12Oct18_16:58) || trigger on TPC/BSC/ext coincidence trigger
|-
| 31 || - || || not used
|-
|}

== reg 0x2B bits ==

Write to this register will pulse corresponding fpga signals:

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || reset_out || 0x5b120c9f (01Jun18_20:18) || reset counters, etc
|-
| 1 || latch_out || 0x5b120c9f (01Jun18_20:18) || latch counters, sas bits, etc
|-
| 2 || trigger_out || 0x5b120c9f (01Jun18_20:18) || generate a software trigger
|-
|}

= UDP data format =

== firmware 0x5bc8f90f ==

{| cellpadding="10" cellspacing="0" border="1"
! Offset || Name || Quartus name || FwRev || Description
|-
| 0 || packet counter || none || all || 31-bit UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
|-
| 1 || 0x8 packet header || || all || 28 bits of counter_trig_out
|-
| 2 || trigger timestamp || trig_ts || all || 62.5MHz trigger timestamp
|-
| 3 || accepted triggers || counter_trig_out || all || counter of accepted triggers
|-
| 4 || input triggers || counter_trig_in || all || counter of trigger input
|-
| 5 || pulser triggers || counter_pulser || all || counter of pulser triggers
|-
| 6 || trigger bitmap || udp_trig_bits || 0x5a48448d (30Dec17_17:59) || bitmap of trigger information, see below
|-
| 7 || nim bits || udp_nim_bits_masked || ??? || 32 bits of ADC NIM inputs (2 bits per ADC)
|-
| 8 || esata bits || udp_esata_bits_masked || ??? || 32 bits of ADC ESATA inputs (2 bits per ADC)
|-
| 9 || mlu bits || aw16_prompt || 0x5b398983 (01Jul18_19:10) || 16 bits of MLU input, 1 bit per preamp
|-
| 10 || drift-blank-off counter || udp_drift_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the drift blank-off
|-
| 11 || scaledown counter || udp_scaledown_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the scaledown
|-
| X || || || ||
|-
| 12 || 0xE packet footer || || all || 28 bits of counter_trig_out
|-
|}

== firmware 0x618b790b (Nov 2021) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

== firmware 0x62d1c47e (Jul 2022) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, 8'h00, 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= conf_fw_rev;
18 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

Values of udp_coinc_latch[7:0]:
* aaa

Values of udp_aw16_mult[7:0] and udp_aw16_bus[15:0]:
* aaa

Values of udp_bsc64_mult[7:0] and udp_bsc64_bus[63:0]
* aaa

== trigger bitmap ==

Firmware ??? (one of the very early revisions)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= adc16_coinc_top;
udp_trig_bits[5] <= adc16_coinc_bot;
udp_trig_bits[6] <= adc16_coinc;
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
udp_trig_bits[31:24] <= mult16[7:0];

</pre>

Firmware 0x5b08938c (25May18_15:51)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= 0; // not used
udp_trig_bits[31:24] <= mult16[7:0];
</pre>

Firmware 0x5b217dc4 (13Jun18_13:25)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5b3aa19f (02Jul18_15:05)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= udp_mlu_out;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5bc8f90f (18Oct18_14:20)

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_run_pulser
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = 0; // not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x618b790b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x62c77f0b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = 0; // aw16_coinc_a;
assign trig32_in[17] = 0; // aw16_coinc_b;
assign trig32_in[18] = 0; // aw16_coinc_c;
assign trig32_in[19] = 0; // aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = 0; // aw16_mult_1ormore;
assign trig32_in[25] = 0; // aw16_mult_2ormore;
assign trig32_in[26] = 0; // aw16_mult_3ormore;
assign trig32_in[27] = 0; // aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc64_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

= TRG chronobox inputs =

from trg_firmware/toplevel/grifc.v

<pre>
localparam CB_N = 23;
localparam CB_N1 = CB_N-1;

wire [CB_N1:0] cb_xinputs_async;

assign cb_xinputs_async[0] = ag_trig_out;
assign cb_xinputs_async[1] = ag_trig_scaledown_out;
assign cb_xinputs_async[2] = ag_trig_drift_out;
assign cb_xinputs_async[3] = ag_trig_received_out;

assign cb_xinputs_async[4] = ag_cb_sw_trig;
assign cb_xinputs_async[5] = ag_cb_pulser_trig;
assign cb_xinputs_async[6] = ag_cb_esata_nim_trig;
assign cb_xinputs_async[7] = ag_cb_adc16_grand_or_trig;
assign cb_xinputs_async[8] = ag_cb_adc32_grand_or_trig;

assign cb_xinputs_async[9] = ag_cb_aw16_grand_or_trig;
assign cb_xinputs_async[10] = ag_cb_aw16_mult_1ormore;
assign cb_xinputs_async[11] = ag_cb_aw16_mult_2ormore;
assign cb_xinputs_async[12] = ag_cb_aw16_mult_3ormore;
assign cb_xinputs_async[13] = ag_cb_aw16_mult_4ormore;
assign cb_xinputs_async[14] = ag_cb_aw16_mlu_trig;

assign cb_xinputs_async[15] = ag_cb_bsc64_grand_or_trig;
assign cb_xinputs_async[16] = ag_cb_bsc64_mult_1ormore;
assign cb_xinputs_async[17] = ag_cb_bsc64_mult_2ormore;
assign cb_xinputs_async[18] = ag_cb_bsc64_mult_3ormore;
assign cb_xinputs_async[19] = ag_cb_bsc64_mult_4ormore;
assign cb_xinputs_async[20] = ag_cb_bsc64_mult_trig;

assign cb_xinputs_async[21] = ag_cb_coinc_trig;

assign cb_xinputs_async[22] = ag_cb_timeout_trig;
</pre>

= Example UDP packets =

* trigger data, marker words 0x8

<pre>
ReadDataThread read 76
0: 0x003666ed -- UDP packet counter from UDP transmitter
1: 0x80000bf8 -- 0x8 is trigger data packet, 0xbf8 is the trigger counter from alphag.v
2: 0x2edf8b41 -- trigger data
3: 0x00000bf8
4: 0x00000bf8
5: 0x00000bee
6: 0x00000001
7: 0x00000000
8: 0x00000000
9: 0x00000003
10: 0x00000bf8
11: 0x00000bf8
12: 0x00000000
13: 0x00000000
14: 0x00000000
15: 0x00000000
16: 0x00000000
17: 0x00000000
18: 0xe0000bf8 -- 0xE is end of trigger data, counter 0xbf8 must match the counter in the 0x8 word.
ReadDataThread read 76 -- next packet
0: 0x003666ee -- UDP packet counter from UDP transmitter
...
</pre>

* chronobox fifo data, marker word 0xC, see [[Chronobox#FIFO_data_format]]

<pre>
ReadDataThread read 404
0: 0x003658ed -- UDP packet counter from UDP transmitter
1: 0xc000eacc -- 0xC is FIFO data, fifo packet counter 0xeacc from fifo_to_udp.v
2: 0x00000061 -- FIFO status, low bits the the word counter, so up to 0x61 fifo words are to follow
3: 0x87fb3d72 -- tsc hits
4: 0x8ffb3d74
5: 0x90fb3d74
6: 0x91fb3d74
7: 0x92fb3d74
8: 0x93fb3d74
9: 0x93fb3d75
10: 0x94fb3d74
11: 0x94fb3d77
12: 0x87fb3d77
13: 0x8ffb3d77
14: 0x90fb3d77
15: 0x91fb3d77
16: 0x92fb3d77
17: 0xfe000018 -- 0xFE scaler data starts, 0x18 words to follow
18: 0x00000000
19: 0x00000000
20: 0x00000000
21: 0x00000000
22: 0x00000000
23: 0x00000000
24: 0x00000000
25: 0x00000108
26: 0x00000000
27: 0x00000000
28: 0x00000000
29: 0x00000000
30: 0x00000000
31: 0x00000000
32: 0x00000000
33: 0x00000108
34: 0x00000108
35: 0x00000108
36: 0x00000108
37: 0x00000108
38: 0x00000108
39: 0x00000000
40: 0x00000000
41: 0xce56fa93 -- last word of scaler data is the sysclock counter (125 MHz)
42: 0xff800048 -- timestamp wraparound
43: 0x8f1f36e4 -- tsc hits
44: 0x901f36e4
45: 0x911f36e4
46: 0x921f36e4
47: 0x931f36e4
48: 0x941f36e4
49: 0x871f36e4
50: 0x871f36e7
51: 0x8f1f36e7
52: 0x901f36e9
53: 0x911f36e7
54: 0x921f36e9
55: 0x931f36e7
56: 0x941f36e9
57: 0x904330ac
58: 0x914330ac
59: 0x924330ac
60: 0x934330ac
61: 0x934330ad
62: 0x944330ac
63: 0x944330ad
64: 0x874330ac
65: 0x874330ad
66: 0x8f4330ac
67: 0x8f4330ad
68: 0x904330ad
69: 0x914330ad
70: 0x924330ad
71: 0x8f672a62
72: 0x90672a62
73: 0x91672a62
74: 0x92672a62
75: 0x93672a62
76: 0x94672a62
77: 0x87672a62
78: 0x87672a65
79: 0x8f672a65
80: 0x90672a65
81: 0x91672a65
82: 0x92672a65
83: 0x93672a65
84: 0x94672a65
85: 0xff000049
86: 0x878b2422
87: 0x8f8b2424
88: 0x908b2424
89: 0x918b2424
90: 0x928b2424
91: 0x938b2424
92: 0x938b2425
93: 0x948b2424
94: 0x948b2427
95: 0x878b2427
96: 0x8f8b2427
97: 0x908b2427
98: 0x918b2427
99: 0x928b2427
100: 0xe000eacc -- 0xE is end of fifo data, counter 0xeacc must match the counter in the 0xC word.
ReadDataThread read 344 -- next packet
...
</pre>

= TODO =

* DONE July 2022. add FwRev to the UDP data output
* RJ45 SFP: PROBLEM, D.A. CABLE: GOOD, Fiber SFP: ???. fix "write did not happen" (send udp write command, there is no reply, read returns old data as if write never happened). suspect udp "write" packet is lost?
* PROBLEM GONE Aug 2021. fix reply to wrong socket - udp packets should reply to same socket as they came from, udp data packets should be sent to same socket as requested them, not same socket as last command.
* DONE 2021jul30. add fixes from Chris P. for the auto-negotiation and dhcp (see email from him).
* DONE flash chip connected to FPGA. Aug 2021. implement ethernet flash programmer
* DONE Aug 2021. updated maxv firmware. implement FPGA reboot
* speed up programming the MLU by writing more than 1 bit at a time
* DONE Nov 2021. add 64-bit bitmap of BSC trigger bits
* DONE. add chronobox code
* DONE. add avalon mux for alphag and chronobox packets
* DONE. add chronobox fifo to udp packet sequencer
* check that TxReadyOut is correct and it is safe to send an avalon packet while previous packet is still transmitting.
* DONE. test fiber SFP is working
* complete the UDP flash programmer (parallel flash erase and write)

= End =

//KO

TRG

2022-07-16T22:18:24Z

Olchansk: /* Firmware revisions */

= TRG, the trigger control board for the ALPHA-g detector =

= Links =

* xxx
* https://bitbucket.org/expalpha/trg_firmware - firmware sources on bitbucket

= General characteristics =

== Photos ==

== Board schematics ==

* https://bitbucket.org/expalpha/trg_firmware/src/master/3xFMC_VME_Motherboard.pdf

== Available hardware ==

* Altera Stratix IV - main FPGA
* Altera Max V - boot FPGA
* boot flash: PC28F512M29EW - 512 Mbit parallel NOR flash.

= TRG front panel connections =

From top to bottom:

<pre>
|
| minisas-C - links 8-11
| minisas-D - links 12-15
|
| ethernet sfp - use copper sfp only
| minisas - not used, do not connect
| esata - clock in, trigger out
|
| minisas-A - links 0-3
| minisas-B - links 4-7
|
| LEDs
|
</pre>

MiniSAS and SATA flail cable connections:

<pre>
P1 <--> link 3
P2 <--> link 2
P3 <--> link 1
P4 <--> link 0
</pre>

LEDs:

<pre>
--PCB-- (left)
LED[0] - trigger out - ag_trig_out
LED[1] - network packet received - sfp_rx_data_valid
LED[2] - Xilinx FPGA boot ok - FMC1_CFG_DONE
LED[3] - not used
(right)
</pre>

= TRG onboard jumpers and switches =

* rotary switches: select IP address: 00=192.168.1.50, 11=.51, 22=.52, 33=.53, 44=.54, otherwire=.251

= Firmware update procedure =

* use quartus to generate the grifc.pof file (use grifc.cof)
* open quartus programmer
* attach grifc.pof to the 1st CFI_512 flash
* mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
* check that "initiate configuration after programming" is set in tools->options
* say "start"
* should take about 5 minutes
* grifc should reboot into the new firmware

If CFI_512 flash is not visible to the quartus programmer, load correct
code into the MaxV CPLD:

* open quartus programmer,
* say "auto detect"
* change file for the 5M2210 device
* use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
* say "program", it should finish in 10-15 seconds
* say "auto detect"
* CFI_512 flash should be visible now.

= Firmware revisions =

* 0x5bc8f90f - original firmware used for all data
* 0x6147c0f9 - added cbtrg, etc. installed at CERN on 20 Sep 2021.
* 0x618376ae - bigger cbtrg fifo, data rate tested up to 30 Mbytes/sec
* 0x6189c7f3 - fix loss of trigger packets. (missing fifo between alphag block and ethernet mux)
* 0x618b790b - fix loss of timestamps. (cbtrg inputs stretched to 100 ns long). installed at CERN 10 Nov 2021.
* 0x62d32d95 - updated cbtrg, switched to edge-triggered cbtrg inputs, improved BSC multiplicity trigger, improved coinc trigger, added burst pulser.

= Firmware build =

* use quartus 20.1
* see Makefile in the trg_firmware project

= Jtag remote connection =

* ssh agmini@daq16
* /opt/intelFPGA/16.1/quartus/bin/jtagd --config /home/agmini/.jtagd.conf
* netstat -an | grep 1309 ### note listen address is "0.0.0.0", NOT "127.0.0.1"
<pre>
tcp 0 0 0.0.0.0:1309 0.0.0.0:* LISTEN
</pre>
* opt/intelFPGA/16.1/quartus/bin/jtagconfig ### should work
* ssh olchansk@daq01
* cd git/trg_firmware
* /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
* jtagconfig ### should work
<pre>
daq01:trg_firmware$ jtagconfig
1) DE-SoC on daq16 [2-1.2.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) USB-Blaster on daq16 [2-1.3]
024090DD EP4SGX230(.|ES)
020A40DD 5M(1270ZF324|2210Z)/EPM2210

daq01:trg_firmware$
</pre>

= ALPHA-g trigger functions =

Trigger options:
* software trigger
* pulser trigger
* trigger on GRIF16 ADC NIM and ESATA inputs ("external trigger")
* adc16 grand-or
* adc32 grand-or
* adc16 wire multiplicity
* TPC anode wire per-preamp trigger (aw16 section)
** trigger on coincidences of preamps (removed fw 0x62c77f0b)
** trigger on multiplicity of preamps (removed fw 0x62c77f0b)
** trigger on specific topology of preamps (multiplicity of preamp clusters, etc) via the aw16_mlu trigger
* BSC trigger
** BSC grand_or
** BSC bar multiplicity
* coincidence trigger - select coincidence of external trigger, TPC AW grand-or, TPC AW MLU, BSC grand-or and BSC bar multiplicity triggers

== software trigger ==

to programmatically fire the trigger, one should:
* set the conf_enable_sw_trigger bit in conf_trig_enable, this will permit the software trigger to fire the trigger
* write value 0x4 to register 0x2B, this will cause the software trigger to fire

== pulser trigger ==

To use the pulser trigger, one should program:
* pulser period (in clocks)
* pulser width (in clocks, use value 5, the pulser no longer goes outside of the trigger board, so changing the width does not do anything)
* set the run_pulser bit in conf_trig_enable, this will cause the pulser to run
* set the enable_pulser bit in conf_trig_enable, this will cause the pulser to fire the trigger
* set the output_pulser bit in conf_trig_enable, this will cause the pulser to be output from the alphag firmware block (the pulser no longer goes outside of the trigger board, so changing the bit does not do anything)

== timeout trigger ==

The event builder uses event timestamps to assemble physics events. The timestamps
are usually 32 bit wide and run at 125 MHz (8 ns) or 62.5 MHz (16 ns). If
triggers are generated often (1 per second or more), timestamp wrap around
is easily detected by the event builder. If triggers come infrequently,
timestamp wrap around may occur while there are no triggers, not be seen
by the event builder causing loss of event synchronization.

To avoid this problem in the event builder, a timeout trigger should be generated
if no triggers were generated inside a 10 second interval.

The guaranties that even if all physics triggers temporarily stop for any reason,
the event builder will stay synchronized. (0.1 Hz timeout trigger frequency).

To enable the timeout trigger:
* program timeout trigger timeout in reg 0x43 in units of 8 ns clock
* enable it in bit 23 of [[#conf_trig_enable bits]]

== adc16 multiplicity trigger ==

This trigger is intended for use with the barrel scintillator signals connected to adc16 digitizers. It does not work well with TPC AW signals.

The 16 adc16 trigger bits (16x16=256) are added together to form the hit multiplicity value (adc16_mult, 16 bits, actual range 0 to 256).

Four threshold signals are computed: adc16_mult_1ormore = adc16_mult>=1, 2ormore, 3ormore, 4ormore.

There is a counter for each of these four signals.

Each of these four signals can fire the trigger, see [[#conf_trig_enable bits]].

== TPC anode wire triggers ==

=== aw16 bus ===

TPC Anode Wire trigger is based on the aw16[15:0] (xaw16) bus.

Each bit corresponds to one AW preamp. 16 preamps, 16 bits.

The aw16[15:0] bus can be fed by
* adc16_or16[15:0] - or16 of 100 MHz ADCs, 16 ADC sas links
* adc32_or16[15:0] - or16 of 62.5 MHz ADCs, FMC-ADC32 has 32 channels, so 2 bits per ADC: low 16 channels and high 16 channels, sas links 7..0
* adc32_or16[31:16] - or16 of 62.5 MHz ADCs, ditto, sas links 15..8
as selected by conf_enable_aw_adc16, conf_enable_aw_adc32a, conf_enable_aw_adc32b in [[#conf_control bits]]

<pre>
///////////////////////////////////////////////////////////
// TPC Anode Wire trigger logic (aw16)
///////////////////////////////////////////////////////////

// map adc signals into aw16

wire [15:0] aw16 = ({16{conf_enable_aw_adc16}} & adc16_or16[15:0]) |
({16{conf_enable_aw_adc32a}} & adc32_or16[15:0]) |
({16{conf_enable_aw_adc32b}} & adc32_or16[31:16]);
...
ag_conditioner cond_adc16_or16_0(.clk(clk), .in(aw16[0]), .out(xxaw16[0]));
...
xaw16 <= xxaw16;
</pre>

=== aw16_grand_or ===

TPC AW "grand or" trigger: use aw16_mult_1ormore (before fw 0x62c77f0b)

(256 anode wires, 16 wires per preamp, 16 preamps, 16 aw16 signals)

=== aw16_mlu ===

TPC AW preamp MLU trigger: the MLU (memory lookup
table) implements an arbitrary logical function
to map the 16 aw16 preamp signals into 1 aw16_mlu_trig trigger output.

Description of the aw16 mlu trigger.

In words:

* any aw16 signal starts the aw16_prompt_run gate
* aw16 signals are collected for the duration of conf_mlu_prompt (125MHz/8ns clock)
* this corresponds to time spread of TPC AW signals due to the drift time in the AW drift cell and to the variation in signal transmission time from the ADC to the TRG (digital trigger data link).
* when this prompt time expires, the MLU looks at the accumulated aw16_prompt bit pattern and makes the "yes/no" trigger decision
* after the trigger decision is made, we wait for the TPC to become quiet:
* we wait until all aw16 signals are empty (no timeout)
* we run the aw16_prompt_wait gate, length conf_mlu_wait (8ns clock), if any aw16 signals arrive, we wait for aw16 empty again, rinse, repeat.
* now, after TPC aw16 have been empty for conf_mlu_wait clocks (8ns clock), MLU trigger is ready for the next event.

In logic: (see alphag.v)

* aw16_or <= grand-or of 16 aw16 signals
* "aw16_or" starts the "aw16_prompt_cnt" counter, opens the aw16_prompt_run gate
* during the aw16_prompt_run gate, aw16_prompt collects (latches) the aw16 bits (aw16_prompt <= aw16_prompt | aw16)
* this is the time when we wait for all "prompt" signals from the TPC to arrive into the trigger
* at the end of the aw16_prompt_run gate, the signal aw16_prompt_out is pulsed, latching the output of the MLU into aw16_mlu_trig
* this is the MLU trigger "yes/no" trigger decision.
* after the MLU trigger decision is made, we wait for the arrival and passing of all TPC drift signals
* the aw16_prompt_wait_cnt and aw_prompt_wait gate opens
* if any new aw16 signals arrive (they are TPC drift signals at this time), the aw16_prompt_wait gate is restarted
* if no aw16 signals arrive during the full run of the aw16_prompt_wait gate ("TPC quiet time")
* the aw16_prompt_wait and aw16_prompt gates are cleared and the MLU trigger is ready for the next event.

Good settings are:
* conf_mlu_prompt: 64 (512 ns)
* conf_mlu_wait: 128 (1024 ns)

== BSC trigger ==

=== bsc_adc16 bus ===

The BSC trigger is based on the [15:0]bsc_adc16[7:0] bus: 16 trigger discriminator bits from 8 ADC sas links. (8*16 = 64+64 bars, top and bottom).

The bsc_adc16 bus can be fed from sas links 0..7 or 8..15, controlled by conf_bsc_adc16_a and conf_bsc_adc16_b bits on [[#conf_bsc_control bits]].

bsc_adc16 can be fed only from GRIF-16 100 MHz ADC trigger discriminators.

=== bsc64_top and bsc64_bot buses ===

* firmware 0x5bc8f90f: bsc_adc16 is remapped into 64 bits of top (bsc64_top) and bottom (bsc64_bot):
<pre>
ag_bsc_remap bsc_remap_a(.adc(bsc_adc16[0]), .bsc_bot(bsc64_bot[7:0]), .bsc_top(bsc64_top[7:0]));
ag_bsc_remap bsc_remap_b(.adc(bsc_adc16[1]), .bsc_bot(bsc64_bot[8+7:8+0]), .bsc_top(bsc64_top[8+7:8+0]));
ag_bsc_remap bsc_remap_c(.adc(bsc_adc16[2]), .bsc_bot(bsc64_bot[2*8+7:2*8+0]), .bsc_top(bsc64_top[2*8+7:2*8+0]));
ag_bsc_remap bsc_remap_d(.adc(bsc_adc16[3]), .bsc_bot(bsc64_bot[3*8+7:3*8+0]), .bsc_top(bsc64_top[3*8+7:3*8+0]));

ag_bsc_remap bsc_remap_e(.adc(bsc_adc16[4]), .bsc_bot(bsc64_bot[4*8+7:4*8+0]), .bsc_top(bsc64_top[4*8+7:4*8+0]));
ag_bsc_remap bsc_remap_f(.adc(bsc_adc16[5]), .bsc_bot(bsc64_bot[5*8+7:5*8+0]), .bsc_top(bsc64_top[5*8+7:5*8+0]));
ag_bsc_remap bsc_remap_g(.adc(bsc_adc16[6]), .bsc_bot(bsc64_bot[6*8+7:6*8+0]), .bsc_top(bsc64_top[6*8+7:6*8+0]));
ag_bsc_remap bsc_remap_h(.adc(bsc_adc16[7]), .bsc_bot(bsc64_bot[7*8+7:7*8+0]), .bsc_top(bsc64_top[7*8+7:7*8+0]));

module ag_bsc_remap
(
input wire [15:0] adc,
output wire [7:0] bsc_bot,
output wire [7:0] bsc_top
);

assign bsc_top[3] = adc[0];
assign bsc_top[2] = adc[1];
assign bsc_top[1] = adc[2];
assign bsc_top[0] = adc[3];

assign bsc_top[7] = adc[4];
assign bsc_top[6] = adc[5];
assign bsc_top[5] = adc[6];
assign bsc_top[4] = adc[7];

assign bsc_bot[0] = adc[8];
assign bsc_bot[1] = adc[9];
assign bsc_bot[2] = adc[10];
assign bsc_bot[3] = adc[11];

assign bsc_bot[4] = adc[12];
assign bsc_bot[5] = adc[13];
assign bsc_bot[6] = adc[14];
assign bsc_bot[7] = adc[15];

endmodule
</pre>

=== bsc64 bus ===

the bsc64 bus is the 64 bars used by the trigger, formed from bsc64_top and bsc64_bot:
<pre>
if (conf_bsc64_bot_only) begin
bsc64 <= bsc64_bot;
end else if (conf_bsc64_top_only) begin
bsc64 <= bsc64_top;
end else if (conf_bsc64_bot_top_or) begin
bsc64 <= bsc64_bot | bsc64_top;
end else if (conf_bsc64_bot_top_and) begin
bsc64 <= bsc64_bot & bsc64_top;
end else begin
bsc64 <= 64'b0;
end
</pre>

=== bsc_grand_or_trig ===

bsc_grand_or_trig is the grand-or of 64 bits of the bsc64 bus

to enable triggering on bsc_grand_or_trig, set corresponding bit in [[#conf_trig_enable bits]]

=== old bsc_mult_trig ===

(from fw 0x62c77f0b, old bsc_mult_trig was replaced by new bsc64 multiplicity trigger)

* bsc64_mult is computed as multiplicity of the bsc64 bus (number of 64 bsc64 bits that fired)
* bsc_mult_trig is computed:
<pre>
if (bsc64_mult >= conf_bsc64_mult) begin
bsc_mult_trig <= 1;
end else begin
bsc_mult_trig <= 0;
end
</pre>

to enable the bsc multiplicity trigger, set the multiplicity value conf_bsc64_mult in [[#conf_bsc_control bits]] and enable the corresponding bit in [[#conf_trig_enable bits]].

=== bsc64 multiplicity trigger ===

bsc64 BSC bar multiplicity trigger uses a time window. this time window is started by bsc64_grand_or and runs for conf_bsc64_mult_window clocks (8 nc clock). During this time, hits in bsc64_bus are accumulated (latched) and their multiplicity is computed. If multiplicity condition is satisfied (bigger or equal to conf_bsc64_mult_min), bsc64_mult_trig is fired and the bsc64 bit pattern is saved to the UDP packet. Then trigger waits for the bsc64_bus to be empty. Then trigger waits for conf_bsc64_empty_window clocks, if there is any bsc64 hits, we wait for empty again. So after bsc64 has been empty for conf_bsc64_empty_window clocks, multiplicity trigger is ready for the next event. This scheme cannot implement max multiplicity.

recommended values:
* conf_bsc64_mult_window (8 bits): slightly longer than 3 cycles of SAS link: 3*18 = 54 clocks, good value is 80 (640 ns).
* conf_bsc64_mult_min (8 bits): 2
* conf_bsc64_empty_window (8 bits): 80 (640 ns)

== Coincidence trigger ==

Coincidence trigger provides a combination of TPC, BSC and external scintillator (esata_nim_grand_or) signals:

<pre>
assign coinc_input[0] = aw16_grand_or; // was aw16_mult_1ormore;
assign coinc_input[1] = aw16_mlu_trig;
assign coinc_input[2] = bsc_grand_or_trig;
assign coinc_input[3] = bsc_mult_trig;
assign coinc_input[4] = esata_nim_grand_or;
assign coinc_input[5] = 0;
assign coinc_input[6] = 0;
assign coinc_input[7] = 0;
</pre>

Coincidence trigger "start" mask selects which of the inputs can start the coincidence window.

Coincidence trigger "require" mask selects which inputs must have a hits for the coincidence to be satisfied.

Input hits are collected for the duration of the coincidence window, if all required inputs have hits, coinc_trig is fired.

Example settings:

* coincidence of external scintillator, BSC and TPC AW "grand or" signals: start 0x10, required 0x15
* coincidence of BSC grand-or and TPC AW grand-or signals: start 0x5, required 0x5
* coincidence of BSC multiplicity and TPC AW grand-or triggers: start 0x9, required 0x9

= Control registers =

== Register addresses ==

Note: all registers are 32 bits unless otherwise noted.

Note: RW means read-write register, RO means read-only, ROL means read-only, contents is latched by the "latch_out" bit

{| cellpadding="10" cellspacing="0" border="1"
! Address || Quartus Name || Access || FwRev || Description
|-
| 0x08 || num_sample || RW || GRIF-C || magic 16-bit register to control UDP packet size
|-
| 0x08 || scratch_reg || RW || 0x618b790b || 32-bit scratch register
|-
| 0x1F || compilation_time || RO || || Firmware revision
|-
| 0x20 || conf_trig_width || RW || || Trigger signal width, 16 ns clock
|-
| 0x21 || conf_busy_width || RW || || Busy signal width, 16 ns clock (not used)
|-
| 0x22 || conf_pulser_width || RW || || Pulser signal width, 16 ns clock
|-
| 0x23 || conf_pulser_period || RW || || Pulser signal period, 16 ns clock
|-
| 0x24 || conf_pulser_burst_ctrl || RW || 0x62d1c47e || Generate bursts of pulses: 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses, 16 ns clocks
|-
| 0x25 || conf_trig_enable || RW || || see [[#conf_trig_enable bits]]
|-
| 0x26 || || || not used
|-
| 0x27 || || || not used
|-
| 0x28 || || || not used
|-
| 0x29 || conf_nim_mask || RW || || enable bits for ADC NIM inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2A || conf_esata_mask || RW || || enable bits for ADC eSATA inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2B || reset_out, latch_out, trigger_out || W || || see [[#reg 0x2B bits]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x5bc8f90f || configure AW coincidence trigger, see [[#aw16_coinc]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x62c77f0b || removed
|-
| 0x2D || conf_aw16_coinc_b || RW || 0x5bc8f90f ||
|-
| 0x2E || conf_aw16_coinc_c || RW || 0x5bc8f90f ||
|-
| 0x2F || conf_aw16_coinc_d || RW || 0x5bc8f90f ||
|-
| 0x30 || sas_sd[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect for each link
|-
| 0x31 || pll_625_status || ROL || 0x5b2057f5 (12Jun18_16:32) || 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter
|-
| 0x32 || clk_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the system 125 MHz clock
|-
| 0x33 || clk_625_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625)
|-
| 0x34 || conf_control || RW || 0x5b398983 (01Jul18_19:10) || see [[#conf_control bits]] below
|-
| 0x35 || conf_drift_width || RW || 0x5b398983 (01Jul18_19:10) || width of drift time blank-out in 16 ns clocks
|-
| 0x36 || conf_scaledown || RW || 0x5b398983 (01Jul18_19:10) || trigger scaledown, 0=no scaledown, 1=divide-by-2, 2=divide-by-3, etc
|-
| 0x37 || conf_mlu || RW || 0x5b398983 (01Jul18_19:10) || AW MLU control bits, see [[#conf_mlu bits]]
|-
| 0x38 || conf_trig_delay || RW || 0x5baedfca (28Sep18_19:13) || delay the trigger pulse, 16 ns clock
|-
| 0x39 || esata_clk_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the TRG 125 MHz clock
|-
| 0x3A || esata_clk_esata_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the external clock (eSATA 62.5 MHz clock)
|-
| 0x3B || conf_counter_adc_select || RW || 0x5bb7f6ae (05Oct18_16:41) || select which 16 ADCs are connected to the selected adc counters, 0..15 - connect the adc16 signals, 16..47 connect the adc32 signals
|-
| 0x3C || sysreset_ts || RO || 0x5bb7f6ae (05Oct18_16:41) || 125MHz counter of VME-SYSRESET
|-
| 0x3C || || || 0x618b790b || not used
|-
| 0x3D || GRIF-C csr || RW || GRIF-C || <= csr & ~par_value; // Selective clear
|-
| 0x3E || GRIF-C csr || RW || GRIF-C || <= csr | par_value; // Selective set
|-
| 0x3F || GRIF-C csr || RW || GRIF-C || <= par_value; // write
|-
| 0x3D || || || 0x618b790b || not used
|-
| 0x3E || || || 0x618b790b || not used
|-
| 0x3F || || || 0x618b790b || not used
|-
| 0x40 || conf_bsc_control || RW || 0x5bc13541 (12Oct18_16:58) || Barrel Scintillator trigger control, see [[#conf_bsc_control bits]]
|-
| 0x41 || conf_coinc_control || RW || 0x5bc13541 (12Oct18_16:58) || Coincidence trigger control, see [[#conf_coinc_control bits]]
|-
| 0x42 || reconfig_out || WO || 0x5bc13541 (12Oct18_16:58) || reserved for rebooting the FPGA (does not work)
|-
| 0x43 || conf_trigger_timeout || RW || 0x5bc8f90f (18Oct18_14:20) || Generate timeout trigger if there is no other trigger after given timeout, in 8 ns clocks, must be enabled by bit conf_enable_timeout_trig in [[#conf_trig_enable bits]]
|-
| 0x44 || eth_clk_counter || ROL || 0x618b790b ||
|-
| 0x45 || eth_clk_eth_counter || ROL || 0x618b790b ||
|-
| 0x100 || ts_625 || ROL || || latched timestamp
|-
| 0x101 || counter_trig_out || ROL || || counter of issued triggers
|-
| 0x102 || counter_trig_in || ROL || || counter of triggers
|-
| 0x103 || counter_pulser || ROL || || counter of pulser
|-
| 0x104 || counter_adc16_grand_or || ROL ||
|-
| 0x105 || counter_adc32_grand_or || ROL ||
|-
| 0x106 || counter_adc_grand_or || ROL ||
|-
| 0x107 || counter_esata_nim_grand_or || ROL ||
|-
| 0x108 || counter_adc16_mult_1ormore || ROL ||
|-
| 0x109 || counter_adc16_mult_2ormore || ROL ||
|-
| 0x10A || counter_adc16_mult_3ormore || ROL ||
|-
| 0x10B || counter_adc16_mult_4ormore || ROL ||
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x5bc8f90f || counter of AW coincidence triggers
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x62c77f0b || removed
|-
| 0x10D || counter_aw16_coinc_b || ROL || 0x5bc8f90f ||
|-
| 0x10E || counter_aw16_coinc_c || ROL || 0x5bc8f90f ||
|-
| 0x10F || counter_aw16_coinc_d || ROL || 0x5bc8f90f ||
|-
| 0x110 || counter_drift || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the drift time blank-out
|-
| 0x111 || counter_scaledown || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the scaledown
|-
| 0x112 || counter_aw16_coinc || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW coincidence triggers
|-
| 0x113 || counter_aw16_mlu || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW MLU triggers
|-
| 0x114 || counter_aw16_grand_or || ROL || 0x62c77f0b || counter of AW grand-or triggers
|-
| 0x114 || counter_aw16_mult_1ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 1ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 2ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x62c77f0b || removed
|-
| 0x116 || counter_aw16_mult_3ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 3ormore triggers
|-
| 0x117 || counter_aw16_mult_4ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 4ormore triggers
|-
| 0x118 || counter_bsc_grand_or || ROL || 0x5bc13541 (12Oct18_16:58) || counter of BSC grand-or triggers
|-
| 0x119 || counter_bsc_mult || ROL || 0x5bc13541 (12Oct18_16:58) || counter of old BSC multiplicity triggers
|-
| 0x11A || counter_coinc || ROL || 0x5bc13541 (12Oct18_16:58) || counter of coincidence triggers
|-
| 0x11B || counter_timeout || ROL || 0x618b790b || counter of timeout triggers
|-
| 0x11C || counter_bsc_mult_start || ROL || 0x62c77f0b || counter of BSC multiplicity windows
|-
| 0x11D || counter_bsc_mult_trig || ROL || 0x62c77f0b || counter of BSC multiplicity triggers
|-
| 0x11E || counter_coinc_start || ROL || 0x62d1b152 || counter of coincidence windows
|-
| 0x11F || counter_aw16_mlu_start || ROL || 0x62d1b152 || counter of TPC AW MLU windows
|-
| 0x200..0x207 || conf_adc16_masks || RW || all || adc16 enable bits
|-
| 0x300..0x30F || conf_adc32_masks || RW || all || adc32 enable bits
|-
| 0x400..0x41F || sas_bits[15:0][63:0] || ROL || all || sas data bits for each link
|-
| 0x420..0x42F || sas_sd_counters[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect counter for each link
|-
| 0x430..0x43F || counters_adc16_or16[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 16 counters of adc16 ORes
|-
| 0x440..0x45F || counters_adc32_or16[31:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 32 counters of adc32 ORes
|-
| 0x460..0x46F || counters_adc_selected[15:0] || ROL || 0x5bb7f6ae (05Oct18_16:41) || 16 counters for selected group of adcs, see conf_counter_adc_select
|-
| 0x470..0x4AF || counters_bsc64[63:0] || ROL || 0x5bc13541 (12Oct18_16:58) || 64 counters for the BSC bars
|-
|}

== additional registers ==

<pre>
reg | rw/ro/rol | quartus name | firmware | description
-----------------------------------------------------------------
0x60 | rw | cb_control_out | 0x618b790b | chronobox control
0x61 | rw | cb_status | 0x618b790b | chronobox status
0x62 | rw | cb_invert_a_out | 0x618b790b | chronobox input invert
0x63 | rw | cb_invert_b_out | 0x618b790b |
0x64 | rw | cb_enable_le_a_out | 0x618b790b | timestamp enable leading edge
0x65 | rw | cb_enable_le_b_out | 0x618b790b |
0x66 | rw | cb_enable_te_a_out | 0x618b790b | timestamp enable traiing edge
0x67 | rw | cb_enable_te_b_out | 0x618b790b |
0x6A | ro | cb_input_num | 0x618b790b | chronobox number of inputs
0x6B | rw | cb_sync_mask_a_out | 0x618b790b | chronobox sync signal source
0x6C | rw | cb_sync_mask_b_out | 0x618b790b |
0x6D | rw | cb_sync_reg_out | 0x618b790b | chronobox sync register
0x6E | ro | cb_sync_status | 0x618b790b | chronobox sync status
0x6F | rw | cb_latch_period_out | 0x618b790b | chronobox scalers latch period
0x70 | ro | cb_fifo_status | 0x618b790b | chronobox data fifo status
0x71 | ro | cb_fifo_data | 0x618b790b | read chronobox data fifo (cb_fifo_rdack_out <= 1)
0x72 | rw | cb_udp_period_out | 0x618b790b | period for flushing fifo to UDP
0x73 | rw | cb_udp_threshold_out | 0x618b790b | byte threshold for flushing fifo to UDP
</pre>

== conf_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_clock_select || 0x5b3aa19f (02Jul18_15:05) || select 0=internal 62.5 MHz clock or 1=esata 62.5 MHz clock
|-
| 1 || conf_enable_aw_adc16 || 0x5baedfca (28Sep18_19:13) || select source of TPC AW aw16 bus, see [[#aw16 bus]]
|-
| 2 || conf_enable_aw_adc32a || 0x5baedfca (28Sep18_19:13) ||
|-
| 3 || conf_enable_aw_adc32b || 0x5baedfca (28Sep18_19:13) ||
|-
| 15..4 || || ||
|-
| 23..16 || conf_mlu_prompt || 0x5b3aa19f (02Jul18_15:05) || MLU trigger prompt window, see [[#aw16_mlu]]
|-
| 31..24 || conf_mlu_wait || 0x5b3aa19f (02Jul18_15:05) || MLU trigger wait window, see [[#aw16_mlu]]
|-
|}

== conf_mlu bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 31 || mlu_reset || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 30 || mlu_write || 0x5b3aa19f (02Jul18_15:05) || 1=write data bit into given address
|-
| 16 || mlu_data || 0x5b3aa19f (02Jul18_15:05) || data bit for writing to MLU RAM
|-
| 15..0 || mlu_write_addr || 0x5b3aa19f (02Jul18_15:05) || MLU RAM write address for writing the data bit
|-
|}

== conf_bsc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_bsc_adc_a || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 0..7
|-
| 1 || conf_bsc_adc_b || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 8..15
|-
| 2 || conf_bsc64_bot_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses bottom channels only
|-
| 3 || conf_bsc64_top_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses top channels only
|-
| 4 || conf_bsc64_bot_top_or || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "or" of top and bottom
|-
| 5 || conf_bsc64_bot_top_and || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "and" of top and bottom
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_bsc64_mult_min || 0x5bc13541 (12Oct18_16:58) || minimum bsc64 multiplicity
|-
| 23..16 || conf_bsc64_empty_wondow || 0x62d1c47e || bsc64 empty window length, 8 ns clocks
|-
| 31..24 || conf_bsc64_mult_window || 0x62c77f0b || bsc64 multiplicity window length, 8 ns clocks
|-
|}

== conf_coinc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_coinc_required[0] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mult_1ormore
|-
| 0 || conf_coinc_required[0] || 0x62c77f0b || enable aw16_grand_or
|-
| 1 || conf_coinc_required[1] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mlu_trig
|-
| 2 || conf_coinc_required[2] || 0x5bc13541 (12Oct18_16:58) || enable bsc_grand_or_trig
|-
| 3 || conf_coinc_required[3] || 0x5bc13541 (12Oct18_16:58) || enable bsc_mult_trig
|-
| 3 || conf_coinc_required[3] || 0x62c77f0b || enable bsc64_mult_trig
|-
| 4 || conf_coinc_required[4] || 0x5bc13541 (12Oct18_16:58) || enable esata_nim_grand_or
|-
| 5 || conf_coinc_required[5]
|-
| 6 || conf_coinc_required[6]
|-
| 7 || conf_coinc_required[7]
|-
| 15..8 || conf_coinc_window[7:0] || 0x5bc13541 (12Oct18_16:58) || coincidence window length in units of 125MHz clock (8 ns)
|-
| 23..16 || conf_coinc_start[7:0] || 0x5bc13541 (12Oct18_16:58) || start the coincidence window, same bits as "required"
|-
| 31..24 ||
|-
|}

== conf_trig_enable bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_enable_sw_trigger || || trigger on software trigger (how generated???)
|-
| 1 || conf_enable_pulser || || trigger on pulser
|-
| 2 || - || 0x5b120c9f (01Jun18_20:18) || not used
|-
| 3 || conf_pulser_run || || allow the pulser to run (frequency has to be set beforehand)
|-
| 4 || conf_output_pulser || 0x5bc8f90f || does nothing (top level ag_pulser_out is disconnected)
|-
| 4 || || 0x618b790b || not used
|-
| 5 || conf_enable_esata_nim || || trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand)
|-
| 6 || conf_enable_adc16 || || trigger on adc16_grand_or
|-
| 7 || conf_enable_adc32 || || trigger on adc32_grand_or
|-
| 8 || conf_enable_adc16_1ormore || || trigger on adc16_mult_1ormore "1 or more"
|-
| 9 || conf_enable_adc16_2ormore || || same, "2 or more"
|-
| 10 || conf_enable_adc16_3ormore || || same, "3 or more"
|-
| 11 || conf_enable_adc16_4ormore || || same, "4 or more"
|-
| 12 || - || 0x5b08938c (25May18_15:51) || not used
|-
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
|-
| 14 || - || 0x5bc8f90f || not used
|-
| 15 || conf_enable_adc || 0x5b120c9f (01Jun18_20:18) || trigger on adc_grand_or
|-
| 16 || conf_enable_aw16_coinc_a || 0x5bc8f90f || enable AW coincidence trigger, see [[#aw16_coinc]]
|-
| 16 || - || 0x62c77f0b || aw16_coinc_x removed
|-
| 17 || conf_enable_aw16_coinc_b || 0x5bc8f90f ||
|-
| 18 || conf_enable_aw16_coinc_c || 0x5bc8f90f ||
|-
| 19 || conf_enable_aw16_coinc_d || 0x5bc8f90f ||
|-
| 20 || - || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 20 || conf_enable_aw16_grand_or || 0x618b790b || enable trigger on aw16_grand_or
|-
| 21 || conf_enable_aw16_coinc || 0x5b3aa19f (02Jul18_15:05) || enable trigger on aw16_coinc_trig
|-
| 22 || conf_enable_aw16_mlu || 0x5b3aa19f (02Jul18_15:05) || enable AW MLU trigger
|-
| 23 || conf_enable_timeout_trig || 0x5bc8f90f (18Oct18_14:20) || enable trigger timeout trigger
|-
| 24 || conf_enable_aw16_1ormore || 0x5b3aa19f (02Jul18_15:05) || trigger on aw16_mult_1ormore "1 or more"
|-
| 24 || - || 0x62c77f0b || aw16_mult_xxx removed
|-
| 25 || conf_enable_aw16_2ormore || 0x5b3aa19f (02Jul18_15:05) || same, "2 or more"
|-
| 26 || conf_enable_aw16_3ormore || 0x5b3aa19f (02Jul18_15:05) || same, "3 or more"
|-
| 27 || conf_enable_aw16_4ormore || 0x5b3aa19f (02Jul18_15:05) || same, "4 or more"
|-
| 28 || conf_enable_bsc_grand_or || 0x5bc13541 (12Oct18_16:58) || trigger on BSC grand-or
|-
| 29 || conf_enable_bsc_mult || 0x5bc13541 (12Oct18_16:58) || trigger on BSC multiplicity
|-
| 30 || conf_enable_coinc || 0x5bc13541 (12Oct18_16:58) || trigger on TPC/BSC/ext coincidence trigger
|-
| 31 || - || || not used
|-
|}

== reg 0x2B bits ==

Write to this register will pulse corresponding fpga signals:

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || reset_out || 0x5b120c9f (01Jun18_20:18) || reset counters, etc
|-
| 1 || latch_out || 0x5b120c9f (01Jun18_20:18) || latch counters, sas bits, etc
|-
| 2 || trigger_out || 0x5b120c9f (01Jun18_20:18) || generate a software trigger
|-
|}

= UDP data format =

== firmware 0x5bc8f90f ==

{| cellpadding="10" cellspacing="0" border="1"
! Offset || Name || Quartus name || FwRev || Description
|-
| 0 || packet counter || none || all || 31-bit UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
|-
| 1 || 0x8 packet header || || all || 28 bits of counter_trig_out
|-
| 2 || trigger timestamp || trig_ts || all || 62.5MHz trigger timestamp
|-
| 3 || accepted triggers || counter_trig_out || all || counter of accepted triggers
|-
| 4 || input triggers || counter_trig_in || all || counter of trigger input
|-
| 5 || pulser triggers || counter_pulser || all || counter of pulser triggers
|-
| 6 || trigger bitmap || udp_trig_bits || 0x5a48448d (30Dec17_17:59) || bitmap of trigger information, see below
|-
| 7 || nim bits || udp_nim_bits_masked || ??? || 32 bits of ADC NIM inputs (2 bits per ADC)
|-
| 8 || esata bits || udp_esata_bits_masked || ??? || 32 bits of ADC ESATA inputs (2 bits per ADC)
|-
| 9 || mlu bits || aw16_prompt || 0x5b398983 (01Jul18_19:10) || 16 bits of MLU input, 1 bit per preamp
|-
| 10 || drift-blank-off counter || udp_drift_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the drift blank-off
|-
| 11 || scaledown counter || udp_scaledown_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the scaledown
|-
| X || || || ||
|-
| 12 || 0xE packet footer || || all || 28 bits of counter_trig_out
|-
|}

== firmware 0x618b790b (Nov 2021) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

== firmware 0x62d1c47e (Jul 2022) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, 8'h00, 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= conf_fw_rev;
18 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

Values of udp_coinc_latch[7:0]:
* aaa

Values of udp_aw16_mult[7:0] and udp_aw16_bus[15:0]:
* aaa

Values of udp_bsc64_mult[7:0] and udp_bsc64_bus[63:0]
* aaa

== trigger bitmap ==

Firmware ??? (one of the very early revisions)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= adc16_coinc_top;
udp_trig_bits[5] <= adc16_coinc_bot;
udp_trig_bits[6] <= adc16_coinc;
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
udp_trig_bits[31:24] <= mult16[7:0];

</pre>

Firmware 0x5b08938c (25May18_15:51)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= 0; // not used
udp_trig_bits[31:24] <= mult16[7:0];
</pre>

Firmware 0x5b217dc4 (13Jun18_13:25)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5b3aa19f (02Jul18_15:05)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= udp_mlu_out;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5bc8f90f (18Oct18_14:20)

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_run_pulser
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = 0; // not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x618b790b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x62c77f0b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = 0; // aw16_coinc_a;
assign trig32_in[17] = 0; // aw16_coinc_b;
assign trig32_in[18] = 0; // aw16_coinc_c;
assign trig32_in[19] = 0; // aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = 0; // aw16_mult_1ormore;
assign trig32_in[25] = 0; // aw16_mult_2ormore;
assign trig32_in[26] = 0; // aw16_mult_3ormore;
assign trig32_in[27] = 0; // aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc64_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

= TRG chronobox inputs =

from trg_firmware/toplevel/grifc.v

<pre>
localparam CB_N = 23;
localparam CB_N1 = CB_N-1;

wire [CB_N1:0] cb_xinputs_async;

assign cb_xinputs_async[0] = ag_trig_out;
assign cb_xinputs_async[1] = ag_trig_scaledown_out;
assign cb_xinputs_async[2] = ag_trig_drift_out;
assign cb_xinputs_async[3] = ag_trig_received_out;

assign cb_xinputs_async[4] = ag_cb_sw_trig;
assign cb_xinputs_async[5] = ag_cb_pulser_trig;
assign cb_xinputs_async[6] = ag_cb_esata_nim_trig;
assign cb_xinputs_async[7] = ag_cb_adc16_grand_or_trig;
assign cb_xinputs_async[8] = ag_cb_adc32_grand_or_trig;

assign cb_xinputs_async[9] = ag_cb_aw16_grand_or_trig;
assign cb_xinputs_async[10] = ag_cb_aw16_mult_1ormore;
assign cb_xinputs_async[11] = ag_cb_aw16_mult_2ormore;
assign cb_xinputs_async[12] = ag_cb_aw16_mult_3ormore;
assign cb_xinputs_async[13] = ag_cb_aw16_mult_4ormore;
assign cb_xinputs_async[14] = ag_cb_aw16_mlu_trig;

assign cb_xinputs_async[15] = ag_cb_bsc64_grand_or_trig;
assign cb_xinputs_async[16] = ag_cb_bsc64_mult_1ormore;
assign cb_xinputs_async[17] = ag_cb_bsc64_mult_2ormore;
assign cb_xinputs_async[18] = ag_cb_bsc64_mult_3ormore;
assign cb_xinputs_async[19] = ag_cb_bsc64_mult_4ormore;
assign cb_xinputs_async[20] = ag_cb_bsc64_mult_trig;

assign cb_xinputs_async[21] = ag_cb_coinc_trig;

assign cb_xinputs_async[22] = ag_cb_timeout_trig;
</pre>

= Example UDP packets =

* trigger data, marker words 0x8

<pre>
ReadDataThread read 76
0: 0x003666ed -- UDP packet counter from UDP transmitter
1: 0x80000bf8 -- 0x8 is trigger data packet, 0xbf8 is the trigger counter from alphag.v
2: 0x2edf8b41 -- trigger data
3: 0x00000bf8
4: 0x00000bf8
5: 0x00000bee
6: 0x00000001
7: 0x00000000
8: 0x00000000
9: 0x00000003
10: 0x00000bf8
11: 0x00000bf8
12: 0x00000000
13: 0x00000000
14: 0x00000000
15: 0x00000000
16: 0x00000000
17: 0x00000000
18: 0xe0000bf8 -- 0xE is end of trigger data, counter 0xbf8 must match the counter in the 0x8 word.
ReadDataThread read 76 -- next packet
0: 0x003666ee -- UDP packet counter from UDP transmitter
...
</pre>

* chronobox fifo data, marker word 0xC, see [[Chronobox#FIFO_data_format]]

<pre>
ReadDataThread read 404
0: 0x003658ed -- UDP packet counter from UDP transmitter
1: 0xc000eacc -- 0xC is FIFO data, fifo packet counter 0xeacc from fifo_to_udp.v
2: 0x00000061 -- FIFO status, low bits the the word counter, so up to 0x61 fifo words are to follow
3: 0x87fb3d72 -- tsc hits
4: 0x8ffb3d74
5: 0x90fb3d74
6: 0x91fb3d74
7: 0x92fb3d74
8: 0x93fb3d74
9: 0x93fb3d75
10: 0x94fb3d74
11: 0x94fb3d77
12: 0x87fb3d77
13: 0x8ffb3d77
14: 0x90fb3d77
15: 0x91fb3d77
16: 0x92fb3d77
17: 0xfe000018 -- 0xFE scaler data starts, 0x18 words to follow
18: 0x00000000
19: 0x00000000
20: 0x00000000
21: 0x00000000
22: 0x00000000
23: 0x00000000
24: 0x00000000
25: 0x00000108
26: 0x00000000
27: 0x00000000
28: 0x00000000
29: 0x00000000
30: 0x00000000
31: 0x00000000
32: 0x00000000
33: 0x00000108
34: 0x00000108
35: 0x00000108
36: 0x00000108
37: 0x00000108
38: 0x00000108
39: 0x00000000
40: 0x00000000
41: 0xce56fa93 -- last word of scaler data is the sysclock counter (125 MHz)
42: 0xff800048 -- timestamp wraparound
43: 0x8f1f36e4 -- tsc hits
44: 0x901f36e4
45: 0x911f36e4
46: 0x921f36e4
47: 0x931f36e4
48: 0x941f36e4
49: 0x871f36e4
50: 0x871f36e7
51: 0x8f1f36e7
52: 0x901f36e9
53: 0x911f36e7
54: 0x921f36e9
55: 0x931f36e7
56: 0x941f36e9
57: 0x904330ac
58: 0x914330ac
59: 0x924330ac
60: 0x934330ac
61: 0x934330ad
62: 0x944330ac
63: 0x944330ad
64: 0x874330ac
65: 0x874330ad
66: 0x8f4330ac
67: 0x8f4330ad
68: 0x904330ad
69: 0x914330ad
70: 0x924330ad
71: 0x8f672a62
72: 0x90672a62
73: 0x91672a62
74: 0x92672a62
75: 0x93672a62
76: 0x94672a62
77: 0x87672a62
78: 0x87672a65
79: 0x8f672a65
80: 0x90672a65
81: 0x91672a65
82: 0x92672a65
83: 0x93672a65
84: 0x94672a65
85: 0xff000049
86: 0x878b2422
87: 0x8f8b2424
88: 0x908b2424
89: 0x918b2424
90: 0x928b2424
91: 0x938b2424
92: 0x938b2425
93: 0x948b2424
94: 0x948b2427
95: 0x878b2427
96: 0x8f8b2427
97: 0x908b2427
98: 0x918b2427
99: 0x928b2427
100: 0xe000eacc -- 0xE is end of fifo data, counter 0xeacc must match the counter in the 0xC word.
ReadDataThread read 344 -- next packet
...
</pre>

= TODO =

* DONE July 2022. add FwRev to the UDP data output
* RJ45 SFP: PROBLEM, D.A. CABLE: GOOD, Fiber SFP: ???. fix "write did not happen" (send udp write command, there is no reply, read returns old data as if write never happened). suspect udp "write" packet is lost?
* PROBLEM GONE Aug 2021. fix reply to wrong socket - udp packets should reply to same socket as they came from, udp data packets should be sent to same socket as requested them, not same socket as last command.
* DONE 2021jul30. add fixes from Chris P. for the auto-negotiation and dhcp (see email from him).
* DONE flash chip connected to FPGA. Aug 2021. implement ethernet flash programmer
* DONE Aug 2021. updated maxv firmware. implement FPGA reboot
* speed up programming the MLU by writing more than 1 bit at a time
* DONE Nov 2021. add 64-bit bitmap of BSC trigger bits
* DONE. add chronobox code
* DONE. add avalon mux for alphag and chronobox packets
* DONE. add chronobox fifo to udp packet sequencer
* check that TxReadyOut is correct and it is safe to send an avalon packet while previous packet is still transmitting.
* DONE. test fiber SFP is working
* complete the UDP flash programmer (parallel flash erase and write)

= End =

//KO

TRG

2022-07-16T21:43:19Z

Olchansk: /* additional registers */

= TRG, the trigger control board for the ALPHA-g detector =

= Links =

* xxx
* https://bitbucket.org/expalpha/trg_firmware - firmware sources on bitbucket

= General characteristics =

== Photos ==

== Board schematics ==

* https://bitbucket.org/expalpha/trg_firmware/src/master/3xFMC_VME_Motherboard.pdf

== Available hardware ==

* Altera Stratix IV - main FPGA
* Altera Max V - boot FPGA
* boot flash: PC28F512M29EW - 512 Mbit parallel NOR flash.

= TRG front panel connections =

From top to bottom:

<pre>
|
| minisas-C - links 8-11
| minisas-D - links 12-15
|
| ethernet sfp - use copper sfp only
| minisas - not used, do not connect
| esata - clock in, trigger out
|
| minisas-A - links 0-3
| minisas-B - links 4-7
|
| LEDs
|
</pre>

MiniSAS and SATA flail cable connections:

<pre>
P1 <--> link 3
P2 <--> link 2
P3 <--> link 1
P4 <--> link 0
</pre>

LEDs:

<pre>
--PCB-- (left)
LED[0] - trigger out - ag_trig_out
LED[1] - network packet received - sfp_rx_data_valid
LED[2] - Xilinx FPGA boot ok - FMC1_CFG_DONE
LED[3] - not used
(right)
</pre>

= TRG onboard jumpers and switches =

* rotary switches: select IP address: 00=192.168.1.50, 11=.51, 22=.52, 33=.53, 44=.54, otherwire=.251

= Firmware update procedure =

* use quartus to generate the grifc.pof file (use grifc.cof)
* open quartus programmer
* attach grifc.pof to the 1st CFI_512 flash
* mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
* check that "initiate configuration after programming" is set in tools->options
* say "start"
* should take about 5 minutes
* grifc should reboot into the new firmware

If CFI_512 flash is not visible to the quartus programmer, load correct
code into the MaxV CPLD:

* open quartus programmer,
* say "auto detect"
* change file for the 5M2210 device
* use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
* say "program", it should finish in 10-15 seconds
* say "auto detect"
* CFI_512 flash should be visible now.

= Firmware revisions =

* 0x5bc8f90f - original firmware used for all data
* 0x6147c0f9 - added cbtrg, etc. installed at CERN on 20 Sep 2021.
* 0x618376ae - bigger cbtrg fifo, data rate tested up to 30 Mbytes/sec
* 0x6189c7f3 - fix loss of trigger packets. (missing fifo between alphag block and ethernet mux)
* 0x618b790b - fix loss of timestamps. (cbtrg inputs stretched to 100 ns long). installed at CERN 10 Nov 2021.

= Firmware build =

* use quartus 20.1
* see Makefile in the trg_firmware project

= Jtag remote connection =

* ssh agmini@daq16
* /opt/intelFPGA/16.1/quartus/bin/jtagd --config /home/agmini/.jtagd.conf
* netstat -an | grep 1309 ### note listen address is "0.0.0.0", NOT "127.0.0.1"
<pre>
tcp 0 0 0.0.0.0:1309 0.0.0.0:* LISTEN
</pre>
* opt/intelFPGA/16.1/quartus/bin/jtagconfig ### should work
* ssh olchansk@daq01
* cd git/trg_firmware
* /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
* jtagconfig ### should work
<pre>
daq01:trg_firmware$ jtagconfig
1) DE-SoC on daq16 [2-1.2.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) USB-Blaster on daq16 [2-1.3]
024090DD EP4SGX230(.|ES)
020A40DD 5M(1270ZF324|2210Z)/EPM2210

daq01:trg_firmware$
</pre>

= ALPHA-g trigger functions =

Trigger options:
* software trigger
* pulser trigger
* trigger on GRIF16 ADC NIM and ESATA inputs ("external trigger")
* adc16 grand-or
* adc32 grand-or
* adc16 wire multiplicity
* TPC anode wire per-preamp trigger (aw16 section)
** trigger on coincidences of preamps (removed fw 0x62c77f0b)
** trigger on multiplicity of preamps (removed fw 0x62c77f0b)
** trigger on specific topology of preamps (multiplicity of preamp clusters, etc) via the aw16_mlu trigger
* BSC trigger
** BSC grand_or
** BSC bar multiplicity
* coincidence trigger - select coincidence of external trigger, TPC AW grand-or, TPC AW MLU, BSC grand-or and BSC bar multiplicity triggers

== software trigger ==

to programmatically fire the trigger, one should:
* set the conf_enable_sw_trigger bit in conf_trig_enable, this will permit the software trigger to fire the trigger
* write value 0x4 to register 0x2B, this will cause the software trigger to fire

== pulser trigger ==

To use the pulser trigger, one should program:
* pulser period (in clocks)
* pulser width (in clocks, use value 5, the pulser no longer goes outside of the trigger board, so changing the width does not do anything)
* set the run_pulser bit in conf_trig_enable, this will cause the pulser to run
* set the enable_pulser bit in conf_trig_enable, this will cause the pulser to fire the trigger
* set the output_pulser bit in conf_trig_enable, this will cause the pulser to be output from the alphag firmware block (the pulser no longer goes outside of the trigger board, so changing the bit does not do anything)

== timeout trigger ==

The event builder uses event timestamps to assemble physics events. The timestamps
are usually 32 bit wide and run at 125 MHz (8 ns) or 62.5 MHz (16 ns). If
triggers are generated often (1 per second or more), timestamp wrap around
is easily detected by the event builder. If triggers come infrequently,
timestamp wrap around may occur while there are no triggers, not be seen
by the event builder causing loss of event synchronization.

To avoid this problem in the event builder, a timeout trigger should be generated
if no triggers were generated inside a 10 second interval.

The guaranties that even if all physics triggers temporarily stop for any reason,
the event builder will stay synchronized. (0.1 Hz timeout trigger frequency).

To enable the timeout trigger:
* program timeout trigger timeout in reg 0x43 in units of 8 ns clock
* enable it in bit 23 of [[#conf_trig_enable bits]]

== adc16 multiplicity trigger ==

This trigger is intended for use with the barrel scintillator signals connected to adc16 digitizers. It does not work well with TPC AW signals.

The 16 adc16 trigger bits (16x16=256) are added together to form the hit multiplicity value (adc16_mult, 16 bits, actual range 0 to 256).

Four threshold signals are computed: adc16_mult_1ormore = adc16_mult>=1, 2ormore, 3ormore, 4ormore.

There is a counter for each of these four signals.

Each of these four signals can fire the trigger, see [[#conf_trig_enable bits]].

== TPC anode wire triggers ==

=== aw16 bus ===

TPC Anode Wire trigger is based on the aw16[15:0] (xaw16) bus.

Each bit corresponds to one AW preamp. 16 preamps, 16 bits.

The aw16[15:0] bus can be fed by
* adc16_or16[15:0] - or16 of 100 MHz ADCs, 16 ADC sas links
* adc32_or16[15:0] - or16 of 62.5 MHz ADCs, FMC-ADC32 has 32 channels, so 2 bits per ADC: low 16 channels and high 16 channels, sas links 7..0
* adc32_or16[31:16] - or16 of 62.5 MHz ADCs, ditto, sas links 15..8
as selected by conf_enable_aw_adc16, conf_enable_aw_adc32a, conf_enable_aw_adc32b in [[#conf_control bits]]

<pre>
///////////////////////////////////////////////////////////
// TPC Anode Wire trigger logic (aw16)
///////////////////////////////////////////////////////////

// map adc signals into aw16

wire [15:0] aw16 = ({16{conf_enable_aw_adc16}} & adc16_or16[15:0]) |
({16{conf_enable_aw_adc32a}} & adc32_or16[15:0]) |
({16{conf_enable_aw_adc32b}} & adc32_or16[31:16]);
...
ag_conditioner cond_adc16_or16_0(.clk(clk), .in(aw16[0]), .out(xxaw16[0]));
...
xaw16 <= xxaw16;
</pre>

=== aw16_grand_or ===

TPC AW "grand or" trigger: use aw16_mult_1ormore (before fw 0x62c77f0b)

(256 anode wires, 16 wires per preamp, 16 preamps, 16 aw16 signals)

=== aw16_mlu ===

TPC AW preamp MLU trigger: the MLU (memory lookup
table) implements an arbitrary logical function
to map the 16 aw16 preamp signals into 1 aw16_mlu_trig trigger output.

Description of the aw16 mlu trigger.

In words:

* any aw16 signal starts the aw16_prompt_run gate
* aw16 signals are collected for the duration of conf_mlu_prompt (125MHz/8ns clock)
* this corresponds to time spread of TPC AW signals due to the drift time in the AW drift cell and to the variation in signal transmission time from the ADC to the TRG (digital trigger data link).
* when this prompt time expires, the MLU looks at the accumulated aw16_prompt bit pattern and makes the "yes/no" trigger decision
* after the trigger decision is made, we wait for the TPC to become quiet:
* we wait until all aw16 signals are empty (no timeout)
* we run the aw16_prompt_wait gate, length conf_mlu_wait (8ns clock), if any aw16 signals arrive, we wait for aw16 empty again, rinse, repeat.
* now, after TPC aw16 have been empty for conf_mlu_wait clocks (8ns clock), MLU trigger is ready for the next event.

In logic: (see alphag.v)

* aw16_or <= grand-or of 16 aw16 signals
* "aw16_or" starts the "aw16_prompt_cnt" counter, opens the aw16_prompt_run gate
* during the aw16_prompt_run gate, aw16_prompt collects (latches) the aw16 bits (aw16_prompt <= aw16_prompt | aw16)
* this is the time when we wait for all "prompt" signals from the TPC to arrive into the trigger
* at the end of the aw16_prompt_run gate, the signal aw16_prompt_out is pulsed, latching the output of the MLU into aw16_mlu_trig
* this is the MLU trigger "yes/no" trigger decision.
* after the MLU trigger decision is made, we wait for the arrival and passing of all TPC drift signals
* the aw16_prompt_wait_cnt and aw_prompt_wait gate opens
* if any new aw16 signals arrive (they are TPC drift signals at this time), the aw16_prompt_wait gate is restarted
* if no aw16 signals arrive during the full run of the aw16_prompt_wait gate ("TPC quiet time")
* the aw16_prompt_wait and aw16_prompt gates are cleared and the MLU trigger is ready for the next event.

Good settings are:
* conf_mlu_prompt: 64 (512 ns)
* conf_mlu_wait: 128 (1024 ns)

== BSC trigger ==

=== bsc_adc16 bus ===

The BSC trigger is based on the [15:0]bsc_adc16[7:0] bus: 16 trigger discriminator bits from 8 ADC sas links. (8*16 = 64+64 bars, top and bottom).

The bsc_adc16 bus can be fed from sas links 0..7 or 8..15, controlled by conf_bsc_adc16_a and conf_bsc_adc16_b bits on [[#conf_bsc_control bits]].

bsc_adc16 can be fed only from GRIF-16 100 MHz ADC trigger discriminators.

=== bsc64_top and bsc64_bot buses ===

* firmware 0x5bc8f90f: bsc_adc16 is remapped into 64 bits of top (bsc64_top) and bottom (bsc64_bot):
<pre>
ag_bsc_remap bsc_remap_a(.adc(bsc_adc16[0]), .bsc_bot(bsc64_bot[7:0]), .bsc_top(bsc64_top[7:0]));
ag_bsc_remap bsc_remap_b(.adc(bsc_adc16[1]), .bsc_bot(bsc64_bot[8+7:8+0]), .bsc_top(bsc64_top[8+7:8+0]));
ag_bsc_remap bsc_remap_c(.adc(bsc_adc16[2]), .bsc_bot(bsc64_bot[2*8+7:2*8+0]), .bsc_top(bsc64_top[2*8+7:2*8+0]));
ag_bsc_remap bsc_remap_d(.adc(bsc_adc16[3]), .bsc_bot(bsc64_bot[3*8+7:3*8+0]), .bsc_top(bsc64_top[3*8+7:3*8+0]));

ag_bsc_remap bsc_remap_e(.adc(bsc_adc16[4]), .bsc_bot(bsc64_bot[4*8+7:4*8+0]), .bsc_top(bsc64_top[4*8+7:4*8+0]));
ag_bsc_remap bsc_remap_f(.adc(bsc_adc16[5]), .bsc_bot(bsc64_bot[5*8+7:5*8+0]), .bsc_top(bsc64_top[5*8+7:5*8+0]));
ag_bsc_remap bsc_remap_g(.adc(bsc_adc16[6]), .bsc_bot(bsc64_bot[6*8+7:6*8+0]), .bsc_top(bsc64_top[6*8+7:6*8+0]));
ag_bsc_remap bsc_remap_h(.adc(bsc_adc16[7]), .bsc_bot(bsc64_bot[7*8+7:7*8+0]), .bsc_top(bsc64_top[7*8+7:7*8+0]));

module ag_bsc_remap
(
input wire [15:0] adc,
output wire [7:0] bsc_bot,
output wire [7:0] bsc_top
);

assign bsc_top[3] = adc[0];
assign bsc_top[2] = adc[1];
assign bsc_top[1] = adc[2];
assign bsc_top[0] = adc[3];

assign bsc_top[7] = adc[4];
assign bsc_top[6] = adc[5];
assign bsc_top[5] = adc[6];
assign bsc_top[4] = adc[7];

assign bsc_bot[0] = adc[8];
assign bsc_bot[1] = adc[9];
assign bsc_bot[2] = adc[10];
assign bsc_bot[3] = adc[11];

assign bsc_bot[4] = adc[12];
assign bsc_bot[5] = adc[13];
assign bsc_bot[6] = adc[14];
assign bsc_bot[7] = adc[15];

endmodule
</pre>

=== bsc64 bus ===

the bsc64 bus is the 64 bars used by the trigger, formed from bsc64_top and bsc64_bot:
<pre>
if (conf_bsc64_bot_only) begin
bsc64 <= bsc64_bot;
end else if (conf_bsc64_top_only) begin
bsc64 <= bsc64_top;
end else if (conf_bsc64_bot_top_or) begin
bsc64 <= bsc64_bot | bsc64_top;
end else if (conf_bsc64_bot_top_and) begin
bsc64 <= bsc64_bot & bsc64_top;
end else begin
bsc64 <= 64'b0;
end
</pre>

=== bsc_grand_or_trig ===

bsc_grand_or_trig is the grand-or of 64 bits of the bsc64 bus

to enable triggering on bsc_grand_or_trig, set corresponding bit in [[#conf_trig_enable bits]]

=== old bsc_mult_trig ===

(from fw 0x62c77f0b, old bsc_mult_trig was replaced by new bsc64 multiplicity trigger)

* bsc64_mult is computed as multiplicity of the bsc64 bus (number of 64 bsc64 bits that fired)
* bsc_mult_trig is computed:
<pre>
if (bsc64_mult >= conf_bsc64_mult) begin
bsc_mult_trig <= 1;
end else begin
bsc_mult_trig <= 0;
end
</pre>

to enable the bsc multiplicity trigger, set the multiplicity value conf_bsc64_mult in [[#conf_bsc_control bits]] and enable the corresponding bit in [[#conf_trig_enable bits]].

=== bsc64 multiplicity trigger ===

bsc64 BSC bar multiplicity trigger uses a time window. this time window is started by bsc64_grand_or and runs for conf_bsc64_mult_window clocks (8 nc clock). During this time, hits in bsc64_bus are accumulated (latched) and their multiplicity is computed. If multiplicity condition is satisfied (bigger or equal to conf_bsc64_mult_min), bsc64_mult_trig is fired and the bsc64 bit pattern is saved to the UDP packet. Then trigger waits for the bsc64_bus to be empty. Then trigger waits for conf_bsc64_empty_window clocks, if there is any bsc64 hits, we wait for empty again. So after bsc64 has been empty for conf_bsc64_empty_window clocks, multiplicity trigger is ready for the next event. This scheme cannot implement max multiplicity.

recommended values:
* conf_bsc64_mult_window (8 bits): slightly longer than 3 cycles of SAS link: 3*18 = 54 clocks, good value is 80 (640 ns).
* conf_bsc64_mult_min (8 bits): 2
* conf_bsc64_empty_window (8 bits): 80 (640 ns)

== Coincidence trigger ==

Coincidence trigger provides a combination of TPC, BSC and external scintillator (esata_nim_grand_or) signals:

<pre>
assign coinc_input[0] = aw16_grand_or; // was aw16_mult_1ormore;
assign coinc_input[1] = aw16_mlu_trig;
assign coinc_input[2] = bsc_grand_or_trig;
assign coinc_input[3] = bsc_mult_trig;
assign coinc_input[4] = esata_nim_grand_or;
assign coinc_input[5] = 0;
assign coinc_input[6] = 0;
assign coinc_input[7] = 0;
</pre>

Coincidence trigger "start" mask selects which of the inputs can start the coincidence window.

Coincidence trigger "require" mask selects which inputs must have a hits for the coincidence to be satisfied.

Input hits are collected for the duration of the coincidence window, if all required inputs have hits, coinc_trig is fired.

Example settings:

* coincidence of external scintillator, BSC and TPC AW "grand or" signals: start 0x10, required 0x15
* coincidence of BSC grand-or and TPC AW grand-or signals: start 0x5, required 0x5
* coincidence of BSC multiplicity and TPC AW grand-or triggers: start 0x9, required 0x9

= Control registers =

== Register addresses ==

Note: all registers are 32 bits unless otherwise noted.

Note: RW means read-write register, RO means read-only, ROL means read-only, contents is latched by the "latch_out" bit

{| cellpadding="10" cellspacing="0" border="1"
! Address || Quartus Name || Access || FwRev || Description
|-
| 0x08 || num_sample || RW || GRIF-C || magic 16-bit register to control UDP packet size
|-
| 0x08 || scratch_reg || RW || 0x618b790b || 32-bit scratch register
|-
| 0x1F || compilation_time || RO || || Firmware revision
|-
| 0x20 || conf_trig_width || RW || || Trigger signal width, 16 ns clock
|-
| 0x21 || conf_busy_width || RW || || Busy signal width, 16 ns clock (not used)
|-
| 0x22 || conf_pulser_width || RW || || Pulser signal width, 16 ns clock
|-
| 0x23 || conf_pulser_period || RW || || Pulser signal period, 16 ns clock
|-
| 0x24 || conf_pulser_burst_ctrl || RW || 0x62d1c47e || Generate bursts of pulses: 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses, 16 ns clocks
|-
| 0x25 || conf_trig_enable || RW || || see [[#conf_trig_enable bits]]
|-
| 0x26 || || || not used
|-
| 0x27 || || || not used
|-
| 0x28 || || || not used
|-
| 0x29 || conf_nim_mask || RW || || enable bits for ADC NIM inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2A || conf_esata_mask || RW || || enable bits for ADC eSATA inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2B || reset_out, latch_out, trigger_out || W || || see [[#reg 0x2B bits]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x5bc8f90f || configure AW coincidence trigger, see [[#aw16_coinc]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x62c77f0b || removed
|-
| 0x2D || conf_aw16_coinc_b || RW || 0x5bc8f90f ||
|-
| 0x2E || conf_aw16_coinc_c || RW || 0x5bc8f90f ||
|-
| 0x2F || conf_aw16_coinc_d || RW || 0x5bc8f90f ||
|-
| 0x30 || sas_sd[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect for each link
|-
| 0x31 || pll_625_status || ROL || 0x5b2057f5 (12Jun18_16:32) || 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter
|-
| 0x32 || clk_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the system 125 MHz clock
|-
| 0x33 || clk_625_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625)
|-
| 0x34 || conf_control || RW || 0x5b398983 (01Jul18_19:10) || see [[#conf_control bits]] below
|-
| 0x35 || conf_drift_width || RW || 0x5b398983 (01Jul18_19:10) || width of drift time blank-out in 16 ns clocks
|-
| 0x36 || conf_scaledown || RW || 0x5b398983 (01Jul18_19:10) || trigger scaledown, 0=no scaledown, 1=divide-by-2, 2=divide-by-3, etc
|-
| 0x37 || conf_mlu || RW || 0x5b398983 (01Jul18_19:10) || AW MLU control bits, see [[#conf_mlu bits]]
|-
| 0x38 || conf_trig_delay || RW || 0x5baedfca (28Sep18_19:13) || delay the trigger pulse, 16 ns clock
|-
| 0x39 || esata_clk_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the TRG 125 MHz clock
|-
| 0x3A || esata_clk_esata_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the external clock (eSATA 62.5 MHz clock)
|-
| 0x3B || conf_counter_adc_select || RW || 0x5bb7f6ae (05Oct18_16:41) || select which 16 ADCs are connected to the selected adc counters, 0..15 - connect the adc16 signals, 16..47 connect the adc32 signals
|-
| 0x3C || sysreset_ts || RO || 0x5bb7f6ae (05Oct18_16:41) || 125MHz counter of VME-SYSRESET
|-
| 0x3C || || || 0x618b790b || not used
|-
| 0x3D || GRIF-C csr || RW || GRIF-C || <= csr & ~par_value; // Selective clear
|-
| 0x3E || GRIF-C csr || RW || GRIF-C || <= csr | par_value; // Selective set
|-
| 0x3F || GRIF-C csr || RW || GRIF-C || <= par_value; // write
|-
| 0x3D || || || 0x618b790b || not used
|-
| 0x3E || || || 0x618b790b || not used
|-
| 0x3F || || || 0x618b790b || not used
|-
| 0x40 || conf_bsc_control || RW || 0x5bc13541 (12Oct18_16:58) || Barrel Scintillator trigger control, see [[#conf_bsc_control bits]]
|-
| 0x41 || conf_coinc_control || RW || 0x5bc13541 (12Oct18_16:58) || Coincidence trigger control, see [[#conf_coinc_control bits]]
|-
| 0x42 || reconfig_out || WO || 0x5bc13541 (12Oct18_16:58) || reserved for rebooting the FPGA (does not work)
|-
| 0x43 || conf_trigger_timeout || RW || 0x5bc8f90f (18Oct18_14:20) || Generate timeout trigger if there is no other trigger after given timeout, in 8 ns clocks, must be enabled by bit conf_enable_timeout_trig in [[#conf_trig_enable bits]]
|-
| 0x44 || eth_clk_counter || ROL || 0x618b790b ||
|-
| 0x45 || eth_clk_eth_counter || ROL || 0x618b790b ||
|-
| 0x100 || ts_625 || ROL || || latched timestamp
|-
| 0x101 || counter_trig_out || ROL || || counter of issued triggers
|-
| 0x102 || counter_trig_in || ROL || || counter of triggers
|-
| 0x103 || counter_pulser || ROL || || counter of pulser
|-
| 0x104 || counter_adc16_grand_or || ROL ||
|-
| 0x105 || counter_adc32_grand_or || ROL ||
|-
| 0x106 || counter_adc_grand_or || ROL ||
|-
| 0x107 || counter_esata_nim_grand_or || ROL ||
|-
| 0x108 || counter_adc16_mult_1ormore || ROL ||
|-
| 0x109 || counter_adc16_mult_2ormore || ROL ||
|-
| 0x10A || counter_adc16_mult_3ormore || ROL ||
|-
| 0x10B || counter_adc16_mult_4ormore || ROL ||
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x5bc8f90f || counter of AW coincidence triggers
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x62c77f0b || removed
|-
| 0x10D || counter_aw16_coinc_b || ROL || 0x5bc8f90f ||
|-
| 0x10E || counter_aw16_coinc_c || ROL || 0x5bc8f90f ||
|-
| 0x10F || counter_aw16_coinc_d || ROL || 0x5bc8f90f ||
|-
| 0x110 || counter_drift || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the drift time blank-out
|-
| 0x111 || counter_scaledown || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the scaledown
|-
| 0x112 || counter_aw16_coinc || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW coincidence triggers
|-
| 0x113 || counter_aw16_mlu || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW MLU triggers
|-
| 0x114 || counter_aw16_grand_or || ROL || 0x62c77f0b || counter of AW grand-or triggers
|-
| 0x114 || counter_aw16_mult_1ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 1ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 2ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x62c77f0b || removed
|-
| 0x116 || counter_aw16_mult_3ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 3ormore triggers
|-
| 0x117 || counter_aw16_mult_4ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 4ormore triggers
|-
| 0x118 || counter_bsc_grand_or || ROL || 0x5bc13541 (12Oct18_16:58) || counter of BSC grand-or triggers
|-
| 0x119 || counter_bsc_mult || ROL || 0x5bc13541 (12Oct18_16:58) || counter of old BSC multiplicity triggers
|-
| 0x11A || counter_coinc || ROL || 0x5bc13541 (12Oct18_16:58) || counter of coincidence triggers
|-
| 0x11B || counter_timeout || ROL || 0x618b790b || counter of timeout triggers
|-
| 0x11C || counter_bsc_mult_start || ROL || 0x62c77f0b || counter of BSC multiplicity windows
|-
| 0x11D || counter_bsc_mult_trig || ROL || 0x62c77f0b || counter of BSC multiplicity triggers
|-
| 0x11E || counter_coinc_start || ROL || 0x62d1b152 || counter of coincidence windows
|-
| 0x11F || counter_aw16_mlu_start || ROL || 0x62d1b152 || counter of TPC AW MLU windows
|-
| 0x200..0x207 || conf_adc16_masks || RW || all || adc16 enable bits
|-
| 0x300..0x30F || conf_adc32_masks || RW || all || adc32 enable bits
|-
| 0x400..0x41F || sas_bits[15:0][63:0] || ROL || all || sas data bits for each link
|-
| 0x420..0x42F || sas_sd_counters[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect counter for each link
|-
| 0x430..0x43F || counters_adc16_or16[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 16 counters of adc16 ORes
|-
| 0x440..0x45F || counters_adc32_or16[31:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 32 counters of adc32 ORes
|-
| 0x460..0x46F || counters_adc_selected[15:0] || ROL || 0x5bb7f6ae (05Oct18_16:41) || 16 counters for selected group of adcs, see conf_counter_adc_select
|-
| 0x470..0x4AF || counters_bsc64[63:0] || ROL || 0x5bc13541 (12Oct18_16:58) || 64 counters for the BSC bars
|-
|}

== additional registers ==

<pre>
reg | rw/ro/rol | quartus name | firmware | description
-----------------------------------------------------------------
0x60 | rw | cb_control_out | 0x618b790b | chronobox control
0x61 | rw | cb_status | 0x618b790b | chronobox status
0x62 | rw | cb_invert_a_out | 0x618b790b | chronobox input invert
0x63 | rw | cb_invert_b_out | 0x618b790b |
0x64 | rw | cb_enable_le_a_out | 0x618b790b | timestamp enable leading edge
0x65 | rw | cb_enable_le_b_out | 0x618b790b |
0x66 | rw | cb_enable_te_a_out | 0x618b790b | timestamp enable traiing edge
0x67 | rw | cb_enable_te_b_out | 0x618b790b |
0x6A | ro | cb_input_num | 0x618b790b | chronobox number of inputs
0x6B | rw | cb_sync_mask_a_out | 0x618b790b | chronobox sync signal source
0x6C | rw | cb_sync_mask_b_out | 0x618b790b |
0x6D | rw | cb_sync_reg_out | 0x618b790b | chronobox sync register
0x6E | ro | cb_sync_status | 0x618b790b | chronobox sync status
0x6F | rw | cb_latch_period_out | 0x618b790b | chronobox scalers latch period
0x70 | ro | cb_fifo_status | 0x618b790b | chronobox data fifo status
0x71 | ro | cb_fifo_data | 0x618b790b | read chronobox data fifo (cb_fifo_rdack_out <= 1)
0x72 | rw | cb_udp_period_out | 0x618b790b | period for flushing fifo to UDP
0x73 | rw | cb_udp_threshold_out | 0x618b790b | byte threshold for flushing fifo to UDP
</pre>

== conf_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_clock_select || 0x5b3aa19f (02Jul18_15:05) || select 0=internal 62.5 MHz clock or 1=esata 62.5 MHz clock
|-
| 1 || conf_enable_aw_adc16 || 0x5baedfca (28Sep18_19:13) || select source of TPC AW aw16 bus, see [[#aw16 bus]]
|-
| 2 || conf_enable_aw_adc32a || 0x5baedfca (28Sep18_19:13) ||
|-
| 3 || conf_enable_aw_adc32b || 0x5baedfca (28Sep18_19:13) ||
|-
| 15..4 || || ||
|-
| 23..16 || conf_mlu_prompt || 0x5b3aa19f (02Jul18_15:05) || MLU trigger prompt window, see [[#aw16_mlu]]
|-
| 31..24 || conf_mlu_wait || 0x5b3aa19f (02Jul18_15:05) || MLU trigger wait window, see [[#aw16_mlu]]
|-
|}

== conf_mlu bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 31 || mlu_reset || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 30 || mlu_write || 0x5b3aa19f (02Jul18_15:05) || 1=write data bit into given address
|-
| 16 || mlu_data || 0x5b3aa19f (02Jul18_15:05) || data bit for writing to MLU RAM
|-
| 15..0 || mlu_write_addr || 0x5b3aa19f (02Jul18_15:05) || MLU RAM write address for writing the data bit
|-
|}

== conf_bsc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_bsc_adc_a || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 0..7
|-
| 1 || conf_bsc_adc_b || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 8..15
|-
| 2 || conf_bsc64_bot_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses bottom channels only
|-
| 3 || conf_bsc64_top_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses top channels only
|-
| 4 || conf_bsc64_bot_top_or || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "or" of top and bottom
|-
| 5 || conf_bsc64_bot_top_and || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "and" of top and bottom
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_bsc64_mult_min || 0x5bc13541 (12Oct18_16:58) || minimum bsc64 multiplicity
|-
| 23..16 || conf_bsc64_empty_wondow || 0x62d1c47e || bsc64 empty window length, 8 ns clocks
|-
| 31..24 || conf_bsc64_mult_window || 0x62c77f0b || bsc64 multiplicity window length, 8 ns clocks
|-
|}

== conf_coinc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_coinc_required[0] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mult_1ormore
|-
| 0 || conf_coinc_required[0] || 0x62c77f0b || enable aw16_grand_or
|-
| 1 || conf_coinc_required[1] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mlu_trig
|-
| 2 || conf_coinc_required[2] || 0x5bc13541 (12Oct18_16:58) || enable bsc_grand_or_trig
|-
| 3 || conf_coinc_required[3] || 0x5bc13541 (12Oct18_16:58) || enable bsc_mult_trig
|-
| 3 || conf_coinc_required[3] || 0x62c77f0b || enable bsc64_mult_trig
|-
| 4 || conf_coinc_required[4] || 0x5bc13541 (12Oct18_16:58) || enable esata_nim_grand_or
|-
| 5 || conf_coinc_required[5]
|-
| 6 || conf_coinc_required[6]
|-
| 7 || conf_coinc_required[7]
|-
| 15..8 || conf_coinc_window[7:0] || 0x5bc13541 (12Oct18_16:58) || coincidence window length in units of 125MHz clock (8 ns)
|-
| 23..16 || conf_coinc_start[7:0] || 0x5bc13541 (12Oct18_16:58) || start the coincidence window, same bits as "required"
|-
| 31..24 ||
|-
|}

== conf_trig_enable bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_enable_sw_trigger || || trigger on software trigger (how generated???)
|-
| 1 || conf_enable_pulser || || trigger on pulser
|-
| 2 || - || 0x5b120c9f (01Jun18_20:18) || not used
|-
| 3 || conf_pulser_run || || allow the pulser to run (frequency has to be set beforehand)
|-
| 4 || conf_output_pulser || 0x5bc8f90f || does nothing (top level ag_pulser_out is disconnected)
|-
| 4 || || 0x618b790b || not used
|-
| 5 || conf_enable_esata_nim || || trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand)
|-
| 6 || conf_enable_adc16 || || trigger on adc16_grand_or
|-
| 7 || conf_enable_adc32 || || trigger on adc32_grand_or
|-
| 8 || conf_enable_adc16_1ormore || || trigger on adc16_mult_1ormore "1 or more"
|-
| 9 || conf_enable_adc16_2ormore || || same, "2 or more"
|-
| 10 || conf_enable_adc16_3ormore || || same, "3 or more"
|-
| 11 || conf_enable_adc16_4ormore || || same, "4 or more"
|-
| 12 || - || 0x5b08938c (25May18_15:51) || not used
|-
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
|-
| 14 || - || 0x5bc8f90f || not used
|-
| 15 || conf_enable_adc || 0x5b120c9f (01Jun18_20:18) || trigger on adc_grand_or
|-
| 16 || conf_enable_aw16_coinc_a || 0x5bc8f90f || enable AW coincidence trigger, see [[#aw16_coinc]]
|-
| 16 || - || 0x62c77f0b || aw16_coinc_x removed
|-
| 17 || conf_enable_aw16_coinc_b || 0x5bc8f90f ||
|-
| 18 || conf_enable_aw16_coinc_c || 0x5bc8f90f ||
|-
| 19 || conf_enable_aw16_coinc_d || 0x5bc8f90f ||
|-
| 20 || - || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 20 || conf_enable_aw16_grand_or || 0x618b790b || enable trigger on aw16_grand_or
|-
| 21 || conf_enable_aw16_coinc || 0x5b3aa19f (02Jul18_15:05) || enable trigger on aw16_coinc_trig
|-
| 22 || conf_enable_aw16_mlu || 0x5b3aa19f (02Jul18_15:05) || enable AW MLU trigger
|-
| 23 || conf_enable_timeout_trig || 0x5bc8f90f (18Oct18_14:20) || enable trigger timeout trigger
|-
| 24 || conf_enable_aw16_1ormore || 0x5b3aa19f (02Jul18_15:05) || trigger on aw16_mult_1ormore "1 or more"
|-
| 24 || - || 0x62c77f0b || aw16_mult_xxx removed
|-
| 25 || conf_enable_aw16_2ormore || 0x5b3aa19f (02Jul18_15:05) || same, "2 or more"
|-
| 26 || conf_enable_aw16_3ormore || 0x5b3aa19f (02Jul18_15:05) || same, "3 or more"
|-
| 27 || conf_enable_aw16_4ormore || 0x5b3aa19f (02Jul18_15:05) || same, "4 or more"
|-
| 28 || conf_enable_bsc_grand_or || 0x5bc13541 (12Oct18_16:58) || trigger on BSC grand-or
|-
| 29 || conf_enable_bsc_mult || 0x5bc13541 (12Oct18_16:58) || trigger on BSC multiplicity
|-
| 30 || conf_enable_coinc || 0x5bc13541 (12Oct18_16:58) || trigger on TPC/BSC/ext coincidence trigger
|-
| 31 || - || || not used
|-
|}

== reg 0x2B bits ==

Write to this register will pulse corresponding fpga signals:

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || reset_out || 0x5b120c9f (01Jun18_20:18) || reset counters, etc
|-
| 1 || latch_out || 0x5b120c9f (01Jun18_20:18) || latch counters, sas bits, etc
|-
| 2 || trigger_out || 0x5b120c9f (01Jun18_20:18) || generate a software trigger
|-
|}

= UDP data format =

== firmware 0x5bc8f90f ==

{| cellpadding="10" cellspacing="0" border="1"
! Offset || Name || Quartus name || FwRev || Description
|-
| 0 || packet counter || none || all || 31-bit UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
|-
| 1 || 0x8 packet header || || all || 28 bits of counter_trig_out
|-
| 2 || trigger timestamp || trig_ts || all || 62.5MHz trigger timestamp
|-
| 3 || accepted triggers || counter_trig_out || all || counter of accepted triggers
|-
| 4 || input triggers || counter_trig_in || all || counter of trigger input
|-
| 5 || pulser triggers || counter_pulser || all || counter of pulser triggers
|-
| 6 || trigger bitmap || udp_trig_bits || 0x5a48448d (30Dec17_17:59) || bitmap of trigger information, see below
|-
| 7 || nim bits || udp_nim_bits_masked || ??? || 32 bits of ADC NIM inputs (2 bits per ADC)
|-
| 8 || esata bits || udp_esata_bits_masked || ??? || 32 bits of ADC ESATA inputs (2 bits per ADC)
|-
| 9 || mlu bits || aw16_prompt || 0x5b398983 (01Jul18_19:10) || 16 bits of MLU input, 1 bit per preamp
|-
| 10 || drift-blank-off counter || udp_drift_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the drift blank-off
|-
| 11 || scaledown counter || udp_scaledown_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the scaledown
|-
| X || || || ||
|-
| 12 || 0xE packet footer || || all || 28 bits of counter_trig_out
|-
|}

== firmware 0x618b790b (Nov 2021) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

== firmware 0x62d1c47e (Jul 2022) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, 8'h00, 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= conf_fw_rev;
18 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

Values of udp_coinc_latch[7:0]:
* aaa

Values of udp_aw16_mult[7:0] and udp_aw16_bus[15:0]:
* aaa

Values of udp_bsc64_mult[7:0] and udp_bsc64_bus[63:0]
* aaa

== trigger bitmap ==

Firmware ??? (one of the very early revisions)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= adc16_coinc_top;
udp_trig_bits[5] <= adc16_coinc_bot;
udp_trig_bits[6] <= adc16_coinc;
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
udp_trig_bits[31:24] <= mult16[7:0];

</pre>

Firmware 0x5b08938c (25May18_15:51)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= 0; // not used
udp_trig_bits[31:24] <= mult16[7:0];
</pre>

Firmware 0x5b217dc4 (13Jun18_13:25)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5b3aa19f (02Jul18_15:05)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= udp_mlu_out;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5bc8f90f (18Oct18_14:20)

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_run_pulser
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = 0; // not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x618b790b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x62c77f0b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = 0; // aw16_coinc_a;
assign trig32_in[17] = 0; // aw16_coinc_b;
assign trig32_in[18] = 0; // aw16_coinc_c;
assign trig32_in[19] = 0; // aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = 0; // aw16_mult_1ormore;
assign trig32_in[25] = 0; // aw16_mult_2ormore;
assign trig32_in[26] = 0; // aw16_mult_3ormore;
assign trig32_in[27] = 0; // aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc64_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

= TRG chronobox inputs =

from trg_firmware/toplevel/grifc.v

<pre>
localparam CB_N = 23;
localparam CB_N1 = CB_N-1;

wire [CB_N1:0] cb_xinputs_async;

assign cb_xinputs_async[0] = ag_trig_out;
assign cb_xinputs_async[1] = ag_trig_scaledown_out;
assign cb_xinputs_async[2] = ag_trig_drift_out;
assign cb_xinputs_async[3] = ag_trig_received_out;

assign cb_xinputs_async[4] = ag_cb_sw_trig;
assign cb_xinputs_async[5] = ag_cb_pulser_trig;
assign cb_xinputs_async[6] = ag_cb_esata_nim_trig;
assign cb_xinputs_async[7] = ag_cb_adc16_grand_or_trig;
assign cb_xinputs_async[8] = ag_cb_adc32_grand_or_trig;

assign cb_xinputs_async[9] = ag_cb_aw16_grand_or_trig;
assign cb_xinputs_async[10] = ag_cb_aw16_mult_1ormore;
assign cb_xinputs_async[11] = ag_cb_aw16_mult_2ormore;
assign cb_xinputs_async[12] = ag_cb_aw16_mult_3ormore;
assign cb_xinputs_async[13] = ag_cb_aw16_mult_4ormore;
assign cb_xinputs_async[14] = ag_cb_aw16_mlu_trig;

assign cb_xinputs_async[15] = ag_cb_bsc64_grand_or_trig;
assign cb_xinputs_async[16] = ag_cb_bsc64_mult_1ormore;
assign cb_xinputs_async[17] = ag_cb_bsc64_mult_2ormore;
assign cb_xinputs_async[18] = ag_cb_bsc64_mult_3ormore;
assign cb_xinputs_async[19] = ag_cb_bsc64_mult_4ormore;
assign cb_xinputs_async[20] = ag_cb_bsc64_mult_trig;

assign cb_xinputs_async[21] = ag_cb_coinc_trig;

assign cb_xinputs_async[22] = ag_cb_timeout_trig;
</pre>

= Example UDP packets =

* trigger data, marker words 0x8

<pre>
ReadDataThread read 76
0: 0x003666ed -- UDP packet counter from UDP transmitter
1: 0x80000bf8 -- 0x8 is trigger data packet, 0xbf8 is the trigger counter from alphag.v
2: 0x2edf8b41 -- trigger data
3: 0x00000bf8
4: 0x00000bf8
5: 0x00000bee
6: 0x00000001
7: 0x00000000
8: 0x00000000
9: 0x00000003
10: 0x00000bf8
11: 0x00000bf8
12: 0x00000000
13: 0x00000000
14: 0x00000000
15: 0x00000000
16: 0x00000000
17: 0x00000000
18: 0xe0000bf8 -- 0xE is end of trigger data, counter 0xbf8 must match the counter in the 0x8 word.
ReadDataThread read 76 -- next packet
0: 0x003666ee -- UDP packet counter from UDP transmitter
...
</pre>

* chronobox fifo data, marker word 0xC, see [[Chronobox#FIFO_data_format]]

<pre>
ReadDataThread read 404
0: 0x003658ed -- UDP packet counter from UDP transmitter
1: 0xc000eacc -- 0xC is FIFO data, fifo packet counter 0xeacc from fifo_to_udp.v
2: 0x00000061 -- FIFO status, low bits the the word counter, so up to 0x61 fifo words are to follow
3: 0x87fb3d72 -- tsc hits
4: 0x8ffb3d74
5: 0x90fb3d74
6: 0x91fb3d74
7: 0x92fb3d74
8: 0x93fb3d74
9: 0x93fb3d75
10: 0x94fb3d74
11: 0x94fb3d77
12: 0x87fb3d77
13: 0x8ffb3d77
14: 0x90fb3d77
15: 0x91fb3d77
16: 0x92fb3d77
17: 0xfe000018 -- 0xFE scaler data starts, 0x18 words to follow
18: 0x00000000
19: 0x00000000
20: 0x00000000
21: 0x00000000
22: 0x00000000
23: 0x00000000
24: 0x00000000
25: 0x00000108
26: 0x00000000
27: 0x00000000
28: 0x00000000
29: 0x00000000
30: 0x00000000
31: 0x00000000
32: 0x00000000
33: 0x00000108
34: 0x00000108
35: 0x00000108
36: 0x00000108
37: 0x00000108
38: 0x00000108
39: 0x00000000
40: 0x00000000
41: 0xce56fa93 -- last word of scaler data is the sysclock counter (125 MHz)
42: 0xff800048 -- timestamp wraparound
43: 0x8f1f36e4 -- tsc hits
44: 0x901f36e4
45: 0x911f36e4
46: 0x921f36e4
47: 0x931f36e4
48: 0x941f36e4
49: 0x871f36e4
50: 0x871f36e7
51: 0x8f1f36e7
52: 0x901f36e9
53: 0x911f36e7
54: 0x921f36e9
55: 0x931f36e7
56: 0x941f36e9
57: 0x904330ac
58: 0x914330ac
59: 0x924330ac
60: 0x934330ac
61: 0x934330ad
62: 0x944330ac
63: 0x944330ad
64: 0x874330ac
65: 0x874330ad
66: 0x8f4330ac
67: 0x8f4330ad
68: 0x904330ad
69: 0x914330ad
70: 0x924330ad
71: 0x8f672a62
72: 0x90672a62
73: 0x91672a62
74: 0x92672a62
75: 0x93672a62
76: 0x94672a62
77: 0x87672a62
78: 0x87672a65
79: 0x8f672a65
80: 0x90672a65
81: 0x91672a65
82: 0x92672a65
83: 0x93672a65
84: 0x94672a65
85: 0xff000049
86: 0x878b2422
87: 0x8f8b2424
88: 0x908b2424
89: 0x918b2424
90: 0x928b2424
91: 0x938b2424
92: 0x938b2425
93: 0x948b2424
94: 0x948b2427
95: 0x878b2427
96: 0x8f8b2427
97: 0x908b2427
98: 0x918b2427
99: 0x928b2427
100: 0xe000eacc -- 0xE is end of fifo data, counter 0xeacc must match the counter in the 0xC word.
ReadDataThread read 344 -- next packet
...
</pre>

= TODO =

* DONE July 2022. add FwRev to the UDP data output
* RJ45 SFP: PROBLEM, D.A. CABLE: GOOD, Fiber SFP: ???. fix "write did not happen" (send udp write command, there is no reply, read returns old data as if write never happened). suspect udp "write" packet is lost?
* PROBLEM GONE Aug 2021. fix reply to wrong socket - udp packets should reply to same socket as they came from, udp data packets should be sent to same socket as requested them, not same socket as last command.
* DONE 2021jul30. add fixes from Chris P. for the auto-negotiation and dhcp (see email from him).
* DONE flash chip connected to FPGA. Aug 2021. implement ethernet flash programmer
* DONE Aug 2021. updated maxv firmware. implement FPGA reboot
* speed up programming the MLU by writing more than 1 bit at a time
* DONE Nov 2021. add 64-bit bitmap of BSC trigger bits
* DONE. add chronobox code
* DONE. add avalon mux for alphag and chronobox packets
* DONE. add chronobox fifo to udp packet sequencer
* check that TxReadyOut is correct and it is safe to send an avalon packet while previous packet is still transmitting.
* DONE. test fiber SFP is working
* complete the UDP flash programmer (parallel flash erase and write)

= End =

//KO

TRG

2022-07-16T21:43:06Z

Olchansk: /* additional registers */

= TRG, the trigger control board for the ALPHA-g detector =

= Links =

* xxx
* https://bitbucket.org/expalpha/trg_firmware - firmware sources on bitbucket

= General characteristics =

== Photos ==

== Board schematics ==

* https://bitbucket.org/expalpha/trg_firmware/src/master/3xFMC_VME_Motherboard.pdf

== Available hardware ==

* Altera Stratix IV - main FPGA
* Altera Max V - boot FPGA
* boot flash: PC28F512M29EW - 512 Mbit parallel NOR flash.

= TRG front panel connections =

From top to bottom:

<pre>
|
| minisas-C - links 8-11
| minisas-D - links 12-15
|
| ethernet sfp - use copper sfp only
| minisas - not used, do not connect
| esata - clock in, trigger out
|
| minisas-A - links 0-3
| minisas-B - links 4-7
|
| LEDs
|
</pre>

MiniSAS and SATA flail cable connections:

<pre>
P1 <--> link 3
P2 <--> link 2
P3 <--> link 1
P4 <--> link 0
</pre>

LEDs:

<pre>
--PCB-- (left)
LED[0] - trigger out - ag_trig_out
LED[1] - network packet received - sfp_rx_data_valid
LED[2] - Xilinx FPGA boot ok - FMC1_CFG_DONE
LED[3] - not used
(right)
</pre>

= TRG onboard jumpers and switches =

* rotary switches: select IP address: 00=192.168.1.50, 11=.51, 22=.52, 33=.53, 44=.54, otherwire=.251

= Firmware update procedure =

* use quartus to generate the grifc.pof file (use grifc.cof)
* open quartus programmer
* attach grifc.pof to the 1st CFI_512 flash
* mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
* check that "initiate configuration after programming" is set in tools->options
* say "start"
* should take about 5 minutes
* grifc should reboot into the new firmware

If CFI_512 flash is not visible to the quartus programmer, load correct
code into the MaxV CPLD:

* open quartus programmer,
* say "auto detect"
* change file for the 5M2210 device
* use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
* say "program", it should finish in 10-15 seconds
* say "auto detect"
* CFI_512 flash should be visible now.

= Firmware revisions =

* 0x5bc8f90f - original firmware used for all data
* 0x6147c0f9 - added cbtrg, etc. installed at CERN on 20 Sep 2021.
* 0x618376ae - bigger cbtrg fifo, data rate tested up to 30 Mbytes/sec
* 0x6189c7f3 - fix loss of trigger packets. (missing fifo between alphag block and ethernet mux)
* 0x618b790b - fix loss of timestamps. (cbtrg inputs stretched to 100 ns long). installed at CERN 10 Nov 2021.

= Firmware build =

* use quartus 20.1
* see Makefile in the trg_firmware project

= Jtag remote connection =

* ssh agmini@daq16
* /opt/intelFPGA/16.1/quartus/bin/jtagd --config /home/agmini/.jtagd.conf
* netstat -an | grep 1309 ### note listen address is "0.0.0.0", NOT "127.0.0.1"
<pre>
tcp 0 0 0.0.0.0:1309 0.0.0.0:* LISTEN
</pre>
* opt/intelFPGA/16.1/quartus/bin/jtagconfig ### should work
* ssh olchansk@daq01
* cd git/trg_firmware
* /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
* jtagconfig ### should work
<pre>
daq01:trg_firmware$ jtagconfig
1) DE-SoC on daq16 [2-1.2.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) USB-Blaster on daq16 [2-1.3]
024090DD EP4SGX230(.|ES)
020A40DD 5M(1270ZF324|2210Z)/EPM2210

daq01:trg_firmware$
</pre>

= ALPHA-g trigger functions =

Trigger options:
* software trigger
* pulser trigger
* trigger on GRIF16 ADC NIM and ESATA inputs ("external trigger")
* adc16 grand-or
* adc32 grand-or
* adc16 wire multiplicity
* TPC anode wire per-preamp trigger (aw16 section)
** trigger on coincidences of preamps (removed fw 0x62c77f0b)
** trigger on multiplicity of preamps (removed fw 0x62c77f0b)
** trigger on specific topology of preamps (multiplicity of preamp clusters, etc) via the aw16_mlu trigger
* BSC trigger
** BSC grand_or
** BSC bar multiplicity
* coincidence trigger - select coincidence of external trigger, TPC AW grand-or, TPC AW MLU, BSC grand-or and BSC bar multiplicity triggers

== software trigger ==

to programmatically fire the trigger, one should:
* set the conf_enable_sw_trigger bit in conf_trig_enable, this will permit the software trigger to fire the trigger
* write value 0x4 to register 0x2B, this will cause the software trigger to fire

== pulser trigger ==

To use the pulser trigger, one should program:
* pulser period (in clocks)
* pulser width (in clocks, use value 5, the pulser no longer goes outside of the trigger board, so changing the width does not do anything)
* set the run_pulser bit in conf_trig_enable, this will cause the pulser to run
* set the enable_pulser bit in conf_trig_enable, this will cause the pulser to fire the trigger
* set the output_pulser bit in conf_trig_enable, this will cause the pulser to be output from the alphag firmware block (the pulser no longer goes outside of the trigger board, so changing the bit does not do anything)

== timeout trigger ==

The event builder uses event timestamps to assemble physics events. The timestamps
are usually 32 bit wide and run at 125 MHz (8 ns) or 62.5 MHz (16 ns). If
triggers are generated often (1 per second or more), timestamp wrap around
is easily detected by the event builder. If triggers come infrequently,
timestamp wrap around may occur while there are no triggers, not be seen
by the event builder causing loss of event synchronization.

To avoid this problem in the event builder, a timeout trigger should be generated
if no triggers were generated inside a 10 second interval.

The guaranties that even if all physics triggers temporarily stop for any reason,
the event builder will stay synchronized. (0.1 Hz timeout trigger frequency).

To enable the timeout trigger:
* program timeout trigger timeout in reg 0x43 in units of 8 ns clock
* enable it in bit 23 of [[#conf_trig_enable bits]]

== adc16 multiplicity trigger ==

This trigger is intended for use with the barrel scintillator signals connected to adc16 digitizers. It does not work well with TPC AW signals.

The 16 adc16 trigger bits (16x16=256) are added together to form the hit multiplicity value (adc16_mult, 16 bits, actual range 0 to 256).

Four threshold signals are computed: adc16_mult_1ormore = adc16_mult>=1, 2ormore, 3ormore, 4ormore.

There is a counter for each of these four signals.

Each of these four signals can fire the trigger, see [[#conf_trig_enable bits]].

== TPC anode wire triggers ==

=== aw16 bus ===

TPC Anode Wire trigger is based on the aw16[15:0] (xaw16) bus.

Each bit corresponds to one AW preamp. 16 preamps, 16 bits.

The aw16[15:0] bus can be fed by
* adc16_or16[15:0] - or16 of 100 MHz ADCs, 16 ADC sas links
* adc32_or16[15:0] - or16 of 62.5 MHz ADCs, FMC-ADC32 has 32 channels, so 2 bits per ADC: low 16 channels and high 16 channels, sas links 7..0
* adc32_or16[31:16] - or16 of 62.5 MHz ADCs, ditto, sas links 15..8
as selected by conf_enable_aw_adc16, conf_enable_aw_adc32a, conf_enable_aw_adc32b in [[#conf_control bits]]

<pre>
///////////////////////////////////////////////////////////
// TPC Anode Wire trigger logic (aw16)
///////////////////////////////////////////////////////////

// map adc signals into aw16

wire [15:0] aw16 = ({16{conf_enable_aw_adc16}} & adc16_or16[15:0]) |
({16{conf_enable_aw_adc32a}} & adc32_or16[15:0]) |
({16{conf_enable_aw_adc32b}} & adc32_or16[31:16]);
...
ag_conditioner cond_adc16_or16_0(.clk(clk), .in(aw16[0]), .out(xxaw16[0]));
...
xaw16 <= xxaw16;
</pre>

=== aw16_grand_or ===

TPC AW "grand or" trigger: use aw16_mult_1ormore (before fw 0x62c77f0b)

(256 anode wires, 16 wires per preamp, 16 preamps, 16 aw16 signals)

=== aw16_mlu ===

TPC AW preamp MLU trigger: the MLU (memory lookup
table) implements an arbitrary logical function
to map the 16 aw16 preamp signals into 1 aw16_mlu_trig trigger output.

Description of the aw16 mlu trigger.

In words:

* any aw16 signal starts the aw16_prompt_run gate
* aw16 signals are collected for the duration of conf_mlu_prompt (125MHz/8ns clock)
* this corresponds to time spread of TPC AW signals due to the drift time in the AW drift cell and to the variation in signal transmission time from the ADC to the TRG (digital trigger data link).
* when this prompt time expires, the MLU looks at the accumulated aw16_prompt bit pattern and makes the "yes/no" trigger decision
* after the trigger decision is made, we wait for the TPC to become quiet:
* we wait until all aw16 signals are empty (no timeout)
* we run the aw16_prompt_wait gate, length conf_mlu_wait (8ns clock), if any aw16 signals arrive, we wait for aw16 empty again, rinse, repeat.
* now, after TPC aw16 have been empty for conf_mlu_wait clocks (8ns clock), MLU trigger is ready for the next event.

In logic: (see alphag.v)

* aw16_or <= grand-or of 16 aw16 signals
* "aw16_or" starts the "aw16_prompt_cnt" counter, opens the aw16_prompt_run gate
* during the aw16_prompt_run gate, aw16_prompt collects (latches) the aw16 bits (aw16_prompt <= aw16_prompt | aw16)
* this is the time when we wait for all "prompt" signals from the TPC to arrive into the trigger
* at the end of the aw16_prompt_run gate, the signal aw16_prompt_out is pulsed, latching the output of the MLU into aw16_mlu_trig
* this is the MLU trigger "yes/no" trigger decision.
* after the MLU trigger decision is made, we wait for the arrival and passing of all TPC drift signals
* the aw16_prompt_wait_cnt and aw_prompt_wait gate opens
* if any new aw16 signals arrive (they are TPC drift signals at this time), the aw16_prompt_wait gate is restarted
* if no aw16 signals arrive during the full run of the aw16_prompt_wait gate ("TPC quiet time")
* the aw16_prompt_wait and aw16_prompt gates are cleared and the MLU trigger is ready for the next event.

Good settings are:
* conf_mlu_prompt: 64 (512 ns)
* conf_mlu_wait: 128 (1024 ns)

== BSC trigger ==

=== bsc_adc16 bus ===

The BSC trigger is based on the [15:0]bsc_adc16[7:0] bus: 16 trigger discriminator bits from 8 ADC sas links. (8*16 = 64+64 bars, top and bottom).

The bsc_adc16 bus can be fed from sas links 0..7 or 8..15, controlled by conf_bsc_adc16_a and conf_bsc_adc16_b bits on [[#conf_bsc_control bits]].

bsc_adc16 can be fed only from GRIF-16 100 MHz ADC trigger discriminators.

=== bsc64_top and bsc64_bot buses ===

* firmware 0x5bc8f90f: bsc_adc16 is remapped into 64 bits of top (bsc64_top) and bottom (bsc64_bot):
<pre>
ag_bsc_remap bsc_remap_a(.adc(bsc_adc16[0]), .bsc_bot(bsc64_bot[7:0]), .bsc_top(bsc64_top[7:0]));
ag_bsc_remap bsc_remap_b(.adc(bsc_adc16[1]), .bsc_bot(bsc64_bot[8+7:8+0]), .bsc_top(bsc64_top[8+7:8+0]));
ag_bsc_remap bsc_remap_c(.adc(bsc_adc16[2]), .bsc_bot(bsc64_bot[2*8+7:2*8+0]), .bsc_top(bsc64_top[2*8+7:2*8+0]));
ag_bsc_remap bsc_remap_d(.adc(bsc_adc16[3]), .bsc_bot(bsc64_bot[3*8+7:3*8+0]), .bsc_top(bsc64_top[3*8+7:3*8+0]));

ag_bsc_remap bsc_remap_e(.adc(bsc_adc16[4]), .bsc_bot(bsc64_bot[4*8+7:4*8+0]), .bsc_top(bsc64_top[4*8+7:4*8+0]));
ag_bsc_remap bsc_remap_f(.adc(bsc_adc16[5]), .bsc_bot(bsc64_bot[5*8+7:5*8+0]), .bsc_top(bsc64_top[5*8+7:5*8+0]));
ag_bsc_remap bsc_remap_g(.adc(bsc_adc16[6]), .bsc_bot(bsc64_bot[6*8+7:6*8+0]), .bsc_top(bsc64_top[6*8+7:6*8+0]));
ag_bsc_remap bsc_remap_h(.adc(bsc_adc16[7]), .bsc_bot(bsc64_bot[7*8+7:7*8+0]), .bsc_top(bsc64_top[7*8+7:7*8+0]));

module ag_bsc_remap
(
input wire [15:0] adc,
output wire [7:0] bsc_bot,
output wire [7:0] bsc_top
);

assign bsc_top[3] = adc[0];
assign bsc_top[2] = adc[1];
assign bsc_top[1] = adc[2];
assign bsc_top[0] = adc[3];

assign bsc_top[7] = adc[4];
assign bsc_top[6] = adc[5];
assign bsc_top[5] = adc[6];
assign bsc_top[4] = adc[7];

assign bsc_bot[0] = adc[8];
assign bsc_bot[1] = adc[9];
assign bsc_bot[2] = adc[10];
assign bsc_bot[3] = adc[11];

assign bsc_bot[4] = adc[12];
assign bsc_bot[5] = adc[13];
assign bsc_bot[6] = adc[14];
assign bsc_bot[7] = adc[15];

endmodule
</pre>

=== bsc64 bus ===

the bsc64 bus is the 64 bars used by the trigger, formed from bsc64_top and bsc64_bot:
<pre>
if (conf_bsc64_bot_only) begin
bsc64 <= bsc64_bot;
end else if (conf_bsc64_top_only) begin
bsc64 <= bsc64_top;
end else if (conf_bsc64_bot_top_or) begin
bsc64 <= bsc64_bot | bsc64_top;
end else if (conf_bsc64_bot_top_and) begin
bsc64 <= bsc64_bot & bsc64_top;
end else begin
bsc64 <= 64'b0;
end
</pre>

=== bsc_grand_or_trig ===

bsc_grand_or_trig is the grand-or of 64 bits of the bsc64 bus

to enable triggering on bsc_grand_or_trig, set corresponding bit in [[#conf_trig_enable bits]]

=== old bsc_mult_trig ===

(from fw 0x62c77f0b, old bsc_mult_trig was replaced by new bsc64 multiplicity trigger)

* bsc64_mult is computed as multiplicity of the bsc64 bus (number of 64 bsc64 bits that fired)
* bsc_mult_trig is computed:
<pre>
if (bsc64_mult >= conf_bsc64_mult) begin
bsc_mult_trig <= 1;
end else begin
bsc_mult_trig <= 0;
end
</pre>

to enable the bsc multiplicity trigger, set the multiplicity value conf_bsc64_mult in [[#conf_bsc_control bits]] and enable the corresponding bit in [[#conf_trig_enable bits]].

=== bsc64 multiplicity trigger ===

bsc64 BSC bar multiplicity trigger uses a time window. this time window is started by bsc64_grand_or and runs for conf_bsc64_mult_window clocks (8 nc clock). During this time, hits in bsc64_bus are accumulated (latched) and their multiplicity is computed. If multiplicity condition is satisfied (bigger or equal to conf_bsc64_mult_min), bsc64_mult_trig is fired and the bsc64 bit pattern is saved to the UDP packet. Then trigger waits for the bsc64_bus to be empty. Then trigger waits for conf_bsc64_empty_window clocks, if there is any bsc64 hits, we wait for empty again. So after bsc64 has been empty for conf_bsc64_empty_window clocks, multiplicity trigger is ready for the next event. This scheme cannot implement max multiplicity.

recommended values:
* conf_bsc64_mult_window (8 bits): slightly longer than 3 cycles of SAS link: 3*18 = 54 clocks, good value is 80 (640 ns).
* conf_bsc64_mult_min (8 bits): 2
* conf_bsc64_empty_window (8 bits): 80 (640 ns)

== Coincidence trigger ==

Coincidence trigger provides a combination of TPC, BSC and external scintillator (esata_nim_grand_or) signals:

<pre>
assign coinc_input[0] = aw16_grand_or; // was aw16_mult_1ormore;
assign coinc_input[1] = aw16_mlu_trig;
assign coinc_input[2] = bsc_grand_or_trig;
assign coinc_input[3] = bsc_mult_trig;
assign coinc_input[4] = esata_nim_grand_or;
assign coinc_input[5] = 0;
assign coinc_input[6] = 0;
assign coinc_input[7] = 0;
</pre>

Coincidence trigger "start" mask selects which of the inputs can start the coincidence window.

Coincidence trigger "require" mask selects which inputs must have a hits for the coincidence to be satisfied.

Input hits are collected for the duration of the coincidence window, if all required inputs have hits, coinc_trig is fired.

Example settings:

* coincidence of external scintillator, BSC and TPC AW "grand or" signals: start 0x10, required 0x15
* coincidence of BSC grand-or and TPC AW grand-or signals: start 0x5, required 0x5
* coincidence of BSC multiplicity and TPC AW grand-or triggers: start 0x9, required 0x9

= Control registers =

== Register addresses ==

Note: all registers are 32 bits unless otherwise noted.

Note: RW means read-write register, RO means read-only, ROL means read-only, contents is latched by the "latch_out" bit

{| cellpadding="10" cellspacing="0" border="1"
! Address || Quartus Name || Access || FwRev || Description
|-
| 0x08 || num_sample || RW || GRIF-C || magic 16-bit register to control UDP packet size
|-
| 0x08 || scratch_reg || RW || 0x618b790b || 32-bit scratch register
|-
| 0x1F || compilation_time || RO || || Firmware revision
|-
| 0x20 || conf_trig_width || RW || || Trigger signal width, 16 ns clock
|-
| 0x21 || conf_busy_width || RW || || Busy signal width, 16 ns clock (not used)
|-
| 0x22 || conf_pulser_width || RW || || Pulser signal width, 16 ns clock
|-
| 0x23 || conf_pulser_period || RW || || Pulser signal period, 16 ns clock
|-
| 0x24 || conf_pulser_burst_ctrl || RW || 0x62d1c47e || Generate bursts of pulses: 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses, 16 ns clocks
|-
| 0x25 || conf_trig_enable || RW || || see [[#conf_trig_enable bits]]
|-
| 0x26 || || || not used
|-
| 0x27 || || || not used
|-
| 0x28 || || || not used
|-
| 0x29 || conf_nim_mask || RW || || enable bits for ADC NIM inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2A || conf_esata_mask || RW || || enable bits for ADC eSATA inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2B || reset_out, latch_out, trigger_out || W || || see [[#reg 0x2B bits]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x5bc8f90f || configure AW coincidence trigger, see [[#aw16_coinc]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x62c77f0b || removed
|-
| 0x2D || conf_aw16_coinc_b || RW || 0x5bc8f90f ||
|-
| 0x2E || conf_aw16_coinc_c || RW || 0x5bc8f90f ||
|-
| 0x2F || conf_aw16_coinc_d || RW || 0x5bc8f90f ||
|-
| 0x30 || sas_sd[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect for each link
|-
| 0x31 || pll_625_status || ROL || 0x5b2057f5 (12Jun18_16:32) || 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter
|-
| 0x32 || clk_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the system 125 MHz clock
|-
| 0x33 || clk_625_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625)
|-
| 0x34 || conf_control || RW || 0x5b398983 (01Jul18_19:10) || see [[#conf_control bits]] below
|-
| 0x35 || conf_drift_width || RW || 0x5b398983 (01Jul18_19:10) || width of drift time blank-out in 16 ns clocks
|-
| 0x36 || conf_scaledown || RW || 0x5b398983 (01Jul18_19:10) || trigger scaledown, 0=no scaledown, 1=divide-by-2, 2=divide-by-3, etc
|-
| 0x37 || conf_mlu || RW || 0x5b398983 (01Jul18_19:10) || AW MLU control bits, see [[#conf_mlu bits]]
|-
| 0x38 || conf_trig_delay || RW || 0x5baedfca (28Sep18_19:13) || delay the trigger pulse, 16 ns clock
|-
| 0x39 || esata_clk_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the TRG 125 MHz clock
|-
| 0x3A || esata_clk_esata_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the external clock (eSATA 62.5 MHz clock)
|-
| 0x3B || conf_counter_adc_select || RW || 0x5bb7f6ae (05Oct18_16:41) || select which 16 ADCs are connected to the selected adc counters, 0..15 - connect the adc16 signals, 16..47 connect the adc32 signals
|-
| 0x3C || sysreset_ts || RO || 0x5bb7f6ae (05Oct18_16:41) || 125MHz counter of VME-SYSRESET
|-
| 0x3C || || || 0x618b790b || not used
|-
| 0x3D || GRIF-C csr || RW || GRIF-C || <= csr & ~par_value; // Selective clear
|-
| 0x3E || GRIF-C csr || RW || GRIF-C || <= csr | par_value; // Selective set
|-
| 0x3F || GRIF-C csr || RW || GRIF-C || <= par_value; // write
|-
| 0x3D || || || 0x618b790b || not used
|-
| 0x3E || || || 0x618b790b || not used
|-
| 0x3F || || || 0x618b790b || not used
|-
| 0x40 || conf_bsc_control || RW || 0x5bc13541 (12Oct18_16:58) || Barrel Scintillator trigger control, see [[#conf_bsc_control bits]]
|-
| 0x41 || conf_coinc_control || RW || 0x5bc13541 (12Oct18_16:58) || Coincidence trigger control, see [[#conf_coinc_control bits]]
|-
| 0x42 || reconfig_out || WO || 0x5bc13541 (12Oct18_16:58) || reserved for rebooting the FPGA (does not work)
|-
| 0x43 || conf_trigger_timeout || RW || 0x5bc8f90f (18Oct18_14:20) || Generate timeout trigger if there is no other trigger after given timeout, in 8 ns clocks, must be enabled by bit conf_enable_timeout_trig in [[#conf_trig_enable bits]]
|-
| 0x44 || eth_clk_counter || ROL || 0x618b790b ||
|-
| 0x45 || eth_clk_eth_counter || ROL || 0x618b790b ||
|-
| 0x100 || ts_625 || ROL || || latched timestamp
|-
| 0x101 || counter_trig_out || ROL || || counter of issued triggers
|-
| 0x102 || counter_trig_in || ROL || || counter of triggers
|-
| 0x103 || counter_pulser || ROL || || counter of pulser
|-
| 0x104 || counter_adc16_grand_or || ROL ||
|-
| 0x105 || counter_adc32_grand_or || ROL ||
|-
| 0x106 || counter_adc_grand_or || ROL ||
|-
| 0x107 || counter_esata_nim_grand_or || ROL ||
|-
| 0x108 || counter_adc16_mult_1ormore || ROL ||
|-
| 0x109 || counter_adc16_mult_2ormore || ROL ||
|-
| 0x10A || counter_adc16_mult_3ormore || ROL ||
|-
| 0x10B || counter_adc16_mult_4ormore || ROL ||
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x5bc8f90f || counter of AW coincidence triggers
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x62c77f0b || removed
|-
| 0x10D || counter_aw16_coinc_b || ROL || 0x5bc8f90f ||
|-
| 0x10E || counter_aw16_coinc_c || ROL || 0x5bc8f90f ||
|-
| 0x10F || counter_aw16_coinc_d || ROL || 0x5bc8f90f ||
|-
| 0x110 || counter_drift || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the drift time blank-out
|-
| 0x111 || counter_scaledown || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the scaledown
|-
| 0x112 || counter_aw16_coinc || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW coincidence triggers
|-
| 0x113 || counter_aw16_mlu || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW MLU triggers
|-
| 0x114 || counter_aw16_grand_or || ROL || 0x62c77f0b || counter of AW grand-or triggers
|-
| 0x114 || counter_aw16_mult_1ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 1ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 2ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x62c77f0b || removed
|-
| 0x116 || counter_aw16_mult_3ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 3ormore triggers
|-
| 0x117 || counter_aw16_mult_4ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 4ormore triggers
|-
| 0x118 || counter_bsc_grand_or || ROL || 0x5bc13541 (12Oct18_16:58) || counter of BSC grand-or triggers
|-
| 0x119 || counter_bsc_mult || ROL || 0x5bc13541 (12Oct18_16:58) || counter of old BSC multiplicity triggers
|-
| 0x11A || counter_coinc || ROL || 0x5bc13541 (12Oct18_16:58) || counter of coincidence triggers
|-
| 0x11B || counter_timeout || ROL || 0x618b790b || counter of timeout triggers
|-
| 0x11C || counter_bsc_mult_start || ROL || 0x62c77f0b || counter of BSC multiplicity windows
|-
| 0x11D || counter_bsc_mult_trig || ROL || 0x62c77f0b || counter of BSC multiplicity triggers
|-
| 0x11E || counter_coinc_start || ROL || 0x62d1b152 || counter of coincidence windows
|-
| 0x11F || counter_aw16_mlu_start || ROL || 0x62d1b152 || counter of TPC AW MLU windows
|-
| 0x200..0x207 || conf_adc16_masks || RW || all || adc16 enable bits
|-
| 0x300..0x30F || conf_adc32_masks || RW || all || adc32 enable bits
|-
| 0x400..0x41F || sas_bits[15:0][63:0] || ROL || all || sas data bits for each link
|-
| 0x420..0x42F || sas_sd_counters[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect counter for each link
|-
| 0x430..0x43F || counters_adc16_or16[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 16 counters of adc16 ORes
|-
| 0x440..0x45F || counters_adc32_or16[31:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 32 counters of adc32 ORes
|-
| 0x460..0x46F || counters_adc_selected[15:0] || ROL || 0x5bb7f6ae (05Oct18_16:41) || 16 counters for selected group of adcs, see conf_counter_adc_select
|-
| 0x470..0x4AF || counters_bsc64[63:0] || ROL || 0x5bc13541 (12Oct18_16:58) || 64 counters for the BSC bars
|-
|}

== additional registers ==

<pre>
reg | rw/ro/rol | quartus name | firmware | description
0x60 | rw | cb_control_out | 0x618b790b | chronobox control
0x61 | rw | cb_status | 0x618b790b | chronobox status
0x62 | rw | cb_invert_a_out | 0x618b790b | chronobox input invert
0x63 | rw | cb_invert_b_out | 0x618b790b |
0x64 | rw | cb_enable_le_a_out | 0x618b790b | timestamp enable leading edge
0x65 | rw | cb_enable_le_b_out | 0x618b790b |
0x66 | rw | cb_enable_te_a_out | 0x618b790b | timestamp enable traiing edge
0x67 | rw | cb_enable_te_b_out | 0x618b790b |
0x6A | ro | cb_input_num | 0x618b790b | chronobox number of inputs
0x6B | rw | cb_sync_mask_a_out | 0x618b790b | chronobox sync signal source
0x6C | rw | cb_sync_mask_b_out | 0x618b790b |
0x6D | rw | cb_sync_reg_out | 0x618b790b | chronobox sync register
0x6E | ro | cb_sync_status | 0x618b790b | chronobox sync status
0x6F | rw | cb_latch_period_out | 0x618b790b | chronobox scalers latch period
0x70 | ro | cb_fifo_status | 0x618b790b | chronobox data fifo status
0x71 | ro | cb_fifo_data | 0x618b790b | read chronobox data fifo (cb_fifo_rdack_out <= 1)
0x72 | rw | cb_udp_period_out | 0x618b790b | period for flushing fifo to UDP
0x73 | rw | cb_udp_threshold_out | 0x618b790b | byte threshold for flushing fifo to UDP
</pre>

== conf_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_clock_select || 0x5b3aa19f (02Jul18_15:05) || select 0=internal 62.5 MHz clock or 1=esata 62.5 MHz clock
|-
| 1 || conf_enable_aw_adc16 || 0x5baedfca (28Sep18_19:13) || select source of TPC AW aw16 bus, see [[#aw16 bus]]
|-
| 2 || conf_enable_aw_adc32a || 0x5baedfca (28Sep18_19:13) ||
|-
| 3 || conf_enable_aw_adc32b || 0x5baedfca (28Sep18_19:13) ||
|-
| 15..4 || || ||
|-
| 23..16 || conf_mlu_prompt || 0x5b3aa19f (02Jul18_15:05) || MLU trigger prompt window, see [[#aw16_mlu]]
|-
| 31..24 || conf_mlu_wait || 0x5b3aa19f (02Jul18_15:05) || MLU trigger wait window, see [[#aw16_mlu]]
|-
|}

== conf_mlu bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 31 || mlu_reset || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 30 || mlu_write || 0x5b3aa19f (02Jul18_15:05) || 1=write data bit into given address
|-
| 16 || mlu_data || 0x5b3aa19f (02Jul18_15:05) || data bit for writing to MLU RAM
|-
| 15..0 || mlu_write_addr || 0x5b3aa19f (02Jul18_15:05) || MLU RAM write address for writing the data bit
|-
|}

== conf_bsc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_bsc_adc_a || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 0..7
|-
| 1 || conf_bsc_adc_b || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 8..15
|-
| 2 || conf_bsc64_bot_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses bottom channels only
|-
| 3 || conf_bsc64_top_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses top channels only
|-
| 4 || conf_bsc64_bot_top_or || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "or" of top and bottom
|-
| 5 || conf_bsc64_bot_top_and || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "and" of top and bottom
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_bsc64_mult_min || 0x5bc13541 (12Oct18_16:58) || minimum bsc64 multiplicity
|-
| 23..16 || conf_bsc64_empty_wondow || 0x62d1c47e || bsc64 empty window length, 8 ns clocks
|-
| 31..24 || conf_bsc64_mult_window || 0x62c77f0b || bsc64 multiplicity window length, 8 ns clocks
|-
|}

== conf_coinc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_coinc_required[0] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mult_1ormore
|-
| 0 || conf_coinc_required[0] || 0x62c77f0b || enable aw16_grand_or
|-
| 1 || conf_coinc_required[1] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mlu_trig
|-
| 2 || conf_coinc_required[2] || 0x5bc13541 (12Oct18_16:58) || enable bsc_grand_or_trig
|-
| 3 || conf_coinc_required[3] || 0x5bc13541 (12Oct18_16:58) || enable bsc_mult_trig
|-
| 3 || conf_coinc_required[3] || 0x62c77f0b || enable bsc64_mult_trig
|-
| 4 || conf_coinc_required[4] || 0x5bc13541 (12Oct18_16:58) || enable esata_nim_grand_or
|-
| 5 || conf_coinc_required[5]
|-
| 6 || conf_coinc_required[6]
|-
| 7 || conf_coinc_required[7]
|-
| 15..8 || conf_coinc_window[7:0] || 0x5bc13541 (12Oct18_16:58) || coincidence window length in units of 125MHz clock (8 ns)
|-
| 23..16 || conf_coinc_start[7:0] || 0x5bc13541 (12Oct18_16:58) || start the coincidence window, same bits as "required"
|-
| 31..24 ||
|-
|}

== conf_trig_enable bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_enable_sw_trigger || || trigger on software trigger (how generated???)
|-
| 1 || conf_enable_pulser || || trigger on pulser
|-
| 2 || - || 0x5b120c9f (01Jun18_20:18) || not used
|-
| 3 || conf_pulser_run || || allow the pulser to run (frequency has to be set beforehand)
|-
| 4 || conf_output_pulser || 0x5bc8f90f || does nothing (top level ag_pulser_out is disconnected)
|-
| 4 || || 0x618b790b || not used
|-
| 5 || conf_enable_esata_nim || || trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand)
|-
| 6 || conf_enable_adc16 || || trigger on adc16_grand_or
|-
| 7 || conf_enable_adc32 || || trigger on adc32_grand_or
|-
| 8 || conf_enable_adc16_1ormore || || trigger on adc16_mult_1ormore "1 or more"
|-
| 9 || conf_enable_adc16_2ormore || || same, "2 or more"
|-
| 10 || conf_enable_adc16_3ormore || || same, "3 or more"
|-
| 11 || conf_enable_adc16_4ormore || || same, "4 or more"
|-
| 12 || - || 0x5b08938c (25May18_15:51) || not used
|-
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
|-
| 14 || - || 0x5bc8f90f || not used
|-
| 15 || conf_enable_adc || 0x5b120c9f (01Jun18_20:18) || trigger on adc_grand_or
|-
| 16 || conf_enable_aw16_coinc_a || 0x5bc8f90f || enable AW coincidence trigger, see [[#aw16_coinc]]
|-
| 16 || - || 0x62c77f0b || aw16_coinc_x removed
|-
| 17 || conf_enable_aw16_coinc_b || 0x5bc8f90f ||
|-
| 18 || conf_enable_aw16_coinc_c || 0x5bc8f90f ||
|-
| 19 || conf_enable_aw16_coinc_d || 0x5bc8f90f ||
|-
| 20 || - || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 20 || conf_enable_aw16_grand_or || 0x618b790b || enable trigger on aw16_grand_or
|-
| 21 || conf_enable_aw16_coinc || 0x5b3aa19f (02Jul18_15:05) || enable trigger on aw16_coinc_trig
|-
| 22 || conf_enable_aw16_mlu || 0x5b3aa19f (02Jul18_15:05) || enable AW MLU trigger
|-
| 23 || conf_enable_timeout_trig || 0x5bc8f90f (18Oct18_14:20) || enable trigger timeout trigger
|-
| 24 || conf_enable_aw16_1ormore || 0x5b3aa19f (02Jul18_15:05) || trigger on aw16_mult_1ormore "1 or more"
|-
| 24 || - || 0x62c77f0b || aw16_mult_xxx removed
|-
| 25 || conf_enable_aw16_2ormore || 0x5b3aa19f (02Jul18_15:05) || same, "2 or more"
|-
| 26 || conf_enable_aw16_3ormore || 0x5b3aa19f (02Jul18_15:05) || same, "3 or more"
|-
| 27 || conf_enable_aw16_4ormore || 0x5b3aa19f (02Jul18_15:05) || same, "4 or more"
|-
| 28 || conf_enable_bsc_grand_or || 0x5bc13541 (12Oct18_16:58) || trigger on BSC grand-or
|-
| 29 || conf_enable_bsc_mult || 0x5bc13541 (12Oct18_16:58) || trigger on BSC multiplicity
|-
| 30 || conf_enable_coinc || 0x5bc13541 (12Oct18_16:58) || trigger on TPC/BSC/ext coincidence trigger
|-
| 31 || - || || not used
|-
|}

== reg 0x2B bits ==

Write to this register will pulse corresponding fpga signals:

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || reset_out || 0x5b120c9f (01Jun18_20:18) || reset counters, etc
|-
| 1 || latch_out || 0x5b120c9f (01Jun18_20:18) || latch counters, sas bits, etc
|-
| 2 || trigger_out || 0x5b120c9f (01Jun18_20:18) || generate a software trigger
|-
|}

= UDP data format =

== firmware 0x5bc8f90f ==

{| cellpadding="10" cellspacing="0" border="1"
! Offset || Name || Quartus name || FwRev || Description
|-
| 0 || packet counter || none || all || 31-bit UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
|-
| 1 || 0x8 packet header || || all || 28 bits of counter_trig_out
|-
| 2 || trigger timestamp || trig_ts || all || 62.5MHz trigger timestamp
|-
| 3 || accepted triggers || counter_trig_out || all || counter of accepted triggers
|-
| 4 || input triggers || counter_trig_in || all || counter of trigger input
|-
| 5 || pulser triggers || counter_pulser || all || counter of pulser triggers
|-
| 6 || trigger bitmap || udp_trig_bits || 0x5a48448d (30Dec17_17:59) || bitmap of trigger information, see below
|-
| 7 || nim bits || udp_nim_bits_masked || ??? || 32 bits of ADC NIM inputs (2 bits per ADC)
|-
| 8 || esata bits || udp_esata_bits_masked || ??? || 32 bits of ADC ESATA inputs (2 bits per ADC)
|-
| 9 || mlu bits || aw16_prompt || 0x5b398983 (01Jul18_19:10) || 16 bits of MLU input, 1 bit per preamp
|-
| 10 || drift-blank-off counter || udp_drift_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the drift blank-off
|-
| 11 || scaledown counter || udp_scaledown_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the scaledown
|-
| X || || || ||
|-
| 12 || 0xE packet footer || || all || 28 bits of counter_trig_out
|-
|}

== firmware 0x618b790b (Nov 2021) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

== firmware 0x62d1c47e (Jul 2022) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, 8'h00, 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= conf_fw_rev;
18 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

Values of udp_coinc_latch[7:0]:
* aaa

Values of udp_aw16_mult[7:0] and udp_aw16_bus[15:0]:
* aaa

Values of udp_bsc64_mult[7:0] and udp_bsc64_bus[63:0]
* aaa

== trigger bitmap ==

Firmware ??? (one of the very early revisions)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= adc16_coinc_top;
udp_trig_bits[5] <= adc16_coinc_bot;
udp_trig_bits[6] <= adc16_coinc;
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
udp_trig_bits[31:24] <= mult16[7:0];

</pre>

Firmware 0x5b08938c (25May18_15:51)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= 0; // not used
udp_trig_bits[31:24] <= mult16[7:0];
</pre>

Firmware 0x5b217dc4 (13Jun18_13:25)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5b3aa19f (02Jul18_15:05)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= udp_mlu_out;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5bc8f90f (18Oct18_14:20)

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_run_pulser
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = 0; // not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x618b790b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x62c77f0b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = 0; // aw16_coinc_a;
assign trig32_in[17] = 0; // aw16_coinc_b;
assign trig32_in[18] = 0; // aw16_coinc_c;
assign trig32_in[19] = 0; // aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = 0; // aw16_mult_1ormore;
assign trig32_in[25] = 0; // aw16_mult_2ormore;
assign trig32_in[26] = 0; // aw16_mult_3ormore;
assign trig32_in[27] = 0; // aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc64_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

= TRG chronobox inputs =

from trg_firmware/toplevel/grifc.v

<pre>
localparam CB_N = 23;
localparam CB_N1 = CB_N-1;

wire [CB_N1:0] cb_xinputs_async;

assign cb_xinputs_async[0] = ag_trig_out;
assign cb_xinputs_async[1] = ag_trig_scaledown_out;
assign cb_xinputs_async[2] = ag_trig_drift_out;
assign cb_xinputs_async[3] = ag_trig_received_out;

assign cb_xinputs_async[4] = ag_cb_sw_trig;
assign cb_xinputs_async[5] = ag_cb_pulser_trig;
assign cb_xinputs_async[6] = ag_cb_esata_nim_trig;
assign cb_xinputs_async[7] = ag_cb_adc16_grand_or_trig;
assign cb_xinputs_async[8] = ag_cb_adc32_grand_or_trig;

assign cb_xinputs_async[9] = ag_cb_aw16_grand_or_trig;
assign cb_xinputs_async[10] = ag_cb_aw16_mult_1ormore;
assign cb_xinputs_async[11] = ag_cb_aw16_mult_2ormore;
assign cb_xinputs_async[12] = ag_cb_aw16_mult_3ormore;
assign cb_xinputs_async[13] = ag_cb_aw16_mult_4ormore;
assign cb_xinputs_async[14] = ag_cb_aw16_mlu_trig;

assign cb_xinputs_async[15] = ag_cb_bsc64_grand_or_trig;
assign cb_xinputs_async[16] = ag_cb_bsc64_mult_1ormore;
assign cb_xinputs_async[17] = ag_cb_bsc64_mult_2ormore;
assign cb_xinputs_async[18] = ag_cb_bsc64_mult_3ormore;
assign cb_xinputs_async[19] = ag_cb_bsc64_mult_4ormore;
assign cb_xinputs_async[20] = ag_cb_bsc64_mult_trig;

assign cb_xinputs_async[21] = ag_cb_coinc_trig;

assign cb_xinputs_async[22] = ag_cb_timeout_trig;
</pre>

= Example UDP packets =

* trigger data, marker words 0x8

<pre>
ReadDataThread read 76
0: 0x003666ed -- UDP packet counter from UDP transmitter
1: 0x80000bf8 -- 0x8 is trigger data packet, 0xbf8 is the trigger counter from alphag.v
2: 0x2edf8b41 -- trigger data
3: 0x00000bf8
4: 0x00000bf8
5: 0x00000bee
6: 0x00000001
7: 0x00000000
8: 0x00000000
9: 0x00000003
10: 0x00000bf8
11: 0x00000bf8
12: 0x00000000
13: 0x00000000
14: 0x00000000
15: 0x00000000
16: 0x00000000
17: 0x00000000
18: 0xe0000bf8 -- 0xE is end of trigger data, counter 0xbf8 must match the counter in the 0x8 word.
ReadDataThread read 76 -- next packet
0: 0x003666ee -- UDP packet counter from UDP transmitter
...
</pre>

* chronobox fifo data, marker word 0xC, see [[Chronobox#FIFO_data_format]]

<pre>
ReadDataThread read 404
0: 0x003658ed -- UDP packet counter from UDP transmitter
1: 0xc000eacc -- 0xC is FIFO data, fifo packet counter 0xeacc from fifo_to_udp.v
2: 0x00000061 -- FIFO status, low bits the the word counter, so up to 0x61 fifo words are to follow
3: 0x87fb3d72 -- tsc hits
4: 0x8ffb3d74
5: 0x90fb3d74
6: 0x91fb3d74
7: 0x92fb3d74
8: 0x93fb3d74
9: 0x93fb3d75
10: 0x94fb3d74
11: 0x94fb3d77
12: 0x87fb3d77
13: 0x8ffb3d77
14: 0x90fb3d77
15: 0x91fb3d77
16: 0x92fb3d77
17: 0xfe000018 -- 0xFE scaler data starts, 0x18 words to follow
18: 0x00000000
19: 0x00000000
20: 0x00000000
21: 0x00000000
22: 0x00000000
23: 0x00000000
24: 0x00000000
25: 0x00000108
26: 0x00000000
27: 0x00000000
28: 0x00000000
29: 0x00000000
30: 0x00000000
31: 0x00000000
32: 0x00000000
33: 0x00000108
34: 0x00000108
35: 0x00000108
36: 0x00000108
37: 0x00000108
38: 0x00000108
39: 0x00000000
40: 0x00000000
41: 0xce56fa93 -- last word of scaler data is the sysclock counter (125 MHz)
42: 0xff800048 -- timestamp wraparound
43: 0x8f1f36e4 -- tsc hits
44: 0x901f36e4
45: 0x911f36e4
46: 0x921f36e4
47: 0x931f36e4
48: 0x941f36e4
49: 0x871f36e4
50: 0x871f36e7
51: 0x8f1f36e7
52: 0x901f36e9
53: 0x911f36e7
54: 0x921f36e9
55: 0x931f36e7
56: 0x941f36e9
57: 0x904330ac
58: 0x914330ac
59: 0x924330ac
60: 0x934330ac
61: 0x934330ad
62: 0x944330ac
63: 0x944330ad
64: 0x874330ac
65: 0x874330ad
66: 0x8f4330ac
67: 0x8f4330ad
68: 0x904330ad
69: 0x914330ad
70: 0x924330ad
71: 0x8f672a62
72: 0x90672a62
73: 0x91672a62
74: 0x92672a62
75: 0x93672a62
76: 0x94672a62
77: 0x87672a62
78: 0x87672a65
79: 0x8f672a65
80: 0x90672a65
81: 0x91672a65
82: 0x92672a65
83: 0x93672a65
84: 0x94672a65
85: 0xff000049
86: 0x878b2422
87: 0x8f8b2424
88: 0x908b2424
89: 0x918b2424
90: 0x928b2424
91: 0x938b2424
92: 0x938b2425
93: 0x948b2424
94: 0x948b2427
95: 0x878b2427
96: 0x8f8b2427
97: 0x908b2427
98: 0x918b2427
99: 0x928b2427
100: 0xe000eacc -- 0xE is end of fifo data, counter 0xeacc must match the counter in the 0xC word.
ReadDataThread read 344 -- next packet
...
</pre>

= TODO =

* DONE July 2022. add FwRev to the UDP data output
* RJ45 SFP: PROBLEM, D.A. CABLE: GOOD, Fiber SFP: ???. fix "write did not happen" (send udp write command, there is no reply, read returns old data as if write never happened). suspect udp "write" packet is lost?
* PROBLEM GONE Aug 2021. fix reply to wrong socket - udp packets should reply to same socket as they came from, udp data packets should be sent to same socket as requested them, not same socket as last command.
* DONE 2021jul30. add fixes from Chris P. for the auto-negotiation and dhcp (see email from him).
* DONE flash chip connected to FPGA. Aug 2021. implement ethernet flash programmer
* DONE Aug 2021. updated maxv firmware. implement FPGA reboot
* speed up programming the MLU by writing more than 1 bit at a time
* DONE Nov 2021. add 64-bit bitmap of BSC trigger bits
* DONE. add chronobox code
* DONE. add avalon mux for alphag and chronobox packets
* DONE. add chronobox fifo to udp packet sequencer
* check that TxReadyOut is correct and it is safe to send an avalon packet while previous packet is still transmitting.
* DONE. test fiber SFP is working
* complete the UDP flash programmer (parallel flash erase and write)

= End =

//KO

TRG

2022-07-16T21:42:16Z

Olchansk: /* additional registers */

= TRG, the trigger control board for the ALPHA-g detector =

= Links =

* xxx
* https://bitbucket.org/expalpha/trg_firmware - firmware sources on bitbucket

= General characteristics =

== Photos ==

== Board schematics ==

* https://bitbucket.org/expalpha/trg_firmware/src/master/3xFMC_VME_Motherboard.pdf

== Available hardware ==

* Altera Stratix IV - main FPGA
* Altera Max V - boot FPGA
* boot flash: PC28F512M29EW - 512 Mbit parallel NOR flash.

= TRG front panel connections =

From top to bottom:

<pre>
|
| minisas-C - links 8-11
| minisas-D - links 12-15
|
| ethernet sfp - use copper sfp only
| minisas - not used, do not connect
| esata - clock in, trigger out
|
| minisas-A - links 0-3
| minisas-B - links 4-7
|
| LEDs
|
</pre>

MiniSAS and SATA flail cable connections:

<pre>
P1 <--> link 3
P2 <--> link 2
P3 <--> link 1
P4 <--> link 0
</pre>

LEDs:

<pre>
--PCB-- (left)
LED[0] - trigger out - ag_trig_out
LED[1] - network packet received - sfp_rx_data_valid
LED[2] - Xilinx FPGA boot ok - FMC1_CFG_DONE
LED[3] - not used
(right)
</pre>

= TRG onboard jumpers and switches =

* rotary switches: select IP address: 00=192.168.1.50, 11=.51, 22=.52, 33=.53, 44=.54, otherwire=.251

= Firmware update procedure =

* use quartus to generate the grifc.pof file (use grifc.cof)
* open quartus programmer
* attach grifc.pof to the 1st CFI_512 flash
* mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
* check that "initiate configuration after programming" is set in tools->options
* say "start"
* should take about 5 minutes
* grifc should reboot into the new firmware

If CFI_512 flash is not visible to the quartus programmer, load correct
code into the MaxV CPLD:

* open quartus programmer,
* say "auto detect"
* change file for the 5M2210 device
* use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
* say "program", it should finish in 10-15 seconds
* say "auto detect"
* CFI_512 flash should be visible now.

= Firmware revisions =

* 0x5bc8f90f - original firmware used for all data
* 0x6147c0f9 - added cbtrg, etc. installed at CERN on 20 Sep 2021.
* 0x618376ae - bigger cbtrg fifo, data rate tested up to 30 Mbytes/sec
* 0x6189c7f3 - fix loss of trigger packets. (missing fifo between alphag block and ethernet mux)
* 0x618b790b - fix loss of timestamps. (cbtrg inputs stretched to 100 ns long). installed at CERN 10 Nov 2021.

= Firmware build =

* use quartus 20.1
* see Makefile in the trg_firmware project

= Jtag remote connection =

* ssh agmini@daq16
* /opt/intelFPGA/16.1/quartus/bin/jtagd --config /home/agmini/.jtagd.conf
* netstat -an | grep 1309 ### note listen address is "0.0.0.0", NOT "127.0.0.1"
<pre>
tcp 0 0 0.0.0.0:1309 0.0.0.0:* LISTEN
</pre>
* opt/intelFPGA/16.1/quartus/bin/jtagconfig ### should work
* ssh olchansk@daq01
* cd git/trg_firmware
* /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
* jtagconfig ### should work
<pre>
daq01:trg_firmware$ jtagconfig
1) DE-SoC on daq16 [2-1.2.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) USB-Blaster on daq16 [2-1.3]
024090DD EP4SGX230(.|ES)
020A40DD 5M(1270ZF324|2210Z)/EPM2210

daq01:trg_firmware$
</pre>

= ALPHA-g trigger functions =

Trigger options:
* software trigger
* pulser trigger
* trigger on GRIF16 ADC NIM and ESATA inputs ("external trigger")
* adc16 grand-or
* adc32 grand-or
* adc16 wire multiplicity
* TPC anode wire per-preamp trigger (aw16 section)
** trigger on coincidences of preamps (removed fw 0x62c77f0b)
** trigger on multiplicity of preamps (removed fw 0x62c77f0b)
** trigger on specific topology of preamps (multiplicity of preamp clusters, etc) via the aw16_mlu trigger
* BSC trigger
** BSC grand_or
** BSC bar multiplicity
* coincidence trigger - select coincidence of external trigger, TPC AW grand-or, TPC AW MLU, BSC grand-or and BSC bar multiplicity triggers

== software trigger ==

to programmatically fire the trigger, one should:
* set the conf_enable_sw_trigger bit in conf_trig_enable, this will permit the software trigger to fire the trigger
* write value 0x4 to register 0x2B, this will cause the software trigger to fire

== pulser trigger ==

To use the pulser trigger, one should program:
* pulser period (in clocks)
* pulser width (in clocks, use value 5, the pulser no longer goes outside of the trigger board, so changing the width does not do anything)
* set the run_pulser bit in conf_trig_enable, this will cause the pulser to run
* set the enable_pulser bit in conf_trig_enable, this will cause the pulser to fire the trigger
* set the output_pulser bit in conf_trig_enable, this will cause the pulser to be output from the alphag firmware block (the pulser no longer goes outside of the trigger board, so changing the bit does not do anything)

== timeout trigger ==

The event builder uses event timestamps to assemble physics events. The timestamps
are usually 32 bit wide and run at 125 MHz (8 ns) or 62.5 MHz (16 ns). If
triggers are generated often (1 per second or more), timestamp wrap around
is easily detected by the event builder. If triggers come infrequently,
timestamp wrap around may occur while there are no triggers, not be seen
by the event builder causing loss of event synchronization.

To avoid this problem in the event builder, a timeout trigger should be generated
if no triggers were generated inside a 10 second interval.

The guaranties that even if all physics triggers temporarily stop for any reason,
the event builder will stay synchronized. (0.1 Hz timeout trigger frequency).

To enable the timeout trigger:
* program timeout trigger timeout in reg 0x43 in units of 8 ns clock
* enable it in bit 23 of [[#conf_trig_enable bits]]

== adc16 multiplicity trigger ==

This trigger is intended for use with the barrel scintillator signals connected to adc16 digitizers. It does not work well with TPC AW signals.

The 16 adc16 trigger bits (16x16=256) are added together to form the hit multiplicity value (adc16_mult, 16 bits, actual range 0 to 256).

Four threshold signals are computed: adc16_mult_1ormore = adc16_mult>=1, 2ormore, 3ormore, 4ormore.

There is a counter for each of these four signals.

Each of these four signals can fire the trigger, see [[#conf_trig_enable bits]].

== TPC anode wire triggers ==

=== aw16 bus ===

TPC Anode Wire trigger is based on the aw16[15:0] (xaw16) bus.

Each bit corresponds to one AW preamp. 16 preamps, 16 bits.

The aw16[15:0] bus can be fed by
* adc16_or16[15:0] - or16 of 100 MHz ADCs, 16 ADC sas links
* adc32_or16[15:0] - or16 of 62.5 MHz ADCs, FMC-ADC32 has 32 channels, so 2 bits per ADC: low 16 channels and high 16 channels, sas links 7..0
* adc32_or16[31:16] - or16 of 62.5 MHz ADCs, ditto, sas links 15..8
as selected by conf_enable_aw_adc16, conf_enable_aw_adc32a, conf_enable_aw_adc32b in [[#conf_control bits]]

<pre>
///////////////////////////////////////////////////////////
// TPC Anode Wire trigger logic (aw16)
///////////////////////////////////////////////////////////

// map adc signals into aw16

wire [15:0] aw16 = ({16{conf_enable_aw_adc16}} & adc16_or16[15:0]) |
({16{conf_enable_aw_adc32a}} & adc32_or16[15:0]) |
({16{conf_enable_aw_adc32b}} & adc32_or16[31:16]);
...
ag_conditioner cond_adc16_or16_0(.clk(clk), .in(aw16[0]), .out(xxaw16[0]));
...
xaw16 <= xxaw16;
</pre>

=== aw16_grand_or ===

TPC AW "grand or" trigger: use aw16_mult_1ormore (before fw 0x62c77f0b)

(256 anode wires, 16 wires per preamp, 16 preamps, 16 aw16 signals)

=== aw16_mlu ===

TPC AW preamp MLU trigger: the MLU (memory lookup
table) implements an arbitrary logical function
to map the 16 aw16 preamp signals into 1 aw16_mlu_trig trigger output.

Description of the aw16 mlu trigger.

In words:

* any aw16 signal starts the aw16_prompt_run gate
* aw16 signals are collected for the duration of conf_mlu_prompt (125MHz/8ns clock)
* this corresponds to time spread of TPC AW signals due to the drift time in the AW drift cell and to the variation in signal transmission time from the ADC to the TRG (digital trigger data link).
* when this prompt time expires, the MLU looks at the accumulated aw16_prompt bit pattern and makes the "yes/no" trigger decision
* after the trigger decision is made, we wait for the TPC to become quiet:
* we wait until all aw16 signals are empty (no timeout)
* we run the aw16_prompt_wait gate, length conf_mlu_wait (8ns clock), if any aw16 signals arrive, we wait for aw16 empty again, rinse, repeat.
* now, after TPC aw16 have been empty for conf_mlu_wait clocks (8ns clock), MLU trigger is ready for the next event.

In logic: (see alphag.v)

* aw16_or <= grand-or of 16 aw16 signals
* "aw16_or" starts the "aw16_prompt_cnt" counter, opens the aw16_prompt_run gate
* during the aw16_prompt_run gate, aw16_prompt collects (latches) the aw16 bits (aw16_prompt <= aw16_prompt | aw16)
* this is the time when we wait for all "prompt" signals from the TPC to arrive into the trigger
* at the end of the aw16_prompt_run gate, the signal aw16_prompt_out is pulsed, latching the output of the MLU into aw16_mlu_trig
* this is the MLU trigger "yes/no" trigger decision.
* after the MLU trigger decision is made, we wait for the arrival and passing of all TPC drift signals
* the aw16_prompt_wait_cnt and aw_prompt_wait gate opens
* if any new aw16 signals arrive (they are TPC drift signals at this time), the aw16_prompt_wait gate is restarted
* if no aw16 signals arrive during the full run of the aw16_prompt_wait gate ("TPC quiet time")
* the aw16_prompt_wait and aw16_prompt gates are cleared and the MLU trigger is ready for the next event.

Good settings are:
* conf_mlu_prompt: 64 (512 ns)
* conf_mlu_wait: 128 (1024 ns)

== BSC trigger ==

=== bsc_adc16 bus ===

The BSC trigger is based on the [15:0]bsc_adc16[7:0] bus: 16 trigger discriminator bits from 8 ADC sas links. (8*16 = 64+64 bars, top and bottom).

The bsc_adc16 bus can be fed from sas links 0..7 or 8..15, controlled by conf_bsc_adc16_a and conf_bsc_adc16_b bits on [[#conf_bsc_control bits]].

bsc_adc16 can be fed only from GRIF-16 100 MHz ADC trigger discriminators.

=== bsc64_top and bsc64_bot buses ===

* firmware 0x5bc8f90f: bsc_adc16 is remapped into 64 bits of top (bsc64_top) and bottom (bsc64_bot):
<pre>
ag_bsc_remap bsc_remap_a(.adc(bsc_adc16[0]), .bsc_bot(bsc64_bot[7:0]), .bsc_top(bsc64_top[7:0]));
ag_bsc_remap bsc_remap_b(.adc(bsc_adc16[1]), .bsc_bot(bsc64_bot[8+7:8+0]), .bsc_top(bsc64_top[8+7:8+0]));
ag_bsc_remap bsc_remap_c(.adc(bsc_adc16[2]), .bsc_bot(bsc64_bot[2*8+7:2*8+0]), .bsc_top(bsc64_top[2*8+7:2*8+0]));
ag_bsc_remap bsc_remap_d(.adc(bsc_adc16[3]), .bsc_bot(bsc64_bot[3*8+7:3*8+0]), .bsc_top(bsc64_top[3*8+7:3*8+0]));

ag_bsc_remap bsc_remap_e(.adc(bsc_adc16[4]), .bsc_bot(bsc64_bot[4*8+7:4*8+0]), .bsc_top(bsc64_top[4*8+7:4*8+0]));
ag_bsc_remap bsc_remap_f(.adc(bsc_adc16[5]), .bsc_bot(bsc64_bot[5*8+7:5*8+0]), .bsc_top(bsc64_top[5*8+7:5*8+0]));
ag_bsc_remap bsc_remap_g(.adc(bsc_adc16[6]), .bsc_bot(bsc64_bot[6*8+7:6*8+0]), .bsc_top(bsc64_top[6*8+7:6*8+0]));
ag_bsc_remap bsc_remap_h(.adc(bsc_adc16[7]), .bsc_bot(bsc64_bot[7*8+7:7*8+0]), .bsc_top(bsc64_top[7*8+7:7*8+0]));

module ag_bsc_remap
(
input wire [15:0] adc,
output wire [7:0] bsc_bot,
output wire [7:0] bsc_top
);

assign bsc_top[3] = adc[0];
assign bsc_top[2] = adc[1];
assign bsc_top[1] = adc[2];
assign bsc_top[0] = adc[3];

assign bsc_top[7] = adc[4];
assign bsc_top[6] = adc[5];
assign bsc_top[5] = adc[6];
assign bsc_top[4] = adc[7];

assign bsc_bot[0] = adc[8];
assign bsc_bot[1] = adc[9];
assign bsc_bot[2] = adc[10];
assign bsc_bot[3] = adc[11];

assign bsc_bot[4] = adc[12];
assign bsc_bot[5] = adc[13];
assign bsc_bot[6] = adc[14];
assign bsc_bot[7] = adc[15];

endmodule
</pre>

=== bsc64 bus ===

the bsc64 bus is the 64 bars used by the trigger, formed from bsc64_top and bsc64_bot:
<pre>
if (conf_bsc64_bot_only) begin
bsc64 <= bsc64_bot;
end else if (conf_bsc64_top_only) begin
bsc64 <= bsc64_top;
end else if (conf_bsc64_bot_top_or) begin
bsc64 <= bsc64_bot | bsc64_top;
end else if (conf_bsc64_bot_top_and) begin
bsc64 <= bsc64_bot & bsc64_top;
end else begin
bsc64 <= 64'b0;
end
</pre>

=== bsc_grand_or_trig ===

bsc_grand_or_trig is the grand-or of 64 bits of the bsc64 bus

to enable triggering on bsc_grand_or_trig, set corresponding bit in [[#conf_trig_enable bits]]

=== old bsc_mult_trig ===

(from fw 0x62c77f0b, old bsc_mult_trig was replaced by new bsc64 multiplicity trigger)

* bsc64_mult is computed as multiplicity of the bsc64 bus (number of 64 bsc64 bits that fired)
* bsc_mult_trig is computed:
<pre>
if (bsc64_mult >= conf_bsc64_mult) begin
bsc_mult_trig <= 1;
end else begin
bsc_mult_trig <= 0;
end
</pre>

to enable the bsc multiplicity trigger, set the multiplicity value conf_bsc64_mult in [[#conf_bsc_control bits]] and enable the corresponding bit in [[#conf_trig_enable bits]].

=== bsc64 multiplicity trigger ===

bsc64 BSC bar multiplicity trigger uses a time window. this time window is started by bsc64_grand_or and runs for conf_bsc64_mult_window clocks (8 nc clock). During this time, hits in bsc64_bus are accumulated (latched) and their multiplicity is computed. If multiplicity condition is satisfied (bigger or equal to conf_bsc64_mult_min), bsc64_mult_trig is fired and the bsc64 bit pattern is saved to the UDP packet. Then trigger waits for the bsc64_bus to be empty. Then trigger waits for conf_bsc64_empty_window clocks, if there is any bsc64 hits, we wait for empty again. So after bsc64 has been empty for conf_bsc64_empty_window clocks, multiplicity trigger is ready for the next event. This scheme cannot implement max multiplicity.

recommended values:
* conf_bsc64_mult_window (8 bits): slightly longer than 3 cycles of SAS link: 3*18 = 54 clocks, good value is 80 (640 ns).
* conf_bsc64_mult_min (8 bits): 2
* conf_bsc64_empty_window (8 bits): 80 (640 ns)

== Coincidence trigger ==

Coincidence trigger provides a combination of TPC, BSC and external scintillator (esata_nim_grand_or) signals:

<pre>
assign coinc_input[0] = aw16_grand_or; // was aw16_mult_1ormore;
assign coinc_input[1] = aw16_mlu_trig;
assign coinc_input[2] = bsc_grand_or_trig;
assign coinc_input[3] = bsc_mult_trig;
assign coinc_input[4] = esata_nim_grand_or;
assign coinc_input[5] = 0;
assign coinc_input[6] = 0;
assign coinc_input[7] = 0;
</pre>

Coincidence trigger "start" mask selects which of the inputs can start the coincidence window.

Coincidence trigger "require" mask selects which inputs must have a hits for the coincidence to be satisfied.

Input hits are collected for the duration of the coincidence window, if all required inputs have hits, coinc_trig is fired.

Example settings:

* coincidence of external scintillator, BSC and TPC AW "grand or" signals: start 0x10, required 0x15
* coincidence of BSC grand-or and TPC AW grand-or signals: start 0x5, required 0x5
* coincidence of BSC multiplicity and TPC AW grand-or triggers: start 0x9, required 0x9

= Control registers =

== Register addresses ==

Note: all registers are 32 bits unless otherwise noted.

Note: RW means read-write register, RO means read-only, ROL means read-only, contents is latched by the "latch_out" bit

{| cellpadding="10" cellspacing="0" border="1"
! Address || Quartus Name || Access || FwRev || Description
|-
| 0x08 || num_sample || RW || GRIF-C || magic 16-bit register to control UDP packet size
|-
| 0x08 || scratch_reg || RW || 0x618b790b || 32-bit scratch register
|-
| 0x1F || compilation_time || RO || || Firmware revision
|-
| 0x20 || conf_trig_width || RW || || Trigger signal width, 16 ns clock
|-
| 0x21 || conf_busy_width || RW || || Busy signal width, 16 ns clock (not used)
|-
| 0x22 || conf_pulser_width || RW || || Pulser signal width, 16 ns clock
|-
| 0x23 || conf_pulser_period || RW || || Pulser signal period, 16 ns clock
|-
| 0x24 || conf_pulser_burst_ctrl || RW || 0x62d1c47e || Generate bursts of pulses: 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses, 16 ns clocks
|-
| 0x25 || conf_trig_enable || RW || || see [[#conf_trig_enable bits]]
|-
| 0x26 || || || not used
|-
| 0x27 || || || not used
|-
| 0x28 || || || not used
|-
| 0x29 || conf_nim_mask || RW || || enable bits for ADC NIM inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2A || conf_esata_mask || RW || || enable bits for ADC eSATA inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2B || reset_out, latch_out, trigger_out || W || || see [[#reg 0x2B bits]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x5bc8f90f || configure AW coincidence trigger, see [[#aw16_coinc]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x62c77f0b || removed
|-
| 0x2D || conf_aw16_coinc_b || RW || 0x5bc8f90f ||
|-
| 0x2E || conf_aw16_coinc_c || RW || 0x5bc8f90f ||
|-
| 0x2F || conf_aw16_coinc_d || RW || 0x5bc8f90f ||
|-
| 0x30 || sas_sd[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect for each link
|-
| 0x31 || pll_625_status || ROL || 0x5b2057f5 (12Jun18_16:32) || 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter
|-
| 0x32 || clk_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the system 125 MHz clock
|-
| 0x33 || clk_625_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625)
|-
| 0x34 || conf_control || RW || 0x5b398983 (01Jul18_19:10) || see [[#conf_control bits]] below
|-
| 0x35 || conf_drift_width || RW || 0x5b398983 (01Jul18_19:10) || width of drift time blank-out in 16 ns clocks
|-
| 0x36 || conf_scaledown || RW || 0x5b398983 (01Jul18_19:10) || trigger scaledown, 0=no scaledown, 1=divide-by-2, 2=divide-by-3, etc
|-
| 0x37 || conf_mlu || RW || 0x5b398983 (01Jul18_19:10) || AW MLU control bits, see [[#conf_mlu bits]]
|-
| 0x38 || conf_trig_delay || RW || 0x5baedfca (28Sep18_19:13) || delay the trigger pulse, 16 ns clock
|-
| 0x39 || esata_clk_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the TRG 125 MHz clock
|-
| 0x3A || esata_clk_esata_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the external clock (eSATA 62.5 MHz clock)
|-
| 0x3B || conf_counter_adc_select || RW || 0x5bb7f6ae (05Oct18_16:41) || select which 16 ADCs are connected to the selected adc counters, 0..15 - connect the adc16 signals, 16..47 connect the adc32 signals
|-
| 0x3C || sysreset_ts || RO || 0x5bb7f6ae (05Oct18_16:41) || 125MHz counter of VME-SYSRESET
|-
| 0x3C || || || 0x618b790b || not used
|-
| 0x3D || GRIF-C csr || RW || GRIF-C || <= csr & ~par_value; // Selective clear
|-
| 0x3E || GRIF-C csr || RW || GRIF-C || <= csr | par_value; // Selective set
|-
| 0x3F || GRIF-C csr || RW || GRIF-C || <= par_value; // write
|-
| 0x3D || || || 0x618b790b || not used
|-
| 0x3E || || || 0x618b790b || not used
|-
| 0x3F || || || 0x618b790b || not used
|-
| 0x40 || conf_bsc_control || RW || 0x5bc13541 (12Oct18_16:58) || Barrel Scintillator trigger control, see [[#conf_bsc_control bits]]
|-
| 0x41 || conf_coinc_control || RW || 0x5bc13541 (12Oct18_16:58) || Coincidence trigger control, see [[#conf_coinc_control bits]]
|-
| 0x42 || reconfig_out || WO || 0x5bc13541 (12Oct18_16:58) || reserved for rebooting the FPGA (does not work)
|-
| 0x43 || conf_trigger_timeout || RW || 0x5bc8f90f (18Oct18_14:20) || Generate timeout trigger if there is no other trigger after given timeout, in 8 ns clocks, must be enabled by bit conf_enable_timeout_trig in [[#conf_trig_enable bits]]
|-
| 0x44 || eth_clk_counter || ROL || 0x618b790b ||
|-
| 0x45 || eth_clk_eth_counter || ROL || 0x618b790b ||
|-
| 0x100 || ts_625 || ROL || || latched timestamp
|-
| 0x101 || counter_trig_out || ROL || || counter of issued triggers
|-
| 0x102 || counter_trig_in || ROL || || counter of triggers
|-
| 0x103 || counter_pulser || ROL || || counter of pulser
|-
| 0x104 || counter_adc16_grand_or || ROL ||
|-
| 0x105 || counter_adc32_grand_or || ROL ||
|-
| 0x106 || counter_adc_grand_or || ROL ||
|-
| 0x107 || counter_esata_nim_grand_or || ROL ||
|-
| 0x108 || counter_adc16_mult_1ormore || ROL ||
|-
| 0x109 || counter_adc16_mult_2ormore || ROL ||
|-
| 0x10A || counter_adc16_mult_3ormore || ROL ||
|-
| 0x10B || counter_adc16_mult_4ormore || ROL ||
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x5bc8f90f || counter of AW coincidence triggers
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x62c77f0b || removed
|-
| 0x10D || counter_aw16_coinc_b || ROL || 0x5bc8f90f ||
|-
| 0x10E || counter_aw16_coinc_c || ROL || 0x5bc8f90f ||
|-
| 0x10F || counter_aw16_coinc_d || ROL || 0x5bc8f90f ||
|-
| 0x110 || counter_drift || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the drift time blank-out
|-
| 0x111 || counter_scaledown || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the scaledown
|-
| 0x112 || counter_aw16_coinc || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW coincidence triggers
|-
| 0x113 || counter_aw16_mlu || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW MLU triggers
|-
| 0x114 || counter_aw16_grand_or || ROL || 0x62c77f0b || counter of AW grand-or triggers
|-
| 0x114 || counter_aw16_mult_1ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 1ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 2ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x62c77f0b || removed
|-
| 0x116 || counter_aw16_mult_3ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 3ormore triggers
|-
| 0x117 || counter_aw16_mult_4ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 4ormore triggers
|-
| 0x118 || counter_bsc_grand_or || ROL || 0x5bc13541 (12Oct18_16:58) || counter of BSC grand-or triggers
|-
| 0x119 || counter_bsc_mult || ROL || 0x5bc13541 (12Oct18_16:58) || counter of old BSC multiplicity triggers
|-
| 0x11A || counter_coinc || ROL || 0x5bc13541 (12Oct18_16:58) || counter of coincidence triggers
|-
| 0x11B || counter_timeout || ROL || 0x618b790b || counter of timeout triggers
|-
| 0x11C || counter_bsc_mult_start || ROL || 0x62c77f0b || counter of BSC multiplicity windows
|-
| 0x11D || counter_bsc_mult_trig || ROL || 0x62c77f0b || counter of BSC multiplicity triggers
|-
| 0x11E || counter_coinc_start || ROL || 0x62d1b152 || counter of coincidence windows
|-
| 0x11F || counter_aw16_mlu_start || ROL || 0x62d1b152 || counter of TPC AW MLU windows
|-
| 0x200..0x207 || conf_adc16_masks || RW || all || adc16 enable bits
|-
| 0x300..0x30F || conf_adc32_masks || RW || all || adc32 enable bits
|-
| 0x400..0x41F || sas_bits[15:0][63:0] || ROL || all || sas data bits for each link
|-
| 0x420..0x42F || sas_sd_counters[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect counter for each link
|-
| 0x430..0x43F || counters_adc16_or16[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 16 counters of adc16 ORes
|-
| 0x440..0x45F || counters_adc32_or16[31:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 32 counters of adc32 ORes
|-
| 0x460..0x46F || counters_adc_selected[15:0] || ROL || 0x5bb7f6ae (05Oct18_16:41) || 16 counters for selected group of adcs, see conf_counter_adc_select
|-
| 0x470..0x4AF || counters_bsc64[63:0] || ROL || 0x5bc13541 (12Oct18_16:58) || 64 counters for the BSC bars
|-
|}

== additional registers ==

<pre>
reg | rw/ro/rol | quartus name | firmware | description
0x60 | rw | cb_control_out | 0x618b790b | chronobox control
0x61 | rw | cb_status | 0x618b790b | chronobox status
0x62 | rw | cb_invert_a_out | 0x618b790b | chronobox input invert
0x63 | rw | cb_invert_b_out | 0x618b790b |
0x64 | rw | cb_enable_le_a_out | 0x618b790b | timestamp enable leading edge
0x65 | rw | cb_enable_le_b_out | 0x618b790b |
0x66 | rw | cb_enable_te_a_out | 0x618b790b | timestamp enable traiing edge
0x67 | rw | cb_enable_te_b_out | 0x618b790b |
0x6A | ro | cb_input_num | 0x618b790b | chronobox number of inputs
0x6B | rw | cb_sync_mask_a_out | 0x618b790b | chronobox sync signal source
0x6C | rw | cb_sync_mask_b_out | 0x618b790b |
0x6D | rw | cb_sync_reg_out | 0x618b790b | chronobox sync register
0x6E | ro | cb_sync_status | 0x618b790b | chronobox sync status
0x6F | rw | cb_latch_period_out | 0x618b790b | chronobox scalers latch period
0x70 | ro | cb_fifo_status | 0x618b790b | chronobox data fifo status
0x71 | ro | cb_fifo_data | 0x618b790b | read chronobox data fifo (cb_fifo_rdack_out <= 1)
0x72 | rw | cb_udp_period_out | 0x618b790b | period for flushing fifo to UDP
0x73 | rw | cb_udp_threshold_out | 0x618b790b | byte threshold for flushing fifo to UDP
</pre>

== conf_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_clock_select || 0x5b3aa19f (02Jul18_15:05) || select 0=internal 62.5 MHz clock or 1=esata 62.5 MHz clock
|-
| 1 || conf_enable_aw_adc16 || 0x5baedfca (28Sep18_19:13) || select source of TPC AW aw16 bus, see [[#aw16 bus]]
|-
| 2 || conf_enable_aw_adc32a || 0x5baedfca (28Sep18_19:13) ||
|-
| 3 || conf_enable_aw_adc32b || 0x5baedfca (28Sep18_19:13) ||
|-
| 15..4 || || ||
|-
| 23..16 || conf_mlu_prompt || 0x5b3aa19f (02Jul18_15:05) || MLU trigger prompt window, see [[#aw16_mlu]]
|-
| 31..24 || conf_mlu_wait || 0x5b3aa19f (02Jul18_15:05) || MLU trigger wait window, see [[#aw16_mlu]]
|-
|}

== conf_mlu bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 31 || mlu_reset || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 30 || mlu_write || 0x5b3aa19f (02Jul18_15:05) || 1=write data bit into given address
|-
| 16 || mlu_data || 0x5b3aa19f (02Jul18_15:05) || data bit for writing to MLU RAM
|-
| 15..0 || mlu_write_addr || 0x5b3aa19f (02Jul18_15:05) || MLU RAM write address for writing the data bit
|-
|}

== conf_bsc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_bsc_adc_a || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 0..7
|-
| 1 || conf_bsc_adc_b || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 8..15
|-
| 2 || conf_bsc64_bot_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses bottom channels only
|-
| 3 || conf_bsc64_top_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses top channels only
|-
| 4 || conf_bsc64_bot_top_or || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "or" of top and bottom
|-
| 5 || conf_bsc64_bot_top_and || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "and" of top and bottom
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_bsc64_mult_min || 0x5bc13541 (12Oct18_16:58) || minimum bsc64 multiplicity
|-
| 23..16 || conf_bsc64_empty_wondow || 0x62d1c47e || bsc64 empty window length, 8 ns clocks
|-
| 31..24 || conf_bsc64_mult_window || 0x62c77f0b || bsc64 multiplicity window length, 8 ns clocks
|-
|}

== conf_coinc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_coinc_required[0] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mult_1ormore
|-
| 0 || conf_coinc_required[0] || 0x62c77f0b || enable aw16_grand_or
|-
| 1 || conf_coinc_required[1] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mlu_trig
|-
| 2 || conf_coinc_required[2] || 0x5bc13541 (12Oct18_16:58) || enable bsc_grand_or_trig
|-
| 3 || conf_coinc_required[3] || 0x5bc13541 (12Oct18_16:58) || enable bsc_mult_trig
|-
| 3 || conf_coinc_required[3] || 0x62c77f0b || enable bsc64_mult_trig
|-
| 4 || conf_coinc_required[4] || 0x5bc13541 (12Oct18_16:58) || enable esata_nim_grand_or
|-
| 5 || conf_coinc_required[5]
|-
| 6 || conf_coinc_required[6]
|-
| 7 || conf_coinc_required[7]
|-
| 15..8 || conf_coinc_window[7:0] || 0x5bc13541 (12Oct18_16:58) || coincidence window length in units of 125MHz clock (8 ns)
|-
| 23..16 || conf_coinc_start[7:0] || 0x5bc13541 (12Oct18_16:58) || start the coincidence window, same bits as "required"
|-
| 31..24 ||
|-
|}

== conf_trig_enable bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_enable_sw_trigger || || trigger on software trigger (how generated???)
|-
| 1 || conf_enable_pulser || || trigger on pulser
|-
| 2 || - || 0x5b120c9f (01Jun18_20:18) || not used
|-
| 3 || conf_pulser_run || || allow the pulser to run (frequency has to be set beforehand)
|-
| 4 || conf_output_pulser || 0x5bc8f90f || does nothing (top level ag_pulser_out is disconnected)
|-
| 4 || || 0x618b790b || not used
|-
| 5 || conf_enable_esata_nim || || trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand)
|-
| 6 || conf_enable_adc16 || || trigger on adc16_grand_or
|-
| 7 || conf_enable_adc32 || || trigger on adc32_grand_or
|-
| 8 || conf_enable_adc16_1ormore || || trigger on adc16_mult_1ormore "1 or more"
|-
| 9 || conf_enable_adc16_2ormore || || same, "2 or more"
|-
| 10 || conf_enable_adc16_3ormore || || same, "3 or more"
|-
| 11 || conf_enable_adc16_4ormore || || same, "4 or more"
|-
| 12 || - || 0x5b08938c (25May18_15:51) || not used
|-
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
|-
| 14 || - || 0x5bc8f90f || not used
|-
| 15 || conf_enable_adc || 0x5b120c9f (01Jun18_20:18) || trigger on adc_grand_or
|-
| 16 || conf_enable_aw16_coinc_a || 0x5bc8f90f || enable AW coincidence trigger, see [[#aw16_coinc]]
|-
| 16 || - || 0x62c77f0b || aw16_coinc_x removed
|-
| 17 || conf_enable_aw16_coinc_b || 0x5bc8f90f ||
|-
| 18 || conf_enable_aw16_coinc_c || 0x5bc8f90f ||
|-
| 19 || conf_enable_aw16_coinc_d || 0x5bc8f90f ||
|-
| 20 || - || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 20 || conf_enable_aw16_grand_or || 0x618b790b || enable trigger on aw16_grand_or
|-
| 21 || conf_enable_aw16_coinc || 0x5b3aa19f (02Jul18_15:05) || enable trigger on aw16_coinc_trig
|-
| 22 || conf_enable_aw16_mlu || 0x5b3aa19f (02Jul18_15:05) || enable AW MLU trigger
|-
| 23 || conf_enable_timeout_trig || 0x5bc8f90f (18Oct18_14:20) || enable trigger timeout trigger
|-
| 24 || conf_enable_aw16_1ormore || 0x5b3aa19f (02Jul18_15:05) || trigger on aw16_mult_1ormore "1 or more"
|-
| 24 || - || 0x62c77f0b || aw16_mult_xxx removed
|-
| 25 || conf_enable_aw16_2ormore || 0x5b3aa19f (02Jul18_15:05) || same, "2 or more"
|-
| 26 || conf_enable_aw16_3ormore || 0x5b3aa19f (02Jul18_15:05) || same, "3 or more"
|-
| 27 || conf_enable_aw16_4ormore || 0x5b3aa19f (02Jul18_15:05) || same, "4 or more"
|-
| 28 || conf_enable_bsc_grand_or || 0x5bc13541 (12Oct18_16:58) || trigger on BSC grand-or
|-
| 29 || conf_enable_bsc_mult || 0x5bc13541 (12Oct18_16:58) || trigger on BSC multiplicity
|-
| 30 || conf_enable_coinc || 0x5bc13541 (12Oct18_16:58) || trigger on TPC/BSC/ext coincidence trigger
|-
| 31 || - || || not used
|-
|}

== reg 0x2B bits ==

Write to this register will pulse corresponding fpga signals:

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || reset_out || 0x5b120c9f (01Jun18_20:18) || reset counters, etc
|-
| 1 || latch_out || 0x5b120c9f (01Jun18_20:18) || latch counters, sas bits, etc
|-
| 2 || trigger_out || 0x5b120c9f (01Jun18_20:18) || generate a software trigger
|-
|}

= UDP data format =

== firmware 0x5bc8f90f ==

{| cellpadding="10" cellspacing="0" border="1"
! Offset || Name || Quartus name || FwRev || Description
|-
| 0 || packet counter || none || all || 31-bit UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
|-
| 1 || 0x8 packet header || || all || 28 bits of counter_trig_out
|-
| 2 || trigger timestamp || trig_ts || all || 62.5MHz trigger timestamp
|-
| 3 || accepted triggers || counter_trig_out || all || counter of accepted triggers
|-
| 4 || input triggers || counter_trig_in || all || counter of trigger input
|-
| 5 || pulser triggers || counter_pulser || all || counter of pulser triggers
|-
| 6 || trigger bitmap || udp_trig_bits || 0x5a48448d (30Dec17_17:59) || bitmap of trigger information, see below
|-
| 7 || nim bits || udp_nim_bits_masked || ??? || 32 bits of ADC NIM inputs (2 bits per ADC)
|-
| 8 || esata bits || udp_esata_bits_masked || ??? || 32 bits of ADC ESATA inputs (2 bits per ADC)
|-
| 9 || mlu bits || aw16_prompt || 0x5b398983 (01Jul18_19:10) || 16 bits of MLU input, 1 bit per preamp
|-
| 10 || drift-blank-off counter || udp_drift_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the drift blank-off
|-
| 11 || scaledown counter || udp_scaledown_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the scaledown
|-
| X || || || ||
|-
| 12 || 0xE packet footer || || all || 28 bits of counter_trig_out
|-
|}

== firmware 0x618b790b (Nov 2021) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

== firmware 0x62d1c47e (Jul 2022) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, 8'h00, 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= conf_fw_rev;
18 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

Values of udp_coinc_latch[7:0]:
* aaa

Values of udp_aw16_mult[7:0] and udp_aw16_bus[15:0]:
* aaa

Values of udp_bsc64_mult[7:0] and udp_bsc64_bus[63:0]
* aaa

== trigger bitmap ==

Firmware ??? (one of the very early revisions)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= adc16_coinc_top;
udp_trig_bits[5] <= adc16_coinc_bot;
udp_trig_bits[6] <= adc16_coinc;
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
udp_trig_bits[31:24] <= mult16[7:0];

</pre>

Firmware 0x5b08938c (25May18_15:51)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= 0; // not used
udp_trig_bits[31:24] <= mult16[7:0];
</pre>

Firmware 0x5b217dc4 (13Jun18_13:25)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5b3aa19f (02Jul18_15:05)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= udp_mlu_out;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5bc8f90f (18Oct18_14:20)

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_run_pulser
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = 0; // not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x618b790b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x62c77f0b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = 0; // aw16_coinc_a;
assign trig32_in[17] = 0; // aw16_coinc_b;
assign trig32_in[18] = 0; // aw16_coinc_c;
assign trig32_in[19] = 0; // aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = 0; // aw16_mult_1ormore;
assign trig32_in[25] = 0; // aw16_mult_2ormore;
assign trig32_in[26] = 0; // aw16_mult_3ormore;
assign trig32_in[27] = 0; // aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc64_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

= TRG chronobox inputs =

from trg_firmware/toplevel/grifc.v

<pre>
localparam CB_N = 23;
localparam CB_N1 = CB_N-1;

wire [CB_N1:0] cb_xinputs_async;

assign cb_xinputs_async[0] = ag_trig_out;
assign cb_xinputs_async[1] = ag_trig_scaledown_out;
assign cb_xinputs_async[2] = ag_trig_drift_out;
assign cb_xinputs_async[3] = ag_trig_received_out;

assign cb_xinputs_async[4] = ag_cb_sw_trig;
assign cb_xinputs_async[5] = ag_cb_pulser_trig;
assign cb_xinputs_async[6] = ag_cb_esata_nim_trig;
assign cb_xinputs_async[7] = ag_cb_adc16_grand_or_trig;
assign cb_xinputs_async[8] = ag_cb_adc32_grand_or_trig;

assign cb_xinputs_async[9] = ag_cb_aw16_grand_or_trig;
assign cb_xinputs_async[10] = ag_cb_aw16_mult_1ormore;
assign cb_xinputs_async[11] = ag_cb_aw16_mult_2ormore;
assign cb_xinputs_async[12] = ag_cb_aw16_mult_3ormore;
assign cb_xinputs_async[13] = ag_cb_aw16_mult_4ormore;
assign cb_xinputs_async[14] = ag_cb_aw16_mlu_trig;

assign cb_xinputs_async[15] = ag_cb_bsc64_grand_or_trig;
assign cb_xinputs_async[16] = ag_cb_bsc64_mult_1ormore;
assign cb_xinputs_async[17] = ag_cb_bsc64_mult_2ormore;
assign cb_xinputs_async[18] = ag_cb_bsc64_mult_3ormore;
assign cb_xinputs_async[19] = ag_cb_bsc64_mult_4ormore;
assign cb_xinputs_async[20] = ag_cb_bsc64_mult_trig;

assign cb_xinputs_async[21] = ag_cb_coinc_trig;

assign cb_xinputs_async[22] = ag_cb_timeout_trig;
</pre>

= Example UDP packets =

* trigger data, marker words 0x8

<pre>
ReadDataThread read 76
0: 0x003666ed -- UDP packet counter from UDP transmitter
1: 0x80000bf8 -- 0x8 is trigger data packet, 0xbf8 is the trigger counter from alphag.v
2: 0x2edf8b41 -- trigger data
3: 0x00000bf8
4: 0x00000bf8
5: 0x00000bee
6: 0x00000001
7: 0x00000000
8: 0x00000000
9: 0x00000003
10: 0x00000bf8
11: 0x00000bf8
12: 0x00000000
13: 0x00000000
14: 0x00000000
15: 0x00000000
16: 0x00000000
17: 0x00000000
18: 0xe0000bf8 -- 0xE is end of trigger data, counter 0xbf8 must match the counter in the 0x8 word.
ReadDataThread read 76 -- next packet
0: 0x003666ee -- UDP packet counter from UDP transmitter
...
</pre>

* chronobox fifo data, marker word 0xC, see [[Chronobox#FIFO_data_format]]

<pre>
ReadDataThread read 404
0: 0x003658ed -- UDP packet counter from UDP transmitter
1: 0xc000eacc -- 0xC is FIFO data, fifo packet counter 0xeacc from fifo_to_udp.v
2: 0x00000061 -- FIFO status, low bits the the word counter, so up to 0x61 fifo words are to follow
3: 0x87fb3d72 -- tsc hits
4: 0x8ffb3d74
5: 0x90fb3d74
6: 0x91fb3d74
7: 0x92fb3d74
8: 0x93fb3d74
9: 0x93fb3d75
10: 0x94fb3d74
11: 0x94fb3d77
12: 0x87fb3d77
13: 0x8ffb3d77
14: 0x90fb3d77
15: 0x91fb3d77
16: 0x92fb3d77
17: 0xfe000018 -- 0xFE scaler data starts, 0x18 words to follow
18: 0x00000000
19: 0x00000000
20: 0x00000000
21: 0x00000000
22: 0x00000000
23: 0x00000000
24: 0x00000000
25: 0x00000108
26: 0x00000000
27: 0x00000000
28: 0x00000000
29: 0x00000000
30: 0x00000000
31: 0x00000000
32: 0x00000000
33: 0x00000108
34: 0x00000108
35: 0x00000108
36: 0x00000108
37: 0x00000108
38: 0x00000108
39: 0x00000000
40: 0x00000000
41: 0xce56fa93 -- last word of scaler data is the sysclock counter (125 MHz)
42: 0xff800048 -- timestamp wraparound
43: 0x8f1f36e4 -- tsc hits
44: 0x901f36e4
45: 0x911f36e4
46: 0x921f36e4
47: 0x931f36e4
48: 0x941f36e4
49: 0x871f36e4
50: 0x871f36e7
51: 0x8f1f36e7
52: 0x901f36e9
53: 0x911f36e7
54: 0x921f36e9
55: 0x931f36e7
56: 0x941f36e9
57: 0x904330ac
58: 0x914330ac
59: 0x924330ac
60: 0x934330ac
61: 0x934330ad
62: 0x944330ac
63: 0x944330ad
64: 0x874330ac
65: 0x874330ad
66: 0x8f4330ac
67: 0x8f4330ad
68: 0x904330ad
69: 0x914330ad
70: 0x924330ad
71: 0x8f672a62
72: 0x90672a62
73: 0x91672a62
74: 0x92672a62
75: 0x93672a62
76: 0x94672a62
77: 0x87672a62
78: 0x87672a65
79: 0x8f672a65
80: 0x90672a65
81: 0x91672a65
82: 0x92672a65
83: 0x93672a65
84: 0x94672a65
85: 0xff000049
86: 0x878b2422
87: 0x8f8b2424
88: 0x908b2424
89: 0x918b2424
90: 0x928b2424
91: 0x938b2424
92: 0x938b2425
93: 0x948b2424
94: 0x948b2427
95: 0x878b2427
96: 0x8f8b2427
97: 0x908b2427
98: 0x918b2427
99: 0x928b2427
100: 0xe000eacc -- 0xE is end of fifo data, counter 0xeacc must match the counter in the 0xC word.
ReadDataThread read 344 -- next packet
...
</pre>

= TODO =

* DONE July 2022. add FwRev to the UDP data output
* RJ45 SFP: PROBLEM, D.A. CABLE: GOOD, Fiber SFP: ???. fix "write did not happen" (send udp write command, there is no reply, read returns old data as if write never happened). suspect udp "write" packet is lost?
* PROBLEM GONE Aug 2021. fix reply to wrong socket - udp packets should reply to same socket as they came from, udp data packets should be sent to same socket as requested them, not same socket as last command.
* DONE 2021jul30. add fixes from Chris P. for the auto-negotiation and dhcp (see email from him).
* DONE flash chip connected to FPGA. Aug 2021. implement ethernet flash programmer
* DONE Aug 2021. updated maxv firmware. implement FPGA reboot
* speed up programming the MLU by writing more than 1 bit at a time
* DONE Nov 2021. add 64-bit bitmap of BSC trigger bits
* DONE. add chronobox code
* DONE. add avalon mux for alphag and chronobox packets
* DONE. add chronobox fifo to udp packet sequencer
* check that TxReadyOut is correct and it is safe to send an avalon packet while previous packet is still transmitting.
* DONE. test fiber SFP is working
* complete the UDP flash programmer (parallel flash erase and write)

= End =

//KO

TRG

2022-07-16T21:33:15Z

Olchansk: /* Coincidence trigger */

= TRG, the trigger control board for the ALPHA-g detector =

= Links =

* xxx
* https://bitbucket.org/expalpha/trg_firmware - firmware sources on bitbucket

= General characteristics =

== Photos ==

== Board schematics ==

* https://bitbucket.org/expalpha/trg_firmware/src/master/3xFMC_VME_Motherboard.pdf

== Available hardware ==

* Altera Stratix IV - main FPGA
* Altera Max V - boot FPGA
* boot flash: PC28F512M29EW - 512 Mbit parallel NOR flash.

= TRG front panel connections =

From top to bottom:

<pre>
|
| minisas-C - links 8-11
| minisas-D - links 12-15
|
| ethernet sfp - use copper sfp only
| minisas - not used, do not connect
| esata - clock in, trigger out
|
| minisas-A - links 0-3
| minisas-B - links 4-7
|
| LEDs
|
</pre>

MiniSAS and SATA flail cable connections:

<pre>
P1 <--> link 3
P2 <--> link 2
P3 <--> link 1
P4 <--> link 0
</pre>

LEDs:

<pre>
--PCB-- (left)
LED[0] - trigger out - ag_trig_out
LED[1] - network packet received - sfp_rx_data_valid
LED[2] - Xilinx FPGA boot ok - FMC1_CFG_DONE
LED[3] - not used
(right)
</pre>

= TRG onboard jumpers and switches =

* rotary switches: select IP address: 00=192.168.1.50, 11=.51, 22=.52, 33=.53, 44=.54, otherwire=.251

= Firmware update procedure =

* use quartus to generate the grifc.pof file (use grifc.cof)
* open quartus programmer
* attach grifc.pof to the 1st CFI_512 flash
* mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
* check that "initiate configuration after programming" is set in tools->options
* say "start"
* should take about 5 minutes
* grifc should reboot into the new firmware

If CFI_512 flash is not visible to the quartus programmer, load correct
code into the MaxV CPLD:

* open quartus programmer,
* say "auto detect"
* change file for the 5M2210 device
* use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
* say "program", it should finish in 10-15 seconds
* say "auto detect"
* CFI_512 flash should be visible now.

= Firmware revisions =

* 0x5bc8f90f - original firmware used for all data
* 0x6147c0f9 - added cbtrg, etc. installed at CERN on 20 Sep 2021.
* 0x618376ae - bigger cbtrg fifo, data rate tested up to 30 Mbytes/sec
* 0x6189c7f3 - fix loss of trigger packets. (missing fifo between alphag block and ethernet mux)
* 0x618b790b - fix loss of timestamps. (cbtrg inputs stretched to 100 ns long). installed at CERN 10 Nov 2021.

= Firmware build =

* use quartus 20.1
* see Makefile in the trg_firmware project

= Jtag remote connection =

* ssh agmini@daq16
* /opt/intelFPGA/16.1/quartus/bin/jtagd --config /home/agmini/.jtagd.conf
* netstat -an | grep 1309 ### note listen address is "0.0.0.0", NOT "127.0.0.1"
<pre>
tcp 0 0 0.0.0.0:1309 0.0.0.0:* LISTEN
</pre>
* opt/intelFPGA/16.1/quartus/bin/jtagconfig ### should work
* ssh olchansk@daq01
* cd git/trg_firmware
* /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
* jtagconfig ### should work
<pre>
daq01:trg_firmware$ jtagconfig
1) DE-SoC on daq16 [2-1.2.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) USB-Blaster on daq16 [2-1.3]
024090DD EP4SGX230(.|ES)
020A40DD 5M(1270ZF324|2210Z)/EPM2210

daq01:trg_firmware$
</pre>

= ALPHA-g trigger functions =

Trigger options:
* software trigger
* pulser trigger
* trigger on GRIF16 ADC NIM and ESATA inputs ("external trigger")
* adc16 grand-or
* adc32 grand-or
* adc16 wire multiplicity
* TPC anode wire per-preamp trigger (aw16 section)
** trigger on coincidences of preamps (removed fw 0x62c77f0b)
** trigger on multiplicity of preamps (removed fw 0x62c77f0b)
** trigger on specific topology of preamps (multiplicity of preamp clusters, etc) via the aw16_mlu trigger
* BSC trigger
** BSC grand_or
** BSC bar multiplicity
* coincidence trigger - select coincidence of external trigger, TPC AW grand-or, TPC AW MLU, BSC grand-or and BSC bar multiplicity triggers

== software trigger ==

to programmatically fire the trigger, one should:
* set the conf_enable_sw_trigger bit in conf_trig_enable, this will permit the software trigger to fire the trigger
* write value 0x4 to register 0x2B, this will cause the software trigger to fire

== pulser trigger ==

To use the pulser trigger, one should program:
* pulser period (in clocks)
* pulser width (in clocks, use value 5, the pulser no longer goes outside of the trigger board, so changing the width does not do anything)
* set the run_pulser bit in conf_trig_enable, this will cause the pulser to run
* set the enable_pulser bit in conf_trig_enable, this will cause the pulser to fire the trigger
* set the output_pulser bit in conf_trig_enable, this will cause the pulser to be output from the alphag firmware block (the pulser no longer goes outside of the trigger board, so changing the bit does not do anything)

== timeout trigger ==

The event builder uses event timestamps to assemble physics events. The timestamps
are usually 32 bit wide and run at 125 MHz (8 ns) or 62.5 MHz (16 ns). If
triggers are generated often (1 per second or more), timestamp wrap around
is easily detected by the event builder. If triggers come infrequently,
timestamp wrap around may occur while there are no triggers, not be seen
by the event builder causing loss of event synchronization.

To avoid this problem in the event builder, a timeout trigger should be generated
if no triggers were generated inside a 10 second interval.

The guaranties that even if all physics triggers temporarily stop for any reason,
the event builder will stay synchronized. (0.1 Hz timeout trigger frequency).

To enable the timeout trigger:
* program timeout trigger timeout in reg 0x43 in units of 8 ns clock
* enable it in bit 23 of [[#conf_trig_enable bits]]

== adc16 multiplicity trigger ==

This trigger is intended for use with the barrel scintillator signals connected to adc16 digitizers. It does not work well with TPC AW signals.

The 16 adc16 trigger bits (16x16=256) are added together to form the hit multiplicity value (adc16_mult, 16 bits, actual range 0 to 256).

Four threshold signals are computed: adc16_mult_1ormore = adc16_mult>=1, 2ormore, 3ormore, 4ormore.

There is a counter for each of these four signals.

Each of these four signals can fire the trigger, see [[#conf_trig_enable bits]].

== TPC anode wire triggers ==

=== aw16 bus ===

TPC Anode Wire trigger is based on the aw16[15:0] (xaw16) bus.

Each bit corresponds to one AW preamp. 16 preamps, 16 bits.

The aw16[15:0] bus can be fed by
* adc16_or16[15:0] - or16 of 100 MHz ADCs, 16 ADC sas links
* adc32_or16[15:0] - or16 of 62.5 MHz ADCs, FMC-ADC32 has 32 channels, so 2 bits per ADC: low 16 channels and high 16 channels, sas links 7..0
* adc32_or16[31:16] - or16 of 62.5 MHz ADCs, ditto, sas links 15..8
as selected by conf_enable_aw_adc16, conf_enable_aw_adc32a, conf_enable_aw_adc32b in [[#conf_control bits]]

<pre>
///////////////////////////////////////////////////////////
// TPC Anode Wire trigger logic (aw16)
///////////////////////////////////////////////////////////

// map adc signals into aw16

wire [15:0] aw16 = ({16{conf_enable_aw_adc16}} & adc16_or16[15:0]) |
({16{conf_enable_aw_adc32a}} & adc32_or16[15:0]) |
({16{conf_enable_aw_adc32b}} & adc32_or16[31:16]);
...
ag_conditioner cond_adc16_or16_0(.clk(clk), .in(aw16[0]), .out(xxaw16[0]));
...
xaw16 <= xxaw16;
</pre>

=== aw16_grand_or ===

TPC AW "grand or" trigger: use aw16_mult_1ormore (before fw 0x62c77f0b)

(256 anode wires, 16 wires per preamp, 16 preamps, 16 aw16 signals)

=== aw16_mlu ===

TPC AW preamp MLU trigger: the MLU (memory lookup
table) implements an arbitrary logical function
to map the 16 aw16 preamp signals into 1 aw16_mlu_trig trigger output.

Description of the aw16 mlu trigger.

In words:

* any aw16 signal starts the aw16_prompt_run gate
* aw16 signals are collected for the duration of conf_mlu_prompt (125MHz/8ns clock)
* this corresponds to time spread of TPC AW signals due to the drift time in the AW drift cell and to the variation in signal transmission time from the ADC to the TRG (digital trigger data link).
* when this prompt time expires, the MLU looks at the accumulated aw16_prompt bit pattern and makes the "yes/no" trigger decision
* after the trigger decision is made, we wait for the TPC to become quiet:
* we wait until all aw16 signals are empty (no timeout)
* we run the aw16_prompt_wait gate, length conf_mlu_wait (8ns clock), if any aw16 signals arrive, we wait for aw16 empty again, rinse, repeat.
* now, after TPC aw16 have been empty for conf_mlu_wait clocks (8ns clock), MLU trigger is ready for the next event.

In logic: (see alphag.v)

* aw16_or <= grand-or of 16 aw16 signals
* "aw16_or" starts the "aw16_prompt_cnt" counter, opens the aw16_prompt_run gate
* during the aw16_prompt_run gate, aw16_prompt collects (latches) the aw16 bits (aw16_prompt <= aw16_prompt | aw16)
* this is the time when we wait for all "prompt" signals from the TPC to arrive into the trigger
* at the end of the aw16_prompt_run gate, the signal aw16_prompt_out is pulsed, latching the output of the MLU into aw16_mlu_trig
* this is the MLU trigger "yes/no" trigger decision.
* after the MLU trigger decision is made, we wait for the arrival and passing of all TPC drift signals
* the aw16_prompt_wait_cnt and aw_prompt_wait gate opens
* if any new aw16 signals arrive (they are TPC drift signals at this time), the aw16_prompt_wait gate is restarted
* if no aw16 signals arrive during the full run of the aw16_prompt_wait gate ("TPC quiet time")
* the aw16_prompt_wait and aw16_prompt gates are cleared and the MLU trigger is ready for the next event.

Good settings are:
* conf_mlu_prompt: 64 (512 ns)
* conf_mlu_wait: 128 (1024 ns)

== BSC trigger ==

=== bsc_adc16 bus ===

The BSC trigger is based on the [15:0]bsc_adc16[7:0] bus: 16 trigger discriminator bits from 8 ADC sas links. (8*16 = 64+64 bars, top and bottom).

The bsc_adc16 bus can be fed from sas links 0..7 or 8..15, controlled by conf_bsc_adc16_a and conf_bsc_adc16_b bits on [[#conf_bsc_control bits]].

bsc_adc16 can be fed only from GRIF-16 100 MHz ADC trigger discriminators.

=== bsc64_top and bsc64_bot buses ===

* firmware 0x5bc8f90f: bsc_adc16 is remapped into 64 bits of top (bsc64_top) and bottom (bsc64_bot):
<pre>
ag_bsc_remap bsc_remap_a(.adc(bsc_adc16[0]), .bsc_bot(bsc64_bot[7:0]), .bsc_top(bsc64_top[7:0]));
ag_bsc_remap bsc_remap_b(.adc(bsc_adc16[1]), .bsc_bot(bsc64_bot[8+7:8+0]), .bsc_top(bsc64_top[8+7:8+0]));
ag_bsc_remap bsc_remap_c(.adc(bsc_adc16[2]), .bsc_bot(bsc64_bot[2*8+7:2*8+0]), .bsc_top(bsc64_top[2*8+7:2*8+0]));
ag_bsc_remap bsc_remap_d(.adc(bsc_adc16[3]), .bsc_bot(bsc64_bot[3*8+7:3*8+0]), .bsc_top(bsc64_top[3*8+7:3*8+0]));

ag_bsc_remap bsc_remap_e(.adc(bsc_adc16[4]), .bsc_bot(bsc64_bot[4*8+7:4*8+0]), .bsc_top(bsc64_top[4*8+7:4*8+0]));
ag_bsc_remap bsc_remap_f(.adc(bsc_adc16[5]), .bsc_bot(bsc64_bot[5*8+7:5*8+0]), .bsc_top(bsc64_top[5*8+7:5*8+0]));
ag_bsc_remap bsc_remap_g(.adc(bsc_adc16[6]), .bsc_bot(bsc64_bot[6*8+7:6*8+0]), .bsc_top(bsc64_top[6*8+7:6*8+0]));
ag_bsc_remap bsc_remap_h(.adc(bsc_adc16[7]), .bsc_bot(bsc64_bot[7*8+7:7*8+0]), .bsc_top(bsc64_top[7*8+7:7*8+0]));

module ag_bsc_remap
(
input wire [15:0] adc,
output wire [7:0] bsc_bot,
output wire [7:0] bsc_top
);

assign bsc_top[3] = adc[0];
assign bsc_top[2] = adc[1];
assign bsc_top[1] = adc[2];
assign bsc_top[0] = adc[3];

assign bsc_top[7] = adc[4];
assign bsc_top[6] = adc[5];
assign bsc_top[5] = adc[6];
assign bsc_top[4] = adc[7];

assign bsc_bot[0] = adc[8];
assign bsc_bot[1] = adc[9];
assign bsc_bot[2] = adc[10];
assign bsc_bot[3] = adc[11];

assign bsc_bot[4] = adc[12];
assign bsc_bot[5] = adc[13];
assign bsc_bot[6] = adc[14];
assign bsc_bot[7] = adc[15];

endmodule
</pre>

=== bsc64 bus ===

the bsc64 bus is the 64 bars used by the trigger, formed from bsc64_top and bsc64_bot:
<pre>
if (conf_bsc64_bot_only) begin
bsc64 <= bsc64_bot;
end else if (conf_bsc64_top_only) begin
bsc64 <= bsc64_top;
end else if (conf_bsc64_bot_top_or) begin
bsc64 <= bsc64_bot | bsc64_top;
end else if (conf_bsc64_bot_top_and) begin
bsc64 <= bsc64_bot & bsc64_top;
end else begin
bsc64 <= 64'b0;
end
</pre>

=== bsc_grand_or_trig ===

bsc_grand_or_trig is the grand-or of 64 bits of the bsc64 bus

to enable triggering on bsc_grand_or_trig, set corresponding bit in [[#conf_trig_enable bits]]

=== old bsc_mult_trig ===

(from fw 0x62c77f0b, old bsc_mult_trig was replaced by new bsc64 multiplicity trigger)

* bsc64_mult is computed as multiplicity of the bsc64 bus (number of 64 bsc64 bits that fired)
* bsc_mult_trig is computed:
<pre>
if (bsc64_mult >= conf_bsc64_mult) begin
bsc_mult_trig <= 1;
end else begin
bsc_mult_trig <= 0;
end
</pre>

to enable the bsc multiplicity trigger, set the multiplicity value conf_bsc64_mult in [[#conf_bsc_control bits]] and enable the corresponding bit in [[#conf_trig_enable bits]].

=== bsc64 multiplicity trigger ===

bsc64 BSC bar multiplicity trigger uses a time window. this time window is started by bsc64_grand_or and runs for conf_bsc64_mult_window clocks (8 nc clock). During this time, hits in bsc64_bus are accumulated (latched) and their multiplicity is computed. If multiplicity condition is satisfied (bigger or equal to conf_bsc64_mult_min), bsc64_mult_trig is fired and the bsc64 bit pattern is saved to the UDP packet. Then trigger waits for the bsc64_bus to be empty. Then trigger waits for conf_bsc64_empty_window clocks, if there is any bsc64 hits, we wait for empty again. So after bsc64 has been empty for conf_bsc64_empty_window clocks, multiplicity trigger is ready for the next event. This scheme cannot implement max multiplicity.

recommended values:
* conf_bsc64_mult_window (8 bits): slightly longer than 3 cycles of SAS link: 3*18 = 54 clocks, good value is 80 (640 ns).
* conf_bsc64_mult_min (8 bits): 2
* conf_bsc64_empty_window (8 bits): 80 (640 ns)

== Coincidence trigger ==

Coincidence trigger provides a combination of TPC, BSC and external scintillator (esata_nim_grand_or) signals:

<pre>
assign coinc_input[0] = aw16_grand_or; // was aw16_mult_1ormore;
assign coinc_input[1] = aw16_mlu_trig;
assign coinc_input[2] = bsc_grand_or_trig;
assign coinc_input[3] = bsc_mult_trig;
assign coinc_input[4] = esata_nim_grand_or;
assign coinc_input[5] = 0;
assign coinc_input[6] = 0;
assign coinc_input[7] = 0;
</pre>

Coincidence trigger "start" mask selects which of the inputs can start the coincidence window.

Coincidence trigger "require" mask selects which inputs must have a hits for the coincidence to be satisfied.

Input hits are collected for the duration of the coincidence window, if all required inputs have hits, coinc_trig is fired.

Example settings:

* coincidence of external scintillator, BSC and TPC AW "grand or" signals: start 0x10, required 0x15
* coincidence of BSC grand-or and TPC AW grand-or signals: start 0x5, required 0x5
* coincidence of BSC multiplicity and TPC AW grand-or triggers: start 0x9, required 0x9

= Control registers =

== Register addresses ==

Note: all registers are 32 bits unless otherwise noted.

Note: RW means read-write register, RO means read-only, ROL means read-only, contents is latched by the "latch_out" bit

{| cellpadding="10" cellspacing="0" border="1"
! Address || Quartus Name || Access || FwRev || Description
|-
| 0x08 || num_sample || RW || GRIF-C || magic 16-bit register to control UDP packet size
|-
| 0x08 || scratch_reg || RW || 0x618b790b || 32-bit scratch register
|-
| 0x1F || compilation_time || RO || || Firmware revision
|-
| 0x20 || conf_trig_width || RW || || Trigger signal width, 16 ns clock
|-
| 0x21 || conf_busy_width || RW || || Busy signal width, 16 ns clock (not used)
|-
| 0x22 || conf_pulser_width || RW || || Pulser signal width, 16 ns clock
|-
| 0x23 || conf_pulser_period || RW || || Pulser signal period, 16 ns clock
|-
| 0x24 || conf_pulser_burst_ctrl || RW || 0x62d1c47e || Generate bursts of pulses: 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses, 16 ns clocks
|-
| 0x25 || conf_trig_enable || RW || || see [[#conf_trig_enable bits]]
|-
| 0x26 || || || not used
|-
| 0x27 || || || not used
|-
| 0x28 || || || not used
|-
| 0x29 || conf_nim_mask || RW || || enable bits for ADC NIM inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2A || conf_esata_mask || RW || || enable bits for ADC eSATA inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2B || reset_out, latch_out, trigger_out || W || || see [[#reg 0x2B bits]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x5bc8f90f || configure AW coincidence trigger, see [[#aw16_coinc]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x62c77f0b || removed
|-
| 0x2D || conf_aw16_coinc_b || RW || 0x5bc8f90f ||
|-
| 0x2E || conf_aw16_coinc_c || RW || 0x5bc8f90f ||
|-
| 0x2F || conf_aw16_coinc_d || RW || 0x5bc8f90f ||
|-
| 0x30 || sas_sd[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect for each link
|-
| 0x31 || pll_625_status || ROL || 0x5b2057f5 (12Jun18_16:32) || 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter
|-
| 0x32 || clk_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the system 125 MHz clock
|-
| 0x33 || clk_625_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625)
|-
| 0x34 || conf_control || RW || 0x5b398983 (01Jul18_19:10) || see [[#conf_control bits]] below
|-
| 0x35 || conf_drift_width || RW || 0x5b398983 (01Jul18_19:10) || width of drift time blank-out in 16 ns clocks
|-
| 0x36 || conf_scaledown || RW || 0x5b398983 (01Jul18_19:10) || trigger scaledown, 0=no scaledown, 1=divide-by-2, 2=divide-by-3, etc
|-
| 0x37 || conf_mlu || RW || 0x5b398983 (01Jul18_19:10) || AW MLU control bits, see [[#conf_mlu bits]]
|-
| 0x38 || conf_trig_delay || RW || 0x5baedfca (28Sep18_19:13) || delay the trigger pulse, 16 ns clock
|-
| 0x39 || esata_clk_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the TRG 125 MHz clock
|-
| 0x3A || esata_clk_esata_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the external clock (eSATA 62.5 MHz clock)
|-
| 0x3B || conf_counter_adc_select || RW || 0x5bb7f6ae (05Oct18_16:41) || select which 16 ADCs are connected to the selected adc counters, 0..15 - connect the adc16 signals, 16..47 connect the adc32 signals
|-
| 0x3C || sysreset_ts || RO || 0x5bb7f6ae (05Oct18_16:41) || 125MHz counter of VME-SYSRESET
|-
| 0x3C || || || 0x618b790b || not used
|-
| 0x3D || GRIF-C csr || RW || GRIF-C || <= csr & ~par_value; // Selective clear
|-
| 0x3E || GRIF-C csr || RW || GRIF-C || <= csr | par_value; // Selective set
|-
| 0x3F || GRIF-C csr || RW || GRIF-C || <= par_value; // write
|-
| 0x3D || || || 0x618b790b || not used
|-
| 0x3E || || || 0x618b790b || not used
|-
| 0x3F || || || 0x618b790b || not used
|-
| 0x40 || conf_bsc_control || RW || 0x5bc13541 (12Oct18_16:58) || Barrel Scintillator trigger control, see [[#conf_bsc_control bits]]
|-
| 0x41 || conf_coinc_control || RW || 0x5bc13541 (12Oct18_16:58) || Coincidence trigger control, see [[#conf_coinc_control bits]]
|-
| 0x42 || reconfig_out || WO || 0x5bc13541 (12Oct18_16:58) || reserved for rebooting the FPGA (does not work)
|-
| 0x43 || conf_trigger_timeout || RW || 0x5bc8f90f (18Oct18_14:20) || Generate timeout trigger if there is no other trigger after given timeout, in 8 ns clocks, must be enabled by bit conf_enable_timeout_trig in [[#conf_trig_enable bits]]
|-
| 0x44 || eth_clk_counter || ROL || 0x618b790b ||
|-
| 0x45 || eth_clk_eth_counter || ROL || 0x618b790b ||
|-
| 0x100 || ts_625 || ROL || || latched timestamp
|-
| 0x101 || counter_trig_out || ROL || || counter of issued triggers
|-
| 0x102 || counter_trig_in || ROL || || counter of triggers
|-
| 0x103 || counter_pulser || ROL || || counter of pulser
|-
| 0x104 || counter_adc16_grand_or || ROL ||
|-
| 0x105 || counter_adc32_grand_or || ROL ||
|-
| 0x106 || counter_adc_grand_or || ROL ||
|-
| 0x107 || counter_esata_nim_grand_or || ROL ||
|-
| 0x108 || counter_adc16_mult_1ormore || ROL ||
|-
| 0x109 || counter_adc16_mult_2ormore || ROL ||
|-
| 0x10A || counter_adc16_mult_3ormore || ROL ||
|-
| 0x10B || counter_adc16_mult_4ormore || ROL ||
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x5bc8f90f || counter of AW coincidence triggers
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x62c77f0b || removed
|-
| 0x10D || counter_aw16_coinc_b || ROL || 0x5bc8f90f ||
|-
| 0x10E || counter_aw16_coinc_c || ROL || 0x5bc8f90f ||
|-
| 0x10F || counter_aw16_coinc_d || ROL || 0x5bc8f90f ||
|-
| 0x110 || counter_drift || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the drift time blank-out
|-
| 0x111 || counter_scaledown || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the scaledown
|-
| 0x112 || counter_aw16_coinc || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW coincidence triggers
|-
| 0x113 || counter_aw16_mlu || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW MLU triggers
|-
| 0x114 || counter_aw16_grand_or || ROL || 0x62c77f0b || counter of AW grand-or triggers
|-
| 0x114 || counter_aw16_mult_1ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 1ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 2ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x62c77f0b || removed
|-
| 0x116 || counter_aw16_mult_3ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 3ormore triggers
|-
| 0x117 || counter_aw16_mult_4ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 4ormore triggers
|-
| 0x118 || counter_bsc_grand_or || ROL || 0x5bc13541 (12Oct18_16:58) || counter of BSC grand-or triggers
|-
| 0x119 || counter_bsc_mult || ROL || 0x5bc13541 (12Oct18_16:58) || counter of old BSC multiplicity triggers
|-
| 0x11A || counter_coinc || ROL || 0x5bc13541 (12Oct18_16:58) || counter of coincidence triggers
|-
| 0x11B || counter_timeout || ROL || 0x618b790b || counter of timeout triggers
|-
| 0x11C || counter_bsc_mult_start || ROL || 0x62c77f0b || counter of BSC multiplicity windows
|-
| 0x11D || counter_bsc_mult_trig || ROL || 0x62c77f0b || counter of BSC multiplicity triggers
|-
| 0x11E || counter_coinc_start || ROL || 0x62d1b152 || counter of coincidence windows
|-
| 0x11F || counter_aw16_mlu_start || ROL || 0x62d1b152 || counter of TPC AW MLU windows
|-
| 0x200..0x207 || conf_adc16_masks || RW || all || adc16 enable bits
|-
| 0x300..0x30F || conf_adc32_masks || RW || all || adc32 enable bits
|-
| 0x400..0x41F || sas_bits[15:0][63:0] || ROL || all || sas data bits for each link
|-
| 0x420..0x42F || sas_sd_counters[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect counter for each link
|-
| 0x430..0x43F || counters_adc16_or16[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 16 counters of adc16 ORes
|-
| 0x440..0x45F || counters_adc32_or16[31:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 32 counters of adc32 ORes
|-
| 0x460..0x46F || counters_adc_selected[15:0] || ROL || 0x5bb7f6ae (05Oct18_16:41) || 16 counters for selected group of adcs, see conf_counter_adc_select
|-
| 0x470..0x4AF || counters_bsc64[63:0] || ROL || 0x5bc13541 (12Oct18_16:58) || 64 counters for the BSC bars
|-
|}

== additional registers ==

<pre>
reg | rw/ro | quartus name | firmware | description
0x60: param_out <= {2'h3, par_id, chan, cb_control_out
0x61: param_out <= {2'h3, par_id, chan, cb_status
0x62: param_out <= {2'h3, par_id, chan, cb_invert_a_out };
0x63: param_out <= {2'h3, par_id, chan, cb_invert_b_out };
0x64: param_out <= {2'h3, par_id, chan, cb_enable_le_a_out };
0x65: param_out <= {2'h3, par_id, chan, cb_enable_le_b_out };
0x66: param_out <= {2'h3, par_id, chan, cb_enable_te_a_out };
0x67: param_out <= {2'h3, par_id, chan, cb_enable_te_b_out };
0x6A | ro | cb_input_num | 0x618b790b | chronobox number of inputs
0x6B: param_out <= {2'h3, par_id, chan, cb_sync_mask_a_out };
0x6C: param_out <= {2'h3, par_id, chan, cb_sync_mask_b_out };
0x6D: param_out <= {2'h3, par_id, chan, cb_sync_reg_out };
0x6E: param_out <= {2'h3, par_id, chan, cb_sync_status };
0x6F: param_out <= {2'h3, par_id, chan, cb_latch_period_out };
0x70: param_out <= {2'h3, par_id, chan, cb_fifo_status };
0x71: begin param_out <= {2'h3, par_id, chan, cb_fifo_data }; cb_fifo_rdack_out <= 1; end
0x72: param_out <= {2'h3, par_id, chan, cb_udp_period_out };
0x73: param_out <= {2'h3, par_id, chan, cb_udp_threshold_out };
</pre>

== conf_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_clock_select || 0x5b3aa19f (02Jul18_15:05) || select 0=internal 62.5 MHz clock or 1=esata 62.5 MHz clock
|-
| 1 || conf_enable_aw_adc16 || 0x5baedfca (28Sep18_19:13) || select source of TPC AW aw16 bus, see [[#aw16 bus]]
|-
| 2 || conf_enable_aw_adc32a || 0x5baedfca (28Sep18_19:13) ||
|-
| 3 || conf_enable_aw_adc32b || 0x5baedfca (28Sep18_19:13) ||
|-
| 15..4 || || ||
|-
| 23..16 || conf_mlu_prompt || 0x5b3aa19f (02Jul18_15:05) || MLU trigger prompt window, see [[#aw16_mlu]]
|-
| 31..24 || conf_mlu_wait || 0x5b3aa19f (02Jul18_15:05) || MLU trigger wait window, see [[#aw16_mlu]]
|-
|}

== conf_mlu bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 31 || mlu_reset || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 30 || mlu_write || 0x5b3aa19f (02Jul18_15:05) || 1=write data bit into given address
|-
| 16 || mlu_data || 0x5b3aa19f (02Jul18_15:05) || data bit for writing to MLU RAM
|-
| 15..0 || mlu_write_addr || 0x5b3aa19f (02Jul18_15:05) || MLU RAM write address for writing the data bit
|-
|}

== conf_bsc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_bsc_adc_a || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 0..7
|-
| 1 || conf_bsc_adc_b || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 8..15
|-
| 2 || conf_bsc64_bot_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses bottom channels only
|-
| 3 || conf_bsc64_top_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses top channels only
|-
| 4 || conf_bsc64_bot_top_or || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "or" of top and bottom
|-
| 5 || conf_bsc64_bot_top_and || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "and" of top and bottom
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_bsc64_mult_min || 0x5bc13541 (12Oct18_16:58) || minimum bsc64 multiplicity
|-
| 23..16 || conf_bsc64_empty_wondow || 0x62d1c47e || bsc64 empty window length, 8 ns clocks
|-
| 31..24 || conf_bsc64_mult_window || 0x62c77f0b || bsc64 multiplicity window length, 8 ns clocks
|-
|}

== conf_coinc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_coinc_required[0] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mult_1ormore
|-
| 0 || conf_coinc_required[0] || 0x62c77f0b || enable aw16_grand_or
|-
| 1 || conf_coinc_required[1] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mlu_trig
|-
| 2 || conf_coinc_required[2] || 0x5bc13541 (12Oct18_16:58) || enable bsc_grand_or_trig
|-
| 3 || conf_coinc_required[3] || 0x5bc13541 (12Oct18_16:58) || enable bsc_mult_trig
|-
| 3 || conf_coinc_required[3] || 0x62c77f0b || enable bsc64_mult_trig
|-
| 4 || conf_coinc_required[4] || 0x5bc13541 (12Oct18_16:58) || enable esata_nim_grand_or
|-
| 5 || conf_coinc_required[5]
|-
| 6 || conf_coinc_required[6]
|-
| 7 || conf_coinc_required[7]
|-
| 15..8 || conf_coinc_window[7:0] || 0x5bc13541 (12Oct18_16:58) || coincidence window length in units of 125MHz clock (8 ns)
|-
| 23..16 || conf_coinc_start[7:0] || 0x5bc13541 (12Oct18_16:58) || start the coincidence window, same bits as "required"
|-
| 31..24 ||
|-
|}

== conf_trig_enable bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_enable_sw_trigger || || trigger on software trigger (how generated???)
|-
| 1 || conf_enable_pulser || || trigger on pulser
|-
| 2 || - || 0x5b120c9f (01Jun18_20:18) || not used
|-
| 3 || conf_pulser_run || || allow the pulser to run (frequency has to be set beforehand)
|-
| 4 || conf_output_pulser || 0x5bc8f90f || does nothing (top level ag_pulser_out is disconnected)
|-
| 4 || || 0x618b790b || not used
|-
| 5 || conf_enable_esata_nim || || trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand)
|-
| 6 || conf_enable_adc16 || || trigger on adc16_grand_or
|-
| 7 || conf_enable_adc32 || || trigger on adc32_grand_or
|-
| 8 || conf_enable_adc16_1ormore || || trigger on adc16_mult_1ormore "1 or more"
|-
| 9 || conf_enable_adc16_2ormore || || same, "2 or more"
|-
| 10 || conf_enable_adc16_3ormore || || same, "3 or more"
|-
| 11 || conf_enable_adc16_4ormore || || same, "4 or more"
|-
| 12 || - || 0x5b08938c (25May18_15:51) || not used
|-
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
|-
| 14 || - || 0x5bc8f90f || not used
|-
| 15 || conf_enable_adc || 0x5b120c9f (01Jun18_20:18) || trigger on adc_grand_or
|-
| 16 || conf_enable_aw16_coinc_a || 0x5bc8f90f || enable AW coincidence trigger, see [[#aw16_coinc]]
|-
| 16 || - || 0x62c77f0b || aw16_coinc_x removed
|-
| 17 || conf_enable_aw16_coinc_b || 0x5bc8f90f ||
|-
| 18 || conf_enable_aw16_coinc_c || 0x5bc8f90f ||
|-
| 19 || conf_enable_aw16_coinc_d || 0x5bc8f90f ||
|-
| 20 || - || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 20 || conf_enable_aw16_grand_or || 0x618b790b || enable trigger on aw16_grand_or
|-
| 21 || conf_enable_aw16_coinc || 0x5b3aa19f (02Jul18_15:05) || enable trigger on aw16_coinc_trig
|-
| 22 || conf_enable_aw16_mlu || 0x5b3aa19f (02Jul18_15:05) || enable AW MLU trigger
|-
| 23 || conf_enable_timeout_trig || 0x5bc8f90f (18Oct18_14:20) || enable trigger timeout trigger
|-
| 24 || conf_enable_aw16_1ormore || 0x5b3aa19f (02Jul18_15:05) || trigger on aw16_mult_1ormore "1 or more"
|-
| 24 || - || 0x62c77f0b || aw16_mult_xxx removed
|-
| 25 || conf_enable_aw16_2ormore || 0x5b3aa19f (02Jul18_15:05) || same, "2 or more"
|-
| 26 || conf_enable_aw16_3ormore || 0x5b3aa19f (02Jul18_15:05) || same, "3 or more"
|-
| 27 || conf_enable_aw16_4ormore || 0x5b3aa19f (02Jul18_15:05) || same, "4 or more"
|-
| 28 || conf_enable_bsc_grand_or || 0x5bc13541 (12Oct18_16:58) || trigger on BSC grand-or
|-
| 29 || conf_enable_bsc_mult || 0x5bc13541 (12Oct18_16:58) || trigger on BSC multiplicity
|-
| 30 || conf_enable_coinc || 0x5bc13541 (12Oct18_16:58) || trigger on TPC/BSC/ext coincidence trigger
|-
| 31 || - || || not used
|-
|}

== reg 0x2B bits ==

Write to this register will pulse corresponding fpga signals:

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || reset_out || 0x5b120c9f (01Jun18_20:18) || reset counters, etc
|-
| 1 || latch_out || 0x5b120c9f (01Jun18_20:18) || latch counters, sas bits, etc
|-
| 2 || trigger_out || 0x5b120c9f (01Jun18_20:18) || generate a software trigger
|-
|}

= UDP data format =

== firmware 0x5bc8f90f ==

{| cellpadding="10" cellspacing="0" border="1"
! Offset || Name || Quartus name || FwRev || Description
|-
| 0 || packet counter || none || all || 31-bit UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
|-
| 1 || 0x8 packet header || || all || 28 bits of counter_trig_out
|-
| 2 || trigger timestamp || trig_ts || all || 62.5MHz trigger timestamp
|-
| 3 || accepted triggers || counter_trig_out || all || counter of accepted triggers
|-
| 4 || input triggers || counter_trig_in || all || counter of trigger input
|-
| 5 || pulser triggers || counter_pulser || all || counter of pulser triggers
|-
| 6 || trigger bitmap || udp_trig_bits || 0x5a48448d (30Dec17_17:59) || bitmap of trigger information, see below
|-
| 7 || nim bits || udp_nim_bits_masked || ??? || 32 bits of ADC NIM inputs (2 bits per ADC)
|-
| 8 || esata bits || udp_esata_bits_masked || ??? || 32 bits of ADC ESATA inputs (2 bits per ADC)
|-
| 9 || mlu bits || aw16_prompt || 0x5b398983 (01Jul18_19:10) || 16 bits of MLU input, 1 bit per preamp
|-
| 10 || drift-blank-off counter || udp_drift_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the drift blank-off
|-
| 11 || scaledown counter || udp_scaledown_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the scaledown
|-
| X || || || ||
|-
| 12 || 0xE packet footer || || all || 28 bits of counter_trig_out
|-
|}

== firmware 0x618b790b (Nov 2021) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

== firmware 0x62d1c47e (Jul 2022) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, 8'h00, 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= conf_fw_rev;
18 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

Values of udp_coinc_latch[7:0]:
* aaa

Values of udp_aw16_mult[7:0] and udp_aw16_bus[15:0]:
* aaa

Values of udp_bsc64_mult[7:0] and udp_bsc64_bus[63:0]
* aaa

== trigger bitmap ==

Firmware ??? (one of the very early revisions)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= adc16_coinc_top;
udp_trig_bits[5] <= adc16_coinc_bot;
udp_trig_bits[6] <= adc16_coinc;
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
udp_trig_bits[31:24] <= mult16[7:0];

</pre>

Firmware 0x5b08938c (25May18_15:51)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= 0; // not used
udp_trig_bits[31:24] <= mult16[7:0];
</pre>

Firmware 0x5b217dc4 (13Jun18_13:25)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5b3aa19f (02Jul18_15:05)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= udp_mlu_out;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5bc8f90f (18Oct18_14:20)

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_run_pulser
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = 0; // not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x618b790b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x62c77f0b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = 0; // aw16_coinc_a;
assign trig32_in[17] = 0; // aw16_coinc_b;
assign trig32_in[18] = 0; // aw16_coinc_c;
assign trig32_in[19] = 0; // aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = 0; // aw16_mult_1ormore;
assign trig32_in[25] = 0; // aw16_mult_2ormore;
assign trig32_in[26] = 0; // aw16_mult_3ormore;
assign trig32_in[27] = 0; // aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc64_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

= TRG chronobox inputs =

from trg_firmware/toplevel/grifc.v

<pre>
localparam CB_N = 23;
localparam CB_N1 = CB_N-1;

wire [CB_N1:0] cb_xinputs_async;

assign cb_xinputs_async[0] = ag_trig_out;
assign cb_xinputs_async[1] = ag_trig_scaledown_out;
assign cb_xinputs_async[2] = ag_trig_drift_out;
assign cb_xinputs_async[3] = ag_trig_received_out;

assign cb_xinputs_async[4] = ag_cb_sw_trig;
assign cb_xinputs_async[5] = ag_cb_pulser_trig;
assign cb_xinputs_async[6] = ag_cb_esata_nim_trig;
assign cb_xinputs_async[7] = ag_cb_adc16_grand_or_trig;
assign cb_xinputs_async[8] = ag_cb_adc32_grand_or_trig;

assign cb_xinputs_async[9] = ag_cb_aw16_grand_or_trig;
assign cb_xinputs_async[10] = ag_cb_aw16_mult_1ormore;
assign cb_xinputs_async[11] = ag_cb_aw16_mult_2ormore;
assign cb_xinputs_async[12] = ag_cb_aw16_mult_3ormore;
assign cb_xinputs_async[13] = ag_cb_aw16_mult_4ormore;
assign cb_xinputs_async[14] = ag_cb_aw16_mlu_trig;

assign cb_xinputs_async[15] = ag_cb_bsc64_grand_or_trig;
assign cb_xinputs_async[16] = ag_cb_bsc64_mult_1ormore;
assign cb_xinputs_async[17] = ag_cb_bsc64_mult_2ormore;
assign cb_xinputs_async[18] = ag_cb_bsc64_mult_3ormore;
assign cb_xinputs_async[19] = ag_cb_bsc64_mult_4ormore;
assign cb_xinputs_async[20] = ag_cb_bsc64_mult_trig;

assign cb_xinputs_async[21] = ag_cb_coinc_trig;

assign cb_xinputs_async[22] = ag_cb_timeout_trig;
</pre>

= Example UDP packets =

* trigger data, marker words 0x8

<pre>
ReadDataThread read 76
0: 0x003666ed -- UDP packet counter from UDP transmitter
1: 0x80000bf8 -- 0x8 is trigger data packet, 0xbf8 is the trigger counter from alphag.v
2: 0x2edf8b41 -- trigger data
3: 0x00000bf8
4: 0x00000bf8
5: 0x00000bee
6: 0x00000001
7: 0x00000000
8: 0x00000000
9: 0x00000003
10: 0x00000bf8
11: 0x00000bf8
12: 0x00000000
13: 0x00000000
14: 0x00000000
15: 0x00000000
16: 0x00000000
17: 0x00000000
18: 0xe0000bf8 -- 0xE is end of trigger data, counter 0xbf8 must match the counter in the 0x8 word.
ReadDataThread read 76 -- next packet
0: 0x003666ee -- UDP packet counter from UDP transmitter
...
</pre>

* chronobox fifo data, marker word 0xC, see [[Chronobox#FIFO_data_format]]

<pre>
ReadDataThread read 404
0: 0x003658ed -- UDP packet counter from UDP transmitter
1: 0xc000eacc -- 0xC is FIFO data, fifo packet counter 0xeacc from fifo_to_udp.v
2: 0x00000061 -- FIFO status, low bits the the word counter, so up to 0x61 fifo words are to follow
3: 0x87fb3d72 -- tsc hits
4: 0x8ffb3d74
5: 0x90fb3d74
6: 0x91fb3d74
7: 0x92fb3d74
8: 0x93fb3d74
9: 0x93fb3d75
10: 0x94fb3d74
11: 0x94fb3d77
12: 0x87fb3d77
13: 0x8ffb3d77
14: 0x90fb3d77
15: 0x91fb3d77
16: 0x92fb3d77
17: 0xfe000018 -- 0xFE scaler data starts, 0x18 words to follow
18: 0x00000000
19: 0x00000000
20: 0x00000000
21: 0x00000000
22: 0x00000000
23: 0x00000000
24: 0x00000000
25: 0x00000108
26: 0x00000000
27: 0x00000000
28: 0x00000000
29: 0x00000000
30: 0x00000000
31: 0x00000000
32: 0x00000000
33: 0x00000108
34: 0x00000108
35: 0x00000108
36: 0x00000108
37: 0x00000108
38: 0x00000108
39: 0x00000000
40: 0x00000000
41: 0xce56fa93 -- last word of scaler data is the sysclock counter (125 MHz)
42: 0xff800048 -- timestamp wraparound
43: 0x8f1f36e4 -- tsc hits
44: 0x901f36e4
45: 0x911f36e4
46: 0x921f36e4
47: 0x931f36e4
48: 0x941f36e4
49: 0x871f36e4
50: 0x871f36e7
51: 0x8f1f36e7
52: 0x901f36e9
53: 0x911f36e7
54: 0x921f36e9
55: 0x931f36e7
56: 0x941f36e9
57: 0x904330ac
58: 0x914330ac
59: 0x924330ac
60: 0x934330ac
61: 0x934330ad
62: 0x944330ac
63: 0x944330ad
64: 0x874330ac
65: 0x874330ad
66: 0x8f4330ac
67: 0x8f4330ad
68: 0x904330ad
69: 0x914330ad
70: 0x924330ad
71: 0x8f672a62
72: 0x90672a62
73: 0x91672a62
74: 0x92672a62
75: 0x93672a62
76: 0x94672a62
77: 0x87672a62
78: 0x87672a65
79: 0x8f672a65
80: 0x90672a65
81: 0x91672a65
82: 0x92672a65
83: 0x93672a65
84: 0x94672a65
85: 0xff000049
86: 0x878b2422
87: 0x8f8b2424
88: 0x908b2424
89: 0x918b2424
90: 0x928b2424
91: 0x938b2424
92: 0x938b2425
93: 0x948b2424
94: 0x948b2427
95: 0x878b2427
96: 0x8f8b2427
97: 0x908b2427
98: 0x918b2427
99: 0x928b2427
100: 0xe000eacc -- 0xE is end of fifo data, counter 0xeacc must match the counter in the 0xC word.
ReadDataThread read 344 -- next packet
...
</pre>

= TODO =

* DONE July 2022. add FwRev to the UDP data output
* RJ45 SFP: PROBLEM, D.A. CABLE: GOOD, Fiber SFP: ???. fix "write did not happen" (send udp write command, there is no reply, read returns old data as if write never happened). suspect udp "write" packet is lost?
* PROBLEM GONE Aug 2021. fix reply to wrong socket - udp packets should reply to same socket as they came from, udp data packets should be sent to same socket as requested them, not same socket as last command.
* DONE 2021jul30. add fixes from Chris P. for the auto-negotiation and dhcp (see email from him).
* DONE flash chip connected to FPGA. Aug 2021. implement ethernet flash programmer
* DONE Aug 2021. updated maxv firmware. implement FPGA reboot
* speed up programming the MLU by writing more than 1 bit at a time
* DONE Nov 2021. add 64-bit bitmap of BSC trigger bits
* DONE. add chronobox code
* DONE. add avalon mux for alphag and chronobox packets
* DONE. add chronobox fifo to udp packet sequencer
* check that TxReadyOut is correct and it is safe to send an avalon packet while previous packet is still transmitting.
* DONE. test fiber SFP is working
* complete the UDP flash programmer (parallel flash erase and write)

= End =

//KO

Daq

2022-07-16T21:16:07Z

Olchansk: /* /Equipment/CTRL/Settings/TRG - trigger settings */

= Links =

* https://alphacpc05.cern.ch/agdaq/ -- midas daq page for the agdaq system at CERN
* https://daq16.triumf.ca -- midas daq page for the agmini system at TRIUMF
* https://daq.triumf.ca/elog-alphag/alphag/ -- elog
* https://daqstore.triumf.ca/AgWiki/index.php/Main_Page -- this wiki
* https://bitbucket.org/ttriumfdaq/agdaq - git repository for agdaq
* https://bitbucket.org/expalpha -- git repository on bitbucket
* https://edev-group.triumf.ca/fw/exp/alphag -- git repository on edev gitlab

= Inventory database =

* https://ladd00.triumf.ca/daqinv/frontend/list/170 - PWB inventory database
* https://ladd00.triumf.ca/daqinv/frontend/list/168 - ADC (GRIF-16) inventory, FMC-ADC32rev0,rev1 inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/176 - FMC-ADC32rev1.1 inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/174 - BSC RTM inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/173 - BSC ASD inventory

= Hardware manuals =

* [[TRG]] - trigger board (GRIF-C) manual
* CDM - https://daq.triumf.ca/DaqWiki/index.php/VME-CDM -- clock VME-CDM manual
* ADC - https://daq.triumf.ca/DaqWiki/index.php/VME-GRIF-ADC16-Rev1 -- GRIF-16 ADC manual
* [[PWB]] - TPC Pad Wing Board manual
* TDC - https://daq.triumf.ca/DaqWiki/index.php/GSI_TRB3
* [[chronobox]] - chronobox manual
* [[ASD]] - BSC preamp board
* [[RTM]] - BSC VME rear transition board

= Performance =

Full system: (ADC fw rel-20201112-ko, PWB fw 20201005_ko)
* 1 Hz stable, ADC adc32 9 supp off rate 0.3 M/s, adc16 off, PWB udp_delay 25 supp off active 64 rate 6.6+4+6+4.6=21.2 M/s, TDC off, total rate 21 M/s
* 500 Hz stable, ADC adc32 9 supp 1500 rate 6 M/s, adc16 off, PWB udp_delay 10 supp 100 active 63 rate 3+4+3+3=13 M/s, TDC off, total rate 19 M/s

Single ADC: (fw rel-20201112-ko)

Fully suppressed data, sthreshold 5000
* 1 Hz: stable
* 500 Hz: stable (nominal max trigger rate)
* 6700 Hz: stable, 8 Mbytes/sec
* 6800 Hz: evb eventually confused
* 6850 Hz: evb confused, no lost triggers in the ADC, no crash in the ADC

All data, 510 samples/event, sthreshold 10 (fw rel-20201122-ko)
* 1 Hz: stable
* 100 Hz: stable, 3.4 Mbytes/sec
* 500 Hz: stable, 17 Mbytes/sec (nominal max trigger rate)
* 1000 Hz: stable, 32 Mbytes/sec
* 3100 Hz: stable, 106 M/s (approaching saturation of 1gige ethernet)
* 3200 Hz: stable, 110 M/s - TRG communication is in trouble
* 3300 Hz: stable, 116 M/s
* 3400 Hz: incomplete events, no ADC crash ("dropped due to full" counting, "dropped due to busy" are zero, this is as expected).

no suppression (different fpga data path)
* 1 Hz: stable
* 100 Hz: stable
* 500 Hz: stable, 17 M/s (nominal max trigger rate)
* 1000 Hz: stable, 32 M/s
* 3000 Hz: stable, 100 M/s (approaching saturation of 1gige ethernet)
* 3300 Hz: incomplete events, no ADC crash ("dropped due to full" counting, "dropped due to busy" are zero, this is as expected).

= Network connections =

The experiment private network number is: 192.168.1.x, gateway 192.168.1.1, netmask 255.255.255.0

network map:
<pre>
---- TRIUMF/CERN network --1gige-- alphagdaq --10gige-- juniper switch --1gige-- centrecom switch
</pre>

== alphagdaq network connections ==

on the rear of the machine:
<pre>
-----------------------------------------
| | rj45 | rj45 | | sfp | sfp |
-----------------------------------------

- left rj45 - copper 1gige - eno1 - spare (inactive)
- right rj45 - copper 1gige - eno2 - dhcp - cern/triumf network
- left sfp - 10gige - enp1s0f1 - spare (inactive)
- right sfp - 10gige - enp1s0f0 - static 192.168.1.1
</pre>

== connections between switches ==

* alphagdaq to juniper switch: direct attach (DAC) 10gige cable into any port of juniper switch
* juniper switch to centrecom switch: rj45 sfp in any port of juniper switch - cat5e/cat6 cable - to any port of centrecom switch
* cat5e/cat6 cable from any port of centrecom switch to the XXX port on the back of the juniper switch

== juniper switch ==

connected to juniper switch front is:

* everything that sends event data to alphagdaq, specifically:
** TRG (rj45 sfp)
** 16x ADC (fiber sfp)
** 64x PWB (fiber sfp)
* 10gige uplink to alphagdaq (10gige DAC cable)
* 1gige link to centrecom switch (rj45 sfp)
* 40gige ports are not used

connected to the juniper switch rear:

* CON is the serial console via RJ45-to-DB9 to USB-serial adapter to alphagdaq USB port (9600bps, 8N1, no flow control)
* C0 is the management ethernet interface port, connect to any port on the centrecom switch (juniper-private will ping)

== centrecom switch ==

* everything with copper rj45 connections, specifically:
** CDM boards
** HV, LV and VME power supplies
** RaspberryPi3 boards
** gas handling MFCs (algas)
** cooling system controller (moxa01)

= USB connections =

Note:
* alphagdaq has USB2 and USB3 connections. They are not the same, they are not generally interchangeable.
* USB3 connections and cables are generally blue coloured.

List of USB connections from alphagdaq:

* front USB3 port (blue): USB-A-to-B cable to USB blaster connected to the trigger board (front of rack)
* rear USB3 port (blue): USB3 short jumper to USB3 hub
* rear USB2 port (black): USB2 unpowered hub (Logiix) to USB-A-to-B cable to UPS USB connector
* rear USB2 port (black): USB-to-Serial adaper to DB9 to RJ45 adapter to Juniper switch console port

Note: UPS USB connection does not work with alphagdaq USB ports (both usb2 and usb3), but combination
using the unpowered USB2 hub seems to work ok.

List of USB connections from the USB hub:

* this is a powered USB3 hub
* USB-A-to-MicroUSB - to lvdb boards
* USB-A-to-Wiener interlock cable

= Clock and trigger distribution =

== Explanation ==

Trigger is generated by the trigger board (aka TRG, aka GRIF-C),
from the TRG eSATA output through the eSATA splitter it is fed into
the master CDM. The master CDM outputs the trigger on all MiniSAS output ports.
One of the master CDM MiniSAS outputs is connected to the CDM slave eSATA input.
The same as the master CDM, the slave CDM outputs the trigger on all MiniSAS output ports.

The master 62.5MHz clock is generated by the master CDM using the internal 10MHz oscillator
or the external 10MHz AD clock. Also on MiniSAS port 6 the master CDM generates
the 200MHz clock for the TDC. This clock is frequency-locked to the master 62.5MHz clock.

Master CDM clock selection (external CD 10MHz clock or internal oscillator 10MHz clock)
is done by a magic esper command (see below).

From the master CDM, the clock is fed to: the slave CDM, the TRG (via the eSATA splitter)
and to the TDC (via the RJ45 splitter).

The slave CDM sends the clock and the trigger to the ADCs and PWBs.

== Chronobox connections ==

Chronoboxes are synchronized with the daq using two signals: 10 MHz timestamp clock and TTL sync.

The sync signal used is the trigger signal - timestamps are reset by the 1st event - which is not a physics event, but the first trigger in the trigger sync sequence.

All chronoboxes are configured in "slave" and "chain" mode.

Slave mode: 10 MHz timestamp clock goes into the CLK_IN input (configured as NIM on the first chronobox and TTL on all others), sync signal goes into TTL input LEMO 4. (bank B direction set to "in").

Chain mode: 10 MHz timestamp clock is TTL output LEMO 0, sync is TTL output LEMO 1. (bank A direction set to "out"). These signals feed into CLK_IN (TTL mode) and TTL input LEMO 4 in the next chronobox in the chain.

The first chronobox receives the 10 MHz timestamp clock and sync signals from the master CDM per diagrams below.

* CDM 10 MHz clock output is NIM, feeds directly into the chronobox CLK_IN (NIM mode).
* CDM "trigger" ("sync") output is NIM, has to go through a NIM-to-TTL converter before feeding chronobox TTL input LEMO 4. I use a LeCroy 222 "gate and delay generator" module. NIM input goes into the "Start" input, TTL output is taken from the "TTL" output. Signal width is adjusted to around 100-1000 ns. Any other sutable NIM-to-TTL converter can also be used.
* "sync" output must be enabled in the master CDM:
<pre>
esper-tool cdm00
cd cdm
write multi_sync 2
</pre>

== Schematic ==

<pre>
TRG (GRIF-C)
------------
eSATA <------> eSATA splitter

eSATA splitter
--------------
trigger ---> eSATA ---> CDM-Master eSATA (trigger signal)
clock <--- (eSATA --- MiniSAS) <--- CDM MiniSAS (62.5MHz clock)
</pre>

<pre>
CDM-Master
----------
LEMO1B <----- 10 MHz AD clock (NIM)
LEMO2A --> (only if there is no external clock) 4ns lemo cable --> LEMO1B (62.5 MHz frequency monitor)
LEMO2B --> chronobox sync (NIM) --> NIM-to-TTL --> long lemo cable to chronobox sync input (TTL)
LEMO3B --> long lemo cable to chronobox clock input (NIM) (CLK_IN configured for NIM input)
eSATA <--- eSATA splitter <--- eSATA from TRG (trigger signal)
MiniSAS 1 --> (MiniSAS --- eSATA) --> CDM-Slave eSATA (62.5 MHz)
MiniSAS 6 --> (MiniSAS --- eSATA) --> eSATA splitter --> RJ45 --> TDC (200 MHz)
</pre>

<pre>
CDM-Slave
---------
LEMO2A --> 4ns lemo cable --> LEMO1B (62.5 MHz frequency monitor)
eSATA <--- trigger and 62.5MHz clock from CDM-Master
MiniSAS 1 --> ADC trigger and 62.5MHz clock
MiniSAS 2 --> same
MiniSAS 3 --> same
MiniSAS 4 --> same
MiniSAS 5 --> PWB trigger and 62.5MHz clock
MiniSAS 6 --> same
</pre>

[[File:VME_Crate_CERN.jpeg|800x450px|Layout of the VME crate at CERN.]]

Layout of the VME crate at CERN. The ALPHA-T module is in the rightmost slot. The Master CDM is next to it and it's labelled as #02. The Slave CDM is on the lefmost position and labelled by #03.

== Setup of CDM boards ==

ALPHA-g uses the Rev3 CDM boards. The 4 CDM boards that belong to ALPHA-g
have serial numbers 0, 1, 2 and 3 and are labeled cdm00, cdm01, cdm02, cdm03.

All the boards can be used as master and slave positions, but have to be
configured appropriately.

=== Slave setup ===

* install the board
* connect ethernet
* connect esata external clock
* esper-tool cdmNN ### i.e. esper-tool cdm01
* cd template
* write current_setup 4
* cd /cdm
* read
* observe clock frequency counters report correct values. "ext_clk" will only count if the lemo jumper is installed (see below)
<pre>
11 esata_clk uint32 R [62500246]
12 ext_clk uint32 R [62500246]
</pre>
* cd /lmk
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
156 ld1_counter uint32 RW [3]
157 ld2_counter uint32 RW [3]
</pre>

If needed, check correct operation of the pll lock monitoring:

* unplug the esata cable from the master CDM
* "red" light should go off
* read of lmk should report "pll1_ld" value 0 and "ld1_counter" and "ld2_counter" should increment
* reconnect the esata cable
* "red" light should return
* read of lmk should report both pll1_ld and pll2_ld locked (values "1").

=== Master setup ===

* install the board
* connect ethernet
* esper-tool cdmNN ### i.e. esper-tool cdm01
* cd template
* write current_setup 3
* cd /lmk
* write clkin_sel_mode 0
* cd /cdm
* read
* observe clock frequency counters report correct values. "ext_clk" will only count if the "clock loopback" lemo jumper is installed (see below)
<pre>
12 ext_clk uint32 R [62500189]
</pre>
* cd /lmk
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
156 ld1_counter uint32 RW [3]
157 ld2_counter uint32 RW [3]
</pre>

Check the 200MHz clock:
* connect MiniSAS-eSATA splitter cable to MiniSAS output 6, connect eSATA end to CDM eSATA input
* in esper-tool, read cdm: esata_clk should report 200MHz clock
<pre>
11 esata_clk uint32 R [200000603]
12 ext_clk uint32 R [62500188]
</pre>

=== Master setup with external 10 MHz clock ===

* setup master CDM as above (using internal clock)
* connect 10MHz external clock to LEMO1A
* esper-tool cdmNN
* cd /cdm
* write sel_nim 1 # if clock is NIM signal
* write sel_nim 0 # if clock is TTL signal (i.e. chronobox LEMO output)
* read ext_clk
<pre>
[http://cdm00:/cdm]> read ext_clk
9999556
</pre>
* if ext_clk reads 0 or does not read something close to 10MHz, stop here. debug the signal, try changing sel_nim, etc.
* cd /lmk
* write clkin_sel_mode 2 # select external clock
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
150 clkin2_sel bool R [True]
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
</pre>
* on the MIDAS TRG page, observe that TRG measured external clock frequency is close to 62.5 MHz

== clkin_sel_mode positions ==

* 0 = 10MHz internal oscillator (use on master CDM in standalone mode)
* 1 = eSATA clock (use on slave CDM)
* 2 = external clock, should be 10MHz (use on master CDM to run from AD clock)

== LEMO connections ==

LEMO connectors:

<pre>
|
|LEMO1A|LEMO1B
|LEMO2A|LEMO2B
|LEMO3A|LEMO3B
|eSATA
|RJ45 ETH
|minisas
|
</pre>

* clock loopback jumper: to read the frequency of the generated 62.5MHz clock, connect LEMO cable from LEMO2B to LEMO1A
* 10MHz internal clock jumper: to feed 10MHz internal oscillator to the external clock, connect LEMO cable from LEMO3A to the LEMO1A
* 10MHz external clock: to feed 10MHz external clock, connect LEMO cable to LEMO1A

= MIDAS frontends =

== UDP ==

feudp receives udp packets from the ADC and PWB boards. For each udp packet 1 midas event is created,
with 1 data bank containing the udp data. Events are sent into the MIDAS event buffer BUFUDP. The names
of the data banks are assigned in ODB /eq/feudp/settings.

{ADC,PWB} --> 1gige --> switch --> 10gige --> alphagdaq --> feudp -> BUFUDP

== CTRL ==

fectrl controls all the ADC, PWB and trigger boards. It provides run start and stop sequencing,
runs the event synchronization sequence at the begin of the run, and records slow controls data (temperatures,
voltages, etc).

fectrl receives UDP data packets from the trigger board and sends them to the MIDAS event buffer BUFUDP.

fectrl receives commands from the control web pages (for ADC, PWB and trigger) to reboot, initialize, etc the boards.

fectrl configures the event builder via odb /eq/fectrl/evbconfig.

ADC <-> http esper <-> fectrl -> slow control data into midas history

PWB <-> http esper <-> fectrl -> slow control data into midas history

TRG <-> udp comm <-> fectrl -> BUFUDP, slow control and counters into midas history

fectrl <-> midas rpc <-> mhttpd <-> json rpc <-> control web pages for ADC, PWB and trigger

== EVB ==

feevb receives udp packet data from the MIDAS event buffer BUFUDP, inspects the packet timestamps
and collects the data with matching timestamps into physics events. feevb has provisions to do
data suppression, reduction and compression in addition to the data reduction done
in the ADC and PWB firmware.

feevb event synchronization relies on the event synchronization sequence done by fectrl when a run is started.

{ADC, PWB, TRG} -> BUFUDP -> feevb -> SYSTEM -> mlogger -> compression -> disk storage

=== internal structure ===

* event buffer readers, instances for BUFTRG, BUFTDC, BUFADC, BUFUDP
<pre>
BufferReader class - reads one midas event buffer:
- BufferReaderThread()
-- in batches of 1000 events
--- lock
--- TickLocked()
----- ReadEvent() -> bm_receive_event_alloc()
----- fHandler->HandleEvent()
-- fHandler->XMaybeFlushBank()
-- sleep 100 usec
</pre>
* event header decoder and intermediate buffer
<pre>
Handler class - accumulates events, sends them to the EVB in batches

- HandleEvent() <- BufferReaderThread() - receive incoming events
-- loop over all banks, examine bank name
--- call AddAdcBank(), AddPwbBank(), AddTrgBank(), AddTdcBank() according to bank name
---- AddXxxBank() -> XAddBank()
--- unknown banks go directly to evb->SendQueue
-- check if synchronization has completed

- XAddBank() - save BankBuf objects in a buffer

- XMaybeFlushBank(), XFlushBank() - send all accumulated data to the Evb class
-- evb->lock()
-- for each buffered BankBuf objects,
--- call evb->AddBankLocked()
-- buffer is now empty
</pre>
* event builder
<pre>
Evb class - assemble event fragments according to timestamps

- fEvents fifo (deque) - time sorted list of partially assembled events
-- new entries are added by FindEvent()
-- entries are modified by MergeSlot()
-- old entries are removed by GetLocked()

- AddBankLocked() <- XFlushBank() <- BufferReaderThread()
-- call fSync->Add()
-- transform BankBuf to EvbEventBuf
-- push it into per-module buffer fBuf[imodule]

- EvbThread()
-- EvbTickLocked()
--- BuildLocked()
---- in a loop, for no more than 1 sec
----- loop over all per-module buffers fBuf
------ pop first entry, pass it to BuildSlot()
------- call FindEvent()
------- call MergeSlot()
------- call CheckEvent()
--- in a loop
---- get all completed events via GetLocked() pass them to SendQueue->PushEvent()
-- if done nothing, sleep 100 usec, otherwise nominal sleep to free the evb lock

- GetNext() <- GetLocked() <- EvbThread() - get completed events
-- examine oldest EvbEvent entry in fEvents:
-- pop it if it is complete
-- pop it if it is too old (to prevent old incomplete events from stalling the evb) ("pop age" on the evb page)
-- pop it if a following event is complete ("pop following" on the evb page)
</pre>
* send queue
<pre>
SendQueue class - prepare events for writing to midas SYSTEM event buffer

- PushEvent() <- EvbThread()
-- push FragmentBuf into the queue

- SendQueueThread()
-- in a batch of 1000 events, call Tick()
--- pop FragmentBuf from the queue, call SendEvent()
--- compose midas event (memcpy()!)
--- TMFE fEq->SendEvent()
--- bm_send_event()
-- sleep 100 usec
</pre>
* equipment object
<pre>
EvbEq class - implements the midas equipment
- HandleBeginRun()
- HandleEndRun()
- HandlePeriodic()
</pre>

=== multithreading ===

* BufferReaderThread() one per midas event buffer
** high CPU use: bm_receive_event(), AddXxxBank()
** lock contention: midas event buffer lock, evb lock into XFlushBank->AddBankLocked()
* EvbThread()
** O(size of fEvents): FindEvent(), GetNext()
** lock contention: evb lock against XFlushBank(), SendQueue lock (1 per output event)
* SendQueueThread()
** high CPU use: memcpy() in SendEvent(), memcpy() in bm_send_event
** lock contention: event queue lock against EvbThread, midas event buffer lock
* main thread
** lock contention: evb lock in ReportEvb() and elsewhere

= ODB entries =

== /Equipment/CTRL/Settings ==
* TBW

== /Equipment/CTRL/Settings/Pulser ==

* ClockFreqHz - unit of 1/sec (Hz), set to 62500000, the TRG 62.5 MHz clock frequency (16 ns)
* PulseWidthClk - unit of 16 ns clocks, set to 25. (400 ns). width of internal pulser signal (used to go to a TRG external output, absent on GRIF-C boards)
* PulsePeriodClk - unit of 16 ns clocks, pulser in clock periods (+1), set to zero.
* PulseFreqHz - unit of 1/sec (Hz), requested pulser frequency, actual frequency is rounded to 16 ns clock granularity, change this value to select desired clock frequency
* BurstCtrl - enable burst of pulses 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses
* OutputEnable - enable TRG pulser external output (absent on GRIF-C boards)
* Enable - allow the pulser to run (bit 3 in TRG conf_trig_enable register)

== /Equipment/CTRL/Settings/TrigSrc - trigger source selection ==
* TrigPulser - trigger on the pulser
* TrigEsataNimGrandOr - trigger on external NIM inputs of GRIF-16 ADC modules
* TrigAdc16GrandOr - trigger on any adc16 signals (see adc16_masks)
* TrigAdc32GrandOr - trigger on any adc32 signals (see adc32_masks)
* TrigAdcGrandOr - trigger on adc16_grand_or or adc32_grand_or
* (removed from trg firmware) Trig1ormore - trigger on adc16 multiplicity 1 or more
* (removed from trg firmware) Trig2ormore - ditto, 2 or more
* (removed from trg firmware) Trig3ormore - ditto, 3 or more
* (removed from trg firmware) Trig4ormore - ditto, 4 or more
* (removed from trg firmware) TrigAwCoincA - trigger on TPC AW coincidence (see [[TRG]] manual)
* (removed from trg firmware) TrigAwCoincB - ditto
* (removed from trg firmware) TrigAwCoincC - ditto
* (removed from trg firmware) TrigAwCoincD - ditto
* (removed from trg firmware) TrigAwCoinc - ditto
* (removed from trg firmware) TrigAw1ormore - trigger on TPC AW per-preamp multiplicity 1 or more (see [[TRG]] manual)
* (removed from trg firmware) TrigAw2ormore - ditto, 2 or more
* (removed from trg firmware) TrigAw3ormore - ditto, 3 or more
* (removed from trg firmware) TrigAw4ormore - ditto, 4 or more
* TrigAwMLU - trigger on TPC AW MLU signal (see [[TRG]] manual)
* TrigBscGrandOr - trigger on any BSC signal
* TrigBscMult - trigger on predefined BSC multiplicity (see [[TRG]] manual)
* TrigCoinc - trigger on predefined coincidence of TPC AW, BSC and external signal (see [[TRG]] manual)

== /Equipment/CTRL/Settings/TRG - trigger settings ==
* Enable - if set to "n", fectrl will not do anything with the trigger board. Normal value "y"
* Modules - hostnames of the trigger board. Normal value "alphat01"
* NimMask - 32-bit mask for the 32x NIM inputs (see TRG manual). Normal value 0, unless external trigger is in use.
* EsataMask - 32-bit mask for the 32x eSATA signals (see TRG manual). Normal value 0.
* adc16_mask[16] - 16x 16-bit mask for the 100MHz GRIF-16 onboard ADCs (see TRG manual). Normal value 0xFFFF for all 16 sas links.
* adc32_mask[16] - 16x 32-bit mask for the 62.5MHz FMC-ADC32 ADCs (see TRG manual). Normal value 0xFFFFFFFF for all 16 sas links.
* PassThrough - if set to "y", trigger is passed through the trigger module without generating any events and without causing deadtime.
* AwCoincA, B, C and D - 32-bit masks for the aw16 coincidence trigger (see TRG manual)
* Aw16FromAdc16 - route AW trigger (aw16) from adc16 (100MHz ADCs 0..15)
* Aw16FromAdc32a - route AW trigger (aw16) from adc32 group 15..0 (62.5MHz FMC-ADC32 minisas links 0..7)
* Aw16FromAdc32b - route AW trigger (aw16) from adc32 group 31..16 (62.5MHz FMC-ADC32 minisas links 8..15)
* MluDir, MluFiles - location of aw16 MLU bit patterns
* MluSelectedFile - currently selected/loaded MLU file. 0="grand or", 1="2 or more hit clusters", 2="2 or more hit clusters, with gap 2 or more", 3="3 or more hit clusters"
* MluPrompt - length of aw16_prompt_run gate in units of 8 ns clock, see [[TRG#aw16_mlu]]
* MluWait - length of aw_prompt_wait gate in units of 8 ns clock, see [[TRG#aw16_mlu]]
* MluTrigDelayClk - "TrigDelay" when triggered of aw16 MLU, in units of 16 ns clock
* (BSC settings, TBW)
* BscFromAdc16a - (at CERN, set to "y") route BSC trigger data (bsc64_bus) from 100 MHz adc16 digitizers minisas links 0..7
* BscFromAdc16b - route BSC trigger data (bsc64_bus) from 100 MHz adc16 digitizers minisas links 8..15
* BscBotOnly - route BSC trigger data from bottom ASD cards, bsc64_bus = bot
* BscTopOnly - route BSC trigger data from top ASD cards, bsc64_bus = top
* BscBotTopOr - (set to "y") use bsc64_bus = (top OR bottom)
* BscBotTopAnd - use bsc64_bus = (top AND bottom)
* BscMultiplicityMin - (set to 2) BSC multiplicity trigger - minimum multiplicity
* BscMultiplicityWindowClk8 - (set to 80) BSC multiplicity window, 8 ns clocks
* BscEmptyWindowClk8 - (set to 80) BSC empty window, 8 ns clocks, see [[TRG#bsc64_multiplicity_trigger]]
* BscGrandOrDelayClk16 - (not implemented) trigger delay used by fectrl when TrigSrc/TrigBscGrandOr is selected
* BscMultTrigDelayClk16 - trigger delay used by fectrl when TrigSrc/TrigBscMult is selected
* CoincStart - set same as CoincRequire
* CoincRequire - 0x5: (BSC grand or)*(TPC aw16_grand_or), 0x9: (BSC multiplicity)*(TWC aw16_grand_or), 0x6: (BSC grand or)*(AW16 MLU), see [[TRG#Coincidence_trigger]] and [[TRG#conf_coinc_control bits]]
* CoincWindow - length of coincidence window in 8ns clocks.
* CoincTrigDelayClk16 - trigger delay used by fectrl when TrigSrc/TrigCoinc is selected

== /Equipment/CTRL/Settings/PWB - PWB settings ==
* Enable - if set to "n", fectrl will not do anything with PWBs. Normal value "y".
* enable_boot_user_page - if set to "n", fectrl will not try to reboot PWBs into the user page firmware. Normal value "y".
* enable_trigger - if set to "n", all PWBs will be set to ignore the trigger. Normal value "y".
* enable_trigger_group_a - field wire pulser defeats the data suppression (every channel has a pulse) resulting in too much data overwhelming the DAQ (lost UDP packets). To permit correct data taking of field wire pulser data, PWBs are split into two groups (a and b), only one of the two groups should be enabled for field wire pulser runs. Both groups should be enabled for normal data taking. Normal value is "y"
* enable_trigger_group_b - see "enable_trigger_group_a". Normal value is "y".
* modules[64] - hostnames of PWB boards
* boot_user_page[64] - if set to "y" and enable_boot_user_page is "y", fectrl will reboot the corresponding PWB to the user page firmware.
* trigger[64] - if set to "y" and enable_trigget is "y", fectrl will set the PWB to accept the trigger.
* ch_enable - if set to "n" disables all PWB channels. Normal value is "y".
* ch_force - is set to "y" disables channel suppression (all PWB channels are read)
* suppress_reset - if set to "y" enables channel suppression for reset channels (threshold has to be set correctly)
* suppress_fpn - if set to "y" enables channel suppression for fpn channels (threshold has to be set correctly)
* suppress_pads - set to "y" enables channel suppression for TPC pad channels (threshold has to be set correctly)
* disable_reset1 - data suppression algorithm does not work for the channel "reset1" and it has to be suppressed explicitly by setting this value to "y". Normal value is "y".
* baseline_{reset,fpn,pads}[64] - waveform baseline for each PWB position
* threshold_{reset,fpn,pads} - waveform suppression threshold, see below:
* ch_threshold - PWB sca_N_ch_threshold, if set to 0, threshold is computed as "baseline_pads[seqpwb]-threshold_pads". Normal value is 0.
* test_mode - enable PWB test mode, the ADC data is replaced with a test pattern, see PWB esper variable signalproc/test_mode

== /Equipment/CTRL/Settings/TDC - TDC settings ==
* Enable - if set to "n", fectrl will tell the event builder that the TDC is not running. Normal value is "y".

== /Equipment/CTRL/Variables ==

* Scalers - TRG scalers and counters. from fectrl.cxx ReadTrgLocked()
<pre>
// 0..15 read the 16 base scalers at 0x100
// 16..31 read the adc16 scalers at 0x430
// 32..63 read the adc32 scalers at 0x440
// 64..79 read the 16 additional scalers at 0x110
// 80..95 read the 16 counters_adc_selected scalers at 0x460
// 96..159 read the 64 bar scalers at 0x470
// additional scalers should be appended at the end.
</pre>

== /Equipment/CTRL/EvbConfig - EVB configuration ==
All arrays have the same size corresponding to the number of EVB slots.
* name[] - slot name for the web page (trg01, adc01, adc01/adc32, pwb31/0, tdc01, etc)
* type[] - slot type: 1=TRG, 2=ADC16 and ADC32, 3=obsolete PWB, 4=obsolete PWB, 5=PWB, 6=TDC
* module[] - module number (adcNN, adcNN+100, pwbNN, etc)
* nbanks[] - number of expected banks (16 for ADC16, 32 for ADC32, not used, set to 1 for all others)
* tsfreq[] - timestamp frequency in Hz.

== /Equipment/ADC_UDP - ADC UDP configuration ==

* Common/Buffer - "BUFADC" - event buffer to use, name is hardwired in feevb.cxx
* Settings/udp_port - 50006 - UDP port number, also used by fectrl to configure the ADC modules
* Settings/rcv_bufsize - 209715200 - udp socket buffer size set by setsockopt(SOL_SOCKET, SO_RCVBUF). must have a corresponding command in /etc/rc.local to increase maximum system socket size: "/usr/sbin/sysctl -w net.core.rmem_max=200000000"
* Settings/packet_size - 1500 - non-jumbo-frame UDP packet maximum size
* Settings/max_buffered_packets - 40000 - maximum size of internal packet fifo. If it overflows, extra packets are discarded.
* Settings/max_packets_per_event - 8000 - how many UDP packets to pack into one midas event==

== /Equipment/PWB_X_UDP - PWB UDP configuration ==

For explanation see ADC_UDP above.

* Common/Buffer - "BUFUDP" - event buffer to use, name is hardwired in feevb.cxx
* Settings/udp_port - 50007, 50008, 50009, 50010 - for A, B, C and D UDP receivers respectively, also used by fectrl to configure the PWB modules
* Settings/rcv_bufsize - 209715200
* Settings/packet_size - 1500
* Settings/max_buffered_packets - 10000
* Settings/max_packets_per_event - 8000

= Trigger configuration =

These trigger modes are implemented:
* (manual trigger from web page)
* software pulser trigger (from fectrl)
* hardware pulser trigger (from the trigger board)
* NIM and eSATA trigger from ADC front panel inputs
* adc16 and adc32 discriminator triggers:
** adc16 grand-or trigger
** adc32 grand-or trigger
** adc (adc16+adc32) grand-or trigger
** adc16 multiplicity trigger (1ormore, 2ormore, 3ormore, 4ormore) for use with barrel scintillator
** anode wire multiplicity trigger (1ormore, 2ormore, 3ormore, 4ormore) (anode wire signals can be fed from adc16 or from adc32 signals)
** anode wire coincidence trigger
** anode wire MLU (memory lookup) trigger

== NIM trigger from ADC front panel ==

Trigger path:
<pre>
NIM signal --> LEMO input on ADC front panel --> data encoder --> data link to trigger board --> data decoder --> mask --> nim-esata-grand-or --> trigger
</pre>

To enable NIM trigger, do this:
* connect NIM signal to ADC front panel input
** Note1: NIM signal must be inverted
** Note2: LEMO connectors should be set to "NIM input" mode by ADC on-board jumpers (see ADC manual)
* observe correct bit goes to zero in the TRG web page: data link high work should change:
<pre>
0xNF00'0000 (N is the module id) to
0xN700'0000 (left lemo) or
0xNB00'0000 (right lemo)
</pre>
* Note3: if data link bits do not change, most likely the LEMO connectors are set to "DAC output" mode. Try to use LEMO inputs of a different ADC.
* compute the NIM mask: there are 32 bits, 2 bits per ADC data link. Bit 0x1 is right LEMO, bit 0x2 is left LEMO
* for example, to use left LEMO of ADC data link 12, set nim mask to (0x2)<<(2*12) = 0x02000000
* development branch of the git repository contains ''scripts/nim_mask.py'', which can compute forwards and backwards
* initialize the trigger board (on the TRG web page press button "initialize"), or start a new run
* on the history plot with "NIM grand or" counter, the rate should change from zero
* if a run is active, if one of the ADC LEMO outputs is set to output the trigger signal as a NIM pulse, one should see it fire use a scope. The delay or jitter between NIM trigger in and NIM trigger out should be around 100-200 ns (FIXME - measure this!)
* to set the DAQ to trigger on the NIM signal, on the run start page, check the box "TrigEsataNimGrandOr".
** Note: remember to set the scaledown to 0 if so desired.

= TPC field wire pulser =

The TPC field wire pulser input should be connected directly to the DAC output of ADC[0] (right lemo connector).

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for pulsing PWBs, baseline -1V, pulse height +2V (maximum possible pulse height in PWBs. Overdrives the AW ADC waveforms)
** dac_baseline: -8000
** dac_amplitude: 8000
** ramp_up_rate: 128
** ramp_down_rate: 70
** ramp_top_len: 128

* for pulsing AW, baseline -0.25V, pulse height +0.7V (AW ADC waveforms are in range. PWB waveforms are too small for goor time resolution)
** dac_baseline: -2000
** dac_amplitude: 4000
** ramp_up_rate: 20
** ramp_down_rate: 20
** ramp_top_len: 128

= BSC pulser =

The BSC pulser input on the BSC VME rear transition board (RTM) should be connected directly to the DAC output of ADC[4,5,6,7] (right lemo connector). (8 RTMs, but 4 ADCs, each signal is split using a LEMO "T" connector).

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for pulsing BSC, baseline -0.950V, pulse height +1.4V
** dac_baseline: -8000
** dac_amplitude: 4000
** ramp_up_rate: 64
** ramp_down_rate: 64
** ramp_top_len: 128

= NIM output =

To configure ADC analog output for NIM compatible pulse:

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for output of NIM pulse: baseline 0V, pulse height -0.9V, pulse width 100 ns
** dac_baseline: 0
** dac_amplitude: 8000
** ramp_up_rate: 128
** ramp_down_rate: 128
** ramp_top_len: 4
** dac_xor: 1 (invert the signal)

= TDC connections =

* SFP8 - fiber SFP to Juniper switch
* right RJ45 - 200MHz clock
* left RJ45 - external trigger

= MIDAS Data banks =

* ATAT - fectrl - UDP packets from GRIF-C/TRG trigger board
* TRBA - fetdc - TDC data
* TRTM - fetdc - TDC FPGA temperatures, TID_FLOAT[5].
* AAnn - feudp - UDP packets from GRIF-16 ADC (before the event builder), "nn" is the ADC module number: adc01 is AA01 through adc20 is AA20.
* BBxx - feudp - UDP packets from PWB, obsolete
* Bnnm, Cnnm - feevb - EVB output banks: ADC data, "nn" is the ADC module number (1..20), "m" is the channel number (0..9,A..F), format is same as AAnn banks.
* PAnn - feudp - UDP packets from PWB, "nn" is the PWB module number (00..99), obsolete
* PBnn - feudp - UDP packets from PWB, "nn" is the PWB module number (00..99), PB01 is pwb01, PB78 is pwb78
* PCnn - feevb - EVB output banks: PWB data, "nn" is the PWB module number (00..99), same as above, format is same as PBnn banks

= ZZZ =

ZZZ

Daq

2022-07-16T21:07:57Z

Olchansk: /* /Equipment/CTRL/Settings/TRG - trigger settings */

= Links =

* https://alphacpc05.cern.ch/agdaq/ -- midas daq page for the agdaq system at CERN
* https://daq16.triumf.ca -- midas daq page for the agmini system at TRIUMF
* https://daq.triumf.ca/elog-alphag/alphag/ -- elog
* https://daqstore.triumf.ca/AgWiki/index.php/Main_Page -- this wiki
* https://bitbucket.org/ttriumfdaq/agdaq - git repository for agdaq
* https://bitbucket.org/expalpha -- git repository on bitbucket
* https://edev-group.triumf.ca/fw/exp/alphag -- git repository on edev gitlab

= Inventory database =

* https://ladd00.triumf.ca/daqinv/frontend/list/170 - PWB inventory database
* https://ladd00.triumf.ca/daqinv/frontend/list/168 - ADC (GRIF-16) inventory, FMC-ADC32rev0,rev1 inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/176 - FMC-ADC32rev1.1 inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/174 - BSC RTM inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/173 - BSC ASD inventory

= Hardware manuals =

* [[TRG]] - trigger board (GRIF-C) manual
* CDM - https://daq.triumf.ca/DaqWiki/index.php/VME-CDM -- clock VME-CDM manual
* ADC - https://daq.triumf.ca/DaqWiki/index.php/VME-GRIF-ADC16-Rev1 -- GRIF-16 ADC manual
* [[PWB]] - TPC Pad Wing Board manual
* TDC - https://daq.triumf.ca/DaqWiki/index.php/GSI_TRB3
* [[chronobox]] - chronobox manual
* [[ASD]] - BSC preamp board
* [[RTM]] - BSC VME rear transition board

= Performance =

Full system: (ADC fw rel-20201112-ko, PWB fw 20201005_ko)
* 1 Hz stable, ADC adc32 9 supp off rate 0.3 M/s, adc16 off, PWB udp_delay 25 supp off active 64 rate 6.6+4+6+4.6=21.2 M/s, TDC off, total rate 21 M/s
* 500 Hz stable, ADC adc32 9 supp 1500 rate 6 M/s, adc16 off, PWB udp_delay 10 supp 100 active 63 rate 3+4+3+3=13 M/s, TDC off, total rate 19 M/s

Single ADC: (fw rel-20201112-ko)

Fully suppressed data, sthreshold 5000
* 1 Hz: stable
* 500 Hz: stable (nominal max trigger rate)
* 6700 Hz: stable, 8 Mbytes/sec
* 6800 Hz: evb eventually confused
* 6850 Hz: evb confused, no lost triggers in the ADC, no crash in the ADC

All data, 510 samples/event, sthreshold 10 (fw rel-20201122-ko)
* 1 Hz: stable
* 100 Hz: stable, 3.4 Mbytes/sec
* 500 Hz: stable, 17 Mbytes/sec (nominal max trigger rate)
* 1000 Hz: stable, 32 Mbytes/sec
* 3100 Hz: stable, 106 M/s (approaching saturation of 1gige ethernet)
* 3200 Hz: stable, 110 M/s - TRG communication is in trouble
* 3300 Hz: stable, 116 M/s
* 3400 Hz: incomplete events, no ADC crash ("dropped due to full" counting, "dropped due to busy" are zero, this is as expected).

no suppression (different fpga data path)
* 1 Hz: stable
* 100 Hz: stable
* 500 Hz: stable, 17 M/s (nominal max trigger rate)
* 1000 Hz: stable, 32 M/s
* 3000 Hz: stable, 100 M/s (approaching saturation of 1gige ethernet)
* 3300 Hz: incomplete events, no ADC crash ("dropped due to full" counting, "dropped due to busy" are zero, this is as expected).

= Network connections =

The experiment private network number is: 192.168.1.x, gateway 192.168.1.1, netmask 255.255.255.0

network map:
<pre>
---- TRIUMF/CERN network --1gige-- alphagdaq --10gige-- juniper switch --1gige-- centrecom switch
</pre>

== alphagdaq network connections ==

on the rear of the machine:
<pre>
-----------------------------------------
| | rj45 | rj45 | | sfp | sfp |
-----------------------------------------

- left rj45 - copper 1gige - eno1 - spare (inactive)
- right rj45 - copper 1gige - eno2 - dhcp - cern/triumf network
- left sfp - 10gige - enp1s0f1 - spare (inactive)
- right sfp - 10gige - enp1s0f0 - static 192.168.1.1
</pre>

== connections between switches ==

* alphagdaq to juniper switch: direct attach (DAC) 10gige cable into any port of juniper switch
* juniper switch to centrecom switch: rj45 sfp in any port of juniper switch - cat5e/cat6 cable - to any port of centrecom switch
* cat5e/cat6 cable from any port of centrecom switch to the XXX port on the back of the juniper switch

== juniper switch ==

connected to juniper switch front is:

* everything that sends event data to alphagdaq, specifically:
** TRG (rj45 sfp)
** 16x ADC (fiber sfp)
** 64x PWB (fiber sfp)
* 10gige uplink to alphagdaq (10gige DAC cable)
* 1gige link to centrecom switch (rj45 sfp)
* 40gige ports are not used

connected to the juniper switch rear:

* CON is the serial console via RJ45-to-DB9 to USB-serial adapter to alphagdaq USB port (9600bps, 8N1, no flow control)
* C0 is the management ethernet interface port, connect to any port on the centrecom switch (juniper-private will ping)

== centrecom switch ==

* everything with copper rj45 connections, specifically:
** CDM boards
** HV, LV and VME power supplies
** RaspberryPi3 boards
** gas handling MFCs (algas)
** cooling system controller (moxa01)

= USB connections =

Note:
* alphagdaq has USB2 and USB3 connections. They are not the same, they are not generally interchangeable.
* USB3 connections and cables are generally blue coloured.

List of USB connections from alphagdaq:

* front USB3 port (blue): USB-A-to-B cable to USB blaster connected to the trigger board (front of rack)
* rear USB3 port (blue): USB3 short jumper to USB3 hub
* rear USB2 port (black): USB2 unpowered hub (Logiix) to USB-A-to-B cable to UPS USB connector
* rear USB2 port (black): USB-to-Serial adaper to DB9 to RJ45 adapter to Juniper switch console port

Note: UPS USB connection does not work with alphagdaq USB ports (both usb2 and usb3), but combination
using the unpowered USB2 hub seems to work ok.

List of USB connections from the USB hub:

* this is a powered USB3 hub
* USB-A-to-MicroUSB - to lvdb boards
* USB-A-to-Wiener interlock cable

= Clock and trigger distribution =

== Explanation ==

Trigger is generated by the trigger board (aka TRG, aka GRIF-C),
from the TRG eSATA output through the eSATA splitter it is fed into
the master CDM. The master CDM outputs the trigger on all MiniSAS output ports.
One of the master CDM MiniSAS outputs is connected to the CDM slave eSATA input.
The same as the master CDM, the slave CDM outputs the trigger on all MiniSAS output ports.

The master 62.5MHz clock is generated by the master CDM using the internal 10MHz oscillator
or the external 10MHz AD clock. Also on MiniSAS port 6 the master CDM generates
the 200MHz clock for the TDC. This clock is frequency-locked to the master 62.5MHz clock.

Master CDM clock selection (external CD 10MHz clock or internal oscillator 10MHz clock)
is done by a magic esper command (see below).

From the master CDM, the clock is fed to: the slave CDM, the TRG (via the eSATA splitter)
and to the TDC (via the RJ45 splitter).

The slave CDM sends the clock and the trigger to the ADCs and PWBs.

== Chronobox connections ==

Chronoboxes are synchronized with the daq using two signals: 10 MHz timestamp clock and TTL sync.

The sync signal used is the trigger signal - timestamps are reset by the 1st event - which is not a physics event, but the first trigger in the trigger sync sequence.

All chronoboxes are configured in "slave" and "chain" mode.

Slave mode: 10 MHz timestamp clock goes into the CLK_IN input (configured as NIM on the first chronobox and TTL on all others), sync signal goes into TTL input LEMO 4. (bank B direction set to "in").

Chain mode: 10 MHz timestamp clock is TTL output LEMO 0, sync is TTL output LEMO 1. (bank A direction set to "out"). These signals feed into CLK_IN (TTL mode) and TTL input LEMO 4 in the next chronobox in the chain.

The first chronobox receives the 10 MHz timestamp clock and sync signals from the master CDM per diagrams below.

* CDM 10 MHz clock output is NIM, feeds directly into the chronobox CLK_IN (NIM mode).
* CDM "trigger" ("sync") output is NIM, has to go through a NIM-to-TTL converter before feeding chronobox TTL input LEMO 4. I use a LeCroy 222 "gate and delay generator" module. NIM input goes into the "Start" input, TTL output is taken from the "TTL" output. Signal width is adjusted to around 100-1000 ns. Any other sutable NIM-to-TTL converter can also be used.
* "sync" output must be enabled in the master CDM:
<pre>
esper-tool cdm00
cd cdm
write multi_sync 2
</pre>

== Schematic ==

<pre>
TRG (GRIF-C)
------------
eSATA <------> eSATA splitter

eSATA splitter
--------------
trigger ---> eSATA ---> CDM-Master eSATA (trigger signal)
clock <--- (eSATA --- MiniSAS) <--- CDM MiniSAS (62.5MHz clock)
</pre>

<pre>
CDM-Master
----------
LEMO1B <----- 10 MHz AD clock (NIM)
LEMO2A --> (only if there is no external clock) 4ns lemo cable --> LEMO1B (62.5 MHz frequency monitor)
LEMO2B --> chronobox sync (NIM) --> NIM-to-TTL --> long lemo cable to chronobox sync input (TTL)
LEMO3B --> long lemo cable to chronobox clock input (NIM) (CLK_IN configured for NIM input)
eSATA <--- eSATA splitter <--- eSATA from TRG (trigger signal)
MiniSAS 1 --> (MiniSAS --- eSATA) --> CDM-Slave eSATA (62.5 MHz)
MiniSAS 6 --> (MiniSAS --- eSATA) --> eSATA splitter --> RJ45 --> TDC (200 MHz)
</pre>

<pre>
CDM-Slave
---------
LEMO2A --> 4ns lemo cable --> LEMO1B (62.5 MHz frequency monitor)
eSATA <--- trigger and 62.5MHz clock from CDM-Master
MiniSAS 1 --> ADC trigger and 62.5MHz clock
MiniSAS 2 --> same
MiniSAS 3 --> same
MiniSAS 4 --> same
MiniSAS 5 --> PWB trigger and 62.5MHz clock
MiniSAS 6 --> same
</pre>

[[File:VME_Crate_CERN.jpeg|800x450px|Layout of the VME crate at CERN.]]

Layout of the VME crate at CERN. The ALPHA-T module is in the rightmost slot. The Master CDM is next to it and it's labelled as #02. The Slave CDM is on the lefmost position and labelled by #03.

== Setup of CDM boards ==

ALPHA-g uses the Rev3 CDM boards. The 4 CDM boards that belong to ALPHA-g
have serial numbers 0, 1, 2 and 3 and are labeled cdm00, cdm01, cdm02, cdm03.

All the boards can be used as master and slave positions, but have to be
configured appropriately.

=== Slave setup ===

* install the board
* connect ethernet
* connect esata external clock
* esper-tool cdmNN ### i.e. esper-tool cdm01
* cd template
* write current_setup 4
* cd /cdm
* read
* observe clock frequency counters report correct values. "ext_clk" will only count if the lemo jumper is installed (see below)
<pre>
11 esata_clk uint32 R [62500246]
12 ext_clk uint32 R [62500246]
</pre>
* cd /lmk
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
156 ld1_counter uint32 RW [3]
157 ld2_counter uint32 RW [3]
</pre>

If needed, check correct operation of the pll lock monitoring:

* unplug the esata cable from the master CDM
* "red" light should go off
* read of lmk should report "pll1_ld" value 0 and "ld1_counter" and "ld2_counter" should increment
* reconnect the esata cable
* "red" light should return
* read of lmk should report both pll1_ld and pll2_ld locked (values "1").

=== Master setup ===

* install the board
* connect ethernet
* esper-tool cdmNN ### i.e. esper-tool cdm01
* cd template
* write current_setup 3
* cd /lmk
* write clkin_sel_mode 0
* cd /cdm
* read
* observe clock frequency counters report correct values. "ext_clk" will only count if the "clock loopback" lemo jumper is installed (see below)
<pre>
12 ext_clk uint32 R [62500189]
</pre>
* cd /lmk
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
156 ld1_counter uint32 RW [3]
157 ld2_counter uint32 RW [3]
</pre>

Check the 200MHz clock:
* connect MiniSAS-eSATA splitter cable to MiniSAS output 6, connect eSATA end to CDM eSATA input
* in esper-tool, read cdm: esata_clk should report 200MHz clock
<pre>
11 esata_clk uint32 R [200000603]
12 ext_clk uint32 R [62500188]
</pre>

=== Master setup with external 10 MHz clock ===

* setup master CDM as above (using internal clock)
* connect 10MHz external clock to LEMO1A
* esper-tool cdmNN
* cd /cdm
* write sel_nim 1 # if clock is NIM signal
* write sel_nim 0 # if clock is TTL signal (i.e. chronobox LEMO output)
* read ext_clk
<pre>
[http://cdm00:/cdm]> read ext_clk
9999556
</pre>
* if ext_clk reads 0 or does not read something close to 10MHz, stop here. debug the signal, try changing sel_nim, etc.
* cd /lmk
* write clkin_sel_mode 2 # select external clock
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
150 clkin2_sel bool R [True]
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
</pre>
* on the MIDAS TRG page, observe that TRG measured external clock frequency is close to 62.5 MHz

== clkin_sel_mode positions ==

* 0 = 10MHz internal oscillator (use on master CDM in standalone mode)
* 1 = eSATA clock (use on slave CDM)
* 2 = external clock, should be 10MHz (use on master CDM to run from AD clock)

== LEMO connections ==

LEMO connectors:

<pre>
|
|LEMO1A|LEMO1B
|LEMO2A|LEMO2B
|LEMO3A|LEMO3B
|eSATA
|RJ45 ETH
|minisas
|
</pre>

* clock loopback jumper: to read the frequency of the generated 62.5MHz clock, connect LEMO cable from LEMO2B to LEMO1A
* 10MHz internal clock jumper: to feed 10MHz internal oscillator to the external clock, connect LEMO cable from LEMO3A to the LEMO1A
* 10MHz external clock: to feed 10MHz external clock, connect LEMO cable to LEMO1A

= MIDAS frontends =

== UDP ==

feudp receives udp packets from the ADC and PWB boards. For each udp packet 1 midas event is created,
with 1 data bank containing the udp data. Events are sent into the MIDAS event buffer BUFUDP. The names
of the data banks are assigned in ODB /eq/feudp/settings.

{ADC,PWB} --> 1gige --> switch --> 10gige --> alphagdaq --> feudp -> BUFUDP

== CTRL ==

fectrl controls all the ADC, PWB and trigger boards. It provides run start and stop sequencing,
runs the event synchronization sequence at the begin of the run, and records slow controls data (temperatures,
voltages, etc).

fectrl receives UDP data packets from the trigger board and sends them to the MIDAS event buffer BUFUDP.

fectrl receives commands from the control web pages (for ADC, PWB and trigger) to reboot, initialize, etc the boards.

fectrl configures the event builder via odb /eq/fectrl/evbconfig.

ADC <-> http esper <-> fectrl -> slow control data into midas history

PWB <-> http esper <-> fectrl -> slow control data into midas history

TRG <-> udp comm <-> fectrl -> BUFUDP, slow control and counters into midas history

fectrl <-> midas rpc <-> mhttpd <-> json rpc <-> control web pages for ADC, PWB and trigger

== EVB ==

feevb receives udp packet data from the MIDAS event buffer BUFUDP, inspects the packet timestamps
and collects the data with matching timestamps into physics events. feevb has provisions to do
data suppression, reduction and compression in addition to the data reduction done
in the ADC and PWB firmware.

feevb event synchronization relies on the event synchronization sequence done by fectrl when a run is started.

{ADC, PWB, TRG} -> BUFUDP -> feevb -> SYSTEM -> mlogger -> compression -> disk storage

=== internal structure ===

* event buffer readers, instances for BUFTRG, BUFTDC, BUFADC, BUFUDP
<pre>
BufferReader class - reads one midas event buffer:
- BufferReaderThread()
-- in batches of 1000 events
--- lock
--- TickLocked()
----- ReadEvent() -> bm_receive_event_alloc()
----- fHandler->HandleEvent()
-- fHandler->XMaybeFlushBank()
-- sleep 100 usec
</pre>
* event header decoder and intermediate buffer
<pre>
Handler class - accumulates events, sends them to the EVB in batches

- HandleEvent() <- BufferReaderThread() - receive incoming events
-- loop over all banks, examine bank name
--- call AddAdcBank(), AddPwbBank(), AddTrgBank(), AddTdcBank() according to bank name
---- AddXxxBank() -> XAddBank()
--- unknown banks go directly to evb->SendQueue
-- check if synchronization has completed

- XAddBank() - save BankBuf objects in a buffer

- XMaybeFlushBank(), XFlushBank() - send all accumulated data to the Evb class
-- evb->lock()
-- for each buffered BankBuf objects,
--- call evb->AddBankLocked()
-- buffer is now empty
</pre>
* event builder
<pre>
Evb class - assemble event fragments according to timestamps

- fEvents fifo (deque) - time sorted list of partially assembled events
-- new entries are added by FindEvent()
-- entries are modified by MergeSlot()
-- old entries are removed by GetLocked()

- AddBankLocked() <- XFlushBank() <- BufferReaderThread()
-- call fSync->Add()
-- transform BankBuf to EvbEventBuf
-- push it into per-module buffer fBuf[imodule]

- EvbThread()
-- EvbTickLocked()
--- BuildLocked()
---- in a loop, for no more than 1 sec
----- loop over all per-module buffers fBuf
------ pop first entry, pass it to BuildSlot()
------- call FindEvent()
------- call MergeSlot()
------- call CheckEvent()
--- in a loop
---- get all completed events via GetLocked() pass them to SendQueue->PushEvent()
-- if done nothing, sleep 100 usec, otherwise nominal sleep to free the evb lock

- GetNext() <- GetLocked() <- EvbThread() - get completed events
-- examine oldest EvbEvent entry in fEvents:
-- pop it if it is complete
-- pop it if it is too old (to prevent old incomplete events from stalling the evb) ("pop age" on the evb page)
-- pop it if a following event is complete ("pop following" on the evb page)
</pre>
* send queue
<pre>
SendQueue class - prepare events for writing to midas SYSTEM event buffer

- PushEvent() <- EvbThread()
-- push FragmentBuf into the queue

- SendQueueThread()
-- in a batch of 1000 events, call Tick()
--- pop FragmentBuf from the queue, call SendEvent()
--- compose midas event (memcpy()!)
--- TMFE fEq->SendEvent()
--- bm_send_event()
-- sleep 100 usec
</pre>
* equipment object
<pre>
EvbEq class - implements the midas equipment
- HandleBeginRun()
- HandleEndRun()
- HandlePeriodic()
</pre>

=== multithreading ===

* BufferReaderThread() one per midas event buffer
** high CPU use: bm_receive_event(), AddXxxBank()
** lock contention: midas event buffer lock, evb lock into XFlushBank->AddBankLocked()
* EvbThread()
** O(size of fEvents): FindEvent(), GetNext()
** lock contention: evb lock against XFlushBank(), SendQueue lock (1 per output event)
* SendQueueThread()
** high CPU use: memcpy() in SendEvent(), memcpy() in bm_send_event
** lock contention: event queue lock against EvbThread, midas event buffer lock
* main thread
** lock contention: evb lock in ReportEvb() and elsewhere

= ODB entries =

== /Equipment/CTRL/Settings ==
* TBW

== /Equipment/CTRL/Settings/Pulser ==

* ClockFreqHz - unit of 1/sec (Hz), set to 62500000, the TRG 62.5 MHz clock frequency (16 ns)
* PulseWidthClk - unit of 16 ns clocks, set to 25. (400 ns). width of internal pulser signal (used to go to a TRG external output, absent on GRIF-C boards)
* PulsePeriodClk - unit of 16 ns clocks, pulser in clock periods (+1), set to zero.
* PulseFreqHz - unit of 1/sec (Hz), requested pulser frequency, actual frequency is rounded to 16 ns clock granularity, change this value to select desired clock frequency
* BurstCtrl - enable burst of pulses 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses
* OutputEnable - enable TRG pulser external output (absent on GRIF-C boards)
* Enable - allow the pulser to run (bit 3 in TRG conf_trig_enable register)

== /Equipment/CTRL/Settings/TrigSrc - trigger source selection ==
* TrigPulser - trigger on the pulser
* TrigEsataNimGrandOr - trigger on external NIM inputs of GRIF-16 ADC modules
* TrigAdc16GrandOr - trigger on any adc16 signals (see adc16_masks)
* TrigAdc32GrandOr - trigger on any adc32 signals (see adc32_masks)
* TrigAdcGrandOr - trigger on adc16_grand_or or adc32_grand_or
* (removed from trg firmware) Trig1ormore - trigger on adc16 multiplicity 1 or more
* (removed from trg firmware) Trig2ormore - ditto, 2 or more
* (removed from trg firmware) Trig3ormore - ditto, 3 or more
* (removed from trg firmware) Trig4ormore - ditto, 4 or more
* (removed from trg firmware) TrigAwCoincA - trigger on TPC AW coincidence (see [[TRG]] manual)
* (removed from trg firmware) TrigAwCoincB - ditto
* (removed from trg firmware) TrigAwCoincC - ditto
* (removed from trg firmware) TrigAwCoincD - ditto
* (removed from trg firmware) TrigAwCoinc - ditto
* (removed from trg firmware) TrigAw1ormore - trigger on TPC AW per-preamp multiplicity 1 or more (see [[TRG]] manual)
* (removed from trg firmware) TrigAw2ormore - ditto, 2 or more
* (removed from trg firmware) TrigAw3ormore - ditto, 3 or more
* (removed from trg firmware) TrigAw4ormore - ditto, 4 or more
* TrigAwMLU - trigger on TPC AW MLU signal (see [[TRG]] manual)
* TrigBscGrandOr - trigger on any BSC signal
* TrigBscMult - trigger on predefined BSC multiplicity (see [[TRG]] manual)
* TrigCoinc - trigger on predefined coincidence of TPC AW, BSC and external signal (see [[TRG]] manual)

== /Equipment/CTRL/Settings/TRG - trigger settings ==
* Enable - if set to "n", fectrl will not do anything with the trigger board. Normal value "y"
* Modules - hostnames of the trigger board. Normal value "alphat01"
* NimMask - 32-bit mask for the 32x NIM inputs (see TRG manual). Normal value 0, unless external trigger is in use.
* EsataMask - 32-bit mask for the 32x eSATA signals (see TRG manual). Normal value 0.
* adc16_mask[16] - 16x 16-bit mask for the 100MHz GRIF-16 onboard ADCs (see TRG manual). Normal value 0xFFFF for all 16 sas links.
* adc32_mask[16] - 16x 32-bit mask for the 62.5MHz FMC-ADC32 ADCs (see TRG manual). Normal value 0xFFFFFFFF for all 16 sas links.
* PassThrough - if set to "y", trigger is passed through the trigger module without generating any events and without causing deadtime.
* AwCoincA, B, C and D - 32-bit masks for the aw16 coincidence trigger (see TRG manual)
* Aw16FromAdc16 - route AW trigger (aw16) from adc16 (100MHz ADCs 0..15)
* Aw16FromAdc32a - route AW trigger (aw16) from adc32 group 15..0 (62.5MHz FMC-ADC32 sas links 0..7)
* Aw16FromAdc32b - route AW trigger (aw16) from adc32 group 31..16 (62.5MHz FMC-ADC32 sas links 8..15)
* MluDir, MluFiles - location of aw16 MLU bit patterns
* MluSelectedFile - currently selected/loaded MLU file. 0="grand or", 1="2 or more hit clusters", 2="2 or more hit clusters, with gap 2 or more", 3="3 or more hit clusters"
* MluPrompt - length of aw16_prompt_run gate in units of 8 ns clock, see [[TRG#aw16_mlu]]
* MluWait - length of aw_prompt_wait gate in units of 8 ns clock, see [[TRG#aw16_mlu]]
* MluTrigDelayClk - "TrigDelay" when triggered of aw16 MLU, in units of 16 ns clock
* (BSC settings, TBW)
* BscFromAdc16a - route BSC trigger (bsc64_bus) from 100 MHz adc16 digitizers sas links 0..7
* BscFromAdc16b - route BSC trigger (bsc64_bus) from 100 MHz adc16 digitizers sas links 8..15
* BscBotOnly
* BscTopOnly
* BscBotTopOr
* BscBotTopAnd
* BscMultiplicityMin
* BscMultiplicityWindowClk8
* BscEmptyWindowClk8
* BscMultTrigDelayClk16
* CoincStart - set same as CoincRequire
* CoincRequire - 0x5: (BSC grand or)*(TPC aw16_1ormore), 0x6: (BSC grand or)*(AW16 MLU), see [[TRG#Coincidence_trigger]] and [[TRG#conf_coinc_control bits]]
* CoincWindow - length of coincidence window in 8ns clocks.
* CoincTrigDelayClk16

== /Equipment/CTRL/Settings/PWB - PWB settings ==
* Enable - if set to "n", fectrl will not do anything with PWBs. Normal value "y".
* enable_boot_user_page - if set to "n", fectrl will not try to reboot PWBs into the user page firmware. Normal value "y".
* enable_trigger - if set to "n", all PWBs will be set to ignore the trigger. Normal value "y".
* enable_trigger_group_a - field wire pulser defeats the data suppression (every channel has a pulse) resulting in too much data overwhelming the DAQ (lost UDP packets). To permit correct data taking of field wire pulser data, PWBs are split into two groups (a and b), only one of the two groups should be enabled for field wire pulser runs. Both groups should be enabled for normal data taking. Normal value is "y"
* enable_trigger_group_b - see "enable_trigger_group_a". Normal value is "y".
* modules[64] - hostnames of PWB boards
* boot_user_page[64] - if set to "y" and enable_boot_user_page is "y", fectrl will reboot the corresponding PWB to the user page firmware.
* trigger[64] - if set to "y" and enable_trigget is "y", fectrl will set the PWB to accept the trigger.
* ch_enable - if set to "n" disables all PWB channels. Normal value is "y".
* ch_force - is set to "y" disables channel suppression (all PWB channels are read)
* suppress_reset - if set to "y" enables channel suppression for reset channels (threshold has to be set correctly)
* suppress_fpn - if set to "y" enables channel suppression for fpn channels (threshold has to be set correctly)
* suppress_pads - set to "y" enables channel suppression for TPC pad channels (threshold has to be set correctly)
* disable_reset1 - data suppression algorithm does not work for the channel "reset1" and it has to be suppressed explicitly by setting this value to "y". Normal value is "y".
* baseline_{reset,fpn,pads}[64] - waveform baseline for each PWB position
* threshold_{reset,fpn,pads} - waveform suppression threshold, see below:
* ch_threshold - PWB sca_N_ch_threshold, if set to 0, threshold is computed as "baseline_pads[seqpwb]-threshold_pads". Normal value is 0.
* test_mode - enable PWB test mode, the ADC data is replaced with a test pattern, see PWB esper variable signalproc/test_mode

== /Equipment/CTRL/Settings/TDC - TDC settings ==
* Enable - if set to "n", fectrl will tell the event builder that the TDC is not running. Normal value is "y".

== /Equipment/CTRL/Variables ==

* Scalers - TRG scalers and counters. from fectrl.cxx ReadTrgLocked()
<pre>
// 0..15 read the 16 base scalers at 0x100
// 16..31 read the adc16 scalers at 0x430
// 32..63 read the adc32 scalers at 0x440
// 64..79 read the 16 additional scalers at 0x110
// 80..95 read the 16 counters_adc_selected scalers at 0x460
// 96..159 read the 64 bar scalers at 0x470
// additional scalers should be appended at the end.
</pre>

== /Equipment/CTRL/EvbConfig - EVB configuration ==
All arrays have the same size corresponding to the number of EVB slots.
* name[] - slot name for the web page (trg01, adc01, adc01/adc32, pwb31/0, tdc01, etc)
* type[] - slot type: 1=TRG, 2=ADC16 and ADC32, 3=obsolete PWB, 4=obsolete PWB, 5=PWB, 6=TDC
* module[] - module number (adcNN, adcNN+100, pwbNN, etc)
* nbanks[] - number of expected banks (16 for ADC16, 32 for ADC32, not used, set to 1 for all others)
* tsfreq[] - timestamp frequency in Hz.

== /Equipment/ADC_UDP - ADC UDP configuration ==

* Common/Buffer - "BUFADC" - event buffer to use, name is hardwired in feevb.cxx
* Settings/udp_port - 50006 - UDP port number, also used by fectrl to configure the ADC modules
* Settings/rcv_bufsize - 209715200 - udp socket buffer size set by setsockopt(SOL_SOCKET, SO_RCVBUF). must have a corresponding command in /etc/rc.local to increase maximum system socket size: "/usr/sbin/sysctl -w net.core.rmem_max=200000000"
* Settings/packet_size - 1500 - non-jumbo-frame UDP packet maximum size
* Settings/max_buffered_packets - 40000 - maximum size of internal packet fifo. If it overflows, extra packets are discarded.
* Settings/max_packets_per_event - 8000 - how many UDP packets to pack into one midas event==

== /Equipment/PWB_X_UDP - PWB UDP configuration ==

For explanation see ADC_UDP above.

* Common/Buffer - "BUFUDP" - event buffer to use, name is hardwired in feevb.cxx
* Settings/udp_port - 50007, 50008, 50009, 50010 - for A, B, C and D UDP receivers respectively, also used by fectrl to configure the PWB modules
* Settings/rcv_bufsize - 209715200
* Settings/packet_size - 1500
* Settings/max_buffered_packets - 10000
* Settings/max_packets_per_event - 8000

= Trigger configuration =

These trigger modes are implemented:
* (manual trigger from web page)
* software pulser trigger (from fectrl)
* hardware pulser trigger (from the trigger board)
* NIM and eSATA trigger from ADC front panel inputs
* adc16 and adc32 discriminator triggers:
** adc16 grand-or trigger
** adc32 grand-or trigger
** adc (adc16+adc32) grand-or trigger
** adc16 multiplicity trigger (1ormore, 2ormore, 3ormore, 4ormore) for use with barrel scintillator
** anode wire multiplicity trigger (1ormore, 2ormore, 3ormore, 4ormore) (anode wire signals can be fed from adc16 or from adc32 signals)
** anode wire coincidence trigger
** anode wire MLU (memory lookup) trigger

== NIM trigger from ADC front panel ==

Trigger path:
<pre>
NIM signal --> LEMO input on ADC front panel --> data encoder --> data link to trigger board --> data decoder --> mask --> nim-esata-grand-or --> trigger
</pre>

To enable NIM trigger, do this:
* connect NIM signal to ADC front panel input
** Note1: NIM signal must be inverted
** Note2: LEMO connectors should be set to "NIM input" mode by ADC on-board jumpers (see ADC manual)
* observe correct bit goes to zero in the TRG web page: data link high work should change:
<pre>
0xNF00'0000 (N is the module id) to
0xN700'0000 (left lemo) or
0xNB00'0000 (right lemo)
</pre>
* Note3: if data link bits do not change, most likely the LEMO connectors are set to "DAC output" mode. Try to use LEMO inputs of a different ADC.
* compute the NIM mask: there are 32 bits, 2 bits per ADC data link. Bit 0x1 is right LEMO, bit 0x2 is left LEMO
* for example, to use left LEMO of ADC data link 12, set nim mask to (0x2)<<(2*12) = 0x02000000
* development branch of the git repository contains ''scripts/nim_mask.py'', which can compute forwards and backwards
* initialize the trigger board (on the TRG web page press button "initialize"), or start a new run
* on the history plot with "NIM grand or" counter, the rate should change from zero
* if a run is active, if one of the ADC LEMO outputs is set to output the trigger signal as a NIM pulse, one should see it fire use a scope. The delay or jitter between NIM trigger in and NIM trigger out should be around 100-200 ns (FIXME - measure this!)
* to set the DAQ to trigger on the NIM signal, on the run start page, check the box "TrigEsataNimGrandOr".
** Note: remember to set the scaledown to 0 if so desired.

= TPC field wire pulser =

The TPC field wire pulser input should be connected directly to the DAC output of ADC[0] (right lemo connector).

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for pulsing PWBs, baseline -1V, pulse height +2V (maximum possible pulse height in PWBs. Overdrives the AW ADC waveforms)
** dac_baseline: -8000
** dac_amplitude: 8000
** ramp_up_rate: 128
** ramp_down_rate: 70
** ramp_top_len: 128

* for pulsing AW, baseline -0.25V, pulse height +0.7V (AW ADC waveforms are in range. PWB waveforms are too small for goor time resolution)
** dac_baseline: -2000
** dac_amplitude: 4000
** ramp_up_rate: 20
** ramp_down_rate: 20
** ramp_top_len: 128

= BSC pulser =

The BSC pulser input on the BSC VME rear transition board (RTM) should be connected directly to the DAC output of ADC[4,5,6,7] (right lemo connector). (8 RTMs, but 4 ADCs, each signal is split using a LEMO "T" connector).

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for pulsing BSC, baseline -0.950V, pulse height +1.4V
** dac_baseline: -8000
** dac_amplitude: 4000
** ramp_up_rate: 64
** ramp_down_rate: 64
** ramp_top_len: 128

= NIM output =

To configure ADC analog output for NIM compatible pulse:

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for output of NIM pulse: baseline 0V, pulse height -0.9V, pulse width 100 ns
** dac_baseline: 0
** dac_amplitude: 8000
** ramp_up_rate: 128
** ramp_down_rate: 128
** ramp_top_len: 4
** dac_xor: 1 (invert the signal)

= TDC connections =

* SFP8 - fiber SFP to Juniper switch
* right RJ45 - 200MHz clock
* left RJ45 - external trigger

= MIDAS Data banks =

* ATAT - fectrl - UDP packets from GRIF-C/TRG trigger board
* TRBA - fetdc - TDC data
* TRTM - fetdc - TDC FPGA temperatures, TID_FLOAT[5].
* AAnn - feudp - UDP packets from GRIF-16 ADC (before the event builder), "nn" is the ADC module number: adc01 is AA01 through adc20 is AA20.
* BBxx - feudp - UDP packets from PWB, obsolete
* Bnnm, Cnnm - feevb - EVB output banks: ADC data, "nn" is the ADC module number (1..20), "m" is the channel number (0..9,A..F), format is same as AAnn banks.
* PAnn - feudp - UDP packets from PWB, "nn" is the PWB module number (00..99), obsolete
* PBnn - feudp - UDP packets from PWB, "nn" is the PWB module number (00..99), PB01 is pwb01, PB78 is pwb78
* PCnn - feevb - EVB output banks: PWB data, "nn" is the PWB module number (00..99), same as above, format is same as PBnn banks

= ZZZ =

ZZZ

Daq

2022-07-16T21:03:54Z

Olchansk: /* /Equipment/CTRL/Settings/TRG - trigger settings */

= Links =

* https://alphacpc05.cern.ch/agdaq/ -- midas daq page for the agdaq system at CERN
* https://daq16.triumf.ca -- midas daq page for the agmini system at TRIUMF
* https://daq.triumf.ca/elog-alphag/alphag/ -- elog
* https://daqstore.triumf.ca/AgWiki/index.php/Main_Page -- this wiki
* https://bitbucket.org/ttriumfdaq/agdaq - git repository for agdaq
* https://bitbucket.org/expalpha -- git repository on bitbucket
* https://edev-group.triumf.ca/fw/exp/alphag -- git repository on edev gitlab

= Inventory database =

* https://ladd00.triumf.ca/daqinv/frontend/list/170 - PWB inventory database
* https://ladd00.triumf.ca/daqinv/frontend/list/168 - ADC (GRIF-16) inventory, FMC-ADC32rev0,rev1 inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/176 - FMC-ADC32rev1.1 inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/174 - BSC RTM inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/173 - BSC ASD inventory

= Hardware manuals =

* [[TRG]] - trigger board (GRIF-C) manual
* CDM - https://daq.triumf.ca/DaqWiki/index.php/VME-CDM -- clock VME-CDM manual
* ADC - https://daq.triumf.ca/DaqWiki/index.php/VME-GRIF-ADC16-Rev1 -- GRIF-16 ADC manual
* [[PWB]] - TPC Pad Wing Board manual
* TDC - https://daq.triumf.ca/DaqWiki/index.php/GSI_TRB3
* [[chronobox]] - chronobox manual
* [[ASD]] - BSC preamp board
* [[RTM]] - BSC VME rear transition board

= Performance =

Full system: (ADC fw rel-20201112-ko, PWB fw 20201005_ko)
* 1 Hz stable, ADC adc32 9 supp off rate 0.3 M/s, adc16 off, PWB udp_delay 25 supp off active 64 rate 6.6+4+6+4.6=21.2 M/s, TDC off, total rate 21 M/s
* 500 Hz stable, ADC adc32 9 supp 1500 rate 6 M/s, adc16 off, PWB udp_delay 10 supp 100 active 63 rate 3+4+3+3=13 M/s, TDC off, total rate 19 M/s

Single ADC: (fw rel-20201112-ko)

Fully suppressed data, sthreshold 5000
* 1 Hz: stable
* 500 Hz: stable (nominal max trigger rate)
* 6700 Hz: stable, 8 Mbytes/sec
* 6800 Hz: evb eventually confused
* 6850 Hz: evb confused, no lost triggers in the ADC, no crash in the ADC

All data, 510 samples/event, sthreshold 10 (fw rel-20201122-ko)
* 1 Hz: stable
* 100 Hz: stable, 3.4 Mbytes/sec
* 500 Hz: stable, 17 Mbytes/sec (nominal max trigger rate)
* 1000 Hz: stable, 32 Mbytes/sec
* 3100 Hz: stable, 106 M/s (approaching saturation of 1gige ethernet)
* 3200 Hz: stable, 110 M/s - TRG communication is in trouble
* 3300 Hz: stable, 116 M/s
* 3400 Hz: incomplete events, no ADC crash ("dropped due to full" counting, "dropped due to busy" are zero, this is as expected).

no suppression (different fpga data path)
* 1 Hz: stable
* 100 Hz: stable
* 500 Hz: stable, 17 M/s (nominal max trigger rate)
* 1000 Hz: stable, 32 M/s
* 3000 Hz: stable, 100 M/s (approaching saturation of 1gige ethernet)
* 3300 Hz: incomplete events, no ADC crash ("dropped due to full" counting, "dropped due to busy" are zero, this is as expected).

= Network connections =

The experiment private network number is: 192.168.1.x, gateway 192.168.1.1, netmask 255.255.255.0

network map:
<pre>
---- TRIUMF/CERN network --1gige-- alphagdaq --10gige-- juniper switch --1gige-- centrecom switch
</pre>

== alphagdaq network connections ==

on the rear of the machine:
<pre>
-----------------------------------------
| | rj45 | rj45 | | sfp | sfp |
-----------------------------------------

- left rj45 - copper 1gige - eno1 - spare (inactive)
- right rj45 - copper 1gige - eno2 - dhcp - cern/triumf network
- left sfp - 10gige - enp1s0f1 - spare (inactive)
- right sfp - 10gige - enp1s0f0 - static 192.168.1.1
</pre>

== connections between switches ==

* alphagdaq to juniper switch: direct attach (DAC) 10gige cable into any port of juniper switch
* juniper switch to centrecom switch: rj45 sfp in any port of juniper switch - cat5e/cat6 cable - to any port of centrecom switch
* cat5e/cat6 cable from any port of centrecom switch to the XXX port on the back of the juniper switch

== juniper switch ==

connected to juniper switch front is:

* everything that sends event data to alphagdaq, specifically:
** TRG (rj45 sfp)
** 16x ADC (fiber sfp)
** 64x PWB (fiber sfp)
* 10gige uplink to alphagdaq (10gige DAC cable)
* 1gige link to centrecom switch (rj45 sfp)
* 40gige ports are not used

connected to the juniper switch rear:

* CON is the serial console via RJ45-to-DB9 to USB-serial adapter to alphagdaq USB port (9600bps, 8N1, no flow control)
* C0 is the management ethernet interface port, connect to any port on the centrecom switch (juniper-private will ping)

== centrecom switch ==

* everything with copper rj45 connections, specifically:
** CDM boards
** HV, LV and VME power supplies
** RaspberryPi3 boards
** gas handling MFCs (algas)
** cooling system controller (moxa01)

= USB connections =

Note:
* alphagdaq has USB2 and USB3 connections. They are not the same, they are not generally interchangeable.
* USB3 connections and cables are generally blue coloured.

List of USB connections from alphagdaq:

* front USB3 port (blue): USB-A-to-B cable to USB blaster connected to the trigger board (front of rack)
* rear USB3 port (blue): USB3 short jumper to USB3 hub
* rear USB2 port (black): USB2 unpowered hub (Logiix) to USB-A-to-B cable to UPS USB connector
* rear USB2 port (black): USB-to-Serial adaper to DB9 to RJ45 adapter to Juniper switch console port

Note: UPS USB connection does not work with alphagdaq USB ports (both usb2 and usb3), but combination
using the unpowered USB2 hub seems to work ok.

List of USB connections from the USB hub:

* this is a powered USB3 hub
* USB-A-to-MicroUSB - to lvdb boards
* USB-A-to-Wiener interlock cable

= Clock and trigger distribution =

== Explanation ==

Trigger is generated by the trigger board (aka TRG, aka GRIF-C),
from the TRG eSATA output through the eSATA splitter it is fed into
the master CDM. The master CDM outputs the trigger on all MiniSAS output ports.
One of the master CDM MiniSAS outputs is connected to the CDM slave eSATA input.
The same as the master CDM, the slave CDM outputs the trigger on all MiniSAS output ports.

The master 62.5MHz clock is generated by the master CDM using the internal 10MHz oscillator
or the external 10MHz AD clock. Also on MiniSAS port 6 the master CDM generates
the 200MHz clock for the TDC. This clock is frequency-locked to the master 62.5MHz clock.

Master CDM clock selection (external CD 10MHz clock or internal oscillator 10MHz clock)
is done by a magic esper command (see below).

From the master CDM, the clock is fed to: the slave CDM, the TRG (via the eSATA splitter)
and to the TDC (via the RJ45 splitter).

The slave CDM sends the clock and the trigger to the ADCs and PWBs.

== Chronobox connections ==

Chronoboxes are synchronized with the daq using two signals: 10 MHz timestamp clock and TTL sync.

The sync signal used is the trigger signal - timestamps are reset by the 1st event - which is not a physics event, but the first trigger in the trigger sync sequence.

All chronoboxes are configured in "slave" and "chain" mode.

Slave mode: 10 MHz timestamp clock goes into the CLK_IN input (configured as NIM on the first chronobox and TTL on all others), sync signal goes into TTL input LEMO 4. (bank B direction set to "in").

Chain mode: 10 MHz timestamp clock is TTL output LEMO 0, sync is TTL output LEMO 1. (bank A direction set to "out"). These signals feed into CLK_IN (TTL mode) and TTL input LEMO 4 in the next chronobox in the chain.

The first chronobox receives the 10 MHz timestamp clock and sync signals from the master CDM per diagrams below.

* CDM 10 MHz clock output is NIM, feeds directly into the chronobox CLK_IN (NIM mode).
* CDM "trigger" ("sync") output is NIM, has to go through a NIM-to-TTL converter before feeding chronobox TTL input LEMO 4. I use a LeCroy 222 "gate and delay generator" module. NIM input goes into the "Start" input, TTL output is taken from the "TTL" output. Signal width is adjusted to around 100-1000 ns. Any other sutable NIM-to-TTL converter can also be used.
* "sync" output must be enabled in the master CDM:
<pre>
esper-tool cdm00
cd cdm
write multi_sync 2
</pre>

== Schematic ==

<pre>
TRG (GRIF-C)
------------
eSATA <------> eSATA splitter

eSATA splitter
--------------
trigger ---> eSATA ---> CDM-Master eSATA (trigger signal)
clock <--- (eSATA --- MiniSAS) <--- CDM MiniSAS (62.5MHz clock)
</pre>

<pre>
CDM-Master
----------
LEMO1B <----- 10 MHz AD clock (NIM)
LEMO2A --> (only if there is no external clock) 4ns lemo cable --> LEMO1B (62.5 MHz frequency monitor)
LEMO2B --> chronobox sync (NIM) --> NIM-to-TTL --> long lemo cable to chronobox sync input (TTL)
LEMO3B --> long lemo cable to chronobox clock input (NIM) (CLK_IN configured for NIM input)
eSATA <--- eSATA splitter <--- eSATA from TRG (trigger signal)
MiniSAS 1 --> (MiniSAS --- eSATA) --> CDM-Slave eSATA (62.5 MHz)
MiniSAS 6 --> (MiniSAS --- eSATA) --> eSATA splitter --> RJ45 --> TDC (200 MHz)
</pre>

<pre>
CDM-Slave
---------
LEMO2A --> 4ns lemo cable --> LEMO1B (62.5 MHz frequency monitor)
eSATA <--- trigger and 62.5MHz clock from CDM-Master
MiniSAS 1 --> ADC trigger and 62.5MHz clock
MiniSAS 2 --> same
MiniSAS 3 --> same
MiniSAS 4 --> same
MiniSAS 5 --> PWB trigger and 62.5MHz clock
MiniSAS 6 --> same
</pre>

[[File:VME_Crate_CERN.jpeg|800x450px|Layout of the VME crate at CERN.]]

Layout of the VME crate at CERN. The ALPHA-T module is in the rightmost slot. The Master CDM is next to it and it's labelled as #02. The Slave CDM is on the lefmost position and labelled by #03.

== Setup of CDM boards ==

ALPHA-g uses the Rev3 CDM boards. The 4 CDM boards that belong to ALPHA-g
have serial numbers 0, 1, 2 and 3 and are labeled cdm00, cdm01, cdm02, cdm03.

All the boards can be used as master and slave positions, but have to be
configured appropriately.

=== Slave setup ===

* install the board
* connect ethernet
* connect esata external clock
* esper-tool cdmNN ### i.e. esper-tool cdm01
* cd template
* write current_setup 4
* cd /cdm
* read
* observe clock frequency counters report correct values. "ext_clk" will only count if the lemo jumper is installed (see below)
<pre>
11 esata_clk uint32 R [62500246]
12 ext_clk uint32 R [62500246]
</pre>
* cd /lmk
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
156 ld1_counter uint32 RW [3]
157 ld2_counter uint32 RW [3]
</pre>

If needed, check correct operation of the pll lock monitoring:

* unplug the esata cable from the master CDM
* "red" light should go off
* read of lmk should report "pll1_ld" value 0 and "ld1_counter" and "ld2_counter" should increment
* reconnect the esata cable
* "red" light should return
* read of lmk should report both pll1_ld and pll2_ld locked (values "1").

=== Master setup ===

* install the board
* connect ethernet
* esper-tool cdmNN ### i.e. esper-tool cdm01
* cd template
* write current_setup 3
* cd /lmk
* write clkin_sel_mode 0
* cd /cdm
* read
* observe clock frequency counters report correct values. "ext_clk" will only count if the "clock loopback" lemo jumper is installed (see below)
<pre>
12 ext_clk uint32 R [62500189]
</pre>
* cd /lmk
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
156 ld1_counter uint32 RW [3]
157 ld2_counter uint32 RW [3]
</pre>

Check the 200MHz clock:
* connect MiniSAS-eSATA splitter cable to MiniSAS output 6, connect eSATA end to CDM eSATA input
* in esper-tool, read cdm: esata_clk should report 200MHz clock
<pre>
11 esata_clk uint32 R [200000603]
12 ext_clk uint32 R [62500188]
</pre>

=== Master setup with external 10 MHz clock ===

* setup master CDM as above (using internal clock)
* connect 10MHz external clock to LEMO1A
* esper-tool cdmNN
* cd /cdm
* write sel_nim 1 # if clock is NIM signal
* write sel_nim 0 # if clock is TTL signal (i.e. chronobox LEMO output)
* read ext_clk
<pre>
[http://cdm00:/cdm]> read ext_clk
9999556
</pre>
* if ext_clk reads 0 or does not read something close to 10MHz, stop here. debug the signal, try changing sel_nim, etc.
* cd /lmk
* write clkin_sel_mode 2 # select external clock
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
150 clkin2_sel bool R [True]
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
</pre>
* on the MIDAS TRG page, observe that TRG measured external clock frequency is close to 62.5 MHz

== clkin_sel_mode positions ==

* 0 = 10MHz internal oscillator (use on master CDM in standalone mode)
* 1 = eSATA clock (use on slave CDM)
* 2 = external clock, should be 10MHz (use on master CDM to run from AD clock)

== LEMO connections ==

LEMO connectors:

<pre>
|
|LEMO1A|LEMO1B
|LEMO2A|LEMO2B
|LEMO3A|LEMO3B
|eSATA
|RJ45 ETH
|minisas
|
</pre>

* clock loopback jumper: to read the frequency of the generated 62.5MHz clock, connect LEMO cable from LEMO2B to LEMO1A
* 10MHz internal clock jumper: to feed 10MHz internal oscillator to the external clock, connect LEMO cable from LEMO3A to the LEMO1A
* 10MHz external clock: to feed 10MHz external clock, connect LEMO cable to LEMO1A

= MIDAS frontends =

== UDP ==

feudp receives udp packets from the ADC and PWB boards. For each udp packet 1 midas event is created,
with 1 data bank containing the udp data. Events are sent into the MIDAS event buffer BUFUDP. The names
of the data banks are assigned in ODB /eq/feudp/settings.

{ADC,PWB} --> 1gige --> switch --> 10gige --> alphagdaq --> feudp -> BUFUDP

== CTRL ==

fectrl controls all the ADC, PWB and trigger boards. It provides run start and stop sequencing,
runs the event synchronization sequence at the begin of the run, and records slow controls data (temperatures,
voltages, etc).

fectrl receives UDP data packets from the trigger board and sends them to the MIDAS event buffer BUFUDP.

fectrl receives commands from the control web pages (for ADC, PWB and trigger) to reboot, initialize, etc the boards.

fectrl configures the event builder via odb /eq/fectrl/evbconfig.

ADC <-> http esper <-> fectrl -> slow control data into midas history

PWB <-> http esper <-> fectrl -> slow control data into midas history

TRG <-> udp comm <-> fectrl -> BUFUDP, slow control and counters into midas history

fectrl <-> midas rpc <-> mhttpd <-> json rpc <-> control web pages for ADC, PWB and trigger

== EVB ==

feevb receives udp packet data from the MIDAS event buffer BUFUDP, inspects the packet timestamps
and collects the data with matching timestamps into physics events. feevb has provisions to do
data suppression, reduction and compression in addition to the data reduction done
in the ADC and PWB firmware.

feevb event synchronization relies on the event synchronization sequence done by fectrl when a run is started.

{ADC, PWB, TRG} -> BUFUDP -> feevb -> SYSTEM -> mlogger -> compression -> disk storage

=== internal structure ===

* event buffer readers, instances for BUFTRG, BUFTDC, BUFADC, BUFUDP
<pre>
BufferReader class - reads one midas event buffer:
- BufferReaderThread()
-- in batches of 1000 events
--- lock
--- TickLocked()
----- ReadEvent() -> bm_receive_event_alloc()
----- fHandler->HandleEvent()
-- fHandler->XMaybeFlushBank()
-- sleep 100 usec
</pre>
* event header decoder and intermediate buffer
<pre>
Handler class - accumulates events, sends them to the EVB in batches

- HandleEvent() <- BufferReaderThread() - receive incoming events
-- loop over all banks, examine bank name
--- call AddAdcBank(), AddPwbBank(), AddTrgBank(), AddTdcBank() according to bank name
---- AddXxxBank() -> XAddBank()
--- unknown banks go directly to evb->SendQueue
-- check if synchronization has completed

- XAddBank() - save BankBuf objects in a buffer

- XMaybeFlushBank(), XFlushBank() - send all accumulated data to the Evb class
-- evb->lock()
-- for each buffered BankBuf objects,
--- call evb->AddBankLocked()
-- buffer is now empty
</pre>
* event builder
<pre>
Evb class - assemble event fragments according to timestamps

- fEvents fifo (deque) - time sorted list of partially assembled events
-- new entries are added by FindEvent()
-- entries are modified by MergeSlot()
-- old entries are removed by GetLocked()

- AddBankLocked() <- XFlushBank() <- BufferReaderThread()
-- call fSync->Add()
-- transform BankBuf to EvbEventBuf
-- push it into per-module buffer fBuf[imodule]

- EvbThread()
-- EvbTickLocked()
--- BuildLocked()
---- in a loop, for no more than 1 sec
----- loop over all per-module buffers fBuf
------ pop first entry, pass it to BuildSlot()
------- call FindEvent()
------- call MergeSlot()
------- call CheckEvent()
--- in a loop
---- get all completed events via GetLocked() pass them to SendQueue->PushEvent()
-- if done nothing, sleep 100 usec, otherwise nominal sleep to free the evb lock

- GetNext() <- GetLocked() <- EvbThread() - get completed events
-- examine oldest EvbEvent entry in fEvents:
-- pop it if it is complete
-- pop it if it is too old (to prevent old incomplete events from stalling the evb) ("pop age" on the evb page)
-- pop it if a following event is complete ("pop following" on the evb page)
</pre>
* send queue
<pre>
SendQueue class - prepare events for writing to midas SYSTEM event buffer

- PushEvent() <- EvbThread()
-- push FragmentBuf into the queue

- SendQueueThread()
-- in a batch of 1000 events, call Tick()
--- pop FragmentBuf from the queue, call SendEvent()
--- compose midas event (memcpy()!)
--- TMFE fEq->SendEvent()
--- bm_send_event()
-- sleep 100 usec
</pre>
* equipment object
<pre>
EvbEq class - implements the midas equipment
- HandleBeginRun()
- HandleEndRun()
- HandlePeriodic()
</pre>

=== multithreading ===

* BufferReaderThread() one per midas event buffer
** high CPU use: bm_receive_event(), AddXxxBank()
** lock contention: midas event buffer lock, evb lock into XFlushBank->AddBankLocked()
* EvbThread()
** O(size of fEvents): FindEvent(), GetNext()
** lock contention: evb lock against XFlushBank(), SendQueue lock (1 per output event)
* SendQueueThread()
** high CPU use: memcpy() in SendEvent(), memcpy() in bm_send_event
** lock contention: event queue lock against EvbThread, midas event buffer lock
* main thread
** lock contention: evb lock in ReportEvb() and elsewhere

= ODB entries =

== /Equipment/CTRL/Settings ==
* TBW

== /Equipment/CTRL/Settings/Pulser ==

* ClockFreqHz - unit of 1/sec (Hz), set to 62500000, the TRG 62.5 MHz clock frequency (16 ns)
* PulseWidthClk - unit of 16 ns clocks, set to 25. (400 ns). width of internal pulser signal (used to go to a TRG external output, absent on GRIF-C boards)
* PulsePeriodClk - unit of 16 ns clocks, pulser in clock periods (+1), set to zero.
* PulseFreqHz - unit of 1/sec (Hz), requested pulser frequency, actual frequency is rounded to 16 ns clock granularity, change this value to select desired clock frequency
* BurstCtrl - enable burst of pulses 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses
* OutputEnable - enable TRG pulser external output (absent on GRIF-C boards)
* Enable - allow the pulser to run (bit 3 in TRG conf_trig_enable register)

== /Equipment/CTRL/Settings/TrigSrc - trigger source selection ==
* TrigPulser - trigger on the pulser
* TrigEsataNimGrandOr - trigger on external NIM inputs of GRIF-16 ADC modules
* TrigAdc16GrandOr - trigger on any adc16 signals (see adc16_masks)
* TrigAdc32GrandOr - trigger on any adc32 signals (see adc32_masks)
* TrigAdcGrandOr - trigger on adc16_grand_or or adc32_grand_or
* (removed from trg firmware) Trig1ormore - trigger on adc16 multiplicity 1 or more
* (removed from trg firmware) Trig2ormore - ditto, 2 or more
* (removed from trg firmware) Trig3ormore - ditto, 3 or more
* (removed from trg firmware) Trig4ormore - ditto, 4 or more
* (removed from trg firmware) TrigAwCoincA - trigger on TPC AW coincidence (see [[TRG]] manual)
* (removed from trg firmware) TrigAwCoincB - ditto
* (removed from trg firmware) TrigAwCoincC - ditto
* (removed from trg firmware) TrigAwCoincD - ditto
* (removed from trg firmware) TrigAwCoinc - ditto
* (removed from trg firmware) TrigAw1ormore - trigger on TPC AW per-preamp multiplicity 1 or more (see [[TRG]] manual)
* (removed from trg firmware) TrigAw2ormore - ditto, 2 or more
* (removed from trg firmware) TrigAw3ormore - ditto, 3 or more
* (removed from trg firmware) TrigAw4ormore - ditto, 4 or more
* TrigAwMLU - trigger on TPC AW MLU signal (see [[TRG]] manual)
* TrigBscGrandOr - trigger on any BSC signal
* TrigBscMult - trigger on predefined BSC multiplicity (see [[TRG]] manual)
* TrigCoinc - trigger on predefined coincidence of TPC AW, BSC and external signal (see [[TRG]] manual)

== /Equipment/CTRL/Settings/TRG - trigger settings ==
* Enable - if set to "n", fectrl will not do anything with the trigger board. Normal value "y"
* Modules - hostnames of the trigger board. Normal value "alphat01"
* NimMask - 32-bit mask for the 32x NIM inputs (see TRG manual). Normal value 0, unless external trigger is in use.
* EsataMask - 32-bit mask for the 32x eSATA signals (see TRG manual). Normal value 0.
* adc16_mask[16] - 16x 16-bit mask for the 100MHz GRIF-16 onboard ADCs (see TRG manual). Normal value 0xFFFF for all 16 data links.
* adc32_mask[16] - 16x 32-bit mask for the 62.5MHz FMC-ADC32 ADCs (see TRG manual). Normal value 0xFFFFFFFF for all 16 data links.
* PassThrough - if set to "y", trigger is passed through the trigger module without generating any events and without causing deadtime.
* AwCoincA, B, C and D - 32-bit masks for the aw16 coincidence trigger (see TRG manual)
* Aw16FromAdc16 - route AW trigger (aw16) from adc16 (100MHz ADCs 0..15)
* Aw16FromAdc32a - route AW trigger (aw16) from adc32 group 15..0 (62.5MHz FMC-ADC32 in ADCs 0..7)
* Aw16FromAdc32b - route AW trigger (aw16) from adc32 group 31..16 (62.5MHz FMC-ADC32 in ADCs 8..15)
* MluDir, MluFiles - location of aw16 MLU bit patterns
* MluSelectedFile - currently selected/loaded MLU file. 0="grand or", 1="2 or more hit clusters", 2="2 or more hit clusters, with gap 2 or more", 3="3 or more hit clusters"
* MluPrompt - length of aw16_prompt_run gate in units of 8 ns clock, see [[TRG#aw16_mlu]]
* MluWait - length of aw_prompt_wait gate in units of 8 ns clock, see [[TRG#aw16_mlu]]
* MluTrigDelayClk - "TrigDelay" when triggered of aw16 MLU, in units of 16 ns clock
* (BSC settings, TBW)
* BscFromAdc16a
* BscFromAdc16b
* BscBotOnly
* BscTopOnly
* BscBotTopOr
* BscBotTopAnd
* BscMultiplicityMin
* BscMultiplicityWindowClk8
* BscEmptyWindowClk8
* BscMultTrigDelayClk16
* CoincStart - set same as CoincRequire
* CoincRequire - 0x5: (BSC grand or)*(TPC aw16_1ormore), 0x6: (BSC grand or)*(AW16 MLU), see [[TRG#Coincidence_trigger]] and [[TRG#conf_coinc_control bits]]
* CoincWindow - length of coincidence window in 8ns clocks.
* CoincTrigDelayClk16

== /Equipment/CTRL/Settings/PWB - PWB settings ==
* Enable - if set to "n", fectrl will not do anything with PWBs. Normal value "y".
* enable_boot_user_page - if set to "n", fectrl will not try to reboot PWBs into the user page firmware. Normal value "y".
* enable_trigger - if set to "n", all PWBs will be set to ignore the trigger. Normal value "y".
* enable_trigger_group_a - field wire pulser defeats the data suppression (every channel has a pulse) resulting in too much data overwhelming the DAQ (lost UDP packets). To permit correct data taking of field wire pulser data, PWBs are split into two groups (a and b), only one of the two groups should be enabled for field wire pulser runs. Both groups should be enabled for normal data taking. Normal value is "y"
* enable_trigger_group_b - see "enable_trigger_group_a". Normal value is "y".
* modules[64] - hostnames of PWB boards
* boot_user_page[64] - if set to "y" and enable_boot_user_page is "y", fectrl will reboot the corresponding PWB to the user page firmware.
* trigger[64] - if set to "y" and enable_trigget is "y", fectrl will set the PWB to accept the trigger.
* ch_enable - if set to "n" disables all PWB channels. Normal value is "y".
* ch_force - is set to "y" disables channel suppression (all PWB channels are read)
* suppress_reset - if set to "y" enables channel suppression for reset channels (threshold has to be set correctly)
* suppress_fpn - if set to "y" enables channel suppression for fpn channels (threshold has to be set correctly)
* suppress_pads - set to "y" enables channel suppression for TPC pad channels (threshold has to be set correctly)
* disable_reset1 - data suppression algorithm does not work for the channel "reset1" and it has to be suppressed explicitly by setting this value to "y". Normal value is "y".
* baseline_{reset,fpn,pads}[64] - waveform baseline for each PWB position
* threshold_{reset,fpn,pads} - waveform suppression threshold, see below:
* ch_threshold - PWB sca_N_ch_threshold, if set to 0, threshold is computed as "baseline_pads[seqpwb]-threshold_pads". Normal value is 0.
* test_mode - enable PWB test mode, the ADC data is replaced with a test pattern, see PWB esper variable signalproc/test_mode

== /Equipment/CTRL/Settings/TDC - TDC settings ==
* Enable - if set to "n", fectrl will tell the event builder that the TDC is not running. Normal value is "y".

== /Equipment/CTRL/Variables ==

* Scalers - TRG scalers and counters. from fectrl.cxx ReadTrgLocked()
<pre>
// 0..15 read the 16 base scalers at 0x100
// 16..31 read the adc16 scalers at 0x430
// 32..63 read the adc32 scalers at 0x440
// 64..79 read the 16 additional scalers at 0x110
// 80..95 read the 16 counters_adc_selected scalers at 0x460
// 96..159 read the 64 bar scalers at 0x470
// additional scalers should be appended at the end.
</pre>

== /Equipment/CTRL/EvbConfig - EVB configuration ==
All arrays have the same size corresponding to the number of EVB slots.
* name[] - slot name for the web page (trg01, adc01, adc01/adc32, pwb31/0, tdc01, etc)
* type[] - slot type: 1=TRG, 2=ADC16 and ADC32, 3=obsolete PWB, 4=obsolete PWB, 5=PWB, 6=TDC
* module[] - module number (adcNN, adcNN+100, pwbNN, etc)
* nbanks[] - number of expected banks (16 for ADC16, 32 for ADC32, not used, set to 1 for all others)
* tsfreq[] - timestamp frequency in Hz.

== /Equipment/ADC_UDP - ADC UDP configuration ==

* Common/Buffer - "BUFADC" - event buffer to use, name is hardwired in feevb.cxx
* Settings/udp_port - 50006 - UDP port number, also used by fectrl to configure the ADC modules
* Settings/rcv_bufsize - 209715200 - udp socket buffer size set by setsockopt(SOL_SOCKET, SO_RCVBUF). must have a corresponding command in /etc/rc.local to increase maximum system socket size: "/usr/sbin/sysctl -w net.core.rmem_max=200000000"
* Settings/packet_size - 1500 - non-jumbo-frame UDP packet maximum size
* Settings/max_buffered_packets - 40000 - maximum size of internal packet fifo. If it overflows, extra packets are discarded.
* Settings/max_packets_per_event - 8000 - how many UDP packets to pack into one midas event==

== /Equipment/PWB_X_UDP - PWB UDP configuration ==

For explanation see ADC_UDP above.

* Common/Buffer - "BUFUDP" - event buffer to use, name is hardwired in feevb.cxx
* Settings/udp_port - 50007, 50008, 50009, 50010 - for A, B, C and D UDP receivers respectively, also used by fectrl to configure the PWB modules
* Settings/rcv_bufsize - 209715200
* Settings/packet_size - 1500
* Settings/max_buffered_packets - 10000
* Settings/max_packets_per_event - 8000

= Trigger configuration =

These trigger modes are implemented:
* (manual trigger from web page)
* software pulser trigger (from fectrl)
* hardware pulser trigger (from the trigger board)
* NIM and eSATA trigger from ADC front panel inputs
* adc16 and adc32 discriminator triggers:
** adc16 grand-or trigger
** adc32 grand-or trigger
** adc (adc16+adc32) grand-or trigger
** adc16 multiplicity trigger (1ormore, 2ormore, 3ormore, 4ormore) for use with barrel scintillator
** anode wire multiplicity trigger (1ormore, 2ormore, 3ormore, 4ormore) (anode wire signals can be fed from adc16 or from adc32 signals)
** anode wire coincidence trigger
** anode wire MLU (memory lookup) trigger

== NIM trigger from ADC front panel ==

Trigger path:
<pre>
NIM signal --> LEMO input on ADC front panel --> data encoder --> data link to trigger board --> data decoder --> mask --> nim-esata-grand-or --> trigger
</pre>

To enable NIM trigger, do this:
* connect NIM signal to ADC front panel input
** Note1: NIM signal must be inverted
** Note2: LEMO connectors should be set to "NIM input" mode by ADC on-board jumpers (see ADC manual)
* observe correct bit goes to zero in the TRG web page: data link high work should change:
<pre>
0xNF00'0000 (N is the module id) to
0xN700'0000 (left lemo) or
0xNB00'0000 (right lemo)
</pre>
* Note3: if data link bits do not change, most likely the LEMO connectors are set to "DAC output" mode. Try to use LEMO inputs of a different ADC.
* compute the NIM mask: there are 32 bits, 2 bits per ADC data link. Bit 0x1 is right LEMO, bit 0x2 is left LEMO
* for example, to use left LEMO of ADC data link 12, set nim mask to (0x2)<<(2*12) = 0x02000000
* development branch of the git repository contains ''scripts/nim_mask.py'', which can compute forwards and backwards
* initialize the trigger board (on the TRG web page press button "initialize"), or start a new run
* on the history plot with "NIM grand or" counter, the rate should change from zero
* if a run is active, if one of the ADC LEMO outputs is set to output the trigger signal as a NIM pulse, one should see it fire use a scope. The delay or jitter between NIM trigger in and NIM trigger out should be around 100-200 ns (FIXME - measure this!)
* to set the DAQ to trigger on the NIM signal, on the run start page, check the box "TrigEsataNimGrandOr".
** Note: remember to set the scaledown to 0 if so desired.

= TPC field wire pulser =

The TPC field wire pulser input should be connected directly to the DAC output of ADC[0] (right lemo connector).

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for pulsing PWBs, baseline -1V, pulse height +2V (maximum possible pulse height in PWBs. Overdrives the AW ADC waveforms)
** dac_baseline: -8000
** dac_amplitude: 8000
** ramp_up_rate: 128
** ramp_down_rate: 70
** ramp_top_len: 128

* for pulsing AW, baseline -0.25V, pulse height +0.7V (AW ADC waveforms are in range. PWB waveforms are too small for goor time resolution)
** dac_baseline: -2000
** dac_amplitude: 4000
** ramp_up_rate: 20
** ramp_down_rate: 20
** ramp_top_len: 128

= BSC pulser =

The BSC pulser input on the BSC VME rear transition board (RTM) should be connected directly to the DAC output of ADC[4,5,6,7] (right lemo connector). (8 RTMs, but 4 ADCs, each signal is split using a LEMO "T" connector).

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for pulsing BSC, baseline -0.950V, pulse height +1.4V
** dac_baseline: -8000
** dac_amplitude: 4000
** ramp_up_rate: 64
** ramp_down_rate: 64
** ramp_top_len: 128

= NIM output =

To configure ADC analog output for NIM compatible pulse:

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for output of NIM pulse: baseline 0V, pulse height -0.9V, pulse width 100 ns
** dac_baseline: 0
** dac_amplitude: 8000
** ramp_up_rate: 128
** ramp_down_rate: 128
** ramp_top_len: 4
** dac_xor: 1 (invert the signal)

= TDC connections =

* SFP8 - fiber SFP to Juniper switch
* right RJ45 - 200MHz clock
* left RJ45 - external trigger

= MIDAS Data banks =

* ATAT - fectrl - UDP packets from GRIF-C/TRG trigger board
* TRBA - fetdc - TDC data
* TRTM - fetdc - TDC FPGA temperatures, TID_FLOAT[5].
* AAnn - feudp - UDP packets from GRIF-16 ADC (before the event builder), "nn" is the ADC module number: adc01 is AA01 through adc20 is AA20.
* BBxx - feudp - UDP packets from PWB, obsolete
* Bnnm, Cnnm - feevb - EVB output banks: ADC data, "nn" is the ADC module number (1..20), "m" is the channel number (0..9,A..F), format is same as AAnn banks.
* PAnn - feudp - UDP packets from PWB, "nn" is the PWB module number (00..99), obsolete
* PBnn - feudp - UDP packets from PWB, "nn" is the PWB module number (00..99), PB01 is pwb01, PB78 is pwb78
* PCnn - feevb - EVB output banks: PWB data, "nn" is the PWB module number (00..99), same as above, format is same as PBnn banks

= ZZZ =

ZZZ

Daq

2022-07-16T21:00:27Z

Olchansk: /* /Equipment/CTRL/Settings/TrigSrc - trigger source selection */

= Links =

* https://alphacpc05.cern.ch/agdaq/ -- midas daq page for the agdaq system at CERN
* https://daq16.triumf.ca -- midas daq page for the agmini system at TRIUMF
* https://daq.triumf.ca/elog-alphag/alphag/ -- elog
* https://daqstore.triumf.ca/AgWiki/index.php/Main_Page -- this wiki
* https://bitbucket.org/ttriumfdaq/agdaq - git repository for agdaq
* https://bitbucket.org/expalpha -- git repository on bitbucket
* https://edev-group.triumf.ca/fw/exp/alphag -- git repository on edev gitlab

= Inventory database =

* https://ladd00.triumf.ca/daqinv/frontend/list/170 - PWB inventory database
* https://ladd00.triumf.ca/daqinv/frontend/list/168 - ADC (GRIF-16) inventory, FMC-ADC32rev0,rev1 inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/176 - FMC-ADC32rev1.1 inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/174 - BSC RTM inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/173 - BSC ASD inventory

= Hardware manuals =

* [[TRG]] - trigger board (GRIF-C) manual
* CDM - https://daq.triumf.ca/DaqWiki/index.php/VME-CDM -- clock VME-CDM manual
* ADC - https://daq.triumf.ca/DaqWiki/index.php/VME-GRIF-ADC16-Rev1 -- GRIF-16 ADC manual
* [[PWB]] - TPC Pad Wing Board manual
* TDC - https://daq.triumf.ca/DaqWiki/index.php/GSI_TRB3
* [[chronobox]] - chronobox manual
* [[ASD]] - BSC preamp board
* [[RTM]] - BSC VME rear transition board

= Performance =

Full system: (ADC fw rel-20201112-ko, PWB fw 20201005_ko)
* 1 Hz stable, ADC adc32 9 supp off rate 0.3 M/s, adc16 off, PWB udp_delay 25 supp off active 64 rate 6.6+4+6+4.6=21.2 M/s, TDC off, total rate 21 M/s
* 500 Hz stable, ADC adc32 9 supp 1500 rate 6 M/s, adc16 off, PWB udp_delay 10 supp 100 active 63 rate 3+4+3+3=13 M/s, TDC off, total rate 19 M/s

Single ADC: (fw rel-20201112-ko)

Fully suppressed data, sthreshold 5000
* 1 Hz: stable
* 500 Hz: stable (nominal max trigger rate)
* 6700 Hz: stable, 8 Mbytes/sec
* 6800 Hz: evb eventually confused
* 6850 Hz: evb confused, no lost triggers in the ADC, no crash in the ADC

All data, 510 samples/event, sthreshold 10 (fw rel-20201122-ko)
* 1 Hz: stable
* 100 Hz: stable, 3.4 Mbytes/sec
* 500 Hz: stable, 17 Mbytes/sec (nominal max trigger rate)
* 1000 Hz: stable, 32 Mbytes/sec
* 3100 Hz: stable, 106 M/s (approaching saturation of 1gige ethernet)
* 3200 Hz: stable, 110 M/s - TRG communication is in trouble
* 3300 Hz: stable, 116 M/s
* 3400 Hz: incomplete events, no ADC crash ("dropped due to full" counting, "dropped due to busy" are zero, this is as expected).

no suppression (different fpga data path)
* 1 Hz: stable
* 100 Hz: stable
* 500 Hz: stable, 17 M/s (nominal max trigger rate)
* 1000 Hz: stable, 32 M/s
* 3000 Hz: stable, 100 M/s (approaching saturation of 1gige ethernet)
* 3300 Hz: incomplete events, no ADC crash ("dropped due to full" counting, "dropped due to busy" are zero, this is as expected).

= Network connections =

The experiment private network number is: 192.168.1.x, gateway 192.168.1.1, netmask 255.255.255.0

network map:
<pre>
---- TRIUMF/CERN network --1gige-- alphagdaq --10gige-- juniper switch --1gige-- centrecom switch
</pre>

== alphagdaq network connections ==

on the rear of the machine:
<pre>
-----------------------------------------
| | rj45 | rj45 | | sfp | sfp |
-----------------------------------------

- left rj45 - copper 1gige - eno1 - spare (inactive)
- right rj45 - copper 1gige - eno2 - dhcp - cern/triumf network
- left sfp - 10gige - enp1s0f1 - spare (inactive)
- right sfp - 10gige - enp1s0f0 - static 192.168.1.1
</pre>

== connections between switches ==

* alphagdaq to juniper switch: direct attach (DAC) 10gige cable into any port of juniper switch
* juniper switch to centrecom switch: rj45 sfp in any port of juniper switch - cat5e/cat6 cable - to any port of centrecom switch
* cat5e/cat6 cable from any port of centrecom switch to the XXX port on the back of the juniper switch

== juniper switch ==

connected to juniper switch front is:

* everything that sends event data to alphagdaq, specifically:
** TRG (rj45 sfp)
** 16x ADC (fiber sfp)
** 64x PWB (fiber sfp)
* 10gige uplink to alphagdaq (10gige DAC cable)
* 1gige link to centrecom switch (rj45 sfp)
* 40gige ports are not used

connected to the juniper switch rear:

* CON is the serial console via RJ45-to-DB9 to USB-serial adapter to alphagdaq USB port (9600bps, 8N1, no flow control)
* C0 is the management ethernet interface port, connect to any port on the centrecom switch (juniper-private will ping)

== centrecom switch ==

* everything with copper rj45 connections, specifically:
** CDM boards
** HV, LV and VME power supplies
** RaspberryPi3 boards
** gas handling MFCs (algas)
** cooling system controller (moxa01)

= USB connections =

Note:
* alphagdaq has USB2 and USB3 connections. They are not the same, they are not generally interchangeable.
* USB3 connections and cables are generally blue coloured.

List of USB connections from alphagdaq:

* front USB3 port (blue): USB-A-to-B cable to USB blaster connected to the trigger board (front of rack)
* rear USB3 port (blue): USB3 short jumper to USB3 hub
* rear USB2 port (black): USB2 unpowered hub (Logiix) to USB-A-to-B cable to UPS USB connector
* rear USB2 port (black): USB-to-Serial adaper to DB9 to RJ45 adapter to Juniper switch console port

Note: UPS USB connection does not work with alphagdaq USB ports (both usb2 and usb3), but combination
using the unpowered USB2 hub seems to work ok.

List of USB connections from the USB hub:

* this is a powered USB3 hub
* USB-A-to-MicroUSB - to lvdb boards
* USB-A-to-Wiener interlock cable

= Clock and trigger distribution =

== Explanation ==

Trigger is generated by the trigger board (aka TRG, aka GRIF-C),
from the TRG eSATA output through the eSATA splitter it is fed into
the master CDM. The master CDM outputs the trigger on all MiniSAS output ports.
One of the master CDM MiniSAS outputs is connected to the CDM slave eSATA input.
The same as the master CDM, the slave CDM outputs the trigger on all MiniSAS output ports.

The master 62.5MHz clock is generated by the master CDM using the internal 10MHz oscillator
or the external 10MHz AD clock. Also on MiniSAS port 6 the master CDM generates
the 200MHz clock for the TDC. This clock is frequency-locked to the master 62.5MHz clock.

Master CDM clock selection (external CD 10MHz clock or internal oscillator 10MHz clock)
is done by a magic esper command (see below).

From the master CDM, the clock is fed to: the slave CDM, the TRG (via the eSATA splitter)
and to the TDC (via the RJ45 splitter).

The slave CDM sends the clock and the trigger to the ADCs and PWBs.

== Chronobox connections ==

Chronoboxes are synchronized with the daq using two signals: 10 MHz timestamp clock and TTL sync.

The sync signal used is the trigger signal - timestamps are reset by the 1st event - which is not a physics event, but the first trigger in the trigger sync sequence.

All chronoboxes are configured in "slave" and "chain" mode.

Slave mode: 10 MHz timestamp clock goes into the CLK_IN input (configured as NIM on the first chronobox and TTL on all others), sync signal goes into TTL input LEMO 4. (bank B direction set to "in").

Chain mode: 10 MHz timestamp clock is TTL output LEMO 0, sync is TTL output LEMO 1. (bank A direction set to "out"). These signals feed into CLK_IN (TTL mode) and TTL input LEMO 4 in the next chronobox in the chain.

The first chronobox receives the 10 MHz timestamp clock and sync signals from the master CDM per diagrams below.

* CDM 10 MHz clock output is NIM, feeds directly into the chronobox CLK_IN (NIM mode).
* CDM "trigger" ("sync") output is NIM, has to go through a NIM-to-TTL converter before feeding chronobox TTL input LEMO 4. I use a LeCroy 222 "gate and delay generator" module. NIM input goes into the "Start" input, TTL output is taken from the "TTL" output. Signal width is adjusted to around 100-1000 ns. Any other sutable NIM-to-TTL converter can also be used.
* "sync" output must be enabled in the master CDM:
<pre>
esper-tool cdm00
cd cdm
write multi_sync 2
</pre>

== Schematic ==

<pre>
TRG (GRIF-C)
------------
eSATA <------> eSATA splitter

eSATA splitter
--------------
trigger ---> eSATA ---> CDM-Master eSATA (trigger signal)
clock <--- (eSATA --- MiniSAS) <--- CDM MiniSAS (62.5MHz clock)
</pre>

<pre>
CDM-Master
----------
LEMO1B <----- 10 MHz AD clock (NIM)
LEMO2A --> (only if there is no external clock) 4ns lemo cable --> LEMO1B (62.5 MHz frequency monitor)
LEMO2B --> chronobox sync (NIM) --> NIM-to-TTL --> long lemo cable to chronobox sync input (TTL)
LEMO3B --> long lemo cable to chronobox clock input (NIM) (CLK_IN configured for NIM input)
eSATA <--- eSATA splitter <--- eSATA from TRG (trigger signal)
MiniSAS 1 --> (MiniSAS --- eSATA) --> CDM-Slave eSATA (62.5 MHz)
MiniSAS 6 --> (MiniSAS --- eSATA) --> eSATA splitter --> RJ45 --> TDC (200 MHz)
</pre>

<pre>
CDM-Slave
---------
LEMO2A --> 4ns lemo cable --> LEMO1B (62.5 MHz frequency monitor)
eSATA <--- trigger and 62.5MHz clock from CDM-Master
MiniSAS 1 --> ADC trigger and 62.5MHz clock
MiniSAS 2 --> same
MiniSAS 3 --> same
MiniSAS 4 --> same
MiniSAS 5 --> PWB trigger and 62.5MHz clock
MiniSAS 6 --> same
</pre>

[[File:VME_Crate_CERN.jpeg|800x450px|Layout of the VME crate at CERN.]]

Layout of the VME crate at CERN. The ALPHA-T module is in the rightmost slot. The Master CDM is next to it and it's labelled as #02. The Slave CDM is on the lefmost position and labelled by #03.

== Setup of CDM boards ==

ALPHA-g uses the Rev3 CDM boards. The 4 CDM boards that belong to ALPHA-g
have serial numbers 0, 1, 2 and 3 and are labeled cdm00, cdm01, cdm02, cdm03.

All the boards can be used as master and slave positions, but have to be
configured appropriately.

=== Slave setup ===

* install the board
* connect ethernet
* connect esata external clock
* esper-tool cdmNN ### i.e. esper-tool cdm01
* cd template
* write current_setup 4
* cd /cdm
* read
* observe clock frequency counters report correct values. "ext_clk" will only count if the lemo jumper is installed (see below)
<pre>
11 esata_clk uint32 R [62500246]
12 ext_clk uint32 R [62500246]
</pre>
* cd /lmk
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
156 ld1_counter uint32 RW [3]
157 ld2_counter uint32 RW [3]
</pre>

If needed, check correct operation of the pll lock monitoring:

* unplug the esata cable from the master CDM
* "red" light should go off
* read of lmk should report "pll1_ld" value 0 and "ld1_counter" and "ld2_counter" should increment
* reconnect the esata cable
* "red" light should return
* read of lmk should report both pll1_ld and pll2_ld locked (values "1").

=== Master setup ===

* install the board
* connect ethernet
* esper-tool cdmNN ### i.e. esper-tool cdm01
* cd template
* write current_setup 3
* cd /lmk
* write clkin_sel_mode 0
* cd /cdm
* read
* observe clock frequency counters report correct values. "ext_clk" will only count if the "clock loopback" lemo jumper is installed (see below)
<pre>
12 ext_clk uint32 R [62500189]
</pre>
* cd /lmk
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
156 ld1_counter uint32 RW [3]
157 ld2_counter uint32 RW [3]
</pre>

Check the 200MHz clock:
* connect MiniSAS-eSATA splitter cable to MiniSAS output 6, connect eSATA end to CDM eSATA input
* in esper-tool, read cdm: esata_clk should report 200MHz clock
<pre>
11 esata_clk uint32 R [200000603]
12 ext_clk uint32 R [62500188]
</pre>

=== Master setup with external 10 MHz clock ===

* setup master CDM as above (using internal clock)
* connect 10MHz external clock to LEMO1A
* esper-tool cdmNN
* cd /cdm
* write sel_nim 1 # if clock is NIM signal
* write sel_nim 0 # if clock is TTL signal (i.e. chronobox LEMO output)
* read ext_clk
<pre>
[http://cdm00:/cdm]> read ext_clk
9999556
</pre>
* if ext_clk reads 0 or does not read something close to 10MHz, stop here. debug the signal, try changing sel_nim, etc.
* cd /lmk
* write clkin_sel_mode 2 # select external clock
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
150 clkin2_sel bool R [True]
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
</pre>
* on the MIDAS TRG page, observe that TRG measured external clock frequency is close to 62.5 MHz

== clkin_sel_mode positions ==

* 0 = 10MHz internal oscillator (use on master CDM in standalone mode)
* 1 = eSATA clock (use on slave CDM)
* 2 = external clock, should be 10MHz (use on master CDM to run from AD clock)

== LEMO connections ==

LEMO connectors:

<pre>
|
|LEMO1A|LEMO1B
|LEMO2A|LEMO2B
|LEMO3A|LEMO3B
|eSATA
|RJ45 ETH
|minisas
|
</pre>

* clock loopback jumper: to read the frequency of the generated 62.5MHz clock, connect LEMO cable from LEMO2B to LEMO1A
* 10MHz internal clock jumper: to feed 10MHz internal oscillator to the external clock, connect LEMO cable from LEMO3A to the LEMO1A
* 10MHz external clock: to feed 10MHz external clock, connect LEMO cable to LEMO1A

= MIDAS frontends =

== UDP ==

feudp receives udp packets from the ADC and PWB boards. For each udp packet 1 midas event is created,
with 1 data bank containing the udp data. Events are sent into the MIDAS event buffer BUFUDP. The names
of the data banks are assigned in ODB /eq/feudp/settings.

{ADC,PWB} --> 1gige --> switch --> 10gige --> alphagdaq --> feudp -> BUFUDP

== CTRL ==

fectrl controls all the ADC, PWB and trigger boards. It provides run start and stop sequencing,
runs the event synchronization sequence at the begin of the run, and records slow controls data (temperatures,
voltages, etc).

fectrl receives UDP data packets from the trigger board and sends them to the MIDAS event buffer BUFUDP.

fectrl receives commands from the control web pages (for ADC, PWB and trigger) to reboot, initialize, etc the boards.

fectrl configures the event builder via odb /eq/fectrl/evbconfig.

ADC <-> http esper <-> fectrl -> slow control data into midas history

PWB <-> http esper <-> fectrl -> slow control data into midas history

TRG <-> udp comm <-> fectrl -> BUFUDP, slow control and counters into midas history

fectrl <-> midas rpc <-> mhttpd <-> json rpc <-> control web pages for ADC, PWB and trigger

== EVB ==

feevb receives udp packet data from the MIDAS event buffer BUFUDP, inspects the packet timestamps
and collects the data with matching timestamps into physics events. feevb has provisions to do
data suppression, reduction and compression in addition to the data reduction done
in the ADC and PWB firmware.

feevb event synchronization relies on the event synchronization sequence done by fectrl when a run is started.

{ADC, PWB, TRG} -> BUFUDP -> feevb -> SYSTEM -> mlogger -> compression -> disk storage

=== internal structure ===

* event buffer readers, instances for BUFTRG, BUFTDC, BUFADC, BUFUDP
<pre>
BufferReader class - reads one midas event buffer:
- BufferReaderThread()
-- in batches of 1000 events
--- lock
--- TickLocked()
----- ReadEvent() -> bm_receive_event_alloc()
----- fHandler->HandleEvent()
-- fHandler->XMaybeFlushBank()
-- sleep 100 usec
</pre>
* event header decoder and intermediate buffer
<pre>
Handler class - accumulates events, sends them to the EVB in batches

- HandleEvent() <- BufferReaderThread() - receive incoming events
-- loop over all banks, examine bank name
--- call AddAdcBank(), AddPwbBank(), AddTrgBank(), AddTdcBank() according to bank name
---- AddXxxBank() -> XAddBank()
--- unknown banks go directly to evb->SendQueue
-- check if synchronization has completed

- XAddBank() - save BankBuf objects in a buffer

- XMaybeFlushBank(), XFlushBank() - send all accumulated data to the Evb class
-- evb->lock()
-- for each buffered BankBuf objects,
--- call evb->AddBankLocked()
-- buffer is now empty
</pre>
* event builder
<pre>
Evb class - assemble event fragments according to timestamps

- fEvents fifo (deque) - time sorted list of partially assembled events
-- new entries are added by FindEvent()
-- entries are modified by MergeSlot()
-- old entries are removed by GetLocked()

- AddBankLocked() <- XFlushBank() <- BufferReaderThread()
-- call fSync->Add()
-- transform BankBuf to EvbEventBuf
-- push it into per-module buffer fBuf[imodule]

- EvbThread()
-- EvbTickLocked()
--- BuildLocked()
---- in a loop, for no more than 1 sec
----- loop over all per-module buffers fBuf
------ pop first entry, pass it to BuildSlot()
------- call FindEvent()
------- call MergeSlot()
------- call CheckEvent()
--- in a loop
---- get all completed events via GetLocked() pass them to SendQueue->PushEvent()
-- if done nothing, sleep 100 usec, otherwise nominal sleep to free the evb lock

- GetNext() <- GetLocked() <- EvbThread() - get completed events
-- examine oldest EvbEvent entry in fEvents:
-- pop it if it is complete
-- pop it if it is too old (to prevent old incomplete events from stalling the evb) ("pop age" on the evb page)
-- pop it if a following event is complete ("pop following" on the evb page)
</pre>
* send queue
<pre>
SendQueue class - prepare events for writing to midas SYSTEM event buffer

- PushEvent() <- EvbThread()
-- push FragmentBuf into the queue

- SendQueueThread()
-- in a batch of 1000 events, call Tick()
--- pop FragmentBuf from the queue, call SendEvent()
--- compose midas event (memcpy()!)
--- TMFE fEq->SendEvent()
--- bm_send_event()
-- sleep 100 usec
</pre>
* equipment object
<pre>
EvbEq class - implements the midas equipment
- HandleBeginRun()
- HandleEndRun()
- HandlePeriodic()
</pre>

=== multithreading ===

* BufferReaderThread() one per midas event buffer
** high CPU use: bm_receive_event(), AddXxxBank()
** lock contention: midas event buffer lock, evb lock into XFlushBank->AddBankLocked()
* EvbThread()
** O(size of fEvents): FindEvent(), GetNext()
** lock contention: evb lock against XFlushBank(), SendQueue lock (1 per output event)
* SendQueueThread()
** high CPU use: memcpy() in SendEvent(), memcpy() in bm_send_event
** lock contention: event queue lock against EvbThread, midas event buffer lock
* main thread
** lock contention: evb lock in ReportEvb() and elsewhere

= ODB entries =

== /Equipment/CTRL/Settings ==
* TBW

== /Equipment/CTRL/Settings/Pulser ==

* ClockFreqHz - unit of 1/sec (Hz), set to 62500000, the TRG 62.5 MHz clock frequency (16 ns)
* PulseWidthClk - unit of 16 ns clocks, set to 25. (400 ns). width of internal pulser signal (used to go to a TRG external output, absent on GRIF-C boards)
* PulsePeriodClk - unit of 16 ns clocks, pulser in clock periods (+1), set to zero.
* PulseFreqHz - unit of 1/sec (Hz), requested pulser frequency, actual frequency is rounded to 16 ns clock granularity, change this value to select desired clock frequency
* BurstCtrl - enable burst of pulses 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses
* OutputEnable - enable TRG pulser external output (absent on GRIF-C boards)
* Enable - allow the pulser to run (bit 3 in TRG conf_trig_enable register)

== /Equipment/CTRL/Settings/TrigSrc - trigger source selection ==
* TrigPulser - trigger on the pulser
* TrigEsataNimGrandOr - trigger on external NIM inputs of GRIF-16 ADC modules
* TrigAdc16GrandOr - trigger on any adc16 signals (see adc16_masks)
* TrigAdc32GrandOr - trigger on any adc32 signals (see adc32_masks)
* TrigAdcGrandOr - trigger on adc16_grand_or or adc32_grand_or
* (removed from trg firmware) Trig1ormore - trigger on adc16 multiplicity 1 or more
* (removed from trg firmware) Trig2ormore - ditto, 2 or more
* (removed from trg firmware) Trig3ormore - ditto, 3 or more
* (removed from trg firmware) Trig4ormore - ditto, 4 or more
* (removed from trg firmware) TrigAwCoincA - trigger on TPC AW coincidence (see [[TRG]] manual)
* (removed from trg firmware) TrigAwCoincB - ditto
* (removed from trg firmware) TrigAwCoincC - ditto
* (removed from trg firmware) TrigAwCoincD - ditto
* (removed from trg firmware) TrigAwCoinc - ditto
* (removed from trg firmware) TrigAw1ormore - trigger on TPC AW per-preamp multiplicity 1 or more (see [[TRG]] manual)
* (removed from trg firmware) TrigAw2ormore - ditto, 2 or more
* (removed from trg firmware) TrigAw3ormore - ditto, 3 or more
* (removed from trg firmware) TrigAw4ormore - ditto, 4 or more
* TrigAwMLU - trigger on TPC AW MLU signal (see [[TRG]] manual)
* TrigBscGrandOr - trigger on any BSC signal
* TrigBscMult - trigger on predefined BSC multiplicity (see [[TRG]] manual)
* TrigCoinc - trigger on predefined coincidence of TPC AW, BSC and external signal (see [[TRG]] manual)

== /Equipment/CTRL/Settings/TRG - trigger settings ==
* Enable - if set to "n", fectrl will not do anything with the trigger board. Normal value "y"
* Modules - hostnames of the trigger board. Normal value "alphat01"
* NimMask - 32-bit mask for the 32x NIM inputs (see TRG manual). Normal value 0, unless external trigger is in use.
* EsataMask - 32-bit mask for the 32x eSATA signals (see TRG manual). Normal value 0.
* adc16_mask[16] - 16x 16-bit mask for the 100MHz GRIF-16 onboard ADCs (see TRG manual). Normal value 0xFFFF for all 16 data links.
* adc32_mask[16] - 16x 32-bit mask for the 62.5MHz FMC-ADC32 ADCs (see TRG manual). Normal value 0xFFFFFFFF for all 16 data links.
* PassThrough - if set to "y", trigger is passed through the trigger module without generating any events and without causing deadtime.
* AwCoincA, B, C and D - 32-bit masks for the aw16 coincidence trigger (see TRG manual)
* Aw16FromAdc16 - route AW trigger (aw16) from adc16 (100MHz ADCs 0..15)
* Aw16FromAdc32a - route AW trigger (aw16) from adc32 group 15..0 (62.5MHz FMC-ADC32 in ADCs 0..7)
* Aw16FromAdc32b - route AW trigger (aw16) from adc32 group 31..16 (62.5MHz FMC-ADC32 in ADCs 8..15)
* MluDir, MluFiles - location of aw16 MLU bit patterns
* MluSelectedFile - currently selected/loaded MLU file. 0="grand or", 1="2 or more hit clusters", 2="2 or more hit clusters, with gap 2 or more", 3="3 or more hit clusters"
* MluPrompt - length of aw16_prompt_run gate in units of 8 ns clock, see [[TRG#aw16_mlu]]
* MluWait - length of aw_prompt_wait gate in units of 8 ns clock, see [[TRG#aw16_mlu]]
* MluTrigDelayClk - "TrigDelay" when triggered of aw16 MLU, in units of 16 ns clock
* (BSC settings, TBW)
* CoincStart - set same as CoincRequire
* CoincRequire - 0x5: (BSC grand or)*(TPC aw16_1ormore), 0x6: (BSC grand or)*(AW16 MLU), see [[TRG#Coincidence_trigger]] and [[TRG#conf_coinc_control bits]]
* CoincWindow - length of coincidence window in 8ns clocks.

== /Equipment/CTRL/Settings/PWB - PWB settings ==
* Enable - if set to "n", fectrl will not do anything with PWBs. Normal value "y".
* enable_boot_user_page - if set to "n", fectrl will not try to reboot PWBs into the user page firmware. Normal value "y".
* enable_trigger - if set to "n", all PWBs will be set to ignore the trigger. Normal value "y".
* enable_trigger_group_a - field wire pulser defeats the data suppression (every channel has a pulse) resulting in too much data overwhelming the DAQ (lost UDP packets). To permit correct data taking of field wire pulser data, PWBs are split into two groups (a and b), only one of the two groups should be enabled for field wire pulser runs. Both groups should be enabled for normal data taking. Normal value is "y"
* enable_trigger_group_b - see "enable_trigger_group_a". Normal value is "y".
* modules[64] - hostnames of PWB boards
* boot_user_page[64] - if set to "y" and enable_boot_user_page is "y", fectrl will reboot the corresponding PWB to the user page firmware.
* trigger[64] - if set to "y" and enable_trigget is "y", fectrl will set the PWB to accept the trigger.
* ch_enable - if set to "n" disables all PWB channels. Normal value is "y".
* ch_force - is set to "y" disables channel suppression (all PWB channels are read)
* suppress_reset - if set to "y" enables channel suppression for reset channels (threshold has to be set correctly)
* suppress_fpn - if set to "y" enables channel suppression for fpn channels (threshold has to be set correctly)
* suppress_pads - set to "y" enables channel suppression for TPC pad channels (threshold has to be set correctly)
* disable_reset1 - data suppression algorithm does not work for the channel "reset1" and it has to be suppressed explicitly by setting this value to "y". Normal value is "y".
* baseline_{reset,fpn,pads}[64] - waveform baseline for each PWB position
* threshold_{reset,fpn,pads} - waveform suppression threshold, see below:
* ch_threshold - PWB sca_N_ch_threshold, if set to 0, threshold is computed as "baseline_pads[seqpwb]-threshold_pads". Normal value is 0.
* test_mode - enable PWB test mode, the ADC data is replaced with a test pattern, see PWB esper variable signalproc/test_mode

== /Equipment/CTRL/Settings/TDC - TDC settings ==
* Enable - if set to "n", fectrl will tell the event builder that the TDC is not running. Normal value is "y".

== /Equipment/CTRL/Variables ==

* Scalers - TRG scalers and counters. from fectrl.cxx ReadTrgLocked()
<pre>
// 0..15 read the 16 base scalers at 0x100
// 16..31 read the adc16 scalers at 0x430
// 32..63 read the adc32 scalers at 0x440
// 64..79 read the 16 additional scalers at 0x110
// 80..95 read the 16 counters_adc_selected scalers at 0x460
// 96..159 read the 64 bar scalers at 0x470
// additional scalers should be appended at the end.
</pre>

== /Equipment/CTRL/EvbConfig - EVB configuration ==
All arrays have the same size corresponding to the number of EVB slots.
* name[] - slot name for the web page (trg01, adc01, adc01/adc32, pwb31/0, tdc01, etc)
* type[] - slot type: 1=TRG, 2=ADC16 and ADC32, 3=obsolete PWB, 4=obsolete PWB, 5=PWB, 6=TDC
* module[] - module number (adcNN, adcNN+100, pwbNN, etc)
* nbanks[] - number of expected banks (16 for ADC16, 32 for ADC32, not used, set to 1 for all others)
* tsfreq[] - timestamp frequency in Hz.

== /Equipment/ADC_UDP - ADC UDP configuration ==

* Common/Buffer - "BUFADC" - event buffer to use, name is hardwired in feevb.cxx
* Settings/udp_port - 50006 - UDP port number, also used by fectrl to configure the ADC modules
* Settings/rcv_bufsize - 209715200 - udp socket buffer size set by setsockopt(SOL_SOCKET, SO_RCVBUF). must have a corresponding command in /etc/rc.local to increase maximum system socket size: "/usr/sbin/sysctl -w net.core.rmem_max=200000000"
* Settings/packet_size - 1500 - non-jumbo-frame UDP packet maximum size
* Settings/max_buffered_packets - 40000 - maximum size of internal packet fifo. If it overflows, extra packets are discarded.
* Settings/max_packets_per_event - 8000 - how many UDP packets to pack into one midas event==

== /Equipment/PWB_X_UDP - PWB UDP configuration ==

For explanation see ADC_UDP above.

* Common/Buffer - "BUFUDP" - event buffer to use, name is hardwired in feevb.cxx
* Settings/udp_port - 50007, 50008, 50009, 50010 - for A, B, C and D UDP receivers respectively, also used by fectrl to configure the PWB modules
* Settings/rcv_bufsize - 209715200
* Settings/packet_size - 1500
* Settings/max_buffered_packets - 10000
* Settings/max_packets_per_event - 8000

= Trigger configuration =

These trigger modes are implemented:
* (manual trigger from web page)
* software pulser trigger (from fectrl)
* hardware pulser trigger (from the trigger board)
* NIM and eSATA trigger from ADC front panel inputs
* adc16 and adc32 discriminator triggers:
** adc16 grand-or trigger
** adc32 grand-or trigger
** adc (adc16+adc32) grand-or trigger
** adc16 multiplicity trigger (1ormore, 2ormore, 3ormore, 4ormore) for use with barrel scintillator
** anode wire multiplicity trigger (1ormore, 2ormore, 3ormore, 4ormore) (anode wire signals can be fed from adc16 or from adc32 signals)
** anode wire coincidence trigger
** anode wire MLU (memory lookup) trigger

== NIM trigger from ADC front panel ==

Trigger path:
<pre>
NIM signal --> LEMO input on ADC front panel --> data encoder --> data link to trigger board --> data decoder --> mask --> nim-esata-grand-or --> trigger
</pre>

To enable NIM trigger, do this:
* connect NIM signal to ADC front panel input
** Note1: NIM signal must be inverted
** Note2: LEMO connectors should be set to "NIM input" mode by ADC on-board jumpers (see ADC manual)
* observe correct bit goes to zero in the TRG web page: data link high work should change:
<pre>
0xNF00'0000 (N is the module id) to
0xN700'0000 (left lemo) or
0xNB00'0000 (right lemo)
</pre>
* Note3: if data link bits do not change, most likely the LEMO connectors are set to "DAC output" mode. Try to use LEMO inputs of a different ADC.
* compute the NIM mask: there are 32 bits, 2 bits per ADC data link. Bit 0x1 is right LEMO, bit 0x2 is left LEMO
* for example, to use left LEMO of ADC data link 12, set nim mask to (0x2)<<(2*12) = 0x02000000
* development branch of the git repository contains ''scripts/nim_mask.py'', which can compute forwards and backwards
* initialize the trigger board (on the TRG web page press button "initialize"), or start a new run
* on the history plot with "NIM grand or" counter, the rate should change from zero
* if a run is active, if one of the ADC LEMO outputs is set to output the trigger signal as a NIM pulse, one should see it fire use a scope. The delay or jitter between NIM trigger in and NIM trigger out should be around 100-200 ns (FIXME - measure this!)
* to set the DAQ to trigger on the NIM signal, on the run start page, check the box "TrigEsataNimGrandOr".
** Note: remember to set the scaledown to 0 if so desired.

= TPC field wire pulser =

The TPC field wire pulser input should be connected directly to the DAC output of ADC[0] (right lemo connector).

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for pulsing PWBs, baseline -1V, pulse height +2V (maximum possible pulse height in PWBs. Overdrives the AW ADC waveforms)
** dac_baseline: -8000
** dac_amplitude: 8000
** ramp_up_rate: 128
** ramp_down_rate: 70
** ramp_top_len: 128

* for pulsing AW, baseline -0.25V, pulse height +0.7V (AW ADC waveforms are in range. PWB waveforms are too small for goor time resolution)
** dac_baseline: -2000
** dac_amplitude: 4000
** ramp_up_rate: 20
** ramp_down_rate: 20
** ramp_top_len: 128

= BSC pulser =

The BSC pulser input on the BSC VME rear transition board (RTM) should be connected directly to the DAC output of ADC[4,5,6,7] (right lemo connector). (8 RTMs, but 4 ADCs, each signal is split using a LEMO "T" connector).

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for pulsing BSC, baseline -0.950V, pulse height +1.4V
** dac_baseline: -8000
** dac_amplitude: 4000
** ramp_up_rate: 64
** ramp_down_rate: 64
** ramp_top_len: 128

= NIM output =

To configure ADC analog output for NIM compatible pulse:

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for output of NIM pulse: baseline 0V, pulse height -0.9V, pulse width 100 ns
** dac_baseline: 0
** dac_amplitude: 8000
** ramp_up_rate: 128
** ramp_down_rate: 128
** ramp_top_len: 4
** dac_xor: 1 (invert the signal)

= TDC connections =

* SFP8 - fiber SFP to Juniper switch
* right RJ45 - 200MHz clock
* left RJ45 - external trigger

= MIDAS Data banks =

* ATAT - fectrl - UDP packets from GRIF-C/TRG trigger board
* TRBA - fetdc - TDC data
* TRTM - fetdc - TDC FPGA temperatures, TID_FLOAT[5].
* AAnn - feudp - UDP packets from GRIF-16 ADC (before the event builder), "nn" is the ADC module number: adc01 is AA01 through adc20 is AA20.
* BBxx - feudp - UDP packets from PWB, obsolete
* Bnnm, Cnnm - feevb - EVB output banks: ADC data, "nn" is the ADC module number (1..20), "m" is the channel number (0..9,A..F), format is same as AAnn banks.
* PAnn - feudp - UDP packets from PWB, "nn" is the PWB module number (00..99), obsolete
* PBnn - feudp - UDP packets from PWB, "nn" is the PWB module number (00..99), PB01 is pwb01, PB78 is pwb78
* PCnn - feevb - EVB output banks: PWB data, "nn" is the PWB module number (00..99), same as above, format is same as PBnn banks

= ZZZ =

ZZZ

TRG

2022-07-15T21:55:08Z

Olchansk: /* firmware 0x62d1c47e (Jul 2022) */

= TRG, the trigger control board for the ALPHA-g detector =

= Links =

* xxx
* https://bitbucket.org/expalpha/trg_firmware - firmware sources on bitbucket

= General characteristics =

== Photos ==

== Board schematics ==

* https://bitbucket.org/expalpha/trg_firmware/src/master/3xFMC_VME_Motherboard.pdf

== Available hardware ==

* Altera Stratix IV - main FPGA
* Altera Max V - boot FPGA
* boot flash: PC28F512M29EW - 512 Mbit parallel NOR flash.

= TRG front panel connections =

From top to bottom:

<pre>
|
| minisas-C - links 8-11
| minisas-D - links 12-15
|
| ethernet sfp - use copper sfp only
| minisas - not used, do not connect
| esata - clock in, trigger out
|
| minisas-A - links 0-3
| minisas-B - links 4-7
|
| LEDs
|
</pre>

MiniSAS and SATA flail cable connections:

<pre>
P1 <--> link 3
P2 <--> link 2
P3 <--> link 1
P4 <--> link 0
</pre>

LEDs:

<pre>
--PCB-- (left)
LED[0] - trigger out - ag_trig_out
LED[1] - network packet received - sfp_rx_data_valid
LED[2] - Xilinx FPGA boot ok - FMC1_CFG_DONE
LED[3] - not used
(right)
</pre>

= TRG onboard jumpers and switches =

* rotary switches: select IP address: 00=192.168.1.50, 11=.51, 22=.52, 33=.53, 44=.54, otherwire=.251

= Firmware update procedure =

* use quartus to generate the grifc.pof file (use grifc.cof)
* open quartus programmer
* attach grifc.pof to the 1st CFI_512 flash
* mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
* check that "initiate configuration after programming" is set in tools->options
* say "start"
* should take about 5 minutes
* grifc should reboot into the new firmware

If CFI_512 flash is not visible to the quartus programmer, load correct
code into the MaxV CPLD:

* open quartus programmer,
* say "auto detect"
* change file for the 5M2210 device
* use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
* say "program", it should finish in 10-15 seconds
* say "auto detect"
* CFI_512 flash should be visible now.

= Firmware revisions =

* 0x5bc8f90f - original firmware used for all data
* 0x6147c0f9 - added cbtrg, etc. installed at CERN on 20 Sep 2021.
* 0x618376ae - bigger cbtrg fifo, data rate tested up to 30 Mbytes/sec
* 0x6189c7f3 - fix loss of trigger packets. (missing fifo between alphag block and ethernet mux)
* 0x618b790b - fix loss of timestamps. (cbtrg inputs stretched to 100 ns long). installed at CERN 10 Nov 2021.

= Firmware build =

* use quartus 20.1
* see Makefile in the trg_firmware project

= Jtag remote connection =

* ssh agmini@daq16
* /opt/intelFPGA/16.1/quartus/bin/jtagd --config /home/agmini/.jtagd.conf
* netstat -an | grep 1309 ### note listen address is "0.0.0.0", NOT "127.0.0.1"
<pre>
tcp 0 0 0.0.0.0:1309 0.0.0.0:* LISTEN
</pre>
* opt/intelFPGA/16.1/quartus/bin/jtagconfig ### should work
* ssh olchansk@daq01
* cd git/trg_firmware
* /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
* jtagconfig ### should work
<pre>
daq01:trg_firmware$ jtagconfig
1) DE-SoC on daq16 [2-1.2.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) USB-Blaster on daq16 [2-1.3]
024090DD EP4SGX230(.|ES)
020A40DD 5M(1270ZF324|2210Z)/EPM2210

daq01:trg_firmware$
</pre>

= ALPHA-g trigger functions =

Trigger options:
* software trigger
* pulser trigger
* trigger on GRIF16 ADC NIM and ESATA inputs ("external trigger")
* adc16 grand-or
* adc32 grand-or
* adc16 wire multiplicity
* TPC anode wire per-preamp trigger (aw16 section)
** trigger on coincidences of preamps (removed fw 0x62c77f0b)
** trigger on multiplicity of preamps (removed fw 0x62c77f0b)
** trigger on specific topology of preamps (multiplicity of preamp clusters, etc) via the aw16_mlu trigger
* BSC trigger
** BSC grand_or
** BSC bar multiplicity
* coincidence trigger - select coincidence of external trigger, TPC AW grand-or, TPC AW MLU, BSC grand-or and BSC bar multiplicity triggers

== software trigger ==

to programmatically fire the trigger, one should:
* set the conf_enable_sw_trigger bit in conf_trig_enable, this will permit the software trigger to fire the trigger
* write value 0x4 to register 0x2B, this will cause the software trigger to fire

== pulser trigger ==

To use the pulser trigger, one should program:
* pulser period (in clocks)
* pulser width (in clocks, use value 5, the pulser no longer goes outside of the trigger board, so changing the width does not do anything)
* set the run_pulser bit in conf_trig_enable, this will cause the pulser to run
* set the enable_pulser bit in conf_trig_enable, this will cause the pulser to fire the trigger
* set the output_pulser bit in conf_trig_enable, this will cause the pulser to be output from the alphag firmware block (the pulser no longer goes outside of the trigger board, so changing the bit does not do anything)

== timeout trigger ==

The event builder uses event timestamps to assemble physics events. The timestamps
are usually 32 bit wide and run at 125 MHz (8 ns) or 62.5 MHz (16 ns). If
triggers are generated often (1 per second or more), timestamp wrap around
is easily detected by the event builder. If triggers come infrequently,
timestamp wrap around may occur while there are no triggers, not be seen
by the event builder causing loss of event synchronization.

To avoid this problem in the event builder, a timeout trigger should be generated
if no triggers were generated inside a 10 second interval.

The guaranties that even if all physics triggers temporarily stop for any reason,
the event builder will stay synchronized. (0.1 Hz timeout trigger frequency).

To enable the timeout trigger:
* program timeout trigger timeout in reg 0x43 in units of 8 ns clock
* enable it in bit 23 of [[#conf_trig_enable bits]]

== adc16 multiplicity trigger ==

This trigger is intended for use with the barrel scintillator signals connected to adc16 digitizers. It does not work well with TPC AW signals.

The 16 adc16 trigger bits (16x16=256) are added together to form the hit multiplicity value (adc16_mult, 16 bits, actual range 0 to 256).

Four threshold signals are computed: adc16_mult_1ormore = adc16_mult>=1, 2ormore, 3ormore, 4ormore.

There is a counter for each of these four signals.

Each of these four signals can fire the trigger, see [[#conf_trig_enable bits]].

== TPC anode wire triggers ==

=== aw16 bus ===

TPC Anode Wire trigger is based on the aw16[15:0] (xaw16) bus.

Each bit corresponds to one AW preamp. 16 preamps, 16 bits.

The aw16[15:0] bus can be fed by
* adc16_or16[15:0] - or16 of 100 MHz ADCs, 16 ADC sas links
* adc32_or16[15:0] - or16 of 62.5 MHz ADCs, FMC-ADC32 has 32 channels, so 2 bits per ADC: low 16 channels and high 16 channels, sas links 7..0
* adc32_or16[31:16] - or16 of 62.5 MHz ADCs, ditto, sas links 15..8
as selected by conf_enable_aw_adc16, conf_enable_aw_adc32a, conf_enable_aw_adc32b in [[#conf_control bits]]

<pre>
///////////////////////////////////////////////////////////
// TPC Anode Wire trigger logic (aw16)
///////////////////////////////////////////////////////////

// map adc signals into aw16

wire [15:0] aw16 = ({16{conf_enable_aw_adc16}} & adc16_or16[15:0]) |
({16{conf_enable_aw_adc32a}} & adc32_or16[15:0]) |
({16{conf_enable_aw_adc32b}} & adc32_or16[31:16]);
...
ag_conditioner cond_adc16_or16_0(.clk(clk), .in(aw16[0]), .out(xxaw16[0]));
...
xaw16 <= xxaw16;
</pre>

=== aw16_grand_or ===

TPC AW "grand or" trigger: use aw16_mult_1ormore (before fw 0x62c77f0b)

(256 anode wires, 16 wires per preamp, 16 preamps, 16 aw16 signals)

=== aw16_mlu ===

TPC AW preamp MLU trigger: the MLU (memory lookup
table) implements an arbitrary logical function
to map the 16 aw16 preamp signals into 1 aw16_mlu_trig trigger output.

Description of the aw16 mlu trigger.

In words:

* any aw16 signal starts the aw16_prompt_run gate
* aw16 signals are collected for the duration of conf_mlu_prompt (125MHz/8ns clock)
* this corresponds to time spread of TPC AW signals due to the drift time in the AW drift cell and to the variation in signal transmission time from the ADC to the TRG (digital trigger data link).
* when this prompt time expires, the MLU looks at the accumulated aw16_prompt bit pattern and makes the "yes/no" trigger decision
* after the trigger decision is made, we wait for the TPC to become quiet:
* we wait until all aw16 signals are empty (no timeout)
* we run the aw16_prompt_wait gate, length conf_mlu_wait (8ns clock), if any aw16 signals arrive, we wait for aw16 empty again, rinse, repeat.
* now, after TPC aw16 have been empty for conf_mlu_wait clocks (8ns clock), MLU trigger is ready for the next event.

In logic: (see alphag.v)

* aw16_or <= grand-or of 16 aw16 signals
* "aw16_or" starts the "aw16_prompt_cnt" counter, opens the aw16_prompt_run gate
* during the aw16_prompt_run gate, aw16_prompt collects (latches) the aw16 bits (aw16_prompt <= aw16_prompt | aw16)
* this is the time when we wait for all "prompt" signals from the TPC to arrive into the trigger
* at the end of the aw16_prompt_run gate, the signal aw16_prompt_out is pulsed, latching the output of the MLU into aw16_mlu_trig
* this is the MLU trigger "yes/no" trigger decision.
* after the MLU trigger decision is made, we wait for the arrival and passing of all TPC drift signals
* the aw16_prompt_wait_cnt and aw_prompt_wait gate opens
* if any new aw16 signals arrive (they are TPC drift signals at this time), the aw16_prompt_wait gate is restarted
* if no aw16 signals arrive during the full run of the aw16_prompt_wait gate ("TPC quiet time")
* the aw16_prompt_wait and aw16_prompt gates are cleared and the MLU trigger is ready for the next event.

Good settings are:
* conf_mlu_prompt: 64 (512 ns)
* conf_mlu_wait: 128 (1024 ns)

== BSC trigger ==

=== bsc_adc16 bus ===

The BSC trigger is based on the [15:0]bsc_adc16[7:0] bus: 16 trigger discriminator bits from 8 ADC sas links. (8*16 = 64+64 bars, top and bottom).

The bsc_adc16 bus can be fed from sas links 0..7 or 8..15, controlled by conf_bsc_adc16_a and conf_bsc_adc16_b bits on [[#conf_bsc_control bits]].

bsc_adc16 can be fed only from GRIF-16 100 MHz ADC trigger discriminators.

=== bsc64_top and bsc64_bot buses ===

* firmware 0x5bc8f90f: bsc_adc16 is remapped into 64 bits of top (bsc64_top) and bottom (bsc64_bot):
<pre>
ag_bsc_remap bsc_remap_a(.adc(bsc_adc16[0]), .bsc_bot(bsc64_bot[7:0]), .bsc_top(bsc64_top[7:0]));
ag_bsc_remap bsc_remap_b(.adc(bsc_adc16[1]), .bsc_bot(bsc64_bot[8+7:8+0]), .bsc_top(bsc64_top[8+7:8+0]));
ag_bsc_remap bsc_remap_c(.adc(bsc_adc16[2]), .bsc_bot(bsc64_bot[2*8+7:2*8+0]), .bsc_top(bsc64_top[2*8+7:2*8+0]));
ag_bsc_remap bsc_remap_d(.adc(bsc_adc16[3]), .bsc_bot(bsc64_bot[3*8+7:3*8+0]), .bsc_top(bsc64_top[3*8+7:3*8+0]));

ag_bsc_remap bsc_remap_e(.adc(bsc_adc16[4]), .bsc_bot(bsc64_bot[4*8+7:4*8+0]), .bsc_top(bsc64_top[4*8+7:4*8+0]));
ag_bsc_remap bsc_remap_f(.adc(bsc_adc16[5]), .bsc_bot(bsc64_bot[5*8+7:5*8+0]), .bsc_top(bsc64_top[5*8+7:5*8+0]));
ag_bsc_remap bsc_remap_g(.adc(bsc_adc16[6]), .bsc_bot(bsc64_bot[6*8+7:6*8+0]), .bsc_top(bsc64_top[6*8+7:6*8+0]));
ag_bsc_remap bsc_remap_h(.adc(bsc_adc16[7]), .bsc_bot(bsc64_bot[7*8+7:7*8+0]), .bsc_top(bsc64_top[7*8+7:7*8+0]));

module ag_bsc_remap
(
input wire [15:0] adc,
output wire [7:0] bsc_bot,
output wire [7:0] bsc_top
);

assign bsc_top[3] = adc[0];
assign bsc_top[2] = adc[1];
assign bsc_top[1] = adc[2];
assign bsc_top[0] = adc[3];

assign bsc_top[7] = adc[4];
assign bsc_top[6] = adc[5];
assign bsc_top[5] = adc[6];
assign bsc_top[4] = adc[7];

assign bsc_bot[0] = adc[8];
assign bsc_bot[1] = adc[9];
assign bsc_bot[2] = adc[10];
assign bsc_bot[3] = adc[11];

assign bsc_bot[4] = adc[12];
assign bsc_bot[5] = adc[13];
assign bsc_bot[6] = adc[14];
assign bsc_bot[7] = adc[15];

endmodule
</pre>

=== bsc64 bus ===

the bsc64 bus is the 64 bars used by the trigger, formed from bsc64_top and bsc64_bot:
<pre>
if (conf_bsc64_bot_only) begin
bsc64 <= bsc64_bot;
end else if (conf_bsc64_top_only) begin
bsc64 <= bsc64_top;
end else if (conf_bsc64_bot_top_or) begin
bsc64 <= bsc64_bot | bsc64_top;
end else if (conf_bsc64_bot_top_and) begin
bsc64 <= bsc64_bot & bsc64_top;
end else begin
bsc64 <= 64'b0;
end
</pre>

=== bsc_grand_or_trig ===

bsc_grand_or_trig is the grand-or of 64 bits of the bsc64 bus

to enable triggering on bsc_grand_or_trig, set corresponding bit in [[#conf_trig_enable bits]]

=== old bsc_mult_trig ===

(from fw 0x62c77f0b, old bsc_mult_trig was replaced by new bsc64 multiplicity trigger)

* bsc64_mult is computed as multiplicity of the bsc64 bus (number of 64 bsc64 bits that fired)
* bsc_mult_trig is computed:
<pre>
if (bsc64_mult >= conf_bsc64_mult) begin
bsc_mult_trig <= 1;
end else begin
bsc_mult_trig <= 0;
end
</pre>

to enable the bsc multiplicity trigger, set the multiplicity value conf_bsc64_mult in [[#conf_bsc_control bits]] and enable the corresponding bit in [[#conf_trig_enable bits]].

=== bsc64 multiplicity trigger ===

bsc64 BSC bar multiplicity trigger uses a time window. this time window is started by bsc64_grand_or and runs for conf_bsc64_mult_window clocks (8 nc clock). During this time, hits in bsc64_bus are accumulated (latched) and their multiplicity is computed. If multiplicity condition is satisfied (bigger or equal to conf_bsc64_mult_min), bsc64_mult_trig is fired and the bsc64 bit pattern is saved to the UDP packet. Then trigger waits for the bsc64_bus to be empty. Then trigger waits for conf_bsc64_empty_window clocks, if there is any bsc64 hits, we wait for empty again. So after bsc64 has been empty for conf_bsc64_empty_window clocks, multiplicity trigger is ready for the next event. This scheme cannot implement max multiplicity.

recommended values:
* conf_bsc64_mult_window (8 bits): slightly longer than 3 cycles of SAS link: 3*18 = 54 clocks, good value is 80 (640 ns).
* conf_bsc64_mult_min (8 bits): 2
* conf_bsc64_empty_window (8 bits): 80 (640 ns)

== Coincidence trigger ==

Coincidence trigger provides a combination of TPC, BSC and external scintillator (esata_nim_grand_or) signals:

<pre>
assign coinc_input[0] = aw16_grand_or; // was aw16_mult_1ormore;
assign coinc_input[1] = aw16_mlu_trig;
assign coinc_input[2] = bsc_grand_or_trig;
assign coinc_input[3] = bsc_mult_trig;
assign coinc_input[4] = esata_nim_grand_or;
assign coinc_input[5] = 0;
assign coinc_input[6] = 0;
assign coinc_input[7] = 0;
</pre>

Coincidence trigger "start" mask selects which of the inputs can start the coincidence window.

Coincidence trigger "require" mask selects which inputs must have a hits for the coincidence ot be satisfied.

Input hits are collected for the duration of the coincidence window, if all required inputs have hits, coinc_trig is fired.

Example settings:

* coincidence of external scintillator, BSC and TPC AW "grand or" signals: start 0x10, required 0x15
* coincidence of BSC and TPC AW "grand or" signals: start 0x4, required 0x5
* coincidence of BSC and TPC AW MLU triggers: start 0x4, required 0x6
* coincidence of BSC multiplicity and TPC AW MLU triggers: start 0x8, required 0xA

= Control registers =

== Register addresses ==

Note: all registers are 32 bits unless otherwise noted.

Note: RW means read-write register, RO means read-only, ROL means read-only, contents is latched by the "latch_out" bit

{| cellpadding="10" cellspacing="0" border="1"
! Address || Quartus Name || Access || FwRev || Description
|-
| 0x08 || num_sample || RW || GRIF-C || magic 16-bit register to control UDP packet size
|-
| 0x08 || scratch_reg || RW || 0x618b790b || 32-bit scratch register
|-
| 0x1F || compilation_time || RO || || Firmware revision
|-
| 0x20 || conf_trig_width || RW || || Trigger signal width, 16 ns clock
|-
| 0x21 || conf_busy_width || RW || || Busy signal width, 16 ns clock (not used)
|-
| 0x22 || conf_pulser_width || RW || || Pulser signal width, 16 ns clock
|-
| 0x23 || conf_pulser_period || RW || || Pulser signal period, 16 ns clock
|-
| 0x24 || conf_pulser_burst_ctrl || RW || 0x62d1c47e || Generate bursts of pulses: 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses, 16 ns clocks
|-
| 0x25 || conf_trig_enable || RW || || see [[#conf_trig_enable bits]]
|-
| 0x26 || || || not used
|-
| 0x27 || || || not used
|-
| 0x28 || || || not used
|-
| 0x29 || conf_nim_mask || RW || || enable bits for ADC NIM inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2A || conf_esata_mask || RW || || enable bits for ADC eSATA inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2B || reset_out, latch_out, trigger_out || W || || see [[#reg 0x2B bits]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x5bc8f90f || configure AW coincidence trigger, see [[#aw16_coinc]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x62c77f0b || removed
|-
| 0x2D || conf_aw16_coinc_b || RW || 0x5bc8f90f ||
|-
| 0x2E || conf_aw16_coinc_c || RW || 0x5bc8f90f ||
|-
| 0x2F || conf_aw16_coinc_d || RW || 0x5bc8f90f ||
|-
| 0x30 || sas_sd[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect for each link
|-
| 0x31 || pll_625_status || ROL || 0x5b2057f5 (12Jun18_16:32) || 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter
|-
| 0x32 || clk_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the system 125 MHz clock
|-
| 0x33 || clk_625_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625)
|-
| 0x34 || conf_control || RW || 0x5b398983 (01Jul18_19:10) || see [[#conf_control bits]] below
|-
| 0x35 || conf_drift_width || RW || 0x5b398983 (01Jul18_19:10) || width of drift time blank-out in 16 ns clocks
|-
| 0x36 || conf_scaledown || RW || 0x5b398983 (01Jul18_19:10) || trigger scaledown, 0=no scaledown, 1=divide-by-2, 2=divide-by-3, etc
|-
| 0x37 || conf_mlu || RW || 0x5b398983 (01Jul18_19:10) || AW MLU control bits, see [[#conf_mlu bits]]
|-
| 0x38 || conf_trig_delay || RW || 0x5baedfca (28Sep18_19:13) || delay the trigger pulse, 16 ns clock
|-
| 0x39 || esata_clk_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the TRG 125 MHz clock
|-
| 0x3A || esata_clk_esata_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the external clock (eSATA 62.5 MHz clock)
|-
| 0x3B || conf_counter_adc_select || RW || 0x5bb7f6ae (05Oct18_16:41) || select which 16 ADCs are connected to the selected adc counters, 0..15 - connect the adc16 signals, 16..47 connect the adc32 signals
|-
| 0x3C || sysreset_ts || RO || 0x5bb7f6ae (05Oct18_16:41) || 125MHz counter of VME-SYSRESET
|-
| 0x3C || || || 0x618b790b || not used
|-
| 0x3D || GRIF-C csr || RW || GRIF-C || <= csr & ~par_value; // Selective clear
|-
| 0x3E || GRIF-C csr || RW || GRIF-C || <= csr | par_value; // Selective set
|-
| 0x3F || GRIF-C csr || RW || GRIF-C || <= par_value; // write
|-
| 0x3D || || || 0x618b790b || not used
|-
| 0x3E || || || 0x618b790b || not used
|-
| 0x3F || || || 0x618b790b || not used
|-
| 0x40 || conf_bsc_control || RW || 0x5bc13541 (12Oct18_16:58) || Barrel Scintillator trigger control, see [[#conf_bsc_control bits]]
|-
| 0x41 || conf_coinc_control || RW || 0x5bc13541 (12Oct18_16:58) || Coincidence trigger control, see [[#conf_coinc_control bits]]
|-
| 0x42 || reconfig_out || WO || 0x5bc13541 (12Oct18_16:58) || reserved for rebooting the FPGA (does not work)
|-
| 0x43 || conf_trigger_timeout || RW || 0x5bc8f90f (18Oct18_14:20) || Generate timeout trigger if there is no other trigger after given timeout, in 8 ns clocks, must be enabled by bit conf_enable_timeout_trig in [[#conf_trig_enable bits]]
|-
| 0x44 || eth_clk_counter || ROL || 0x618b790b ||
|-
| 0x45 || eth_clk_eth_counter || ROL || 0x618b790b ||
|-
| 0x100 || ts_625 || ROL || || latched timestamp
|-
| 0x101 || counter_trig_out || ROL || || counter of issued triggers
|-
| 0x102 || counter_trig_in || ROL || || counter of triggers
|-
| 0x103 || counter_pulser || ROL || || counter of pulser
|-
| 0x104 || counter_adc16_grand_or || ROL ||
|-
| 0x105 || counter_adc32_grand_or || ROL ||
|-
| 0x106 || counter_adc_grand_or || ROL ||
|-
| 0x107 || counter_esata_nim_grand_or || ROL ||
|-
| 0x108 || counter_adc16_mult_1ormore || ROL ||
|-
| 0x109 || counter_adc16_mult_2ormore || ROL ||
|-
| 0x10A || counter_adc16_mult_3ormore || ROL ||
|-
| 0x10B || counter_adc16_mult_4ormore || ROL ||
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x5bc8f90f || counter of AW coincidence triggers
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x62c77f0b || removed
|-
| 0x10D || counter_aw16_coinc_b || ROL || 0x5bc8f90f ||
|-
| 0x10E || counter_aw16_coinc_c || ROL || 0x5bc8f90f ||
|-
| 0x10F || counter_aw16_coinc_d || ROL || 0x5bc8f90f ||
|-
| 0x110 || counter_drift || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the drift time blank-out
|-
| 0x111 || counter_scaledown || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the scaledown
|-
| 0x112 || counter_aw16_coinc || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW coincidence triggers
|-
| 0x113 || counter_aw16_mlu || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW MLU triggers
|-
| 0x114 || counter_aw16_grand_or || ROL || 0x62c77f0b || counter of AW grand-or triggers
|-
| 0x114 || counter_aw16_mult_1ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 1ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 2ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x62c77f0b || removed
|-
| 0x116 || counter_aw16_mult_3ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 3ormore triggers
|-
| 0x117 || counter_aw16_mult_4ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 4ormore triggers
|-
| 0x118 || counter_bsc_grand_or || ROL || 0x5bc13541 (12Oct18_16:58) || counter of BSC grand-or triggers
|-
| 0x119 || counter_bsc_mult || ROL || 0x5bc13541 (12Oct18_16:58) || counter of old BSC multiplicity triggers
|-
| 0x11A || counter_coinc || ROL || 0x5bc13541 (12Oct18_16:58) || counter of coincidence triggers
|-
| 0x11B || counter_timeout || ROL || 0x618b790b || counter of timeout triggers
|-
| 0x11C || counter_bsc_mult_start || ROL || 0x62c77f0b || counter of BSC multiplicity windows
|-
| 0x11D || counter_bsc_mult_trig || ROL || 0x62c77f0b || counter of BSC multiplicity triggers
|-
| 0x11E || counter_coinc_start || ROL || 0x62d1b152 || counter of coincidence windows
|-
| 0x11F || counter_aw16_mlu_start || ROL || 0x62d1b152 || counter of TPC AW MLU windows
|-
| 0x200..0x207 || conf_adc16_masks || RW || all || adc16 enable bits
|-
| 0x300..0x30F || conf_adc32_masks || RW || all || adc32 enable bits
|-
| 0x400..0x41F || sas_bits[15:0][63:0] || ROL || all || sas data bits for each link
|-
| 0x420..0x42F || sas_sd_counters[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect counter for each link
|-
| 0x430..0x43F || counters_adc16_or16[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 16 counters of adc16 ORes
|-
| 0x440..0x45F || counters_adc32_or16[31:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 32 counters of adc32 ORes
|-
| 0x460..0x46F || counters_adc_selected[15:0] || ROL || 0x5bb7f6ae (05Oct18_16:41) || 16 counters for selected group of adcs, see conf_counter_adc_select
|-
| 0x470..0x4AF || counters_bsc64[63:0] || ROL || 0x5bc13541 (12Oct18_16:58) || 64 counters for the BSC bars
|-
|}

== additional registers ==

<pre>
reg | rw/ro | quartus name | firmware | description
0x60: param_out <= {2'h3, par_id, chan, cb_control_out
0x61: param_out <= {2'h3, par_id, chan, cb_status
0x62: param_out <= {2'h3, par_id, chan, cb_invert_a_out };
0x63: param_out <= {2'h3, par_id, chan, cb_invert_b_out };
0x64: param_out <= {2'h3, par_id, chan, cb_enable_le_a_out };
0x65: param_out <= {2'h3, par_id, chan, cb_enable_le_b_out };
0x66: param_out <= {2'h3, par_id, chan, cb_enable_te_a_out };
0x67: param_out <= {2'h3, par_id, chan, cb_enable_te_b_out };
0x6A | ro | cb_input_num | 0x618b790b | chronobox number of inputs
0x6B: param_out <= {2'h3, par_id, chan, cb_sync_mask_a_out };
0x6C: param_out <= {2'h3, par_id, chan, cb_sync_mask_b_out };
0x6D: param_out <= {2'h3, par_id, chan, cb_sync_reg_out };
0x6E: param_out <= {2'h3, par_id, chan, cb_sync_status };
0x6F: param_out <= {2'h3, par_id, chan, cb_latch_period_out };
0x70: param_out <= {2'h3, par_id, chan, cb_fifo_status };
0x71: begin param_out <= {2'h3, par_id, chan, cb_fifo_data }; cb_fifo_rdack_out <= 1; end
0x72: param_out <= {2'h3, par_id, chan, cb_udp_period_out };
0x73: param_out <= {2'h3, par_id, chan, cb_udp_threshold_out };
</pre>

== conf_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_clock_select || 0x5b3aa19f (02Jul18_15:05) || select 0=internal 62.5 MHz clock or 1=esata 62.5 MHz clock
|-
| 1 || conf_enable_aw_adc16 || 0x5baedfca (28Sep18_19:13) || select source of TPC AW aw16 bus, see [[#aw16 bus]]
|-
| 2 || conf_enable_aw_adc32a || 0x5baedfca (28Sep18_19:13) ||
|-
| 3 || conf_enable_aw_adc32b || 0x5baedfca (28Sep18_19:13) ||
|-
| 15..4 || || ||
|-
| 23..16 || conf_mlu_prompt || 0x5b3aa19f (02Jul18_15:05) || MLU trigger prompt window, see [[#aw16_mlu]]
|-
| 31..24 || conf_mlu_wait || 0x5b3aa19f (02Jul18_15:05) || MLU trigger wait window, see [[#aw16_mlu]]
|-
|}

== conf_mlu bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 31 || mlu_reset || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 30 || mlu_write || 0x5b3aa19f (02Jul18_15:05) || 1=write data bit into given address
|-
| 16 || mlu_data || 0x5b3aa19f (02Jul18_15:05) || data bit for writing to MLU RAM
|-
| 15..0 || mlu_write_addr || 0x5b3aa19f (02Jul18_15:05) || MLU RAM write address for writing the data bit
|-
|}

== conf_bsc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_bsc_adc_a || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 0..7
|-
| 1 || conf_bsc_adc_b || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 8..15
|-
| 2 || conf_bsc64_bot_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses bottom channels only
|-
| 3 || conf_bsc64_top_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses top channels only
|-
| 4 || conf_bsc64_bot_top_or || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "or" of top and bottom
|-
| 5 || conf_bsc64_bot_top_and || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "and" of top and bottom
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_bsc64_mult_min || 0x5bc13541 (12Oct18_16:58) || minimum bsc64 multiplicity
|-
| 23..16 || conf_bsc64_empty_wondow || 0x62d1c47e || bsc64 empty window length, 8 ns clocks
|-
| 31..24 || conf_bsc64_mult_window || 0x62c77f0b || bsc64 multiplicity window length, 8 ns clocks
|-
|}

== conf_coinc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_coinc_required[0] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mult_1ormore
|-
| 0 || conf_coinc_required[0] || 0x62c77f0b || enable aw16_grand_or
|-
| 1 || conf_coinc_required[1] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mlu_trig
|-
| 2 || conf_coinc_required[2] || 0x5bc13541 (12Oct18_16:58) || enable bsc_grand_or_trig
|-
| 3 || conf_coinc_required[3] || 0x5bc13541 (12Oct18_16:58) || enable bsc_mult_trig
|-
| 3 || conf_coinc_required[3] || 0x62c77f0b || enable bsc64_mult_trig
|-
| 4 || conf_coinc_required[4] || 0x5bc13541 (12Oct18_16:58) || enable esata_nim_grand_or
|-
| 5 || conf_coinc_required[5]
|-
| 6 || conf_coinc_required[6]
|-
| 7 || conf_coinc_required[7]
|-
| 15..8 || conf_coinc_window[7:0] || 0x5bc13541 (12Oct18_16:58) || coincidence window length in units of 125MHz clock (8 ns)
|-
| 23..16 || conf_coinc_start[7:0] || 0x5bc13541 (12Oct18_16:58) || start the coincidence window, same bits as "required"
|-
| 31..24 ||
|-
|}

== conf_trig_enable bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_enable_sw_trigger || || trigger on software trigger (how generated???)
|-
| 1 || conf_enable_pulser || || trigger on pulser
|-
| 2 || - || 0x5b120c9f (01Jun18_20:18) || not used
|-
| 3 || conf_pulser_run || || allow the pulser to run (frequency has to be set beforehand)
|-
| 4 || conf_output_pulser || 0x5bc8f90f || does nothing (top level ag_pulser_out is disconnected)
|-
| 4 || || 0x618b790b || not used
|-
| 5 || conf_enable_esata_nim || || trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand)
|-
| 6 || conf_enable_adc16 || || trigger on adc16_grand_or
|-
| 7 || conf_enable_adc32 || || trigger on adc32_grand_or
|-
| 8 || conf_enable_adc16_1ormore || || trigger on adc16_mult_1ormore "1 or more"
|-
| 9 || conf_enable_adc16_2ormore || || same, "2 or more"
|-
| 10 || conf_enable_adc16_3ormore || || same, "3 or more"
|-
| 11 || conf_enable_adc16_4ormore || || same, "4 or more"
|-
| 12 || - || 0x5b08938c (25May18_15:51) || not used
|-
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
|-
| 14 || - || 0x5bc8f90f || not used
|-
| 15 || conf_enable_adc || 0x5b120c9f (01Jun18_20:18) || trigger on adc_grand_or
|-
| 16 || conf_enable_aw16_coinc_a || 0x5bc8f90f || enable AW coincidence trigger, see [[#aw16_coinc]]
|-
| 16 || - || 0x62c77f0b || aw16_coinc_x removed
|-
| 17 || conf_enable_aw16_coinc_b || 0x5bc8f90f ||
|-
| 18 || conf_enable_aw16_coinc_c || 0x5bc8f90f ||
|-
| 19 || conf_enable_aw16_coinc_d || 0x5bc8f90f ||
|-
| 20 || - || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 20 || conf_enable_aw16_grand_or || 0x618b790b || enable trigger on aw16_grand_or
|-
| 21 || conf_enable_aw16_coinc || 0x5b3aa19f (02Jul18_15:05) || enable trigger on aw16_coinc_trig
|-
| 22 || conf_enable_aw16_mlu || 0x5b3aa19f (02Jul18_15:05) || enable AW MLU trigger
|-
| 23 || conf_enable_timeout_trig || 0x5bc8f90f (18Oct18_14:20) || enable trigger timeout trigger
|-
| 24 || conf_enable_aw16_1ormore || 0x5b3aa19f (02Jul18_15:05) || trigger on aw16_mult_1ormore "1 or more"
|-
| 24 || - || 0x62c77f0b || aw16_mult_xxx removed
|-
| 25 || conf_enable_aw16_2ormore || 0x5b3aa19f (02Jul18_15:05) || same, "2 or more"
|-
| 26 || conf_enable_aw16_3ormore || 0x5b3aa19f (02Jul18_15:05) || same, "3 or more"
|-
| 27 || conf_enable_aw16_4ormore || 0x5b3aa19f (02Jul18_15:05) || same, "4 or more"
|-
| 28 || conf_enable_bsc_grand_or || 0x5bc13541 (12Oct18_16:58) || trigger on BSC grand-or
|-
| 29 || conf_enable_bsc_mult || 0x5bc13541 (12Oct18_16:58) || trigger on BSC multiplicity
|-
| 30 || conf_enable_coinc || 0x5bc13541 (12Oct18_16:58) || trigger on TPC/BSC/ext coincidence trigger
|-
| 31 || - || || not used
|-
|}

== reg 0x2B bits ==

Write to this register will pulse corresponding fpga signals:

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || reset_out || 0x5b120c9f (01Jun18_20:18) || reset counters, etc
|-
| 1 || latch_out || 0x5b120c9f (01Jun18_20:18) || latch counters, sas bits, etc
|-
| 2 || trigger_out || 0x5b120c9f (01Jun18_20:18) || generate a software trigger
|-
|}

= UDP data format =

== firmware 0x5bc8f90f ==

{| cellpadding="10" cellspacing="0" border="1"
! Offset || Name || Quartus name || FwRev || Description
|-
| 0 || packet counter || none || all || 31-bit UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
|-
| 1 || 0x8 packet header || || all || 28 bits of counter_trig_out
|-
| 2 || trigger timestamp || trig_ts || all || 62.5MHz trigger timestamp
|-
| 3 || accepted triggers || counter_trig_out || all || counter of accepted triggers
|-
| 4 || input triggers || counter_trig_in || all || counter of trigger input
|-
| 5 || pulser triggers || counter_pulser || all || counter of pulser triggers
|-
| 6 || trigger bitmap || udp_trig_bits || 0x5a48448d (30Dec17_17:59) || bitmap of trigger information, see below
|-
| 7 || nim bits || udp_nim_bits_masked || ??? || 32 bits of ADC NIM inputs (2 bits per ADC)
|-
| 8 || esata bits || udp_esata_bits_masked || ??? || 32 bits of ADC ESATA inputs (2 bits per ADC)
|-
| 9 || mlu bits || aw16_prompt || 0x5b398983 (01Jul18_19:10) || 16 bits of MLU input, 1 bit per preamp
|-
| 10 || drift-blank-off counter || udp_drift_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the drift blank-off
|-
| 11 || scaledown counter || udp_scaledown_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the scaledown
|-
| X || || || ||
|-
| 12 || 0xE packet footer || || all || 28 bits of counter_trig_out
|-
|}

== firmware 0x618b790b (Nov 2021) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

== firmware 0x62d1c47e (Jul 2022) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, 8'h00, 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= conf_fw_rev;
18 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

Values of udp_coinc_latch[7:0]:
* aaa

Values of udp_aw16_mult[7:0] and udp_aw16_bus[15:0]:
* aaa

Values of udp_bsc64_mult[7:0] and udp_bsc64_bus[63:0]
* aaa

== trigger bitmap ==

Firmware ??? (one of the very early revisions)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= adc16_coinc_top;
udp_trig_bits[5] <= adc16_coinc_bot;
udp_trig_bits[6] <= adc16_coinc;
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
udp_trig_bits[31:24] <= mult16[7:0];

</pre>

Firmware 0x5b08938c (25May18_15:51)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= 0; // not used
udp_trig_bits[31:24] <= mult16[7:0];
</pre>

Firmware 0x5b217dc4 (13Jun18_13:25)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5b3aa19f (02Jul18_15:05)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= udp_mlu_out;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5bc8f90f (18Oct18_14:20)

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_run_pulser
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = 0; // not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x618b790b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x62c77f0b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = 0; // aw16_coinc_a;
assign trig32_in[17] = 0; // aw16_coinc_b;
assign trig32_in[18] = 0; // aw16_coinc_c;
assign trig32_in[19] = 0; // aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = 0; // aw16_mult_1ormore;
assign trig32_in[25] = 0; // aw16_mult_2ormore;
assign trig32_in[26] = 0; // aw16_mult_3ormore;
assign trig32_in[27] = 0; // aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc64_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

= TRG chronobox inputs =

from trg_firmware/toplevel/grifc.v

<pre>
localparam CB_N = 23;
localparam CB_N1 = CB_N-1;

wire [CB_N1:0] cb_xinputs_async;

assign cb_xinputs_async[0] = ag_trig_out;
assign cb_xinputs_async[1] = ag_trig_scaledown_out;
assign cb_xinputs_async[2] = ag_trig_drift_out;
assign cb_xinputs_async[3] = ag_trig_received_out;

assign cb_xinputs_async[4] = ag_cb_sw_trig;
assign cb_xinputs_async[5] = ag_cb_pulser_trig;
assign cb_xinputs_async[6] = ag_cb_esata_nim_trig;
assign cb_xinputs_async[7] = ag_cb_adc16_grand_or_trig;
assign cb_xinputs_async[8] = ag_cb_adc32_grand_or_trig;

assign cb_xinputs_async[9] = ag_cb_aw16_grand_or_trig;
assign cb_xinputs_async[10] = ag_cb_aw16_mult_1ormore;
assign cb_xinputs_async[11] = ag_cb_aw16_mult_2ormore;
assign cb_xinputs_async[12] = ag_cb_aw16_mult_3ormore;
assign cb_xinputs_async[13] = ag_cb_aw16_mult_4ormore;
assign cb_xinputs_async[14] = ag_cb_aw16_mlu_trig;

assign cb_xinputs_async[15] = ag_cb_bsc64_grand_or_trig;
assign cb_xinputs_async[16] = ag_cb_bsc64_mult_1ormore;
assign cb_xinputs_async[17] = ag_cb_bsc64_mult_2ormore;
assign cb_xinputs_async[18] = ag_cb_bsc64_mult_3ormore;
assign cb_xinputs_async[19] = ag_cb_bsc64_mult_4ormore;
assign cb_xinputs_async[20] = ag_cb_bsc64_mult_trig;

assign cb_xinputs_async[21] = ag_cb_coinc_trig;

assign cb_xinputs_async[22] = ag_cb_timeout_trig;
</pre>

= Example UDP packets =

* trigger data, marker words 0x8

<pre>
ReadDataThread read 76
0: 0x003666ed -- UDP packet counter from UDP transmitter
1: 0x80000bf8 -- 0x8 is trigger data packet, 0xbf8 is the trigger counter from alphag.v
2: 0x2edf8b41 -- trigger data
3: 0x00000bf8
4: 0x00000bf8
5: 0x00000bee
6: 0x00000001
7: 0x00000000
8: 0x00000000
9: 0x00000003
10: 0x00000bf8
11: 0x00000bf8
12: 0x00000000
13: 0x00000000
14: 0x00000000
15: 0x00000000
16: 0x00000000
17: 0x00000000
18: 0xe0000bf8 -- 0xE is end of trigger data, counter 0xbf8 must match the counter in the 0x8 word.
ReadDataThread read 76 -- next packet
0: 0x003666ee -- UDP packet counter from UDP transmitter
...
</pre>

* chronobox fifo data, marker word 0xC, see [[Chronobox#FIFO_data_format]]

<pre>
ReadDataThread read 404
0: 0x003658ed -- UDP packet counter from UDP transmitter
1: 0xc000eacc -- 0xC is FIFO data, fifo packet counter 0xeacc from fifo_to_udp.v
2: 0x00000061 -- FIFO status, low bits the the word counter, so up to 0x61 fifo words are to follow
3: 0x87fb3d72 -- tsc hits
4: 0x8ffb3d74
5: 0x90fb3d74
6: 0x91fb3d74
7: 0x92fb3d74
8: 0x93fb3d74
9: 0x93fb3d75
10: 0x94fb3d74
11: 0x94fb3d77
12: 0x87fb3d77
13: 0x8ffb3d77
14: 0x90fb3d77
15: 0x91fb3d77
16: 0x92fb3d77
17: 0xfe000018 -- 0xFE scaler data starts, 0x18 words to follow
18: 0x00000000
19: 0x00000000
20: 0x00000000
21: 0x00000000
22: 0x00000000
23: 0x00000000
24: 0x00000000
25: 0x00000108
26: 0x00000000
27: 0x00000000
28: 0x00000000
29: 0x00000000
30: 0x00000000
31: 0x00000000
32: 0x00000000
33: 0x00000108
34: 0x00000108
35: 0x00000108
36: 0x00000108
37: 0x00000108
38: 0x00000108
39: 0x00000000
40: 0x00000000
41: 0xce56fa93 -- last word of scaler data is the sysclock counter (125 MHz)
42: 0xff800048 -- timestamp wraparound
43: 0x8f1f36e4 -- tsc hits
44: 0x901f36e4
45: 0x911f36e4
46: 0x921f36e4
47: 0x931f36e4
48: 0x941f36e4
49: 0x871f36e4
50: 0x871f36e7
51: 0x8f1f36e7
52: 0x901f36e9
53: 0x911f36e7
54: 0x921f36e9
55: 0x931f36e7
56: 0x941f36e9
57: 0x904330ac
58: 0x914330ac
59: 0x924330ac
60: 0x934330ac
61: 0x934330ad
62: 0x944330ac
63: 0x944330ad
64: 0x874330ac
65: 0x874330ad
66: 0x8f4330ac
67: 0x8f4330ad
68: 0x904330ad
69: 0x914330ad
70: 0x924330ad
71: 0x8f672a62
72: 0x90672a62
73: 0x91672a62
74: 0x92672a62
75: 0x93672a62
76: 0x94672a62
77: 0x87672a62
78: 0x87672a65
79: 0x8f672a65
80: 0x90672a65
81: 0x91672a65
82: 0x92672a65
83: 0x93672a65
84: 0x94672a65
85: 0xff000049
86: 0x878b2422
87: 0x8f8b2424
88: 0x908b2424
89: 0x918b2424
90: 0x928b2424
91: 0x938b2424
92: 0x938b2425
93: 0x948b2424
94: 0x948b2427
95: 0x878b2427
96: 0x8f8b2427
97: 0x908b2427
98: 0x918b2427
99: 0x928b2427
100: 0xe000eacc -- 0xE is end of fifo data, counter 0xeacc must match the counter in the 0xC word.
ReadDataThread read 344 -- next packet
...
</pre>

= TODO =

* DONE July 2022. add FwRev to the UDP data output
* RJ45 SFP: PROBLEM, D.A. CABLE: GOOD, Fiber SFP: ???. fix "write did not happen" (send udp write command, there is no reply, read returns old data as if write never happened). suspect udp "write" packet is lost?
* PROBLEM GONE Aug 2021. fix reply to wrong socket - udp packets should reply to same socket as they came from, udp data packets should be sent to same socket as requested them, not same socket as last command.
* DONE 2021jul30. add fixes from Chris P. for the auto-negotiation and dhcp (see email from him).
* DONE flash chip connected to FPGA. Aug 2021. implement ethernet flash programmer
* DONE Aug 2021. updated maxv firmware. implement FPGA reboot
* speed up programming the MLU by writing more than 1 bit at a time
* DONE Nov 2021. add 64-bit bitmap of BSC trigger bits
* DONE. add chronobox code
* DONE. add avalon mux for alphag and chronobox packets
* DONE. add chronobox fifo to udp packet sequencer
* check that TxReadyOut is correct and it is safe to send an avalon packet while previous packet is still transmitting.
* DONE. test fiber SFP is working
* complete the UDP flash programmer (parallel flash erase and write)

= End =

//KO

TRG

2022-07-15T21:51:11Z

Olchansk: /* firmware 0x618b790b (Nov 2021) */

= TRG, the trigger control board for the ALPHA-g detector =

= Links =

* xxx
* https://bitbucket.org/expalpha/trg_firmware - firmware sources on bitbucket

= General characteristics =

== Photos ==

== Board schematics ==

* https://bitbucket.org/expalpha/trg_firmware/src/master/3xFMC_VME_Motherboard.pdf

== Available hardware ==

* Altera Stratix IV - main FPGA
* Altera Max V - boot FPGA
* boot flash: PC28F512M29EW - 512 Mbit parallel NOR flash.

= TRG front panel connections =

From top to bottom:

<pre>
|
| minisas-C - links 8-11
| minisas-D - links 12-15
|
| ethernet sfp - use copper sfp only
| minisas - not used, do not connect
| esata - clock in, trigger out
|
| minisas-A - links 0-3
| minisas-B - links 4-7
|
| LEDs
|
</pre>

MiniSAS and SATA flail cable connections:

<pre>
P1 <--> link 3
P2 <--> link 2
P3 <--> link 1
P4 <--> link 0
</pre>

LEDs:

<pre>
--PCB-- (left)
LED[0] - trigger out - ag_trig_out
LED[1] - network packet received - sfp_rx_data_valid
LED[2] - Xilinx FPGA boot ok - FMC1_CFG_DONE
LED[3] - not used
(right)
</pre>

= TRG onboard jumpers and switches =

* rotary switches: select IP address: 00=192.168.1.50, 11=.51, 22=.52, 33=.53, 44=.54, otherwire=.251

= Firmware update procedure =

* use quartus to generate the grifc.pof file (use grifc.cof)
* open quartus programmer
* attach grifc.pof to the 1st CFI_512 flash
* mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
* check that "initiate configuration after programming" is set in tools->options
* say "start"
* should take about 5 minutes
* grifc should reboot into the new firmware

If CFI_512 flash is not visible to the quartus programmer, load correct
code into the MaxV CPLD:

* open quartus programmer,
* say "auto detect"
* change file for the 5M2210 device
* use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
* say "program", it should finish in 10-15 seconds
* say "auto detect"
* CFI_512 flash should be visible now.

= Firmware revisions =

* 0x5bc8f90f - original firmware used for all data
* 0x6147c0f9 - added cbtrg, etc. installed at CERN on 20 Sep 2021.
* 0x618376ae - bigger cbtrg fifo, data rate tested up to 30 Mbytes/sec
* 0x6189c7f3 - fix loss of trigger packets. (missing fifo between alphag block and ethernet mux)
* 0x618b790b - fix loss of timestamps. (cbtrg inputs stretched to 100 ns long). installed at CERN 10 Nov 2021.

= Firmware build =

* use quartus 20.1
* see Makefile in the trg_firmware project

= Jtag remote connection =

* ssh agmini@daq16
* /opt/intelFPGA/16.1/quartus/bin/jtagd --config /home/agmini/.jtagd.conf
* netstat -an | grep 1309 ### note listen address is "0.0.0.0", NOT "127.0.0.1"
<pre>
tcp 0 0 0.0.0.0:1309 0.0.0.0:* LISTEN
</pre>
* opt/intelFPGA/16.1/quartus/bin/jtagconfig ### should work
* ssh olchansk@daq01
* cd git/trg_firmware
* /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
* jtagconfig ### should work
<pre>
daq01:trg_firmware$ jtagconfig
1) DE-SoC on daq16 [2-1.2.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) USB-Blaster on daq16 [2-1.3]
024090DD EP4SGX230(.|ES)
020A40DD 5M(1270ZF324|2210Z)/EPM2210

daq01:trg_firmware$
</pre>

= ALPHA-g trigger functions =

Trigger options:
* software trigger
* pulser trigger
* trigger on GRIF16 ADC NIM and ESATA inputs ("external trigger")
* adc16 grand-or
* adc32 grand-or
* adc16 wire multiplicity
* TPC anode wire per-preamp trigger (aw16 section)
** trigger on coincidences of preamps (removed fw 0x62c77f0b)
** trigger on multiplicity of preamps (removed fw 0x62c77f0b)
** trigger on specific topology of preamps (multiplicity of preamp clusters, etc) via the aw16_mlu trigger
* BSC trigger
** BSC grand_or
** BSC bar multiplicity
* coincidence trigger - select coincidence of external trigger, TPC AW grand-or, TPC AW MLU, BSC grand-or and BSC bar multiplicity triggers

== software trigger ==

to programmatically fire the trigger, one should:
* set the conf_enable_sw_trigger bit in conf_trig_enable, this will permit the software trigger to fire the trigger
* write value 0x4 to register 0x2B, this will cause the software trigger to fire

== pulser trigger ==

To use the pulser trigger, one should program:
* pulser period (in clocks)
* pulser width (in clocks, use value 5, the pulser no longer goes outside of the trigger board, so changing the width does not do anything)
* set the run_pulser bit in conf_trig_enable, this will cause the pulser to run
* set the enable_pulser bit in conf_trig_enable, this will cause the pulser to fire the trigger
* set the output_pulser bit in conf_trig_enable, this will cause the pulser to be output from the alphag firmware block (the pulser no longer goes outside of the trigger board, so changing the bit does not do anything)

== timeout trigger ==

The event builder uses event timestamps to assemble physics events. The timestamps
are usually 32 bit wide and run at 125 MHz (8 ns) or 62.5 MHz (16 ns). If
triggers are generated often (1 per second or more), timestamp wrap around
is easily detected by the event builder. If triggers come infrequently,
timestamp wrap around may occur while there are no triggers, not be seen
by the event builder causing loss of event synchronization.

To avoid this problem in the event builder, a timeout trigger should be generated
if no triggers were generated inside a 10 second interval.

The guaranties that even if all physics triggers temporarily stop for any reason,
the event builder will stay synchronized. (0.1 Hz timeout trigger frequency).

To enable the timeout trigger:
* program timeout trigger timeout in reg 0x43 in units of 8 ns clock
* enable it in bit 23 of [[#conf_trig_enable bits]]

== adc16 multiplicity trigger ==

This trigger is intended for use with the barrel scintillator signals connected to adc16 digitizers. It does not work well with TPC AW signals.

The 16 adc16 trigger bits (16x16=256) are added together to form the hit multiplicity value (adc16_mult, 16 bits, actual range 0 to 256).

Four threshold signals are computed: adc16_mult_1ormore = adc16_mult>=1, 2ormore, 3ormore, 4ormore.

There is a counter for each of these four signals.

Each of these four signals can fire the trigger, see [[#conf_trig_enable bits]].

== TPC anode wire triggers ==

=== aw16 bus ===

TPC Anode Wire trigger is based on the aw16[15:0] (xaw16) bus.

Each bit corresponds to one AW preamp. 16 preamps, 16 bits.

The aw16[15:0] bus can be fed by
* adc16_or16[15:0] - or16 of 100 MHz ADCs, 16 ADC sas links
* adc32_or16[15:0] - or16 of 62.5 MHz ADCs, FMC-ADC32 has 32 channels, so 2 bits per ADC: low 16 channels and high 16 channels, sas links 7..0
* adc32_or16[31:16] - or16 of 62.5 MHz ADCs, ditto, sas links 15..8
as selected by conf_enable_aw_adc16, conf_enable_aw_adc32a, conf_enable_aw_adc32b in [[#conf_control bits]]

<pre>
///////////////////////////////////////////////////////////
// TPC Anode Wire trigger logic (aw16)
///////////////////////////////////////////////////////////

// map adc signals into aw16

wire [15:0] aw16 = ({16{conf_enable_aw_adc16}} & adc16_or16[15:0]) |
({16{conf_enable_aw_adc32a}} & adc32_or16[15:0]) |
({16{conf_enable_aw_adc32b}} & adc32_or16[31:16]);
...
ag_conditioner cond_adc16_or16_0(.clk(clk), .in(aw16[0]), .out(xxaw16[0]));
...
xaw16 <= xxaw16;
</pre>

=== aw16_grand_or ===

TPC AW "grand or" trigger: use aw16_mult_1ormore (before fw 0x62c77f0b)

(256 anode wires, 16 wires per preamp, 16 preamps, 16 aw16 signals)

=== aw16_mlu ===

TPC AW preamp MLU trigger: the MLU (memory lookup
table) implements an arbitrary logical function
to map the 16 aw16 preamp signals into 1 aw16_mlu_trig trigger output.

Description of the aw16 mlu trigger.

In words:

* any aw16 signal starts the aw16_prompt_run gate
* aw16 signals are collected for the duration of conf_mlu_prompt (125MHz/8ns clock)
* this corresponds to time spread of TPC AW signals due to the drift time in the AW drift cell and to the variation in signal transmission time from the ADC to the TRG (digital trigger data link).
* when this prompt time expires, the MLU looks at the accumulated aw16_prompt bit pattern and makes the "yes/no" trigger decision
* after the trigger decision is made, we wait for the TPC to become quiet:
* we wait until all aw16 signals are empty (no timeout)
* we run the aw16_prompt_wait gate, length conf_mlu_wait (8ns clock), if any aw16 signals arrive, we wait for aw16 empty again, rinse, repeat.
* now, after TPC aw16 have been empty for conf_mlu_wait clocks (8ns clock), MLU trigger is ready for the next event.

In logic: (see alphag.v)

* aw16_or <= grand-or of 16 aw16 signals
* "aw16_or" starts the "aw16_prompt_cnt" counter, opens the aw16_prompt_run gate
* during the aw16_prompt_run gate, aw16_prompt collects (latches) the aw16 bits (aw16_prompt <= aw16_prompt | aw16)
* this is the time when we wait for all "prompt" signals from the TPC to arrive into the trigger
* at the end of the aw16_prompt_run gate, the signal aw16_prompt_out is pulsed, latching the output of the MLU into aw16_mlu_trig
* this is the MLU trigger "yes/no" trigger decision.
* after the MLU trigger decision is made, we wait for the arrival and passing of all TPC drift signals
* the aw16_prompt_wait_cnt and aw_prompt_wait gate opens
* if any new aw16 signals arrive (they are TPC drift signals at this time), the aw16_prompt_wait gate is restarted
* if no aw16 signals arrive during the full run of the aw16_prompt_wait gate ("TPC quiet time")
* the aw16_prompt_wait and aw16_prompt gates are cleared and the MLU trigger is ready for the next event.

Good settings are:
* conf_mlu_prompt: 64 (512 ns)
* conf_mlu_wait: 128 (1024 ns)

== BSC trigger ==

=== bsc_adc16 bus ===

The BSC trigger is based on the [15:0]bsc_adc16[7:0] bus: 16 trigger discriminator bits from 8 ADC sas links. (8*16 = 64+64 bars, top and bottom).

The bsc_adc16 bus can be fed from sas links 0..7 or 8..15, controlled by conf_bsc_adc16_a and conf_bsc_adc16_b bits on [[#conf_bsc_control bits]].

bsc_adc16 can be fed only from GRIF-16 100 MHz ADC trigger discriminators.

=== bsc64_top and bsc64_bot buses ===

* firmware 0x5bc8f90f: bsc_adc16 is remapped into 64 bits of top (bsc64_top) and bottom (bsc64_bot):
<pre>
ag_bsc_remap bsc_remap_a(.adc(bsc_adc16[0]), .bsc_bot(bsc64_bot[7:0]), .bsc_top(bsc64_top[7:0]));
ag_bsc_remap bsc_remap_b(.adc(bsc_adc16[1]), .bsc_bot(bsc64_bot[8+7:8+0]), .bsc_top(bsc64_top[8+7:8+0]));
ag_bsc_remap bsc_remap_c(.adc(bsc_adc16[2]), .bsc_bot(bsc64_bot[2*8+7:2*8+0]), .bsc_top(bsc64_top[2*8+7:2*8+0]));
ag_bsc_remap bsc_remap_d(.adc(bsc_adc16[3]), .bsc_bot(bsc64_bot[3*8+7:3*8+0]), .bsc_top(bsc64_top[3*8+7:3*8+0]));

ag_bsc_remap bsc_remap_e(.adc(bsc_adc16[4]), .bsc_bot(bsc64_bot[4*8+7:4*8+0]), .bsc_top(bsc64_top[4*8+7:4*8+0]));
ag_bsc_remap bsc_remap_f(.adc(bsc_adc16[5]), .bsc_bot(bsc64_bot[5*8+7:5*8+0]), .bsc_top(bsc64_top[5*8+7:5*8+0]));
ag_bsc_remap bsc_remap_g(.adc(bsc_adc16[6]), .bsc_bot(bsc64_bot[6*8+7:6*8+0]), .bsc_top(bsc64_top[6*8+7:6*8+0]));
ag_bsc_remap bsc_remap_h(.adc(bsc_adc16[7]), .bsc_bot(bsc64_bot[7*8+7:7*8+0]), .bsc_top(bsc64_top[7*8+7:7*8+0]));

module ag_bsc_remap
(
input wire [15:0] adc,
output wire [7:0] bsc_bot,
output wire [7:0] bsc_top
);

assign bsc_top[3] = adc[0];
assign bsc_top[2] = adc[1];
assign bsc_top[1] = adc[2];
assign bsc_top[0] = adc[3];

assign bsc_top[7] = adc[4];
assign bsc_top[6] = adc[5];
assign bsc_top[5] = adc[6];
assign bsc_top[4] = adc[7];

assign bsc_bot[0] = adc[8];
assign bsc_bot[1] = adc[9];
assign bsc_bot[2] = adc[10];
assign bsc_bot[3] = adc[11];

assign bsc_bot[4] = adc[12];
assign bsc_bot[5] = adc[13];
assign bsc_bot[6] = adc[14];
assign bsc_bot[7] = adc[15];

endmodule
</pre>

=== bsc64 bus ===

the bsc64 bus is the 64 bars used by the trigger, formed from bsc64_top and bsc64_bot:
<pre>
if (conf_bsc64_bot_only) begin
bsc64 <= bsc64_bot;
end else if (conf_bsc64_top_only) begin
bsc64 <= bsc64_top;
end else if (conf_bsc64_bot_top_or) begin
bsc64 <= bsc64_bot | bsc64_top;
end else if (conf_bsc64_bot_top_and) begin
bsc64 <= bsc64_bot & bsc64_top;
end else begin
bsc64 <= 64'b0;
end
</pre>

=== bsc_grand_or_trig ===

bsc_grand_or_trig is the grand-or of 64 bits of the bsc64 bus

to enable triggering on bsc_grand_or_trig, set corresponding bit in [[#conf_trig_enable bits]]

=== old bsc_mult_trig ===

(from fw 0x62c77f0b, old bsc_mult_trig was replaced by new bsc64 multiplicity trigger)

* bsc64_mult is computed as multiplicity of the bsc64 bus (number of 64 bsc64 bits that fired)
* bsc_mult_trig is computed:
<pre>
if (bsc64_mult >= conf_bsc64_mult) begin
bsc_mult_trig <= 1;
end else begin
bsc_mult_trig <= 0;
end
</pre>

to enable the bsc multiplicity trigger, set the multiplicity value conf_bsc64_mult in [[#conf_bsc_control bits]] and enable the corresponding bit in [[#conf_trig_enable bits]].

=== bsc64 multiplicity trigger ===

bsc64 BSC bar multiplicity trigger uses a time window. this time window is started by bsc64_grand_or and runs for conf_bsc64_mult_window clocks (8 nc clock). During this time, hits in bsc64_bus are accumulated (latched) and their multiplicity is computed. If multiplicity condition is satisfied (bigger or equal to conf_bsc64_mult_min), bsc64_mult_trig is fired and the bsc64 bit pattern is saved to the UDP packet. Then trigger waits for the bsc64_bus to be empty. Then trigger waits for conf_bsc64_empty_window clocks, if there is any bsc64 hits, we wait for empty again. So after bsc64 has been empty for conf_bsc64_empty_window clocks, multiplicity trigger is ready for the next event. This scheme cannot implement max multiplicity.

recommended values:
* conf_bsc64_mult_window (8 bits): slightly longer than 3 cycles of SAS link: 3*18 = 54 clocks, good value is 80 (640 ns).
* conf_bsc64_mult_min (8 bits): 2
* conf_bsc64_empty_window (8 bits): 80 (640 ns)

== Coincidence trigger ==

Coincidence trigger provides a combination of TPC, BSC and external scintillator (esata_nim_grand_or) signals:

<pre>
assign coinc_input[0] = aw16_grand_or; // was aw16_mult_1ormore;
assign coinc_input[1] = aw16_mlu_trig;
assign coinc_input[2] = bsc_grand_or_trig;
assign coinc_input[3] = bsc_mult_trig;
assign coinc_input[4] = esata_nim_grand_or;
assign coinc_input[5] = 0;
assign coinc_input[6] = 0;
assign coinc_input[7] = 0;
</pre>

Coincidence trigger "start" mask selects which of the inputs can start the coincidence window.

Coincidence trigger "require" mask selects which inputs must have a hits for the coincidence ot be satisfied.

Input hits are collected for the duration of the coincidence window, if all required inputs have hits, coinc_trig is fired.

Example settings:

* coincidence of external scintillator, BSC and TPC AW "grand or" signals: start 0x10, required 0x15
* coincidence of BSC and TPC AW "grand or" signals: start 0x4, required 0x5
* coincidence of BSC and TPC AW MLU triggers: start 0x4, required 0x6
* coincidence of BSC multiplicity and TPC AW MLU triggers: start 0x8, required 0xA

= Control registers =

== Register addresses ==

Note: all registers are 32 bits unless otherwise noted.

Note: RW means read-write register, RO means read-only, ROL means read-only, contents is latched by the "latch_out" bit

{| cellpadding="10" cellspacing="0" border="1"
! Address || Quartus Name || Access || FwRev || Description
|-
| 0x08 || num_sample || RW || GRIF-C || magic 16-bit register to control UDP packet size
|-
| 0x08 || scratch_reg || RW || 0x618b790b || 32-bit scratch register
|-
| 0x1F || compilation_time || RO || || Firmware revision
|-
| 0x20 || conf_trig_width || RW || || Trigger signal width, 16 ns clock
|-
| 0x21 || conf_busy_width || RW || || Busy signal width, 16 ns clock (not used)
|-
| 0x22 || conf_pulser_width || RW || || Pulser signal width, 16 ns clock
|-
| 0x23 || conf_pulser_period || RW || || Pulser signal period, 16 ns clock
|-
| 0x24 || conf_pulser_burst_ctrl || RW || 0x62d1c47e || Generate bursts of pulses: 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses, 16 ns clocks
|-
| 0x25 || conf_trig_enable || RW || || see [[#conf_trig_enable bits]]
|-
| 0x26 || || || not used
|-
| 0x27 || || || not used
|-
| 0x28 || || || not used
|-
| 0x29 || conf_nim_mask || RW || || enable bits for ADC NIM inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2A || conf_esata_mask || RW || || enable bits for ADC eSATA inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2B || reset_out, latch_out, trigger_out || W || || see [[#reg 0x2B bits]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x5bc8f90f || configure AW coincidence trigger, see [[#aw16_coinc]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x62c77f0b || removed
|-
| 0x2D || conf_aw16_coinc_b || RW || 0x5bc8f90f ||
|-
| 0x2E || conf_aw16_coinc_c || RW || 0x5bc8f90f ||
|-
| 0x2F || conf_aw16_coinc_d || RW || 0x5bc8f90f ||
|-
| 0x30 || sas_sd[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect for each link
|-
| 0x31 || pll_625_status || ROL || 0x5b2057f5 (12Jun18_16:32) || 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter
|-
| 0x32 || clk_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the system 125 MHz clock
|-
| 0x33 || clk_625_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625)
|-
| 0x34 || conf_control || RW || 0x5b398983 (01Jul18_19:10) || see [[#conf_control bits]] below
|-
| 0x35 || conf_drift_width || RW || 0x5b398983 (01Jul18_19:10) || width of drift time blank-out in 16 ns clocks
|-
| 0x36 || conf_scaledown || RW || 0x5b398983 (01Jul18_19:10) || trigger scaledown, 0=no scaledown, 1=divide-by-2, 2=divide-by-3, etc
|-
| 0x37 || conf_mlu || RW || 0x5b398983 (01Jul18_19:10) || AW MLU control bits, see [[#conf_mlu bits]]
|-
| 0x38 || conf_trig_delay || RW || 0x5baedfca (28Sep18_19:13) || delay the trigger pulse, 16 ns clock
|-
| 0x39 || esata_clk_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the TRG 125 MHz clock
|-
| 0x3A || esata_clk_esata_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the external clock (eSATA 62.5 MHz clock)
|-
| 0x3B || conf_counter_adc_select || RW || 0x5bb7f6ae (05Oct18_16:41) || select which 16 ADCs are connected to the selected adc counters, 0..15 - connect the adc16 signals, 16..47 connect the adc32 signals
|-
| 0x3C || sysreset_ts || RO || 0x5bb7f6ae (05Oct18_16:41) || 125MHz counter of VME-SYSRESET
|-
| 0x3C || || || 0x618b790b || not used
|-
| 0x3D || GRIF-C csr || RW || GRIF-C || <= csr & ~par_value; // Selective clear
|-
| 0x3E || GRIF-C csr || RW || GRIF-C || <= csr | par_value; // Selective set
|-
| 0x3F || GRIF-C csr || RW || GRIF-C || <= par_value; // write
|-
| 0x3D || || || 0x618b790b || not used
|-
| 0x3E || || || 0x618b790b || not used
|-
| 0x3F || || || 0x618b790b || not used
|-
| 0x40 || conf_bsc_control || RW || 0x5bc13541 (12Oct18_16:58) || Barrel Scintillator trigger control, see [[#conf_bsc_control bits]]
|-
| 0x41 || conf_coinc_control || RW || 0x5bc13541 (12Oct18_16:58) || Coincidence trigger control, see [[#conf_coinc_control bits]]
|-
| 0x42 || reconfig_out || WO || 0x5bc13541 (12Oct18_16:58) || reserved for rebooting the FPGA (does not work)
|-
| 0x43 || conf_trigger_timeout || RW || 0x5bc8f90f (18Oct18_14:20) || Generate timeout trigger if there is no other trigger after given timeout, in 8 ns clocks, must be enabled by bit conf_enable_timeout_trig in [[#conf_trig_enable bits]]
|-
| 0x44 || eth_clk_counter || ROL || 0x618b790b ||
|-
| 0x45 || eth_clk_eth_counter || ROL || 0x618b790b ||
|-
| 0x100 || ts_625 || ROL || || latched timestamp
|-
| 0x101 || counter_trig_out || ROL || || counter of issued triggers
|-
| 0x102 || counter_trig_in || ROL || || counter of triggers
|-
| 0x103 || counter_pulser || ROL || || counter of pulser
|-
| 0x104 || counter_adc16_grand_or || ROL ||
|-
| 0x105 || counter_adc32_grand_or || ROL ||
|-
| 0x106 || counter_adc_grand_or || ROL ||
|-
| 0x107 || counter_esata_nim_grand_or || ROL ||
|-
| 0x108 || counter_adc16_mult_1ormore || ROL ||
|-
| 0x109 || counter_adc16_mult_2ormore || ROL ||
|-
| 0x10A || counter_adc16_mult_3ormore || ROL ||
|-
| 0x10B || counter_adc16_mult_4ormore || ROL ||
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x5bc8f90f || counter of AW coincidence triggers
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x62c77f0b || removed
|-
| 0x10D || counter_aw16_coinc_b || ROL || 0x5bc8f90f ||
|-
| 0x10E || counter_aw16_coinc_c || ROL || 0x5bc8f90f ||
|-
| 0x10F || counter_aw16_coinc_d || ROL || 0x5bc8f90f ||
|-
| 0x110 || counter_drift || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the drift time blank-out
|-
| 0x111 || counter_scaledown || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the scaledown
|-
| 0x112 || counter_aw16_coinc || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW coincidence triggers
|-
| 0x113 || counter_aw16_mlu || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW MLU triggers
|-
| 0x114 || counter_aw16_grand_or || ROL || 0x62c77f0b || counter of AW grand-or triggers
|-
| 0x114 || counter_aw16_mult_1ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 1ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 2ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x62c77f0b || removed
|-
| 0x116 || counter_aw16_mult_3ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 3ormore triggers
|-
| 0x117 || counter_aw16_mult_4ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 4ormore triggers
|-
| 0x118 || counter_bsc_grand_or || ROL || 0x5bc13541 (12Oct18_16:58) || counter of BSC grand-or triggers
|-
| 0x119 || counter_bsc_mult || ROL || 0x5bc13541 (12Oct18_16:58) || counter of old BSC multiplicity triggers
|-
| 0x11A || counter_coinc || ROL || 0x5bc13541 (12Oct18_16:58) || counter of coincidence triggers
|-
| 0x11B || counter_timeout || ROL || 0x618b790b || counter of timeout triggers
|-
| 0x11C || counter_bsc_mult_start || ROL || 0x62c77f0b || counter of BSC multiplicity windows
|-
| 0x11D || counter_bsc_mult_trig || ROL || 0x62c77f0b || counter of BSC multiplicity triggers
|-
| 0x11E || counter_coinc_start || ROL || 0x62d1b152 || counter of coincidence windows
|-
| 0x11F || counter_aw16_mlu_start || ROL || 0x62d1b152 || counter of TPC AW MLU windows
|-
| 0x200..0x207 || conf_adc16_masks || RW || all || adc16 enable bits
|-
| 0x300..0x30F || conf_adc32_masks || RW || all || adc32 enable bits
|-
| 0x400..0x41F || sas_bits[15:0][63:0] || ROL || all || sas data bits for each link
|-
| 0x420..0x42F || sas_sd_counters[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect counter for each link
|-
| 0x430..0x43F || counters_adc16_or16[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 16 counters of adc16 ORes
|-
| 0x440..0x45F || counters_adc32_or16[31:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 32 counters of adc32 ORes
|-
| 0x460..0x46F || counters_adc_selected[15:0] || ROL || 0x5bb7f6ae (05Oct18_16:41) || 16 counters for selected group of adcs, see conf_counter_adc_select
|-
| 0x470..0x4AF || counters_bsc64[63:0] || ROL || 0x5bc13541 (12Oct18_16:58) || 64 counters for the BSC bars
|-
|}

== additional registers ==

<pre>
reg | rw/ro | quartus name | firmware | description
0x60: param_out <= {2'h3, par_id, chan, cb_control_out
0x61: param_out <= {2'h3, par_id, chan, cb_status
0x62: param_out <= {2'h3, par_id, chan, cb_invert_a_out };
0x63: param_out <= {2'h3, par_id, chan, cb_invert_b_out };
0x64: param_out <= {2'h3, par_id, chan, cb_enable_le_a_out };
0x65: param_out <= {2'h3, par_id, chan, cb_enable_le_b_out };
0x66: param_out <= {2'h3, par_id, chan, cb_enable_te_a_out };
0x67: param_out <= {2'h3, par_id, chan, cb_enable_te_b_out };
0x6A | ro | cb_input_num | 0x618b790b | chronobox number of inputs
0x6B: param_out <= {2'h3, par_id, chan, cb_sync_mask_a_out };
0x6C: param_out <= {2'h3, par_id, chan, cb_sync_mask_b_out };
0x6D: param_out <= {2'h3, par_id, chan, cb_sync_reg_out };
0x6E: param_out <= {2'h3, par_id, chan, cb_sync_status };
0x6F: param_out <= {2'h3, par_id, chan, cb_latch_period_out };
0x70: param_out <= {2'h3, par_id, chan, cb_fifo_status };
0x71: begin param_out <= {2'h3, par_id, chan, cb_fifo_data }; cb_fifo_rdack_out <= 1; end
0x72: param_out <= {2'h3, par_id, chan, cb_udp_period_out };
0x73: param_out <= {2'h3, par_id, chan, cb_udp_threshold_out };
</pre>

== conf_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_clock_select || 0x5b3aa19f (02Jul18_15:05) || select 0=internal 62.5 MHz clock or 1=esata 62.5 MHz clock
|-
| 1 || conf_enable_aw_adc16 || 0x5baedfca (28Sep18_19:13) || select source of TPC AW aw16 bus, see [[#aw16 bus]]
|-
| 2 || conf_enable_aw_adc32a || 0x5baedfca (28Sep18_19:13) ||
|-
| 3 || conf_enable_aw_adc32b || 0x5baedfca (28Sep18_19:13) ||
|-
| 15..4 || || ||
|-
| 23..16 || conf_mlu_prompt || 0x5b3aa19f (02Jul18_15:05) || MLU trigger prompt window, see [[#aw16_mlu]]
|-
| 31..24 || conf_mlu_wait || 0x5b3aa19f (02Jul18_15:05) || MLU trigger wait window, see [[#aw16_mlu]]
|-
|}

== conf_mlu bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 31 || mlu_reset || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 30 || mlu_write || 0x5b3aa19f (02Jul18_15:05) || 1=write data bit into given address
|-
| 16 || mlu_data || 0x5b3aa19f (02Jul18_15:05) || data bit for writing to MLU RAM
|-
| 15..0 || mlu_write_addr || 0x5b3aa19f (02Jul18_15:05) || MLU RAM write address for writing the data bit
|-
|}

== conf_bsc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_bsc_adc_a || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 0..7
|-
| 1 || conf_bsc_adc_b || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 8..15
|-
| 2 || conf_bsc64_bot_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses bottom channels only
|-
| 3 || conf_bsc64_top_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses top channels only
|-
| 4 || conf_bsc64_bot_top_or || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "or" of top and bottom
|-
| 5 || conf_bsc64_bot_top_and || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "and" of top and bottom
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_bsc64_mult_min || 0x5bc13541 (12Oct18_16:58) || minimum bsc64 multiplicity
|-
| 23..16 || conf_bsc64_empty_wondow || 0x62d1c47e || bsc64 empty window length, 8 ns clocks
|-
| 31..24 || conf_bsc64_mult_window || 0x62c77f0b || bsc64 multiplicity window length, 8 ns clocks
|-
|}

== conf_coinc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_coinc_required[0] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mult_1ormore
|-
| 0 || conf_coinc_required[0] || 0x62c77f0b || enable aw16_grand_or
|-
| 1 || conf_coinc_required[1] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mlu_trig
|-
| 2 || conf_coinc_required[2] || 0x5bc13541 (12Oct18_16:58) || enable bsc_grand_or_trig
|-
| 3 || conf_coinc_required[3] || 0x5bc13541 (12Oct18_16:58) || enable bsc_mult_trig
|-
| 3 || conf_coinc_required[3] || 0x62c77f0b || enable bsc64_mult_trig
|-
| 4 || conf_coinc_required[4] || 0x5bc13541 (12Oct18_16:58) || enable esata_nim_grand_or
|-
| 5 || conf_coinc_required[5]
|-
| 6 || conf_coinc_required[6]
|-
| 7 || conf_coinc_required[7]
|-
| 15..8 || conf_coinc_window[7:0] || 0x5bc13541 (12Oct18_16:58) || coincidence window length in units of 125MHz clock (8 ns)
|-
| 23..16 || conf_coinc_start[7:0] || 0x5bc13541 (12Oct18_16:58) || start the coincidence window, same bits as "required"
|-
| 31..24 ||
|-
|}

== conf_trig_enable bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_enable_sw_trigger || || trigger on software trigger (how generated???)
|-
| 1 || conf_enable_pulser || || trigger on pulser
|-
| 2 || - || 0x5b120c9f (01Jun18_20:18) || not used
|-
| 3 || conf_pulser_run || || allow the pulser to run (frequency has to be set beforehand)
|-
| 4 || conf_output_pulser || 0x5bc8f90f || does nothing (top level ag_pulser_out is disconnected)
|-
| 4 || || 0x618b790b || not used
|-
| 5 || conf_enable_esata_nim || || trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand)
|-
| 6 || conf_enable_adc16 || || trigger on adc16_grand_or
|-
| 7 || conf_enable_adc32 || || trigger on adc32_grand_or
|-
| 8 || conf_enable_adc16_1ormore || || trigger on adc16_mult_1ormore "1 or more"
|-
| 9 || conf_enable_adc16_2ormore || || same, "2 or more"
|-
| 10 || conf_enable_adc16_3ormore || || same, "3 or more"
|-
| 11 || conf_enable_adc16_4ormore || || same, "4 or more"
|-
| 12 || - || 0x5b08938c (25May18_15:51) || not used
|-
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
|-
| 14 || - || 0x5bc8f90f || not used
|-
| 15 || conf_enable_adc || 0x5b120c9f (01Jun18_20:18) || trigger on adc_grand_or
|-
| 16 || conf_enable_aw16_coinc_a || 0x5bc8f90f || enable AW coincidence trigger, see [[#aw16_coinc]]
|-
| 16 || - || 0x62c77f0b || aw16_coinc_x removed
|-
| 17 || conf_enable_aw16_coinc_b || 0x5bc8f90f ||
|-
| 18 || conf_enable_aw16_coinc_c || 0x5bc8f90f ||
|-
| 19 || conf_enable_aw16_coinc_d || 0x5bc8f90f ||
|-
| 20 || - || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 20 || conf_enable_aw16_grand_or || 0x618b790b || enable trigger on aw16_grand_or
|-
| 21 || conf_enable_aw16_coinc || 0x5b3aa19f (02Jul18_15:05) || enable trigger on aw16_coinc_trig
|-
| 22 || conf_enable_aw16_mlu || 0x5b3aa19f (02Jul18_15:05) || enable AW MLU trigger
|-
| 23 || conf_enable_timeout_trig || 0x5bc8f90f (18Oct18_14:20) || enable trigger timeout trigger
|-
| 24 || conf_enable_aw16_1ormore || 0x5b3aa19f (02Jul18_15:05) || trigger on aw16_mult_1ormore "1 or more"
|-
| 24 || - || 0x62c77f0b || aw16_mult_xxx removed
|-
| 25 || conf_enable_aw16_2ormore || 0x5b3aa19f (02Jul18_15:05) || same, "2 or more"
|-
| 26 || conf_enable_aw16_3ormore || 0x5b3aa19f (02Jul18_15:05) || same, "3 or more"
|-
| 27 || conf_enable_aw16_4ormore || 0x5b3aa19f (02Jul18_15:05) || same, "4 or more"
|-
| 28 || conf_enable_bsc_grand_or || 0x5bc13541 (12Oct18_16:58) || trigger on BSC grand-or
|-
| 29 || conf_enable_bsc_mult || 0x5bc13541 (12Oct18_16:58) || trigger on BSC multiplicity
|-
| 30 || conf_enable_coinc || 0x5bc13541 (12Oct18_16:58) || trigger on TPC/BSC/ext coincidence trigger
|-
| 31 || - || || not used
|-
|}

== reg 0x2B bits ==

Write to this register will pulse corresponding fpga signals:

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || reset_out || 0x5b120c9f (01Jun18_20:18) || reset counters, etc
|-
| 1 || latch_out || 0x5b120c9f (01Jun18_20:18) || latch counters, sas bits, etc
|-
| 2 || trigger_out || 0x5b120c9f (01Jun18_20:18) || generate a software trigger
|-
|}

= UDP data format =

== firmware 0x5bc8f90f ==

{| cellpadding="10" cellspacing="0" border="1"
! Offset || Name || Quartus name || FwRev || Description
|-
| 0 || packet counter || none || all || 31-bit UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
|-
| 1 || 0x8 packet header || || all || 28 bits of counter_trig_out
|-
| 2 || trigger timestamp || trig_ts || all || 62.5MHz trigger timestamp
|-
| 3 || accepted triggers || counter_trig_out || all || counter of accepted triggers
|-
| 4 || input triggers || counter_trig_in || all || counter of trigger input
|-
| 5 || pulser triggers || counter_pulser || all || counter of pulser triggers
|-
| 6 || trigger bitmap || udp_trig_bits || 0x5a48448d (30Dec17_17:59) || bitmap of trigger information, see below
|-
| 7 || nim bits || udp_nim_bits_masked || ??? || 32 bits of ADC NIM inputs (2 bits per ADC)
|-
| 8 || esata bits || udp_esata_bits_masked || ??? || 32 bits of ADC ESATA inputs (2 bits per ADC)
|-
| 9 || mlu bits || aw16_prompt || 0x5b398983 (01Jul18_19:10) || 16 bits of MLU input, 1 bit per preamp
|-
| 10 || drift-blank-off counter || udp_drift_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the drift blank-off
|-
| 11 || scaledown counter || udp_scaledown_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the scaledown
|-
| X || || || ||
|-
| 12 || 0xE packet footer || || all || 28 bits of counter_trig_out
|-
|}

== firmware 0x618b790b (Nov 2021) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

== firmware 0x62d1c47e (Jul 2022) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

== trigger bitmap ==

Firmware ??? (one of the very early revisions)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= adc16_coinc_top;
udp_trig_bits[5] <= adc16_coinc_bot;
udp_trig_bits[6] <= adc16_coinc;
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
udp_trig_bits[31:24] <= mult16[7:0];

</pre>

Firmware 0x5b08938c (25May18_15:51)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= 0; // not used
udp_trig_bits[31:24] <= mult16[7:0];
</pre>

Firmware 0x5b217dc4 (13Jun18_13:25)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5b3aa19f (02Jul18_15:05)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= udp_mlu_out;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5bc8f90f (18Oct18_14:20)

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_run_pulser
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = 0; // not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x618b790b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x62c77f0b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = 0; // aw16_coinc_a;
assign trig32_in[17] = 0; // aw16_coinc_b;
assign trig32_in[18] = 0; // aw16_coinc_c;
assign trig32_in[19] = 0; // aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = 0; // aw16_mult_1ormore;
assign trig32_in[25] = 0; // aw16_mult_2ormore;
assign trig32_in[26] = 0; // aw16_mult_3ormore;
assign trig32_in[27] = 0; // aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc64_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

= TRG chronobox inputs =

from trg_firmware/toplevel/grifc.v

<pre>
localparam CB_N = 23;
localparam CB_N1 = CB_N-1;

wire [CB_N1:0] cb_xinputs_async;

assign cb_xinputs_async[0] = ag_trig_out;
assign cb_xinputs_async[1] = ag_trig_scaledown_out;
assign cb_xinputs_async[2] = ag_trig_drift_out;
assign cb_xinputs_async[3] = ag_trig_received_out;

assign cb_xinputs_async[4] = ag_cb_sw_trig;
assign cb_xinputs_async[5] = ag_cb_pulser_trig;
assign cb_xinputs_async[6] = ag_cb_esata_nim_trig;
assign cb_xinputs_async[7] = ag_cb_adc16_grand_or_trig;
assign cb_xinputs_async[8] = ag_cb_adc32_grand_or_trig;

assign cb_xinputs_async[9] = ag_cb_aw16_grand_or_trig;
assign cb_xinputs_async[10] = ag_cb_aw16_mult_1ormore;
assign cb_xinputs_async[11] = ag_cb_aw16_mult_2ormore;
assign cb_xinputs_async[12] = ag_cb_aw16_mult_3ormore;
assign cb_xinputs_async[13] = ag_cb_aw16_mult_4ormore;
assign cb_xinputs_async[14] = ag_cb_aw16_mlu_trig;

assign cb_xinputs_async[15] = ag_cb_bsc64_grand_or_trig;
assign cb_xinputs_async[16] = ag_cb_bsc64_mult_1ormore;
assign cb_xinputs_async[17] = ag_cb_bsc64_mult_2ormore;
assign cb_xinputs_async[18] = ag_cb_bsc64_mult_3ormore;
assign cb_xinputs_async[19] = ag_cb_bsc64_mult_4ormore;
assign cb_xinputs_async[20] = ag_cb_bsc64_mult_trig;

assign cb_xinputs_async[21] = ag_cb_coinc_trig;

assign cb_xinputs_async[22] = ag_cb_timeout_trig;
</pre>

= Example UDP packets =

* trigger data, marker words 0x8

<pre>
ReadDataThread read 76
0: 0x003666ed -- UDP packet counter from UDP transmitter
1: 0x80000bf8 -- 0x8 is trigger data packet, 0xbf8 is the trigger counter from alphag.v
2: 0x2edf8b41 -- trigger data
3: 0x00000bf8
4: 0x00000bf8
5: 0x00000bee
6: 0x00000001
7: 0x00000000
8: 0x00000000
9: 0x00000003
10: 0x00000bf8
11: 0x00000bf8
12: 0x00000000
13: 0x00000000
14: 0x00000000
15: 0x00000000
16: 0x00000000
17: 0x00000000
18: 0xe0000bf8 -- 0xE is end of trigger data, counter 0xbf8 must match the counter in the 0x8 word.
ReadDataThread read 76 -- next packet
0: 0x003666ee -- UDP packet counter from UDP transmitter
...
</pre>

* chronobox fifo data, marker word 0xC, see [[Chronobox#FIFO_data_format]]

<pre>
ReadDataThread read 404
0: 0x003658ed -- UDP packet counter from UDP transmitter
1: 0xc000eacc -- 0xC is FIFO data, fifo packet counter 0xeacc from fifo_to_udp.v
2: 0x00000061 -- FIFO status, low bits the the word counter, so up to 0x61 fifo words are to follow
3: 0x87fb3d72 -- tsc hits
4: 0x8ffb3d74
5: 0x90fb3d74
6: 0x91fb3d74
7: 0x92fb3d74
8: 0x93fb3d74
9: 0x93fb3d75
10: 0x94fb3d74
11: 0x94fb3d77
12: 0x87fb3d77
13: 0x8ffb3d77
14: 0x90fb3d77
15: 0x91fb3d77
16: 0x92fb3d77
17: 0xfe000018 -- 0xFE scaler data starts, 0x18 words to follow
18: 0x00000000
19: 0x00000000
20: 0x00000000
21: 0x00000000
22: 0x00000000
23: 0x00000000
24: 0x00000000
25: 0x00000108
26: 0x00000000
27: 0x00000000
28: 0x00000000
29: 0x00000000
30: 0x00000000
31: 0x00000000
32: 0x00000000
33: 0x00000108
34: 0x00000108
35: 0x00000108
36: 0x00000108
37: 0x00000108
38: 0x00000108
39: 0x00000000
40: 0x00000000
41: 0xce56fa93 -- last word of scaler data is the sysclock counter (125 MHz)
42: 0xff800048 -- timestamp wraparound
43: 0x8f1f36e4 -- tsc hits
44: 0x901f36e4
45: 0x911f36e4
46: 0x921f36e4
47: 0x931f36e4
48: 0x941f36e4
49: 0x871f36e4
50: 0x871f36e7
51: 0x8f1f36e7
52: 0x901f36e9
53: 0x911f36e7
54: 0x921f36e9
55: 0x931f36e7
56: 0x941f36e9
57: 0x904330ac
58: 0x914330ac
59: 0x924330ac
60: 0x934330ac
61: 0x934330ad
62: 0x944330ac
63: 0x944330ad
64: 0x874330ac
65: 0x874330ad
66: 0x8f4330ac
67: 0x8f4330ad
68: 0x904330ad
69: 0x914330ad
70: 0x924330ad
71: 0x8f672a62
72: 0x90672a62
73: 0x91672a62
74: 0x92672a62
75: 0x93672a62
76: 0x94672a62
77: 0x87672a62
78: 0x87672a65
79: 0x8f672a65
80: 0x90672a65
81: 0x91672a65
82: 0x92672a65
83: 0x93672a65
84: 0x94672a65
85: 0xff000049
86: 0x878b2422
87: 0x8f8b2424
88: 0x908b2424
89: 0x918b2424
90: 0x928b2424
91: 0x938b2424
92: 0x938b2425
93: 0x948b2424
94: 0x948b2427
95: 0x878b2427
96: 0x8f8b2427
97: 0x908b2427
98: 0x918b2427
99: 0x928b2427
100: 0xe000eacc -- 0xE is end of fifo data, counter 0xeacc must match the counter in the 0xC word.
ReadDataThread read 344 -- next packet
...
</pre>

= TODO =

* DONE July 2022. add FwRev to the UDP data output
* RJ45 SFP: PROBLEM, D.A. CABLE: GOOD, Fiber SFP: ???. fix "write did not happen" (send udp write command, there is no reply, read returns old data as if write never happened). suspect udp "write" packet is lost?
* PROBLEM GONE Aug 2021. fix reply to wrong socket - udp packets should reply to same socket as they came from, udp data packets should be sent to same socket as requested them, not same socket as last command.
* DONE 2021jul30. add fixes from Chris P. for the auto-negotiation and dhcp (see email from him).
* DONE flash chip connected to FPGA. Aug 2021. implement ethernet flash programmer
* DONE Aug 2021. updated maxv firmware. implement FPGA reboot
* speed up programming the MLU by writing more than 1 bit at a time
* DONE Nov 2021. add 64-bit bitmap of BSC trigger bits
* DONE. add chronobox code
* DONE. add avalon mux for alphag and chronobox packets
* DONE. add chronobox fifo to udp packet sequencer
* check that TxReadyOut is correct and it is safe to send an avalon packet while previous packet is still transmitting.
* DONE. test fiber SFP is working
* complete the UDP flash programmer (parallel flash erase and write)

= End =

//KO

TRG

2022-07-15T21:50:01Z

Olchansk: /* conf_coinc_control bits */

= TRG, the trigger control board for the ALPHA-g detector =

= Links =

* xxx
* https://bitbucket.org/expalpha/trg_firmware - firmware sources on bitbucket

= General characteristics =

== Photos ==

== Board schematics ==

* https://bitbucket.org/expalpha/trg_firmware/src/master/3xFMC_VME_Motherboard.pdf

== Available hardware ==

* Altera Stratix IV - main FPGA
* Altera Max V - boot FPGA
* boot flash: PC28F512M29EW - 512 Mbit parallel NOR flash.

= TRG front panel connections =

From top to bottom:

<pre>
|
| minisas-C - links 8-11
| minisas-D - links 12-15
|
| ethernet sfp - use copper sfp only
| minisas - not used, do not connect
| esata - clock in, trigger out
|
| minisas-A - links 0-3
| minisas-B - links 4-7
|
| LEDs
|
</pre>

MiniSAS and SATA flail cable connections:

<pre>
P1 <--> link 3
P2 <--> link 2
P3 <--> link 1
P4 <--> link 0
</pre>

LEDs:

<pre>
--PCB-- (left)
LED[0] - trigger out - ag_trig_out
LED[1] - network packet received - sfp_rx_data_valid
LED[2] - Xilinx FPGA boot ok - FMC1_CFG_DONE
LED[3] - not used
(right)
</pre>

= TRG onboard jumpers and switches =

* rotary switches: select IP address: 00=192.168.1.50, 11=.51, 22=.52, 33=.53, 44=.54, otherwire=.251

= Firmware update procedure =

* use quartus to generate the grifc.pof file (use grifc.cof)
* open quartus programmer
* attach grifc.pof to the 1st CFI_512 flash
* mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
* check that "initiate configuration after programming" is set in tools->options
* say "start"
* should take about 5 minutes
* grifc should reboot into the new firmware

If CFI_512 flash is not visible to the quartus programmer, load correct
code into the MaxV CPLD:

* open quartus programmer,
* say "auto detect"
* change file for the 5M2210 device
* use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
* say "program", it should finish in 10-15 seconds
* say "auto detect"
* CFI_512 flash should be visible now.

= Firmware revisions =

* 0x5bc8f90f - original firmware used for all data
* 0x6147c0f9 - added cbtrg, etc. installed at CERN on 20 Sep 2021.
* 0x618376ae - bigger cbtrg fifo, data rate tested up to 30 Mbytes/sec
* 0x6189c7f3 - fix loss of trigger packets. (missing fifo between alphag block and ethernet mux)
* 0x618b790b - fix loss of timestamps. (cbtrg inputs stretched to 100 ns long). installed at CERN 10 Nov 2021.

= Firmware build =

* use quartus 20.1
* see Makefile in the trg_firmware project

= Jtag remote connection =

* ssh agmini@daq16
* /opt/intelFPGA/16.1/quartus/bin/jtagd --config /home/agmini/.jtagd.conf
* netstat -an | grep 1309 ### note listen address is "0.0.0.0", NOT "127.0.0.1"
<pre>
tcp 0 0 0.0.0.0:1309 0.0.0.0:* LISTEN
</pre>
* opt/intelFPGA/16.1/quartus/bin/jtagconfig ### should work
* ssh olchansk@daq01
* cd git/trg_firmware
* /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
* jtagconfig ### should work
<pre>
daq01:trg_firmware$ jtagconfig
1) DE-SoC on daq16 [2-1.2.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) USB-Blaster on daq16 [2-1.3]
024090DD EP4SGX230(.|ES)
020A40DD 5M(1270ZF324|2210Z)/EPM2210

daq01:trg_firmware$
</pre>

= ALPHA-g trigger functions =

Trigger options:
* software trigger
* pulser trigger
* trigger on GRIF16 ADC NIM and ESATA inputs ("external trigger")
* adc16 grand-or
* adc32 grand-or
* adc16 wire multiplicity
* TPC anode wire per-preamp trigger (aw16 section)
** trigger on coincidences of preamps (removed fw 0x62c77f0b)
** trigger on multiplicity of preamps (removed fw 0x62c77f0b)
** trigger on specific topology of preamps (multiplicity of preamp clusters, etc) via the aw16_mlu trigger
* BSC trigger
** BSC grand_or
** BSC bar multiplicity
* coincidence trigger - select coincidence of external trigger, TPC AW grand-or, TPC AW MLU, BSC grand-or and BSC bar multiplicity triggers

== software trigger ==

to programmatically fire the trigger, one should:
* set the conf_enable_sw_trigger bit in conf_trig_enable, this will permit the software trigger to fire the trigger
* write value 0x4 to register 0x2B, this will cause the software trigger to fire

== pulser trigger ==

To use the pulser trigger, one should program:
* pulser period (in clocks)
* pulser width (in clocks, use value 5, the pulser no longer goes outside of the trigger board, so changing the width does not do anything)
* set the run_pulser bit in conf_trig_enable, this will cause the pulser to run
* set the enable_pulser bit in conf_trig_enable, this will cause the pulser to fire the trigger
* set the output_pulser bit in conf_trig_enable, this will cause the pulser to be output from the alphag firmware block (the pulser no longer goes outside of the trigger board, so changing the bit does not do anything)

== timeout trigger ==

The event builder uses event timestamps to assemble physics events. The timestamps
are usually 32 bit wide and run at 125 MHz (8 ns) or 62.5 MHz (16 ns). If
triggers are generated often (1 per second or more), timestamp wrap around
is easily detected by the event builder. If triggers come infrequently,
timestamp wrap around may occur while there are no triggers, not be seen
by the event builder causing loss of event synchronization.

To avoid this problem in the event builder, a timeout trigger should be generated
if no triggers were generated inside a 10 second interval.

The guaranties that even if all physics triggers temporarily stop for any reason,
the event builder will stay synchronized. (0.1 Hz timeout trigger frequency).

To enable the timeout trigger:
* program timeout trigger timeout in reg 0x43 in units of 8 ns clock
* enable it in bit 23 of [[#conf_trig_enable bits]]

== adc16 multiplicity trigger ==

This trigger is intended for use with the barrel scintillator signals connected to adc16 digitizers. It does not work well with TPC AW signals.

The 16 adc16 trigger bits (16x16=256) are added together to form the hit multiplicity value (adc16_mult, 16 bits, actual range 0 to 256).

Four threshold signals are computed: adc16_mult_1ormore = adc16_mult>=1, 2ormore, 3ormore, 4ormore.

There is a counter for each of these four signals.

Each of these four signals can fire the trigger, see [[#conf_trig_enable bits]].

== TPC anode wire triggers ==

=== aw16 bus ===

TPC Anode Wire trigger is based on the aw16[15:0] (xaw16) bus.

Each bit corresponds to one AW preamp. 16 preamps, 16 bits.

The aw16[15:0] bus can be fed by
* adc16_or16[15:0] - or16 of 100 MHz ADCs, 16 ADC sas links
* adc32_or16[15:0] - or16 of 62.5 MHz ADCs, FMC-ADC32 has 32 channels, so 2 bits per ADC: low 16 channels and high 16 channels, sas links 7..0
* adc32_or16[31:16] - or16 of 62.5 MHz ADCs, ditto, sas links 15..8
as selected by conf_enable_aw_adc16, conf_enable_aw_adc32a, conf_enable_aw_adc32b in [[#conf_control bits]]

<pre>
///////////////////////////////////////////////////////////
// TPC Anode Wire trigger logic (aw16)
///////////////////////////////////////////////////////////

// map adc signals into aw16

wire [15:0] aw16 = ({16{conf_enable_aw_adc16}} & adc16_or16[15:0]) |
({16{conf_enable_aw_adc32a}} & adc32_or16[15:0]) |
({16{conf_enable_aw_adc32b}} & adc32_or16[31:16]);
...
ag_conditioner cond_adc16_or16_0(.clk(clk), .in(aw16[0]), .out(xxaw16[0]));
...
xaw16 <= xxaw16;
</pre>

=== aw16_grand_or ===

TPC AW "grand or" trigger: use aw16_mult_1ormore (before fw 0x62c77f0b)

(256 anode wires, 16 wires per preamp, 16 preamps, 16 aw16 signals)

=== aw16_mlu ===

TPC AW preamp MLU trigger: the MLU (memory lookup
table) implements an arbitrary logical function
to map the 16 aw16 preamp signals into 1 aw16_mlu_trig trigger output.

Description of the aw16 mlu trigger.

In words:

* any aw16 signal starts the aw16_prompt_run gate
* aw16 signals are collected for the duration of conf_mlu_prompt (125MHz/8ns clock)
* this corresponds to time spread of TPC AW signals due to the drift time in the AW drift cell and to the variation in signal transmission time from the ADC to the TRG (digital trigger data link).
* when this prompt time expires, the MLU looks at the accumulated aw16_prompt bit pattern and makes the "yes/no" trigger decision
* after the trigger decision is made, we wait for the TPC to become quiet:
* we wait until all aw16 signals are empty (no timeout)
* we run the aw16_prompt_wait gate, length conf_mlu_wait (8ns clock), if any aw16 signals arrive, we wait for aw16 empty again, rinse, repeat.
* now, after TPC aw16 have been empty for conf_mlu_wait clocks (8ns clock), MLU trigger is ready for the next event.

In logic: (see alphag.v)

* aw16_or <= grand-or of 16 aw16 signals
* "aw16_or" starts the "aw16_prompt_cnt" counter, opens the aw16_prompt_run gate
* during the aw16_prompt_run gate, aw16_prompt collects (latches) the aw16 bits (aw16_prompt <= aw16_prompt | aw16)
* this is the time when we wait for all "prompt" signals from the TPC to arrive into the trigger
* at the end of the aw16_prompt_run gate, the signal aw16_prompt_out is pulsed, latching the output of the MLU into aw16_mlu_trig
* this is the MLU trigger "yes/no" trigger decision.
* after the MLU trigger decision is made, we wait for the arrival and passing of all TPC drift signals
* the aw16_prompt_wait_cnt and aw_prompt_wait gate opens
* if any new aw16 signals arrive (they are TPC drift signals at this time), the aw16_prompt_wait gate is restarted
* if no aw16 signals arrive during the full run of the aw16_prompt_wait gate ("TPC quiet time")
* the aw16_prompt_wait and aw16_prompt gates are cleared and the MLU trigger is ready for the next event.

Good settings are:
* conf_mlu_prompt: 64 (512 ns)
* conf_mlu_wait: 128 (1024 ns)

== BSC trigger ==

=== bsc_adc16 bus ===

The BSC trigger is based on the [15:0]bsc_adc16[7:0] bus: 16 trigger discriminator bits from 8 ADC sas links. (8*16 = 64+64 bars, top and bottom).

The bsc_adc16 bus can be fed from sas links 0..7 or 8..15, controlled by conf_bsc_adc16_a and conf_bsc_adc16_b bits on [[#conf_bsc_control bits]].

bsc_adc16 can be fed only from GRIF-16 100 MHz ADC trigger discriminators.

=== bsc64_top and bsc64_bot buses ===

* firmware 0x5bc8f90f: bsc_adc16 is remapped into 64 bits of top (bsc64_top) and bottom (bsc64_bot):
<pre>
ag_bsc_remap bsc_remap_a(.adc(bsc_adc16[0]), .bsc_bot(bsc64_bot[7:0]), .bsc_top(bsc64_top[7:0]));
ag_bsc_remap bsc_remap_b(.adc(bsc_adc16[1]), .bsc_bot(bsc64_bot[8+7:8+0]), .bsc_top(bsc64_top[8+7:8+0]));
ag_bsc_remap bsc_remap_c(.adc(bsc_adc16[2]), .bsc_bot(bsc64_bot[2*8+7:2*8+0]), .bsc_top(bsc64_top[2*8+7:2*8+0]));
ag_bsc_remap bsc_remap_d(.adc(bsc_adc16[3]), .bsc_bot(bsc64_bot[3*8+7:3*8+0]), .bsc_top(bsc64_top[3*8+7:3*8+0]));

ag_bsc_remap bsc_remap_e(.adc(bsc_adc16[4]), .bsc_bot(bsc64_bot[4*8+7:4*8+0]), .bsc_top(bsc64_top[4*8+7:4*8+0]));
ag_bsc_remap bsc_remap_f(.adc(bsc_adc16[5]), .bsc_bot(bsc64_bot[5*8+7:5*8+0]), .bsc_top(bsc64_top[5*8+7:5*8+0]));
ag_bsc_remap bsc_remap_g(.adc(bsc_adc16[6]), .bsc_bot(bsc64_bot[6*8+7:6*8+0]), .bsc_top(bsc64_top[6*8+7:6*8+0]));
ag_bsc_remap bsc_remap_h(.adc(bsc_adc16[7]), .bsc_bot(bsc64_bot[7*8+7:7*8+0]), .bsc_top(bsc64_top[7*8+7:7*8+0]));

module ag_bsc_remap
(
input wire [15:0] adc,
output wire [7:0] bsc_bot,
output wire [7:0] bsc_top
);

assign bsc_top[3] = adc[0];
assign bsc_top[2] = adc[1];
assign bsc_top[1] = adc[2];
assign bsc_top[0] = adc[3];

assign bsc_top[7] = adc[4];
assign bsc_top[6] = adc[5];
assign bsc_top[5] = adc[6];
assign bsc_top[4] = adc[7];

assign bsc_bot[0] = adc[8];
assign bsc_bot[1] = adc[9];
assign bsc_bot[2] = adc[10];
assign bsc_bot[3] = adc[11];

assign bsc_bot[4] = adc[12];
assign bsc_bot[5] = adc[13];
assign bsc_bot[6] = adc[14];
assign bsc_bot[7] = adc[15];

endmodule
</pre>

=== bsc64 bus ===

the bsc64 bus is the 64 bars used by the trigger, formed from bsc64_top and bsc64_bot:
<pre>
if (conf_bsc64_bot_only) begin
bsc64 <= bsc64_bot;
end else if (conf_bsc64_top_only) begin
bsc64 <= bsc64_top;
end else if (conf_bsc64_bot_top_or) begin
bsc64 <= bsc64_bot | bsc64_top;
end else if (conf_bsc64_bot_top_and) begin
bsc64 <= bsc64_bot & bsc64_top;
end else begin
bsc64 <= 64'b0;
end
</pre>

=== bsc_grand_or_trig ===

bsc_grand_or_trig is the grand-or of 64 bits of the bsc64 bus

to enable triggering on bsc_grand_or_trig, set corresponding bit in [[#conf_trig_enable bits]]

=== old bsc_mult_trig ===

(from fw 0x62c77f0b, old bsc_mult_trig was replaced by new bsc64 multiplicity trigger)

* bsc64_mult is computed as multiplicity of the bsc64 bus (number of 64 bsc64 bits that fired)
* bsc_mult_trig is computed:
<pre>
if (bsc64_mult >= conf_bsc64_mult) begin
bsc_mult_trig <= 1;
end else begin
bsc_mult_trig <= 0;
end
</pre>

to enable the bsc multiplicity trigger, set the multiplicity value conf_bsc64_mult in [[#conf_bsc_control bits]] and enable the corresponding bit in [[#conf_trig_enable bits]].

=== bsc64 multiplicity trigger ===

bsc64 BSC bar multiplicity trigger uses a time window. this time window is started by bsc64_grand_or and runs for conf_bsc64_mult_window clocks (8 nc clock). During this time, hits in bsc64_bus are accumulated (latched) and their multiplicity is computed. If multiplicity condition is satisfied (bigger or equal to conf_bsc64_mult_min), bsc64_mult_trig is fired and the bsc64 bit pattern is saved to the UDP packet. Then trigger waits for the bsc64_bus to be empty. Then trigger waits for conf_bsc64_empty_window clocks, if there is any bsc64 hits, we wait for empty again. So after bsc64 has been empty for conf_bsc64_empty_window clocks, multiplicity trigger is ready for the next event. This scheme cannot implement max multiplicity.

recommended values:
* conf_bsc64_mult_window (8 bits): slightly longer than 3 cycles of SAS link: 3*18 = 54 clocks, good value is 80 (640 ns).
* conf_bsc64_mult_min (8 bits): 2
* conf_bsc64_empty_window (8 bits): 80 (640 ns)

== Coincidence trigger ==

Coincidence trigger provides a combination of TPC, BSC and external scintillator (esata_nim_grand_or) signals:

<pre>
assign coinc_input[0] = aw16_grand_or; // was aw16_mult_1ormore;
assign coinc_input[1] = aw16_mlu_trig;
assign coinc_input[2] = bsc_grand_or_trig;
assign coinc_input[3] = bsc_mult_trig;
assign coinc_input[4] = esata_nim_grand_or;
assign coinc_input[5] = 0;
assign coinc_input[6] = 0;
assign coinc_input[7] = 0;
</pre>

Coincidence trigger "start" mask selects which of the inputs can start the coincidence window.

Coincidence trigger "require" mask selects which inputs must have a hits for the coincidence ot be satisfied.

Input hits are collected for the duration of the coincidence window, if all required inputs have hits, coinc_trig is fired.

Example settings:

* coincidence of external scintillator, BSC and TPC AW "grand or" signals: start 0x10, required 0x15
* coincidence of BSC and TPC AW "grand or" signals: start 0x4, required 0x5
* coincidence of BSC and TPC AW MLU triggers: start 0x4, required 0x6
* coincidence of BSC multiplicity and TPC AW MLU triggers: start 0x8, required 0xA

= Control registers =

== Register addresses ==

Note: all registers are 32 bits unless otherwise noted.

Note: RW means read-write register, RO means read-only, ROL means read-only, contents is latched by the "latch_out" bit

{| cellpadding="10" cellspacing="0" border="1"
! Address || Quartus Name || Access || FwRev || Description
|-
| 0x08 || num_sample || RW || GRIF-C || magic 16-bit register to control UDP packet size
|-
| 0x08 || scratch_reg || RW || 0x618b790b || 32-bit scratch register
|-
| 0x1F || compilation_time || RO || || Firmware revision
|-
| 0x20 || conf_trig_width || RW || || Trigger signal width, 16 ns clock
|-
| 0x21 || conf_busy_width || RW || || Busy signal width, 16 ns clock (not used)
|-
| 0x22 || conf_pulser_width || RW || || Pulser signal width, 16 ns clock
|-
| 0x23 || conf_pulser_period || RW || || Pulser signal period, 16 ns clock
|-
| 0x24 || conf_pulser_burst_ctrl || RW || 0x62d1c47e || Generate bursts of pulses: 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses, 16 ns clocks
|-
| 0x25 || conf_trig_enable || RW || || see [[#conf_trig_enable bits]]
|-
| 0x26 || || || not used
|-
| 0x27 || || || not used
|-
| 0x28 || || || not used
|-
| 0x29 || conf_nim_mask || RW || || enable bits for ADC NIM inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2A || conf_esata_mask || RW || || enable bits for ADC eSATA inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2B || reset_out, latch_out, trigger_out || W || || see [[#reg 0x2B bits]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x5bc8f90f || configure AW coincidence trigger, see [[#aw16_coinc]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x62c77f0b || removed
|-
| 0x2D || conf_aw16_coinc_b || RW || 0x5bc8f90f ||
|-
| 0x2E || conf_aw16_coinc_c || RW || 0x5bc8f90f ||
|-
| 0x2F || conf_aw16_coinc_d || RW || 0x5bc8f90f ||
|-
| 0x30 || sas_sd[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect for each link
|-
| 0x31 || pll_625_status || ROL || 0x5b2057f5 (12Jun18_16:32) || 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter
|-
| 0x32 || clk_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the system 125 MHz clock
|-
| 0x33 || clk_625_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625)
|-
| 0x34 || conf_control || RW || 0x5b398983 (01Jul18_19:10) || see [[#conf_control bits]] below
|-
| 0x35 || conf_drift_width || RW || 0x5b398983 (01Jul18_19:10) || width of drift time blank-out in 16 ns clocks
|-
| 0x36 || conf_scaledown || RW || 0x5b398983 (01Jul18_19:10) || trigger scaledown, 0=no scaledown, 1=divide-by-2, 2=divide-by-3, etc
|-
| 0x37 || conf_mlu || RW || 0x5b398983 (01Jul18_19:10) || AW MLU control bits, see [[#conf_mlu bits]]
|-
| 0x38 || conf_trig_delay || RW || 0x5baedfca (28Sep18_19:13) || delay the trigger pulse, 16 ns clock
|-
| 0x39 || esata_clk_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the TRG 125 MHz clock
|-
| 0x3A || esata_clk_esata_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the external clock (eSATA 62.5 MHz clock)
|-
| 0x3B || conf_counter_adc_select || RW || 0x5bb7f6ae (05Oct18_16:41) || select which 16 ADCs are connected to the selected adc counters, 0..15 - connect the adc16 signals, 16..47 connect the adc32 signals
|-
| 0x3C || sysreset_ts || RO || 0x5bb7f6ae (05Oct18_16:41) || 125MHz counter of VME-SYSRESET
|-
| 0x3C || || || 0x618b790b || not used
|-
| 0x3D || GRIF-C csr || RW || GRIF-C || <= csr & ~par_value; // Selective clear
|-
| 0x3E || GRIF-C csr || RW || GRIF-C || <= csr | par_value; // Selective set
|-
| 0x3F || GRIF-C csr || RW || GRIF-C || <= par_value; // write
|-
| 0x3D || || || 0x618b790b || not used
|-
| 0x3E || || || 0x618b790b || not used
|-
| 0x3F || || || 0x618b790b || not used
|-
| 0x40 || conf_bsc_control || RW || 0x5bc13541 (12Oct18_16:58) || Barrel Scintillator trigger control, see [[#conf_bsc_control bits]]
|-
| 0x41 || conf_coinc_control || RW || 0x5bc13541 (12Oct18_16:58) || Coincidence trigger control, see [[#conf_coinc_control bits]]
|-
| 0x42 || reconfig_out || WO || 0x5bc13541 (12Oct18_16:58) || reserved for rebooting the FPGA (does not work)
|-
| 0x43 || conf_trigger_timeout || RW || 0x5bc8f90f (18Oct18_14:20) || Generate timeout trigger if there is no other trigger after given timeout, in 8 ns clocks, must be enabled by bit conf_enable_timeout_trig in [[#conf_trig_enable bits]]
|-
| 0x44 || eth_clk_counter || ROL || 0x618b790b ||
|-
| 0x45 || eth_clk_eth_counter || ROL || 0x618b790b ||
|-
| 0x100 || ts_625 || ROL || || latched timestamp
|-
| 0x101 || counter_trig_out || ROL || || counter of issued triggers
|-
| 0x102 || counter_trig_in || ROL || || counter of triggers
|-
| 0x103 || counter_pulser || ROL || || counter of pulser
|-
| 0x104 || counter_adc16_grand_or || ROL ||
|-
| 0x105 || counter_adc32_grand_or || ROL ||
|-
| 0x106 || counter_adc_grand_or || ROL ||
|-
| 0x107 || counter_esata_nim_grand_or || ROL ||
|-
| 0x108 || counter_adc16_mult_1ormore || ROL ||
|-
| 0x109 || counter_adc16_mult_2ormore || ROL ||
|-
| 0x10A || counter_adc16_mult_3ormore || ROL ||
|-
| 0x10B || counter_adc16_mult_4ormore || ROL ||
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x5bc8f90f || counter of AW coincidence triggers
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x62c77f0b || removed
|-
| 0x10D || counter_aw16_coinc_b || ROL || 0x5bc8f90f ||
|-
| 0x10E || counter_aw16_coinc_c || ROL || 0x5bc8f90f ||
|-
| 0x10F || counter_aw16_coinc_d || ROL || 0x5bc8f90f ||
|-
| 0x110 || counter_drift || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the drift time blank-out
|-
| 0x111 || counter_scaledown || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the scaledown
|-
| 0x112 || counter_aw16_coinc || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW coincidence triggers
|-
| 0x113 || counter_aw16_mlu || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW MLU triggers
|-
| 0x114 || counter_aw16_grand_or || ROL || 0x62c77f0b || counter of AW grand-or triggers
|-
| 0x114 || counter_aw16_mult_1ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 1ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 2ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x62c77f0b || removed
|-
| 0x116 || counter_aw16_mult_3ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 3ormore triggers
|-
| 0x117 || counter_aw16_mult_4ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 4ormore triggers
|-
| 0x118 || counter_bsc_grand_or || ROL || 0x5bc13541 (12Oct18_16:58) || counter of BSC grand-or triggers
|-
| 0x119 || counter_bsc_mult || ROL || 0x5bc13541 (12Oct18_16:58) || counter of old BSC multiplicity triggers
|-
| 0x11A || counter_coinc || ROL || 0x5bc13541 (12Oct18_16:58) || counter of coincidence triggers
|-
| 0x11B || counter_timeout || ROL || 0x618b790b || counter of timeout triggers
|-
| 0x11C || counter_bsc_mult_start || ROL || 0x62c77f0b || counter of BSC multiplicity windows
|-
| 0x11D || counter_bsc_mult_trig || ROL || 0x62c77f0b || counter of BSC multiplicity triggers
|-
| 0x11E || counter_coinc_start || ROL || 0x62d1b152 || counter of coincidence windows
|-
| 0x11F || counter_aw16_mlu_start || ROL || 0x62d1b152 || counter of TPC AW MLU windows
|-
| 0x200..0x207 || conf_adc16_masks || RW || all || adc16 enable bits
|-
| 0x300..0x30F || conf_adc32_masks || RW || all || adc32 enable bits
|-
| 0x400..0x41F || sas_bits[15:0][63:0] || ROL || all || sas data bits for each link
|-
| 0x420..0x42F || sas_sd_counters[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect counter for each link
|-
| 0x430..0x43F || counters_adc16_or16[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 16 counters of adc16 ORes
|-
| 0x440..0x45F || counters_adc32_or16[31:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 32 counters of adc32 ORes
|-
| 0x460..0x46F || counters_adc_selected[15:0] || ROL || 0x5bb7f6ae (05Oct18_16:41) || 16 counters for selected group of adcs, see conf_counter_adc_select
|-
| 0x470..0x4AF || counters_bsc64[63:0] || ROL || 0x5bc13541 (12Oct18_16:58) || 64 counters for the BSC bars
|-
|}

== additional registers ==

<pre>
reg | rw/ro | quartus name | firmware | description
0x60: param_out <= {2'h3, par_id, chan, cb_control_out
0x61: param_out <= {2'h3, par_id, chan, cb_status
0x62: param_out <= {2'h3, par_id, chan, cb_invert_a_out };
0x63: param_out <= {2'h3, par_id, chan, cb_invert_b_out };
0x64: param_out <= {2'h3, par_id, chan, cb_enable_le_a_out };
0x65: param_out <= {2'h3, par_id, chan, cb_enable_le_b_out };
0x66: param_out <= {2'h3, par_id, chan, cb_enable_te_a_out };
0x67: param_out <= {2'h3, par_id, chan, cb_enable_te_b_out };
0x6A | ro | cb_input_num | 0x618b790b | chronobox number of inputs
0x6B: param_out <= {2'h3, par_id, chan, cb_sync_mask_a_out };
0x6C: param_out <= {2'h3, par_id, chan, cb_sync_mask_b_out };
0x6D: param_out <= {2'h3, par_id, chan, cb_sync_reg_out };
0x6E: param_out <= {2'h3, par_id, chan, cb_sync_status };
0x6F: param_out <= {2'h3, par_id, chan, cb_latch_period_out };
0x70: param_out <= {2'h3, par_id, chan, cb_fifo_status };
0x71: begin param_out <= {2'h3, par_id, chan, cb_fifo_data }; cb_fifo_rdack_out <= 1; end
0x72: param_out <= {2'h3, par_id, chan, cb_udp_period_out };
0x73: param_out <= {2'h3, par_id, chan, cb_udp_threshold_out };
</pre>

== conf_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_clock_select || 0x5b3aa19f (02Jul18_15:05) || select 0=internal 62.5 MHz clock or 1=esata 62.5 MHz clock
|-
| 1 || conf_enable_aw_adc16 || 0x5baedfca (28Sep18_19:13) || select source of TPC AW aw16 bus, see [[#aw16 bus]]
|-
| 2 || conf_enable_aw_adc32a || 0x5baedfca (28Sep18_19:13) ||
|-
| 3 || conf_enable_aw_adc32b || 0x5baedfca (28Sep18_19:13) ||
|-
| 15..4 || || ||
|-
| 23..16 || conf_mlu_prompt || 0x5b3aa19f (02Jul18_15:05) || MLU trigger prompt window, see [[#aw16_mlu]]
|-
| 31..24 || conf_mlu_wait || 0x5b3aa19f (02Jul18_15:05) || MLU trigger wait window, see [[#aw16_mlu]]
|-
|}

== conf_mlu bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 31 || mlu_reset || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 30 || mlu_write || 0x5b3aa19f (02Jul18_15:05) || 1=write data bit into given address
|-
| 16 || mlu_data || 0x5b3aa19f (02Jul18_15:05) || data bit for writing to MLU RAM
|-
| 15..0 || mlu_write_addr || 0x5b3aa19f (02Jul18_15:05) || MLU RAM write address for writing the data bit
|-
|}

== conf_bsc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_bsc_adc_a || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 0..7
|-
| 1 || conf_bsc_adc_b || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 8..15
|-
| 2 || conf_bsc64_bot_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses bottom channels only
|-
| 3 || conf_bsc64_top_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses top channels only
|-
| 4 || conf_bsc64_bot_top_or || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "or" of top and bottom
|-
| 5 || conf_bsc64_bot_top_and || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "and" of top and bottom
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_bsc64_mult_min || 0x5bc13541 (12Oct18_16:58) || minimum bsc64 multiplicity
|-
| 23..16 || conf_bsc64_empty_wondow || 0x62d1c47e || bsc64 empty window length, 8 ns clocks
|-
| 31..24 || conf_bsc64_mult_window || 0x62c77f0b || bsc64 multiplicity window length, 8 ns clocks
|-
|}

== conf_coinc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_coinc_required[0] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mult_1ormore
|-
| 0 || conf_coinc_required[0] || 0x62c77f0b || enable aw16_grand_or
|-
| 1 || conf_coinc_required[1] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mlu_trig
|-
| 2 || conf_coinc_required[2] || 0x5bc13541 (12Oct18_16:58) || enable bsc_grand_or_trig
|-
| 3 || conf_coinc_required[3] || 0x5bc13541 (12Oct18_16:58) || enable bsc_mult_trig
|-
| 3 || conf_coinc_required[3] || 0x62c77f0b || enable bsc64_mult_trig
|-
| 4 || conf_coinc_required[4] || 0x5bc13541 (12Oct18_16:58) || enable esata_nim_grand_or
|-
| 5 || conf_coinc_required[5]
|-
| 6 || conf_coinc_required[6]
|-
| 7 || conf_coinc_required[7]
|-
| 15..8 || conf_coinc_window[7:0] || 0x5bc13541 (12Oct18_16:58) || coincidence window length in units of 125MHz clock (8 ns)
|-
| 23..16 || conf_coinc_start[7:0] || 0x5bc13541 (12Oct18_16:58) || start the coincidence window, same bits as "required"
|-
| 31..24 ||
|-
|}

== conf_trig_enable bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_enable_sw_trigger || || trigger on software trigger (how generated???)
|-
| 1 || conf_enable_pulser || || trigger on pulser
|-
| 2 || - || 0x5b120c9f (01Jun18_20:18) || not used
|-
| 3 || conf_pulser_run || || allow the pulser to run (frequency has to be set beforehand)
|-
| 4 || conf_output_pulser || 0x5bc8f90f || does nothing (top level ag_pulser_out is disconnected)
|-
| 4 || || 0x618b790b || not used
|-
| 5 || conf_enable_esata_nim || || trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand)
|-
| 6 || conf_enable_adc16 || || trigger on adc16_grand_or
|-
| 7 || conf_enable_adc32 || || trigger on adc32_grand_or
|-
| 8 || conf_enable_adc16_1ormore || || trigger on adc16_mult_1ormore "1 or more"
|-
| 9 || conf_enable_adc16_2ormore || || same, "2 or more"
|-
| 10 || conf_enable_adc16_3ormore || || same, "3 or more"
|-
| 11 || conf_enable_adc16_4ormore || || same, "4 or more"
|-
| 12 || - || 0x5b08938c (25May18_15:51) || not used
|-
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
|-
| 14 || - || 0x5bc8f90f || not used
|-
| 15 || conf_enable_adc || 0x5b120c9f (01Jun18_20:18) || trigger on adc_grand_or
|-
| 16 || conf_enable_aw16_coinc_a || 0x5bc8f90f || enable AW coincidence trigger, see [[#aw16_coinc]]
|-
| 16 || - || 0x62c77f0b || aw16_coinc_x removed
|-
| 17 || conf_enable_aw16_coinc_b || 0x5bc8f90f ||
|-
| 18 || conf_enable_aw16_coinc_c || 0x5bc8f90f ||
|-
| 19 || conf_enable_aw16_coinc_d || 0x5bc8f90f ||
|-
| 20 || - || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 20 || conf_enable_aw16_grand_or || 0x618b790b || enable trigger on aw16_grand_or
|-
| 21 || conf_enable_aw16_coinc || 0x5b3aa19f (02Jul18_15:05) || enable trigger on aw16_coinc_trig
|-
| 22 || conf_enable_aw16_mlu || 0x5b3aa19f (02Jul18_15:05) || enable AW MLU trigger
|-
| 23 || conf_enable_timeout_trig || 0x5bc8f90f (18Oct18_14:20) || enable trigger timeout trigger
|-
| 24 || conf_enable_aw16_1ormore || 0x5b3aa19f (02Jul18_15:05) || trigger on aw16_mult_1ormore "1 or more"
|-
| 24 || - || 0x62c77f0b || aw16_mult_xxx removed
|-
| 25 || conf_enable_aw16_2ormore || 0x5b3aa19f (02Jul18_15:05) || same, "2 or more"
|-
| 26 || conf_enable_aw16_3ormore || 0x5b3aa19f (02Jul18_15:05) || same, "3 or more"
|-
| 27 || conf_enable_aw16_4ormore || 0x5b3aa19f (02Jul18_15:05) || same, "4 or more"
|-
| 28 || conf_enable_bsc_grand_or || 0x5bc13541 (12Oct18_16:58) || trigger on BSC grand-or
|-
| 29 || conf_enable_bsc_mult || 0x5bc13541 (12Oct18_16:58) || trigger on BSC multiplicity
|-
| 30 || conf_enable_coinc || 0x5bc13541 (12Oct18_16:58) || trigger on TPC/BSC/ext coincidence trigger
|-
| 31 || - || || not used
|-
|}

== reg 0x2B bits ==

Write to this register will pulse corresponding fpga signals:

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || reset_out || 0x5b120c9f (01Jun18_20:18) || reset counters, etc
|-
| 1 || latch_out || 0x5b120c9f (01Jun18_20:18) || latch counters, sas bits, etc
|-
| 2 || trigger_out || 0x5b120c9f (01Jun18_20:18) || generate a software trigger
|-
|}

= UDP data format =

== firmware 0x5bc8f90f ==

{| cellpadding="10" cellspacing="0" border="1"
! Offset || Name || Quartus name || FwRev || Description
|-
| 0 || packet counter || none || all || 31-bit UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
|-
| 1 || 0x8 packet header || || all || 28 bits of counter_trig_out
|-
| 2 || trigger timestamp || trig_ts || all || 62.5MHz trigger timestamp
|-
| 3 || accepted triggers || counter_trig_out || all || counter of accepted triggers
|-
| 4 || input triggers || counter_trig_in || all || counter of trigger input
|-
| 5 || pulser triggers || counter_pulser || all || counter of pulser triggers
|-
| 6 || trigger bitmap || udp_trig_bits || 0x5a48448d (30Dec17_17:59) || bitmap of trigger information, see below
|-
| 7 || nim bits || udp_nim_bits_masked || ??? || 32 bits of ADC NIM inputs (2 bits per ADC)
|-
| 8 || esata bits || udp_esata_bits_masked || ??? || 32 bits of ADC ESATA inputs (2 bits per ADC)
|-
| 9 || mlu bits || aw16_prompt || 0x5b398983 (01Jul18_19:10) || 16 bits of MLU input, 1 bit per preamp
|-
| 10 || drift-blank-off counter || udp_drift_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the drift blank-off
|-
| 11 || scaledown counter || udp_scaledown_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the scaledown
|-
| X || || || ||
|-
| 12 || 0xE packet footer || || all || 28 bits of counter_trig_out
|-
|}

== firmware 0x618b790b (Nov 2021) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

== trigger bitmap ==

Firmware ??? (one of the very early revisions)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= adc16_coinc_top;
udp_trig_bits[5] <= adc16_coinc_bot;
udp_trig_bits[6] <= adc16_coinc;
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
udp_trig_bits[31:24] <= mult16[7:0];

</pre>

Firmware 0x5b08938c (25May18_15:51)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= 0; // not used
udp_trig_bits[31:24] <= mult16[7:0];
</pre>

Firmware 0x5b217dc4 (13Jun18_13:25)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5b3aa19f (02Jul18_15:05)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= udp_mlu_out;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5bc8f90f (18Oct18_14:20)

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_run_pulser
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = 0; // not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x618b790b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x62c77f0b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = 0; // aw16_coinc_a;
assign trig32_in[17] = 0; // aw16_coinc_b;
assign trig32_in[18] = 0; // aw16_coinc_c;
assign trig32_in[19] = 0; // aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = 0; // aw16_mult_1ormore;
assign trig32_in[25] = 0; // aw16_mult_2ormore;
assign trig32_in[26] = 0; // aw16_mult_3ormore;
assign trig32_in[27] = 0; // aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc64_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

= TRG chronobox inputs =

from trg_firmware/toplevel/grifc.v

<pre>
localparam CB_N = 23;
localparam CB_N1 = CB_N-1;

wire [CB_N1:0] cb_xinputs_async;

assign cb_xinputs_async[0] = ag_trig_out;
assign cb_xinputs_async[1] = ag_trig_scaledown_out;
assign cb_xinputs_async[2] = ag_trig_drift_out;
assign cb_xinputs_async[3] = ag_trig_received_out;

assign cb_xinputs_async[4] = ag_cb_sw_trig;
assign cb_xinputs_async[5] = ag_cb_pulser_trig;
assign cb_xinputs_async[6] = ag_cb_esata_nim_trig;
assign cb_xinputs_async[7] = ag_cb_adc16_grand_or_trig;
assign cb_xinputs_async[8] = ag_cb_adc32_grand_or_trig;

assign cb_xinputs_async[9] = ag_cb_aw16_grand_or_trig;
assign cb_xinputs_async[10] = ag_cb_aw16_mult_1ormore;
assign cb_xinputs_async[11] = ag_cb_aw16_mult_2ormore;
assign cb_xinputs_async[12] = ag_cb_aw16_mult_3ormore;
assign cb_xinputs_async[13] = ag_cb_aw16_mult_4ormore;
assign cb_xinputs_async[14] = ag_cb_aw16_mlu_trig;

assign cb_xinputs_async[15] = ag_cb_bsc64_grand_or_trig;
assign cb_xinputs_async[16] = ag_cb_bsc64_mult_1ormore;
assign cb_xinputs_async[17] = ag_cb_bsc64_mult_2ormore;
assign cb_xinputs_async[18] = ag_cb_bsc64_mult_3ormore;
assign cb_xinputs_async[19] = ag_cb_bsc64_mult_4ormore;
assign cb_xinputs_async[20] = ag_cb_bsc64_mult_trig;

assign cb_xinputs_async[21] = ag_cb_coinc_trig;

assign cb_xinputs_async[22] = ag_cb_timeout_trig;
</pre>

= Example UDP packets =

* trigger data, marker words 0x8

<pre>
ReadDataThread read 76
0: 0x003666ed -- UDP packet counter from UDP transmitter
1: 0x80000bf8 -- 0x8 is trigger data packet, 0xbf8 is the trigger counter from alphag.v
2: 0x2edf8b41 -- trigger data
3: 0x00000bf8
4: 0x00000bf8
5: 0x00000bee
6: 0x00000001
7: 0x00000000
8: 0x00000000
9: 0x00000003
10: 0x00000bf8
11: 0x00000bf8
12: 0x00000000
13: 0x00000000
14: 0x00000000
15: 0x00000000
16: 0x00000000
17: 0x00000000
18: 0xe0000bf8 -- 0xE is end of trigger data, counter 0xbf8 must match the counter in the 0x8 word.
ReadDataThread read 76 -- next packet
0: 0x003666ee -- UDP packet counter from UDP transmitter
...
</pre>

* chronobox fifo data, marker word 0xC, see [[Chronobox#FIFO_data_format]]

<pre>
ReadDataThread read 404
0: 0x003658ed -- UDP packet counter from UDP transmitter
1: 0xc000eacc -- 0xC is FIFO data, fifo packet counter 0xeacc from fifo_to_udp.v
2: 0x00000061 -- FIFO status, low bits the the word counter, so up to 0x61 fifo words are to follow
3: 0x87fb3d72 -- tsc hits
4: 0x8ffb3d74
5: 0x90fb3d74
6: 0x91fb3d74
7: 0x92fb3d74
8: 0x93fb3d74
9: 0x93fb3d75
10: 0x94fb3d74
11: 0x94fb3d77
12: 0x87fb3d77
13: 0x8ffb3d77
14: 0x90fb3d77
15: 0x91fb3d77
16: 0x92fb3d77
17: 0xfe000018 -- 0xFE scaler data starts, 0x18 words to follow
18: 0x00000000
19: 0x00000000
20: 0x00000000
21: 0x00000000
22: 0x00000000
23: 0x00000000
24: 0x00000000
25: 0x00000108
26: 0x00000000
27: 0x00000000
28: 0x00000000
29: 0x00000000
30: 0x00000000
31: 0x00000000
32: 0x00000000
33: 0x00000108
34: 0x00000108
35: 0x00000108
36: 0x00000108
37: 0x00000108
38: 0x00000108
39: 0x00000000
40: 0x00000000
41: 0xce56fa93 -- last word of scaler data is the sysclock counter (125 MHz)
42: 0xff800048 -- timestamp wraparound
43: 0x8f1f36e4 -- tsc hits
44: 0x901f36e4
45: 0x911f36e4
46: 0x921f36e4
47: 0x931f36e4
48: 0x941f36e4
49: 0x871f36e4
50: 0x871f36e7
51: 0x8f1f36e7
52: 0x901f36e9
53: 0x911f36e7
54: 0x921f36e9
55: 0x931f36e7
56: 0x941f36e9
57: 0x904330ac
58: 0x914330ac
59: 0x924330ac
60: 0x934330ac
61: 0x934330ad
62: 0x944330ac
63: 0x944330ad
64: 0x874330ac
65: 0x874330ad
66: 0x8f4330ac
67: 0x8f4330ad
68: 0x904330ad
69: 0x914330ad
70: 0x924330ad
71: 0x8f672a62
72: 0x90672a62
73: 0x91672a62
74: 0x92672a62
75: 0x93672a62
76: 0x94672a62
77: 0x87672a62
78: 0x87672a65
79: 0x8f672a65
80: 0x90672a65
81: 0x91672a65
82: 0x92672a65
83: 0x93672a65
84: 0x94672a65
85: 0xff000049
86: 0x878b2422
87: 0x8f8b2424
88: 0x908b2424
89: 0x918b2424
90: 0x928b2424
91: 0x938b2424
92: 0x938b2425
93: 0x948b2424
94: 0x948b2427
95: 0x878b2427
96: 0x8f8b2427
97: 0x908b2427
98: 0x918b2427
99: 0x928b2427
100: 0xe000eacc -- 0xE is end of fifo data, counter 0xeacc must match the counter in the 0xC word.
ReadDataThread read 344 -- next packet
...
</pre>

= TODO =

* DONE July 2022. add FwRev to the UDP data output
* RJ45 SFP: PROBLEM, D.A. CABLE: GOOD, Fiber SFP: ???. fix "write did not happen" (send udp write command, there is no reply, read returns old data as if write never happened). suspect udp "write" packet is lost?
* PROBLEM GONE Aug 2021. fix reply to wrong socket - udp packets should reply to same socket as they came from, udp data packets should be sent to same socket as requested them, not same socket as last command.
* DONE 2021jul30. add fixes from Chris P. for the auto-negotiation and dhcp (see email from him).
* DONE flash chip connected to FPGA. Aug 2021. implement ethernet flash programmer
* DONE Aug 2021. updated maxv firmware. implement FPGA reboot
* speed up programming the MLU by writing more than 1 bit at a time
* DONE Nov 2021. add 64-bit bitmap of BSC trigger bits
* DONE. add chronobox code
* DONE. add avalon mux for alphag and chronobox packets
* DONE. add chronobox fifo to udp packet sequencer
* check that TxReadyOut is correct and it is safe to send an avalon packet while previous packet is still transmitting.
* DONE. test fiber SFP is working
* complete the UDP flash programmer (parallel flash erase and write)

= End =

//KO

TRG

2022-07-15T21:48:16Z

Olchansk: /* conf_bsc_control bits */

= TRG, the trigger control board for the ALPHA-g detector =

= Links =

* xxx
* https://bitbucket.org/expalpha/trg_firmware - firmware sources on bitbucket

= General characteristics =

== Photos ==

== Board schematics ==

* https://bitbucket.org/expalpha/trg_firmware/src/master/3xFMC_VME_Motherboard.pdf

== Available hardware ==

* Altera Stratix IV - main FPGA
* Altera Max V - boot FPGA
* boot flash: PC28F512M29EW - 512 Mbit parallel NOR flash.

= TRG front panel connections =

From top to bottom:

<pre>
|
| minisas-C - links 8-11
| minisas-D - links 12-15
|
| ethernet sfp - use copper sfp only
| minisas - not used, do not connect
| esata - clock in, trigger out
|
| minisas-A - links 0-3
| minisas-B - links 4-7
|
| LEDs
|
</pre>

MiniSAS and SATA flail cable connections:

<pre>
P1 <--> link 3
P2 <--> link 2
P3 <--> link 1
P4 <--> link 0
</pre>

LEDs:

<pre>
--PCB-- (left)
LED[0] - trigger out - ag_trig_out
LED[1] - network packet received - sfp_rx_data_valid
LED[2] - Xilinx FPGA boot ok - FMC1_CFG_DONE
LED[3] - not used
(right)
</pre>

= TRG onboard jumpers and switches =

* rotary switches: select IP address: 00=192.168.1.50, 11=.51, 22=.52, 33=.53, 44=.54, otherwire=.251

= Firmware update procedure =

* use quartus to generate the grifc.pof file (use grifc.cof)
* open quartus programmer
* attach grifc.pof to the 1st CFI_512 flash
* mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
* check that "initiate configuration after programming" is set in tools->options
* say "start"
* should take about 5 minutes
* grifc should reboot into the new firmware

If CFI_512 flash is not visible to the quartus programmer, load correct
code into the MaxV CPLD:

* open quartus programmer,
* say "auto detect"
* change file for the 5M2210 device
* use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
* say "program", it should finish in 10-15 seconds
* say "auto detect"
* CFI_512 flash should be visible now.

= Firmware revisions =

* 0x5bc8f90f - original firmware used for all data
* 0x6147c0f9 - added cbtrg, etc. installed at CERN on 20 Sep 2021.
* 0x618376ae - bigger cbtrg fifo, data rate tested up to 30 Mbytes/sec
* 0x6189c7f3 - fix loss of trigger packets. (missing fifo between alphag block and ethernet mux)
* 0x618b790b - fix loss of timestamps. (cbtrg inputs stretched to 100 ns long). installed at CERN 10 Nov 2021.

= Firmware build =

* use quartus 20.1
* see Makefile in the trg_firmware project

= Jtag remote connection =

* ssh agmini@daq16
* /opt/intelFPGA/16.1/quartus/bin/jtagd --config /home/agmini/.jtagd.conf
* netstat -an | grep 1309 ### note listen address is "0.0.0.0", NOT "127.0.0.1"
<pre>
tcp 0 0 0.0.0.0:1309 0.0.0.0:* LISTEN
</pre>
* opt/intelFPGA/16.1/quartus/bin/jtagconfig ### should work
* ssh olchansk@daq01
* cd git/trg_firmware
* /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
* jtagconfig ### should work
<pre>
daq01:trg_firmware$ jtagconfig
1) DE-SoC on daq16 [2-1.2.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) USB-Blaster on daq16 [2-1.3]
024090DD EP4SGX230(.|ES)
020A40DD 5M(1270ZF324|2210Z)/EPM2210

daq01:trg_firmware$
</pre>

= ALPHA-g trigger functions =

Trigger options:
* software trigger
* pulser trigger
* trigger on GRIF16 ADC NIM and ESATA inputs ("external trigger")
* adc16 grand-or
* adc32 grand-or
* adc16 wire multiplicity
* TPC anode wire per-preamp trigger (aw16 section)
** trigger on coincidences of preamps (removed fw 0x62c77f0b)
** trigger on multiplicity of preamps (removed fw 0x62c77f0b)
** trigger on specific topology of preamps (multiplicity of preamp clusters, etc) via the aw16_mlu trigger
* BSC trigger
** BSC grand_or
** BSC bar multiplicity
* coincidence trigger - select coincidence of external trigger, TPC AW grand-or, TPC AW MLU, BSC grand-or and BSC bar multiplicity triggers

== software trigger ==

to programmatically fire the trigger, one should:
* set the conf_enable_sw_trigger bit in conf_trig_enable, this will permit the software trigger to fire the trigger
* write value 0x4 to register 0x2B, this will cause the software trigger to fire

== pulser trigger ==

To use the pulser trigger, one should program:
* pulser period (in clocks)
* pulser width (in clocks, use value 5, the pulser no longer goes outside of the trigger board, so changing the width does not do anything)
* set the run_pulser bit in conf_trig_enable, this will cause the pulser to run
* set the enable_pulser bit in conf_trig_enable, this will cause the pulser to fire the trigger
* set the output_pulser bit in conf_trig_enable, this will cause the pulser to be output from the alphag firmware block (the pulser no longer goes outside of the trigger board, so changing the bit does not do anything)

== timeout trigger ==

The event builder uses event timestamps to assemble physics events. The timestamps
are usually 32 bit wide and run at 125 MHz (8 ns) or 62.5 MHz (16 ns). If
triggers are generated often (1 per second or more), timestamp wrap around
is easily detected by the event builder. If triggers come infrequently,
timestamp wrap around may occur while there are no triggers, not be seen
by the event builder causing loss of event synchronization.

To avoid this problem in the event builder, a timeout trigger should be generated
if no triggers were generated inside a 10 second interval.

The guaranties that even if all physics triggers temporarily stop for any reason,
the event builder will stay synchronized. (0.1 Hz timeout trigger frequency).

To enable the timeout trigger:
* program timeout trigger timeout in reg 0x43 in units of 8 ns clock
* enable it in bit 23 of [[#conf_trig_enable bits]]

== adc16 multiplicity trigger ==

This trigger is intended for use with the barrel scintillator signals connected to adc16 digitizers. It does not work well with TPC AW signals.

The 16 adc16 trigger bits (16x16=256) are added together to form the hit multiplicity value (adc16_mult, 16 bits, actual range 0 to 256).

Four threshold signals are computed: adc16_mult_1ormore = adc16_mult>=1, 2ormore, 3ormore, 4ormore.

There is a counter for each of these four signals.

Each of these four signals can fire the trigger, see [[#conf_trig_enable bits]].

== TPC anode wire triggers ==

=== aw16 bus ===

TPC Anode Wire trigger is based on the aw16[15:0] (xaw16) bus.

Each bit corresponds to one AW preamp. 16 preamps, 16 bits.

The aw16[15:0] bus can be fed by
* adc16_or16[15:0] - or16 of 100 MHz ADCs, 16 ADC sas links
* adc32_or16[15:0] - or16 of 62.5 MHz ADCs, FMC-ADC32 has 32 channels, so 2 bits per ADC: low 16 channels and high 16 channels, sas links 7..0
* adc32_or16[31:16] - or16 of 62.5 MHz ADCs, ditto, sas links 15..8
as selected by conf_enable_aw_adc16, conf_enable_aw_adc32a, conf_enable_aw_adc32b in [[#conf_control bits]]

<pre>
///////////////////////////////////////////////////////////
// TPC Anode Wire trigger logic (aw16)
///////////////////////////////////////////////////////////

// map adc signals into aw16

wire [15:0] aw16 = ({16{conf_enable_aw_adc16}} & adc16_or16[15:0]) |
({16{conf_enable_aw_adc32a}} & adc32_or16[15:0]) |
({16{conf_enable_aw_adc32b}} & adc32_or16[31:16]);
...
ag_conditioner cond_adc16_or16_0(.clk(clk), .in(aw16[0]), .out(xxaw16[0]));
...
xaw16 <= xxaw16;
</pre>

=== aw16_grand_or ===

TPC AW "grand or" trigger: use aw16_mult_1ormore (before fw 0x62c77f0b)

(256 anode wires, 16 wires per preamp, 16 preamps, 16 aw16 signals)

=== aw16_mlu ===

TPC AW preamp MLU trigger: the MLU (memory lookup
table) implements an arbitrary logical function
to map the 16 aw16 preamp signals into 1 aw16_mlu_trig trigger output.

Description of the aw16 mlu trigger.

In words:

* any aw16 signal starts the aw16_prompt_run gate
* aw16 signals are collected for the duration of conf_mlu_prompt (125MHz/8ns clock)
* this corresponds to time spread of TPC AW signals due to the drift time in the AW drift cell and to the variation in signal transmission time from the ADC to the TRG (digital trigger data link).
* when this prompt time expires, the MLU looks at the accumulated aw16_prompt bit pattern and makes the "yes/no" trigger decision
* after the trigger decision is made, we wait for the TPC to become quiet:
* we wait until all aw16 signals are empty (no timeout)
* we run the aw16_prompt_wait gate, length conf_mlu_wait (8ns clock), if any aw16 signals arrive, we wait for aw16 empty again, rinse, repeat.
* now, after TPC aw16 have been empty for conf_mlu_wait clocks (8ns clock), MLU trigger is ready for the next event.

In logic: (see alphag.v)

* aw16_or <= grand-or of 16 aw16 signals
* "aw16_or" starts the "aw16_prompt_cnt" counter, opens the aw16_prompt_run gate
* during the aw16_prompt_run gate, aw16_prompt collects (latches) the aw16 bits (aw16_prompt <= aw16_prompt | aw16)
* this is the time when we wait for all "prompt" signals from the TPC to arrive into the trigger
* at the end of the aw16_prompt_run gate, the signal aw16_prompt_out is pulsed, latching the output of the MLU into aw16_mlu_trig
* this is the MLU trigger "yes/no" trigger decision.
* after the MLU trigger decision is made, we wait for the arrival and passing of all TPC drift signals
* the aw16_prompt_wait_cnt and aw_prompt_wait gate opens
* if any new aw16 signals arrive (they are TPC drift signals at this time), the aw16_prompt_wait gate is restarted
* if no aw16 signals arrive during the full run of the aw16_prompt_wait gate ("TPC quiet time")
* the aw16_prompt_wait and aw16_prompt gates are cleared and the MLU trigger is ready for the next event.

Good settings are:
* conf_mlu_prompt: 64 (512 ns)
* conf_mlu_wait: 128 (1024 ns)

== BSC trigger ==

=== bsc_adc16 bus ===

The BSC trigger is based on the [15:0]bsc_adc16[7:0] bus: 16 trigger discriminator bits from 8 ADC sas links. (8*16 = 64+64 bars, top and bottom).

The bsc_adc16 bus can be fed from sas links 0..7 or 8..15, controlled by conf_bsc_adc16_a and conf_bsc_adc16_b bits on [[#conf_bsc_control bits]].

bsc_adc16 can be fed only from GRIF-16 100 MHz ADC trigger discriminators.

=== bsc64_top and bsc64_bot buses ===

* firmware 0x5bc8f90f: bsc_adc16 is remapped into 64 bits of top (bsc64_top) and bottom (bsc64_bot):
<pre>
ag_bsc_remap bsc_remap_a(.adc(bsc_adc16[0]), .bsc_bot(bsc64_bot[7:0]), .bsc_top(bsc64_top[7:0]));
ag_bsc_remap bsc_remap_b(.adc(bsc_adc16[1]), .bsc_bot(bsc64_bot[8+7:8+0]), .bsc_top(bsc64_top[8+7:8+0]));
ag_bsc_remap bsc_remap_c(.adc(bsc_adc16[2]), .bsc_bot(bsc64_bot[2*8+7:2*8+0]), .bsc_top(bsc64_top[2*8+7:2*8+0]));
ag_bsc_remap bsc_remap_d(.adc(bsc_adc16[3]), .bsc_bot(bsc64_bot[3*8+7:3*8+0]), .bsc_top(bsc64_top[3*8+7:3*8+0]));

ag_bsc_remap bsc_remap_e(.adc(bsc_adc16[4]), .bsc_bot(bsc64_bot[4*8+7:4*8+0]), .bsc_top(bsc64_top[4*8+7:4*8+0]));
ag_bsc_remap bsc_remap_f(.adc(bsc_adc16[5]), .bsc_bot(bsc64_bot[5*8+7:5*8+0]), .bsc_top(bsc64_top[5*8+7:5*8+0]));
ag_bsc_remap bsc_remap_g(.adc(bsc_adc16[6]), .bsc_bot(bsc64_bot[6*8+7:6*8+0]), .bsc_top(bsc64_top[6*8+7:6*8+0]));
ag_bsc_remap bsc_remap_h(.adc(bsc_adc16[7]), .bsc_bot(bsc64_bot[7*8+7:7*8+0]), .bsc_top(bsc64_top[7*8+7:7*8+0]));

module ag_bsc_remap
(
input wire [15:0] adc,
output wire [7:0] bsc_bot,
output wire [7:0] bsc_top
);

assign bsc_top[3] = adc[0];
assign bsc_top[2] = adc[1];
assign bsc_top[1] = adc[2];
assign bsc_top[0] = adc[3];

assign bsc_top[7] = adc[4];
assign bsc_top[6] = adc[5];
assign bsc_top[5] = adc[6];
assign bsc_top[4] = adc[7];

assign bsc_bot[0] = adc[8];
assign bsc_bot[1] = adc[9];
assign bsc_bot[2] = adc[10];
assign bsc_bot[3] = adc[11];

assign bsc_bot[4] = adc[12];
assign bsc_bot[5] = adc[13];
assign bsc_bot[6] = adc[14];
assign bsc_bot[7] = adc[15];

endmodule
</pre>

=== bsc64 bus ===

the bsc64 bus is the 64 bars used by the trigger, formed from bsc64_top and bsc64_bot:
<pre>
if (conf_bsc64_bot_only) begin
bsc64 <= bsc64_bot;
end else if (conf_bsc64_top_only) begin
bsc64 <= bsc64_top;
end else if (conf_bsc64_bot_top_or) begin
bsc64 <= bsc64_bot | bsc64_top;
end else if (conf_bsc64_bot_top_and) begin
bsc64 <= bsc64_bot & bsc64_top;
end else begin
bsc64 <= 64'b0;
end
</pre>

=== bsc_grand_or_trig ===

bsc_grand_or_trig is the grand-or of 64 bits of the bsc64 bus

to enable triggering on bsc_grand_or_trig, set corresponding bit in [[#conf_trig_enable bits]]

=== old bsc_mult_trig ===

(from fw 0x62c77f0b, old bsc_mult_trig was replaced by new bsc64 multiplicity trigger)

* bsc64_mult is computed as multiplicity of the bsc64 bus (number of 64 bsc64 bits that fired)
* bsc_mult_trig is computed:
<pre>
if (bsc64_mult >= conf_bsc64_mult) begin
bsc_mult_trig <= 1;
end else begin
bsc_mult_trig <= 0;
end
</pre>

to enable the bsc multiplicity trigger, set the multiplicity value conf_bsc64_mult in [[#conf_bsc_control bits]] and enable the corresponding bit in [[#conf_trig_enable bits]].

=== bsc64 multiplicity trigger ===

bsc64 BSC bar multiplicity trigger uses a time window. this time window is started by bsc64_grand_or and runs for conf_bsc64_mult_window clocks (8 nc clock). During this time, hits in bsc64_bus are accumulated (latched) and their multiplicity is computed. If multiplicity condition is satisfied (bigger or equal to conf_bsc64_mult_min), bsc64_mult_trig is fired and the bsc64 bit pattern is saved to the UDP packet. Then trigger waits for the bsc64_bus to be empty. Then trigger waits for conf_bsc64_empty_window clocks, if there is any bsc64 hits, we wait for empty again. So after bsc64 has been empty for conf_bsc64_empty_window clocks, multiplicity trigger is ready for the next event. This scheme cannot implement max multiplicity.

recommended values:
* conf_bsc64_mult_window (8 bits): slightly longer than 3 cycles of SAS link: 3*18 = 54 clocks, good value is 80 (640 ns).
* conf_bsc64_mult_min (8 bits): 2
* conf_bsc64_empty_window (8 bits): 80 (640 ns)

== Coincidence trigger ==

Coincidence trigger provides a combination of TPC, BSC and external scintillator (esata_nim_grand_or) signals:

<pre>
assign coinc_input[0] = aw16_grand_or; // was aw16_mult_1ormore;
assign coinc_input[1] = aw16_mlu_trig;
assign coinc_input[2] = bsc_grand_or_trig;
assign coinc_input[3] = bsc_mult_trig;
assign coinc_input[4] = esata_nim_grand_or;
assign coinc_input[5] = 0;
assign coinc_input[6] = 0;
assign coinc_input[7] = 0;
</pre>

Coincidence trigger "start" mask selects which of the inputs can start the coincidence window.

Coincidence trigger "require" mask selects which inputs must have a hits for the coincidence ot be satisfied.

Input hits are collected for the duration of the coincidence window, if all required inputs have hits, coinc_trig is fired.

Example settings:

* coincidence of external scintillator, BSC and TPC AW "grand or" signals: start 0x10, required 0x15
* coincidence of BSC and TPC AW "grand or" signals: start 0x4, required 0x5
* coincidence of BSC and TPC AW MLU triggers: start 0x4, required 0x6
* coincidence of BSC multiplicity and TPC AW MLU triggers: start 0x8, required 0xA

= Control registers =

== Register addresses ==

Note: all registers are 32 bits unless otherwise noted.

Note: RW means read-write register, RO means read-only, ROL means read-only, contents is latched by the "latch_out" bit

{| cellpadding="10" cellspacing="0" border="1"
! Address || Quartus Name || Access || FwRev || Description
|-
| 0x08 || num_sample || RW || GRIF-C || magic 16-bit register to control UDP packet size
|-
| 0x08 || scratch_reg || RW || 0x618b790b || 32-bit scratch register
|-
| 0x1F || compilation_time || RO || || Firmware revision
|-
| 0x20 || conf_trig_width || RW || || Trigger signal width, 16 ns clock
|-
| 0x21 || conf_busy_width || RW || || Busy signal width, 16 ns clock (not used)
|-
| 0x22 || conf_pulser_width || RW || || Pulser signal width, 16 ns clock
|-
| 0x23 || conf_pulser_period || RW || || Pulser signal period, 16 ns clock
|-
| 0x24 || conf_pulser_burst_ctrl || RW || 0x62d1c47e || Generate bursts of pulses: 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses, 16 ns clocks
|-
| 0x25 || conf_trig_enable || RW || || see [[#conf_trig_enable bits]]
|-
| 0x26 || || || not used
|-
| 0x27 || || || not used
|-
| 0x28 || || || not used
|-
| 0x29 || conf_nim_mask || RW || || enable bits for ADC NIM inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2A || conf_esata_mask || RW || || enable bits for ADC eSATA inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2B || reset_out, latch_out, trigger_out || W || || see [[#reg 0x2B bits]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x5bc8f90f || configure AW coincidence trigger, see [[#aw16_coinc]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x62c77f0b || removed
|-
| 0x2D || conf_aw16_coinc_b || RW || 0x5bc8f90f ||
|-
| 0x2E || conf_aw16_coinc_c || RW || 0x5bc8f90f ||
|-
| 0x2F || conf_aw16_coinc_d || RW || 0x5bc8f90f ||
|-
| 0x30 || sas_sd[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect for each link
|-
| 0x31 || pll_625_status || ROL || 0x5b2057f5 (12Jun18_16:32) || 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter
|-
| 0x32 || clk_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the system 125 MHz clock
|-
| 0x33 || clk_625_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625)
|-
| 0x34 || conf_control || RW || 0x5b398983 (01Jul18_19:10) || see [[#conf_control bits]] below
|-
| 0x35 || conf_drift_width || RW || 0x5b398983 (01Jul18_19:10) || width of drift time blank-out in 16 ns clocks
|-
| 0x36 || conf_scaledown || RW || 0x5b398983 (01Jul18_19:10) || trigger scaledown, 0=no scaledown, 1=divide-by-2, 2=divide-by-3, etc
|-
| 0x37 || conf_mlu || RW || 0x5b398983 (01Jul18_19:10) || AW MLU control bits, see [[#conf_mlu bits]]
|-
| 0x38 || conf_trig_delay || RW || 0x5baedfca (28Sep18_19:13) || delay the trigger pulse, 16 ns clock
|-
| 0x39 || esata_clk_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the TRG 125 MHz clock
|-
| 0x3A || esata_clk_esata_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the external clock (eSATA 62.5 MHz clock)
|-
| 0x3B || conf_counter_adc_select || RW || 0x5bb7f6ae (05Oct18_16:41) || select which 16 ADCs are connected to the selected adc counters, 0..15 - connect the adc16 signals, 16..47 connect the adc32 signals
|-
| 0x3C || sysreset_ts || RO || 0x5bb7f6ae (05Oct18_16:41) || 125MHz counter of VME-SYSRESET
|-
| 0x3C || || || 0x618b790b || not used
|-
| 0x3D || GRIF-C csr || RW || GRIF-C || <= csr & ~par_value; // Selective clear
|-
| 0x3E || GRIF-C csr || RW || GRIF-C || <= csr | par_value; // Selective set
|-
| 0x3F || GRIF-C csr || RW || GRIF-C || <= par_value; // write
|-
| 0x3D || || || 0x618b790b || not used
|-
| 0x3E || || || 0x618b790b || not used
|-
| 0x3F || || || 0x618b790b || not used
|-
| 0x40 || conf_bsc_control || RW || 0x5bc13541 (12Oct18_16:58) || Barrel Scintillator trigger control, see [[#conf_bsc_control bits]]
|-
| 0x41 || conf_coinc_control || RW || 0x5bc13541 (12Oct18_16:58) || Coincidence trigger control, see [[#conf_coinc_control bits]]
|-
| 0x42 || reconfig_out || WO || 0x5bc13541 (12Oct18_16:58) || reserved for rebooting the FPGA (does not work)
|-
| 0x43 || conf_trigger_timeout || RW || 0x5bc8f90f (18Oct18_14:20) || Generate timeout trigger if there is no other trigger after given timeout, in 8 ns clocks, must be enabled by bit conf_enable_timeout_trig in [[#conf_trig_enable bits]]
|-
| 0x44 || eth_clk_counter || ROL || 0x618b790b ||
|-
| 0x45 || eth_clk_eth_counter || ROL || 0x618b790b ||
|-
| 0x100 || ts_625 || ROL || || latched timestamp
|-
| 0x101 || counter_trig_out || ROL || || counter of issued triggers
|-
| 0x102 || counter_trig_in || ROL || || counter of triggers
|-
| 0x103 || counter_pulser || ROL || || counter of pulser
|-
| 0x104 || counter_adc16_grand_or || ROL ||
|-
| 0x105 || counter_adc32_grand_or || ROL ||
|-
| 0x106 || counter_adc_grand_or || ROL ||
|-
| 0x107 || counter_esata_nim_grand_or || ROL ||
|-
| 0x108 || counter_adc16_mult_1ormore || ROL ||
|-
| 0x109 || counter_adc16_mult_2ormore || ROL ||
|-
| 0x10A || counter_adc16_mult_3ormore || ROL ||
|-
| 0x10B || counter_adc16_mult_4ormore || ROL ||
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x5bc8f90f || counter of AW coincidence triggers
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x62c77f0b || removed
|-
| 0x10D || counter_aw16_coinc_b || ROL || 0x5bc8f90f ||
|-
| 0x10E || counter_aw16_coinc_c || ROL || 0x5bc8f90f ||
|-
| 0x10F || counter_aw16_coinc_d || ROL || 0x5bc8f90f ||
|-
| 0x110 || counter_drift || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the drift time blank-out
|-
| 0x111 || counter_scaledown || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the scaledown
|-
| 0x112 || counter_aw16_coinc || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW coincidence triggers
|-
| 0x113 || counter_aw16_mlu || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW MLU triggers
|-
| 0x114 || counter_aw16_grand_or || ROL || 0x62c77f0b || counter of AW grand-or triggers
|-
| 0x114 || counter_aw16_mult_1ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 1ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 2ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x62c77f0b || removed
|-
| 0x116 || counter_aw16_mult_3ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 3ormore triggers
|-
| 0x117 || counter_aw16_mult_4ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 4ormore triggers
|-
| 0x118 || counter_bsc_grand_or || ROL || 0x5bc13541 (12Oct18_16:58) || counter of BSC grand-or triggers
|-
| 0x119 || counter_bsc_mult || ROL || 0x5bc13541 (12Oct18_16:58) || counter of old BSC multiplicity triggers
|-
| 0x11A || counter_coinc || ROL || 0x5bc13541 (12Oct18_16:58) || counter of coincidence triggers
|-
| 0x11B || counter_timeout || ROL || 0x618b790b || counter of timeout triggers
|-
| 0x11C || counter_bsc_mult_start || ROL || 0x62c77f0b || counter of BSC multiplicity windows
|-
| 0x11D || counter_bsc_mult_trig || ROL || 0x62c77f0b || counter of BSC multiplicity triggers
|-
| 0x11E || counter_coinc_start || ROL || 0x62d1b152 || counter of coincidence windows
|-
| 0x11F || counter_aw16_mlu_start || ROL || 0x62d1b152 || counter of TPC AW MLU windows
|-
| 0x200..0x207 || conf_adc16_masks || RW || all || adc16 enable bits
|-
| 0x300..0x30F || conf_adc32_masks || RW || all || adc32 enable bits
|-
| 0x400..0x41F || sas_bits[15:0][63:0] || ROL || all || sas data bits for each link
|-
| 0x420..0x42F || sas_sd_counters[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect counter for each link
|-
| 0x430..0x43F || counters_adc16_or16[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 16 counters of adc16 ORes
|-
| 0x440..0x45F || counters_adc32_or16[31:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 32 counters of adc32 ORes
|-
| 0x460..0x46F || counters_adc_selected[15:0] || ROL || 0x5bb7f6ae (05Oct18_16:41) || 16 counters for selected group of adcs, see conf_counter_adc_select
|-
| 0x470..0x4AF || counters_bsc64[63:0] || ROL || 0x5bc13541 (12Oct18_16:58) || 64 counters for the BSC bars
|-
|}

== additional registers ==

<pre>
reg | rw/ro | quartus name | firmware | description
0x60: param_out <= {2'h3, par_id, chan, cb_control_out
0x61: param_out <= {2'h3, par_id, chan, cb_status
0x62: param_out <= {2'h3, par_id, chan, cb_invert_a_out };
0x63: param_out <= {2'h3, par_id, chan, cb_invert_b_out };
0x64: param_out <= {2'h3, par_id, chan, cb_enable_le_a_out };
0x65: param_out <= {2'h3, par_id, chan, cb_enable_le_b_out };
0x66: param_out <= {2'h3, par_id, chan, cb_enable_te_a_out };
0x67: param_out <= {2'h3, par_id, chan, cb_enable_te_b_out };
0x6A | ro | cb_input_num | 0x618b790b | chronobox number of inputs
0x6B: param_out <= {2'h3, par_id, chan, cb_sync_mask_a_out };
0x6C: param_out <= {2'h3, par_id, chan, cb_sync_mask_b_out };
0x6D: param_out <= {2'h3, par_id, chan, cb_sync_reg_out };
0x6E: param_out <= {2'h3, par_id, chan, cb_sync_status };
0x6F: param_out <= {2'h3, par_id, chan, cb_latch_period_out };
0x70: param_out <= {2'h3, par_id, chan, cb_fifo_status };
0x71: begin param_out <= {2'h3, par_id, chan, cb_fifo_data }; cb_fifo_rdack_out <= 1; end
0x72: param_out <= {2'h3, par_id, chan, cb_udp_period_out };
0x73: param_out <= {2'h3, par_id, chan, cb_udp_threshold_out };
</pre>

== conf_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_clock_select || 0x5b3aa19f (02Jul18_15:05) || select 0=internal 62.5 MHz clock or 1=esata 62.5 MHz clock
|-
| 1 || conf_enable_aw_adc16 || 0x5baedfca (28Sep18_19:13) || select source of TPC AW aw16 bus, see [[#aw16 bus]]
|-
| 2 || conf_enable_aw_adc32a || 0x5baedfca (28Sep18_19:13) ||
|-
| 3 || conf_enable_aw_adc32b || 0x5baedfca (28Sep18_19:13) ||
|-
| 15..4 || || ||
|-
| 23..16 || conf_mlu_prompt || 0x5b3aa19f (02Jul18_15:05) || MLU trigger prompt window, see [[#aw16_mlu]]
|-
| 31..24 || conf_mlu_wait || 0x5b3aa19f (02Jul18_15:05) || MLU trigger wait window, see [[#aw16_mlu]]
|-
|}

== conf_mlu bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 31 || mlu_reset || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 30 || mlu_write || 0x5b3aa19f (02Jul18_15:05) || 1=write data bit into given address
|-
| 16 || mlu_data || 0x5b3aa19f (02Jul18_15:05) || data bit for writing to MLU RAM
|-
| 15..0 || mlu_write_addr || 0x5b3aa19f (02Jul18_15:05) || MLU RAM write address for writing the data bit
|-
|}

== conf_bsc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_bsc_adc_a || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 0..7
|-
| 1 || conf_bsc_adc_b || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 8..15
|-
| 2 || conf_bsc64_bot_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses bottom channels only
|-
| 3 || conf_bsc64_top_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses top channels only
|-
| 4 || conf_bsc64_bot_top_or || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "or" of top and bottom
|-
| 5 || conf_bsc64_bot_top_and || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "and" of top and bottom
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_bsc64_mult_min || 0x5bc13541 (12Oct18_16:58) || minimum bsc64 multiplicity
|-
| 23..16 || conf_bsc64_empty_wondow || 0x62d1c47e || bsc64 empty window length, 8 ns clocks
|-
| 31..24 || conf_bsc64_mult_window || 0x62c77f0b || bsc64 multiplicity window length, 8 ns clocks
|-
|}

== conf_coinc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_coinc_required[0] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mult_1ormore
|-
| 0 || conf_coinc_required[0] || 0x62c77f0b || enable aw16_grand_or
|-
| 1 || conf_coinc_required[1] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mlu_trig
|-
| 2 || conf_coinc_required[2] || 0x5bc13541 (12Oct18_16:58) || enable bsc_grand_or_trig
|-
| 3 || conf_coinc_required[3] || 0x5bc13541 (12Oct18_16:58) || enable bsc_mult_trig
|-
| 3 || conf_coinc_required[3] || 0x62c77f0b || enable bsc64_mult_trig
|-
| 4 || conf_coinc_required[4] || 0x5bc13541 (12Oct18_16:58) || enable esata_nim_grand_or
|-
| 5 ||
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_coinc_window[7:0] || 0x5bc13541 (12Oct18_16:58) || coincidence window length in units of 125MHz clock (8 ns)
|-
| 23..16 || conf_coinc_start[7:0] || 0x5bc13541 (12Oct18_16:58) || start the coincidence window, same bits as "required"
|-
| 31..24 ||
|-
|}

== conf_trig_enable bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_enable_sw_trigger || || trigger on software trigger (how generated???)
|-
| 1 || conf_enable_pulser || || trigger on pulser
|-
| 2 || - || 0x5b120c9f (01Jun18_20:18) || not used
|-
| 3 || conf_pulser_run || || allow the pulser to run (frequency has to be set beforehand)
|-
| 4 || conf_output_pulser || 0x5bc8f90f || does nothing (top level ag_pulser_out is disconnected)
|-
| 4 || || 0x618b790b || not used
|-
| 5 || conf_enable_esata_nim || || trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand)
|-
| 6 || conf_enable_adc16 || || trigger on adc16_grand_or
|-
| 7 || conf_enable_adc32 || || trigger on adc32_grand_or
|-
| 8 || conf_enable_adc16_1ormore || || trigger on adc16_mult_1ormore "1 or more"
|-
| 9 || conf_enable_adc16_2ormore || || same, "2 or more"
|-
| 10 || conf_enable_adc16_3ormore || || same, "3 or more"
|-
| 11 || conf_enable_adc16_4ormore || || same, "4 or more"
|-
| 12 || - || 0x5b08938c (25May18_15:51) || not used
|-
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
|-
| 14 || - || 0x5bc8f90f || not used
|-
| 15 || conf_enable_adc || 0x5b120c9f (01Jun18_20:18) || trigger on adc_grand_or
|-
| 16 || conf_enable_aw16_coinc_a || 0x5bc8f90f || enable AW coincidence trigger, see [[#aw16_coinc]]
|-
| 16 || - || 0x62c77f0b || aw16_coinc_x removed
|-
| 17 || conf_enable_aw16_coinc_b || 0x5bc8f90f ||
|-
| 18 || conf_enable_aw16_coinc_c || 0x5bc8f90f ||
|-
| 19 || conf_enable_aw16_coinc_d || 0x5bc8f90f ||
|-
| 20 || - || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 20 || conf_enable_aw16_grand_or || 0x618b790b || enable trigger on aw16_grand_or
|-
| 21 || conf_enable_aw16_coinc || 0x5b3aa19f (02Jul18_15:05) || enable trigger on aw16_coinc_trig
|-
| 22 || conf_enable_aw16_mlu || 0x5b3aa19f (02Jul18_15:05) || enable AW MLU trigger
|-
| 23 || conf_enable_timeout_trig || 0x5bc8f90f (18Oct18_14:20) || enable trigger timeout trigger
|-
| 24 || conf_enable_aw16_1ormore || 0x5b3aa19f (02Jul18_15:05) || trigger on aw16_mult_1ormore "1 or more"
|-
| 24 || - || 0x62c77f0b || aw16_mult_xxx removed
|-
| 25 || conf_enable_aw16_2ormore || 0x5b3aa19f (02Jul18_15:05) || same, "2 or more"
|-
| 26 || conf_enable_aw16_3ormore || 0x5b3aa19f (02Jul18_15:05) || same, "3 or more"
|-
| 27 || conf_enable_aw16_4ormore || 0x5b3aa19f (02Jul18_15:05) || same, "4 or more"
|-
| 28 || conf_enable_bsc_grand_or || 0x5bc13541 (12Oct18_16:58) || trigger on BSC grand-or
|-
| 29 || conf_enable_bsc_mult || 0x5bc13541 (12Oct18_16:58) || trigger on BSC multiplicity
|-
| 30 || conf_enable_coinc || 0x5bc13541 (12Oct18_16:58) || trigger on TPC/BSC/ext coincidence trigger
|-
| 31 || - || || not used
|-
|}

== reg 0x2B bits ==

Write to this register will pulse corresponding fpga signals:

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || reset_out || 0x5b120c9f (01Jun18_20:18) || reset counters, etc
|-
| 1 || latch_out || 0x5b120c9f (01Jun18_20:18) || latch counters, sas bits, etc
|-
| 2 || trigger_out || 0x5b120c9f (01Jun18_20:18) || generate a software trigger
|-
|}

= UDP data format =

== firmware 0x5bc8f90f ==

{| cellpadding="10" cellspacing="0" border="1"
! Offset || Name || Quartus name || FwRev || Description
|-
| 0 || packet counter || none || all || 31-bit UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
|-
| 1 || 0x8 packet header || || all || 28 bits of counter_trig_out
|-
| 2 || trigger timestamp || trig_ts || all || 62.5MHz trigger timestamp
|-
| 3 || accepted triggers || counter_trig_out || all || counter of accepted triggers
|-
| 4 || input triggers || counter_trig_in || all || counter of trigger input
|-
| 5 || pulser triggers || counter_pulser || all || counter of pulser triggers
|-
| 6 || trigger bitmap || udp_trig_bits || 0x5a48448d (30Dec17_17:59) || bitmap of trigger information, see below
|-
| 7 || nim bits || udp_nim_bits_masked || ??? || 32 bits of ADC NIM inputs (2 bits per ADC)
|-
| 8 || esata bits || udp_esata_bits_masked || ??? || 32 bits of ADC ESATA inputs (2 bits per ADC)
|-
| 9 || mlu bits || aw16_prompt || 0x5b398983 (01Jul18_19:10) || 16 bits of MLU input, 1 bit per preamp
|-
| 10 || drift-blank-off counter || udp_drift_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the drift blank-off
|-
| 11 || scaledown counter || udp_scaledown_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the scaledown
|-
| X || || || ||
|-
| 12 || 0xE packet footer || || all || 28 bits of counter_trig_out
|-
|}

== firmware 0x618b790b (Nov 2021) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

== trigger bitmap ==

Firmware ??? (one of the very early revisions)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= adc16_coinc_top;
udp_trig_bits[5] <= adc16_coinc_bot;
udp_trig_bits[6] <= adc16_coinc;
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
udp_trig_bits[31:24] <= mult16[7:0];

</pre>

Firmware 0x5b08938c (25May18_15:51)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= 0; // not used
udp_trig_bits[31:24] <= mult16[7:0];
</pre>

Firmware 0x5b217dc4 (13Jun18_13:25)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5b3aa19f (02Jul18_15:05)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= udp_mlu_out;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5bc8f90f (18Oct18_14:20)

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_run_pulser
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = 0; // not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x618b790b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x62c77f0b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = 0; // aw16_coinc_a;
assign trig32_in[17] = 0; // aw16_coinc_b;
assign trig32_in[18] = 0; // aw16_coinc_c;
assign trig32_in[19] = 0; // aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = 0; // aw16_mult_1ormore;
assign trig32_in[25] = 0; // aw16_mult_2ormore;
assign trig32_in[26] = 0; // aw16_mult_3ormore;
assign trig32_in[27] = 0; // aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc64_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

= TRG chronobox inputs =

from trg_firmware/toplevel/grifc.v

<pre>
localparam CB_N = 23;
localparam CB_N1 = CB_N-1;

wire [CB_N1:0] cb_xinputs_async;

assign cb_xinputs_async[0] = ag_trig_out;
assign cb_xinputs_async[1] = ag_trig_scaledown_out;
assign cb_xinputs_async[2] = ag_trig_drift_out;
assign cb_xinputs_async[3] = ag_trig_received_out;

assign cb_xinputs_async[4] = ag_cb_sw_trig;
assign cb_xinputs_async[5] = ag_cb_pulser_trig;
assign cb_xinputs_async[6] = ag_cb_esata_nim_trig;
assign cb_xinputs_async[7] = ag_cb_adc16_grand_or_trig;
assign cb_xinputs_async[8] = ag_cb_adc32_grand_or_trig;

assign cb_xinputs_async[9] = ag_cb_aw16_grand_or_trig;
assign cb_xinputs_async[10] = ag_cb_aw16_mult_1ormore;
assign cb_xinputs_async[11] = ag_cb_aw16_mult_2ormore;
assign cb_xinputs_async[12] = ag_cb_aw16_mult_3ormore;
assign cb_xinputs_async[13] = ag_cb_aw16_mult_4ormore;
assign cb_xinputs_async[14] = ag_cb_aw16_mlu_trig;

assign cb_xinputs_async[15] = ag_cb_bsc64_grand_or_trig;
assign cb_xinputs_async[16] = ag_cb_bsc64_mult_1ormore;
assign cb_xinputs_async[17] = ag_cb_bsc64_mult_2ormore;
assign cb_xinputs_async[18] = ag_cb_bsc64_mult_3ormore;
assign cb_xinputs_async[19] = ag_cb_bsc64_mult_4ormore;
assign cb_xinputs_async[20] = ag_cb_bsc64_mult_trig;

assign cb_xinputs_async[21] = ag_cb_coinc_trig;

assign cb_xinputs_async[22] = ag_cb_timeout_trig;
</pre>

= Example UDP packets =

* trigger data, marker words 0x8

<pre>
ReadDataThread read 76
0: 0x003666ed -- UDP packet counter from UDP transmitter
1: 0x80000bf8 -- 0x8 is trigger data packet, 0xbf8 is the trigger counter from alphag.v
2: 0x2edf8b41 -- trigger data
3: 0x00000bf8
4: 0x00000bf8
5: 0x00000bee
6: 0x00000001
7: 0x00000000
8: 0x00000000
9: 0x00000003
10: 0x00000bf8
11: 0x00000bf8
12: 0x00000000
13: 0x00000000
14: 0x00000000
15: 0x00000000
16: 0x00000000
17: 0x00000000
18: 0xe0000bf8 -- 0xE is end of trigger data, counter 0xbf8 must match the counter in the 0x8 word.
ReadDataThread read 76 -- next packet
0: 0x003666ee -- UDP packet counter from UDP transmitter
...
</pre>

* chronobox fifo data, marker word 0xC, see [[Chronobox#FIFO_data_format]]

<pre>
ReadDataThread read 404
0: 0x003658ed -- UDP packet counter from UDP transmitter
1: 0xc000eacc -- 0xC is FIFO data, fifo packet counter 0xeacc from fifo_to_udp.v
2: 0x00000061 -- FIFO status, low bits the the word counter, so up to 0x61 fifo words are to follow
3: 0x87fb3d72 -- tsc hits
4: 0x8ffb3d74
5: 0x90fb3d74
6: 0x91fb3d74
7: 0x92fb3d74
8: 0x93fb3d74
9: 0x93fb3d75
10: 0x94fb3d74
11: 0x94fb3d77
12: 0x87fb3d77
13: 0x8ffb3d77
14: 0x90fb3d77
15: 0x91fb3d77
16: 0x92fb3d77
17: 0xfe000018 -- 0xFE scaler data starts, 0x18 words to follow
18: 0x00000000
19: 0x00000000
20: 0x00000000
21: 0x00000000
22: 0x00000000
23: 0x00000000
24: 0x00000000
25: 0x00000108
26: 0x00000000
27: 0x00000000
28: 0x00000000
29: 0x00000000
30: 0x00000000
31: 0x00000000
32: 0x00000000
33: 0x00000108
34: 0x00000108
35: 0x00000108
36: 0x00000108
37: 0x00000108
38: 0x00000108
39: 0x00000000
40: 0x00000000
41: 0xce56fa93 -- last word of scaler data is the sysclock counter (125 MHz)
42: 0xff800048 -- timestamp wraparound
43: 0x8f1f36e4 -- tsc hits
44: 0x901f36e4
45: 0x911f36e4
46: 0x921f36e4
47: 0x931f36e4
48: 0x941f36e4
49: 0x871f36e4
50: 0x871f36e7
51: 0x8f1f36e7
52: 0x901f36e9
53: 0x911f36e7
54: 0x921f36e9
55: 0x931f36e7
56: 0x941f36e9
57: 0x904330ac
58: 0x914330ac
59: 0x924330ac
60: 0x934330ac
61: 0x934330ad
62: 0x944330ac
63: 0x944330ad
64: 0x874330ac
65: 0x874330ad
66: 0x8f4330ac
67: 0x8f4330ad
68: 0x904330ad
69: 0x914330ad
70: 0x924330ad
71: 0x8f672a62
72: 0x90672a62
73: 0x91672a62
74: 0x92672a62
75: 0x93672a62
76: 0x94672a62
77: 0x87672a62
78: 0x87672a65
79: 0x8f672a65
80: 0x90672a65
81: 0x91672a65
82: 0x92672a65
83: 0x93672a65
84: 0x94672a65
85: 0xff000049
86: 0x878b2422
87: 0x8f8b2424
88: 0x908b2424
89: 0x918b2424
90: 0x928b2424
91: 0x938b2424
92: 0x938b2425
93: 0x948b2424
94: 0x948b2427
95: 0x878b2427
96: 0x8f8b2427
97: 0x908b2427
98: 0x918b2427
99: 0x928b2427
100: 0xe000eacc -- 0xE is end of fifo data, counter 0xeacc must match the counter in the 0xC word.
ReadDataThread read 344 -- next packet
...
</pre>

= TODO =

* DONE July 2022. add FwRev to the UDP data output
* RJ45 SFP: PROBLEM, D.A. CABLE: GOOD, Fiber SFP: ???. fix "write did not happen" (send udp write command, there is no reply, read returns old data as if write never happened). suspect udp "write" packet is lost?
* PROBLEM GONE Aug 2021. fix reply to wrong socket - udp packets should reply to same socket as they came from, udp data packets should be sent to same socket as requested them, not same socket as last command.
* DONE 2021jul30. add fixes from Chris P. for the auto-negotiation and dhcp (see email from him).
* DONE flash chip connected to FPGA. Aug 2021. implement ethernet flash programmer
* DONE Aug 2021. updated maxv firmware. implement FPGA reboot
* speed up programming the MLU by writing more than 1 bit at a time
* DONE Nov 2021. add 64-bit bitmap of BSC trigger bits
* DONE. add chronobox code
* DONE. add avalon mux for alphag and chronobox packets
* DONE. add chronobox fifo to udp packet sequencer
* check that TxReadyOut is correct and it is safe to send an avalon packet while previous packet is still transmitting.
* DONE. test fiber SFP is working
* complete the UDP flash programmer (parallel flash erase and write)

= End =

//KO

TRG

2022-07-15T20:00:17Z

Olchansk: /* Register addresses */

= TRG, the trigger control board for the ALPHA-g detector =

= Links =

* xxx
* https://bitbucket.org/expalpha/trg_firmware - firmware sources on bitbucket

= General characteristics =

== Photos ==

== Board schematics ==

* https://bitbucket.org/expalpha/trg_firmware/src/master/3xFMC_VME_Motherboard.pdf

== Available hardware ==

* Altera Stratix IV - main FPGA
* Altera Max V - boot FPGA
* boot flash: PC28F512M29EW - 512 Mbit parallel NOR flash.

= TRG front panel connections =

From top to bottom:

<pre>
|
| minisas-C - links 8-11
| minisas-D - links 12-15
|
| ethernet sfp - use copper sfp only
| minisas - not used, do not connect
| esata - clock in, trigger out
|
| minisas-A - links 0-3
| minisas-B - links 4-7
|
| LEDs
|
</pre>

MiniSAS and SATA flail cable connections:

<pre>
P1 <--> link 3
P2 <--> link 2
P3 <--> link 1
P4 <--> link 0
</pre>

LEDs:

<pre>
--PCB-- (left)
LED[0] - trigger out - ag_trig_out
LED[1] - network packet received - sfp_rx_data_valid
LED[2] - Xilinx FPGA boot ok - FMC1_CFG_DONE
LED[3] - not used
(right)
</pre>

= TRG onboard jumpers and switches =

* rotary switches: select IP address: 00=192.168.1.50, 11=.51, 22=.52, 33=.53, 44=.54, otherwire=.251

= Firmware update procedure =

* use quartus to generate the grifc.pof file (use grifc.cof)
* open quartus programmer
* attach grifc.pof to the 1st CFI_512 flash
* mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
* check that "initiate configuration after programming" is set in tools->options
* say "start"
* should take about 5 minutes
* grifc should reboot into the new firmware

If CFI_512 flash is not visible to the quartus programmer, load correct
code into the MaxV CPLD:

* open quartus programmer,
* say "auto detect"
* change file for the 5M2210 device
* use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
* say "program", it should finish in 10-15 seconds
* say "auto detect"
* CFI_512 flash should be visible now.

= Firmware revisions =

* 0x5bc8f90f - original firmware used for all data
* 0x6147c0f9 - added cbtrg, etc. installed at CERN on 20 Sep 2021.
* 0x618376ae - bigger cbtrg fifo, data rate tested up to 30 Mbytes/sec
* 0x6189c7f3 - fix loss of trigger packets. (missing fifo between alphag block and ethernet mux)
* 0x618b790b - fix loss of timestamps. (cbtrg inputs stretched to 100 ns long). installed at CERN 10 Nov 2021.

= Firmware build =

* use quartus 20.1
* see Makefile in the trg_firmware project

= Jtag remote connection =

* ssh agmini@daq16
* /opt/intelFPGA/16.1/quartus/bin/jtagd --config /home/agmini/.jtagd.conf
* netstat -an | grep 1309 ### note listen address is "0.0.0.0", NOT "127.0.0.1"
<pre>
tcp 0 0 0.0.0.0:1309 0.0.0.0:* LISTEN
</pre>
* opt/intelFPGA/16.1/quartus/bin/jtagconfig ### should work
* ssh olchansk@daq01
* cd git/trg_firmware
* /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
* jtagconfig ### should work
<pre>
daq01:trg_firmware$ jtagconfig
1) DE-SoC on daq16 [2-1.2.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) USB-Blaster on daq16 [2-1.3]
024090DD EP4SGX230(.|ES)
020A40DD 5M(1270ZF324|2210Z)/EPM2210

daq01:trg_firmware$
</pre>

= ALPHA-g trigger functions =

Trigger options:
* software trigger
* pulser trigger
* trigger on GRIF16 ADC NIM and ESATA inputs ("external trigger")
* adc16 grand-or
* adc32 grand-or
* adc16 wire multiplicity
* TPC anode wire per-preamp trigger (aw16 section)
** trigger on coincidences of preamps (removed fw 0x62c77f0b)
** trigger on multiplicity of preamps (removed fw 0x62c77f0b)
** trigger on specific topology of preamps (multiplicity of preamp clusters, etc) via the aw16_mlu trigger
* BSC trigger
** BSC grand_or
** BSC bar multiplicity
* coincidence trigger - select coincidence of external trigger, TPC AW grand-or, TPC AW MLU, BSC grand-or and BSC bar multiplicity triggers

== software trigger ==

to programmatically fire the trigger, one should:
* set the conf_enable_sw_trigger bit in conf_trig_enable, this will permit the software trigger to fire the trigger
* write value 0x4 to register 0x2B, this will cause the software trigger to fire

== pulser trigger ==

To use the pulser trigger, one should program:
* pulser period (in clocks)
* pulser width (in clocks, use value 5, the pulser no longer goes outside of the trigger board, so changing the width does not do anything)
* set the run_pulser bit in conf_trig_enable, this will cause the pulser to run
* set the enable_pulser bit in conf_trig_enable, this will cause the pulser to fire the trigger
* set the output_pulser bit in conf_trig_enable, this will cause the pulser to be output from the alphag firmware block (the pulser no longer goes outside of the trigger board, so changing the bit does not do anything)

== timeout trigger ==

The event builder uses event timestamps to assemble physics events. The timestamps
are usually 32 bit wide and run at 125 MHz (8 ns) or 62.5 MHz (16 ns). If
triggers are generated often (1 per second or more), timestamp wrap around
is easily detected by the event builder. If triggers come infrequently,
timestamp wrap around may occur while there are no triggers, not be seen
by the event builder causing loss of event synchronization.

To avoid this problem in the event builder, a timeout trigger should be generated
if no triggers were generated inside a 10 second interval.

The guaranties that even if all physics triggers temporarily stop for any reason,
the event builder will stay synchronized. (0.1 Hz timeout trigger frequency).

To enable the timeout trigger:
* program timeout trigger timeout in reg 0x43 in units of 8 ns clock
* enable it in bit 23 of [[#conf_trig_enable bits]]

== adc16 multiplicity trigger ==

This trigger is intended for use with the barrel scintillator signals connected to adc16 digitizers. It does not work well with TPC AW signals.

The 16 adc16 trigger bits (16x16=256) are added together to form the hit multiplicity value (adc16_mult, 16 bits, actual range 0 to 256).

Four threshold signals are computed: adc16_mult_1ormore = adc16_mult>=1, 2ormore, 3ormore, 4ormore.

There is a counter for each of these four signals.

Each of these four signals can fire the trigger, see [[#conf_trig_enable bits]].

== TPC anode wire triggers ==

=== aw16 bus ===

TPC Anode Wire trigger is based on the aw16[15:0] (xaw16) bus.

Each bit corresponds to one AW preamp. 16 preamps, 16 bits.

The aw16[15:0] bus can be fed by
* adc16_or16[15:0] - or16 of 100 MHz ADCs, 16 ADC sas links
* adc32_or16[15:0] - or16 of 62.5 MHz ADCs, FMC-ADC32 has 32 channels, so 2 bits per ADC: low 16 channels and high 16 channels, sas links 7..0
* adc32_or16[31:16] - or16 of 62.5 MHz ADCs, ditto, sas links 15..8
as selected by conf_enable_aw_adc16, conf_enable_aw_adc32a, conf_enable_aw_adc32b in [[#conf_control bits]]

<pre>
///////////////////////////////////////////////////////////
// TPC Anode Wire trigger logic (aw16)
///////////////////////////////////////////////////////////

// map adc signals into aw16

wire [15:0] aw16 = ({16{conf_enable_aw_adc16}} & adc16_or16[15:0]) |
({16{conf_enable_aw_adc32a}} & adc32_or16[15:0]) |
({16{conf_enable_aw_adc32b}} & adc32_or16[31:16]);
...
ag_conditioner cond_adc16_or16_0(.clk(clk), .in(aw16[0]), .out(xxaw16[0]));
...
xaw16 <= xxaw16;
</pre>

=== aw16_grand_or ===

TPC AW "grand or" trigger: use aw16_mult_1ormore (before fw 0x62c77f0b)

(256 anode wires, 16 wires per preamp, 16 preamps, 16 aw16 signals)

=== aw16_mlu ===

TPC AW preamp MLU trigger: the MLU (memory lookup
table) implements an arbitrary logical function
to map the 16 aw16 preamp signals into 1 aw16_mlu_trig trigger output.

Description of the aw16 mlu trigger.

In words:

* any aw16 signal starts the aw16_prompt_run gate
* aw16 signals are collected for the duration of conf_mlu_prompt (125MHz/8ns clock)
* this corresponds to time spread of TPC AW signals due to the drift time in the AW drift cell and to the variation in signal transmission time from the ADC to the TRG (digital trigger data link).
* when this prompt time expires, the MLU looks at the accumulated aw16_prompt bit pattern and makes the "yes/no" trigger decision
* after the trigger decision is made, we wait for the TPC to become quiet:
* we wait until all aw16 signals are empty (no timeout)
* we run the aw16_prompt_wait gate, length conf_mlu_wait (8ns clock), if any aw16 signals arrive, we wait for aw16 empty again, rinse, repeat.
* now, after TPC aw16 have been empty for conf_mlu_wait clocks (8ns clock), MLU trigger is ready for the next event.

In logic: (see alphag.v)

* aw16_or <= grand-or of 16 aw16 signals
* "aw16_or" starts the "aw16_prompt_cnt" counter, opens the aw16_prompt_run gate
* during the aw16_prompt_run gate, aw16_prompt collects (latches) the aw16 bits (aw16_prompt <= aw16_prompt | aw16)
* this is the time when we wait for all "prompt" signals from the TPC to arrive into the trigger
* at the end of the aw16_prompt_run gate, the signal aw16_prompt_out is pulsed, latching the output of the MLU into aw16_mlu_trig
* this is the MLU trigger "yes/no" trigger decision.
* after the MLU trigger decision is made, we wait for the arrival and passing of all TPC drift signals
* the aw16_prompt_wait_cnt and aw_prompt_wait gate opens
* if any new aw16 signals arrive (they are TPC drift signals at this time), the aw16_prompt_wait gate is restarted
* if no aw16 signals arrive during the full run of the aw16_prompt_wait gate ("TPC quiet time")
* the aw16_prompt_wait and aw16_prompt gates are cleared and the MLU trigger is ready for the next event.

Good settings are:
* conf_mlu_prompt: 64 (512 ns)
* conf_mlu_wait: 128 (1024 ns)

== BSC trigger ==

=== bsc_adc16 bus ===

The BSC trigger is based on the [15:0]bsc_adc16[7:0] bus: 16 trigger discriminator bits from 8 ADC sas links. (8*16 = 64+64 bars, top and bottom).

The bsc_adc16 bus can be fed from sas links 0..7 or 8..15, controlled by conf_bsc_adc16_a and conf_bsc_adc16_b bits on [[#conf_bsc_control bits]].

bsc_adc16 can be fed only from GRIF-16 100 MHz ADC trigger discriminators.

=== bsc64_top and bsc64_bot buses ===

* firmware 0x5bc8f90f: bsc_adc16 is remapped into 64 bits of top (bsc64_top) and bottom (bsc64_bot):
<pre>
ag_bsc_remap bsc_remap_a(.adc(bsc_adc16[0]), .bsc_bot(bsc64_bot[7:0]), .bsc_top(bsc64_top[7:0]));
ag_bsc_remap bsc_remap_b(.adc(bsc_adc16[1]), .bsc_bot(bsc64_bot[8+7:8+0]), .bsc_top(bsc64_top[8+7:8+0]));
ag_bsc_remap bsc_remap_c(.adc(bsc_adc16[2]), .bsc_bot(bsc64_bot[2*8+7:2*8+0]), .bsc_top(bsc64_top[2*8+7:2*8+0]));
ag_bsc_remap bsc_remap_d(.adc(bsc_adc16[3]), .bsc_bot(bsc64_bot[3*8+7:3*8+0]), .bsc_top(bsc64_top[3*8+7:3*8+0]));

ag_bsc_remap bsc_remap_e(.adc(bsc_adc16[4]), .bsc_bot(bsc64_bot[4*8+7:4*8+0]), .bsc_top(bsc64_top[4*8+7:4*8+0]));
ag_bsc_remap bsc_remap_f(.adc(bsc_adc16[5]), .bsc_bot(bsc64_bot[5*8+7:5*8+0]), .bsc_top(bsc64_top[5*8+7:5*8+0]));
ag_bsc_remap bsc_remap_g(.adc(bsc_adc16[6]), .bsc_bot(bsc64_bot[6*8+7:6*8+0]), .bsc_top(bsc64_top[6*8+7:6*8+0]));
ag_bsc_remap bsc_remap_h(.adc(bsc_adc16[7]), .bsc_bot(bsc64_bot[7*8+7:7*8+0]), .bsc_top(bsc64_top[7*8+7:7*8+0]));

module ag_bsc_remap
(
input wire [15:0] adc,
output wire [7:0] bsc_bot,
output wire [7:0] bsc_top
);

assign bsc_top[3] = adc[0];
assign bsc_top[2] = adc[1];
assign bsc_top[1] = adc[2];
assign bsc_top[0] = adc[3];

assign bsc_top[7] = adc[4];
assign bsc_top[6] = adc[5];
assign bsc_top[5] = adc[6];
assign bsc_top[4] = adc[7];

assign bsc_bot[0] = adc[8];
assign bsc_bot[1] = adc[9];
assign bsc_bot[2] = adc[10];
assign bsc_bot[3] = adc[11];

assign bsc_bot[4] = adc[12];
assign bsc_bot[5] = adc[13];
assign bsc_bot[6] = adc[14];
assign bsc_bot[7] = adc[15];

endmodule
</pre>

=== bsc64 bus ===

the bsc64 bus is the 64 bars used by the trigger, formed from bsc64_top and bsc64_bot:
<pre>
if (conf_bsc64_bot_only) begin
bsc64 <= bsc64_bot;
end else if (conf_bsc64_top_only) begin
bsc64 <= bsc64_top;
end else if (conf_bsc64_bot_top_or) begin
bsc64 <= bsc64_bot | bsc64_top;
end else if (conf_bsc64_bot_top_and) begin
bsc64 <= bsc64_bot & bsc64_top;
end else begin
bsc64 <= 64'b0;
end
</pre>

=== bsc_grand_or_trig ===

bsc_grand_or_trig is the grand-or of 64 bits of the bsc64 bus

to enable triggering on bsc_grand_or_trig, set corresponding bit in [[#conf_trig_enable bits]]

=== old bsc_mult_trig ===

(from fw 0x62c77f0b, old bsc_mult_trig was replaced by new bsc64 multiplicity trigger)

* bsc64_mult is computed as multiplicity of the bsc64 bus (number of 64 bsc64 bits that fired)
* bsc_mult_trig is computed:
<pre>
if (bsc64_mult >= conf_bsc64_mult) begin
bsc_mult_trig <= 1;
end else begin
bsc_mult_trig <= 0;
end
</pre>

to enable the bsc multiplicity trigger, set the multiplicity value conf_bsc64_mult in [[#conf_bsc_control bits]] and enable the corresponding bit in [[#conf_trig_enable bits]].

=== bsc64 multiplicity trigger ===

bsc64 BSC bar multiplicity trigger uses a time window. this time window is started by bsc64_grand_or and runs for conf_bsc64_mult_window clocks (8 nc clock). During this time, hits in bsc64_bus are accumulated (latched) and their multiplicity is computed. If multiplicity condition is satisfied (bigger or equal to conf_bsc64_mult_min), bsc64_mult_trig is fired and the bsc64 bit pattern is saved to the UDP packet. Then trigger waits for the bsc64_bus to be empty. Then trigger waits for conf_bsc64_empty_window clocks, if there is any bsc64 hits, we wait for empty again. So after bsc64 has been empty for conf_bsc64_empty_window clocks, multiplicity trigger is ready for the next event. This scheme cannot implement max multiplicity.

recommended values:
* conf_bsc64_mult_window (8 bits): slightly longer than 3 cycles of SAS link: 3*18 = 54 clocks, good value is 80 (640 ns).
* conf_bsc64_mult_min (8 bits): 2
* conf_bsc64_empty_window (8 bits): 80 (640 ns)

== Coincidence trigger ==

Coincidence trigger provides a combination of TPC, BSC and external scintillator (esata_nim_grand_or) signals:

<pre>
assign coinc_input[0] = aw16_grand_or; // was aw16_mult_1ormore;
assign coinc_input[1] = aw16_mlu_trig;
assign coinc_input[2] = bsc_grand_or_trig;
assign coinc_input[3] = bsc_mult_trig;
assign coinc_input[4] = esata_nim_grand_or;
assign coinc_input[5] = 0;
assign coinc_input[6] = 0;
assign coinc_input[7] = 0;
</pre>

Coincidence trigger "start" mask selects which of the inputs can start the coincidence window.

Coincidence trigger "require" mask selects which inputs must have a hits for the coincidence ot be satisfied.

Input hits are collected for the duration of the coincidence window, if all required inputs have hits, coinc_trig is fired.

Example settings:

* coincidence of external scintillator, BSC and TPC AW "grand or" signals: start 0x10, required 0x15
* coincidence of BSC and TPC AW "grand or" signals: start 0x4, required 0x5
* coincidence of BSC and TPC AW MLU triggers: start 0x4, required 0x6
* coincidence of BSC multiplicity and TPC AW MLU triggers: start 0x8, required 0xA

= Control registers =

== Register addresses ==

Note: all registers are 32 bits unless otherwise noted.

Note: RW means read-write register, RO means read-only, ROL means read-only, contents is latched by the "latch_out" bit

{| cellpadding="10" cellspacing="0" border="1"
! Address || Quartus Name || Access || FwRev || Description
|-
| 0x08 || num_sample || RW || GRIF-C || magic 16-bit register to control UDP packet size
|-
| 0x08 || scratch_reg || RW || 0x618b790b || 32-bit scratch register
|-
| 0x1F || compilation_time || RO || || Firmware revision
|-
| 0x20 || conf_trig_width || RW || || Trigger signal width, 16 ns clock
|-
| 0x21 || conf_busy_width || RW || || Busy signal width, 16 ns clock (not used)
|-
| 0x22 || conf_pulser_width || RW || || Pulser signal width, 16 ns clock
|-
| 0x23 || conf_pulser_period || RW || || Pulser signal period, 16 ns clock
|-
| 0x24 || conf_pulser_burst_ctrl || RW || 0x62d1c47e || Generate bursts of pulses: 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses, 16 ns clocks
|-
| 0x25 || conf_trig_enable || RW || || see [[#conf_trig_enable bits]]
|-
| 0x26 || || || not used
|-
| 0x27 || || || not used
|-
| 0x28 || || || not used
|-
| 0x29 || conf_nim_mask || RW || || enable bits for ADC NIM inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2A || conf_esata_mask || RW || || enable bits for ADC eSATA inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2B || reset_out, latch_out, trigger_out || W || || see [[#reg 0x2B bits]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x5bc8f90f || configure AW coincidence trigger, see [[#aw16_coinc]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x62c77f0b || removed
|-
| 0x2D || conf_aw16_coinc_b || RW || 0x5bc8f90f ||
|-
| 0x2E || conf_aw16_coinc_c || RW || 0x5bc8f90f ||
|-
| 0x2F || conf_aw16_coinc_d || RW || 0x5bc8f90f ||
|-
| 0x30 || sas_sd[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect for each link
|-
| 0x31 || pll_625_status || ROL || 0x5b2057f5 (12Jun18_16:32) || 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter
|-
| 0x32 || clk_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the system 125 MHz clock
|-
| 0x33 || clk_625_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625)
|-
| 0x34 || conf_control || RW || 0x5b398983 (01Jul18_19:10) || see [[#conf_control bits]] below
|-
| 0x35 || conf_drift_width || RW || 0x5b398983 (01Jul18_19:10) || width of drift time blank-out in 16 ns clocks
|-
| 0x36 || conf_scaledown || RW || 0x5b398983 (01Jul18_19:10) || trigger scaledown, 0=no scaledown, 1=divide-by-2, 2=divide-by-3, etc
|-
| 0x37 || conf_mlu || RW || 0x5b398983 (01Jul18_19:10) || AW MLU control bits, see [[#conf_mlu bits]]
|-
| 0x38 || conf_trig_delay || RW || 0x5baedfca (28Sep18_19:13) || delay the trigger pulse, 16 ns clock
|-
| 0x39 || esata_clk_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the TRG 125 MHz clock
|-
| 0x3A || esata_clk_esata_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the external clock (eSATA 62.5 MHz clock)
|-
| 0x3B || conf_counter_adc_select || RW || 0x5bb7f6ae (05Oct18_16:41) || select which 16 ADCs are connected to the selected adc counters, 0..15 - connect the adc16 signals, 16..47 connect the adc32 signals
|-
| 0x3C || sysreset_ts || RO || 0x5bb7f6ae (05Oct18_16:41) || 125MHz counter of VME-SYSRESET
|-
| 0x3C || || || 0x618b790b || not used
|-
| 0x3D || GRIF-C csr || RW || GRIF-C || <= csr & ~par_value; // Selective clear
|-
| 0x3E || GRIF-C csr || RW || GRIF-C || <= csr | par_value; // Selective set
|-
| 0x3F || GRIF-C csr || RW || GRIF-C || <= par_value; // write
|-
| 0x3D || || || 0x618b790b || not used
|-
| 0x3E || || || 0x618b790b || not used
|-
| 0x3F || || || 0x618b790b || not used
|-
| 0x40 || conf_bsc_control || RW || 0x5bc13541 (12Oct18_16:58) || Barrel Scintillator trigger control, see [[#conf_bsc_control bits]]
|-
| 0x41 || conf_coinc_control || RW || 0x5bc13541 (12Oct18_16:58) || Coincidence trigger control, see [[#conf_coinc_control bits]]
|-
| 0x42 || reconfig_out || WO || 0x5bc13541 (12Oct18_16:58) || reserved for rebooting the FPGA (does not work)
|-
| 0x43 || conf_trigger_timeout || RW || 0x5bc8f90f (18Oct18_14:20) || Generate timeout trigger if there is no other trigger after given timeout, in 8 ns clocks, must be enabled by bit conf_enable_timeout_trig in [[#conf_trig_enable bits]]
|-
| 0x44 || eth_clk_counter || ROL || 0x618b790b ||
|-
| 0x45 || eth_clk_eth_counter || ROL || 0x618b790b ||
|-
| 0x100 || ts_625 || ROL || || latched timestamp
|-
| 0x101 || counter_trig_out || ROL || || counter of issued triggers
|-
| 0x102 || counter_trig_in || ROL || || counter of triggers
|-
| 0x103 || counter_pulser || ROL || || counter of pulser
|-
| 0x104 || counter_adc16_grand_or || ROL ||
|-
| 0x105 || counter_adc32_grand_or || ROL ||
|-
| 0x106 || counter_adc_grand_or || ROL ||
|-
| 0x107 || counter_esata_nim_grand_or || ROL ||
|-
| 0x108 || counter_adc16_mult_1ormore || ROL ||
|-
| 0x109 || counter_adc16_mult_2ormore || ROL ||
|-
| 0x10A || counter_adc16_mult_3ormore || ROL ||
|-
| 0x10B || counter_adc16_mult_4ormore || ROL ||
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x5bc8f90f || counter of AW coincidence triggers
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x62c77f0b || removed
|-
| 0x10D || counter_aw16_coinc_b || ROL || 0x5bc8f90f ||
|-
| 0x10E || counter_aw16_coinc_c || ROL || 0x5bc8f90f ||
|-
| 0x10F || counter_aw16_coinc_d || ROL || 0x5bc8f90f ||
|-
| 0x110 || counter_drift || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the drift time blank-out
|-
| 0x111 || counter_scaledown || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the scaledown
|-
| 0x112 || counter_aw16_coinc || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW coincidence triggers
|-
| 0x113 || counter_aw16_mlu || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW MLU triggers
|-
| 0x114 || counter_aw16_grand_or || ROL || 0x62c77f0b || counter of AW grand-or triggers
|-
| 0x114 || counter_aw16_mult_1ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 1ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 2ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x62c77f0b || removed
|-
| 0x116 || counter_aw16_mult_3ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 3ormore triggers
|-
| 0x117 || counter_aw16_mult_4ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 4ormore triggers
|-
| 0x118 || counter_bsc_grand_or || ROL || 0x5bc13541 (12Oct18_16:58) || counter of BSC grand-or triggers
|-
| 0x119 || counter_bsc_mult || ROL || 0x5bc13541 (12Oct18_16:58) || counter of old BSC multiplicity triggers
|-
| 0x11A || counter_coinc || ROL || 0x5bc13541 (12Oct18_16:58) || counter of coincidence triggers
|-
| 0x11B || counter_timeout || ROL || 0x618b790b || counter of timeout triggers
|-
| 0x11C || counter_bsc_mult_start || ROL || 0x62c77f0b || counter of BSC multiplicity windows
|-
| 0x11D || counter_bsc_mult_trig || ROL || 0x62c77f0b || counter of BSC multiplicity triggers
|-
| 0x11E || counter_coinc_start || ROL || 0x62d1b152 || counter of coincidence windows
|-
| 0x11F || counter_aw16_mlu_start || ROL || 0x62d1b152 || counter of TPC AW MLU windows
|-
| 0x200..0x207 || conf_adc16_masks || RW || all || adc16 enable bits
|-
| 0x300..0x30F || conf_adc32_masks || RW || all || adc32 enable bits
|-
| 0x400..0x41F || sas_bits[15:0][63:0] || ROL || all || sas data bits for each link
|-
| 0x420..0x42F || sas_sd_counters[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect counter for each link
|-
| 0x430..0x43F || counters_adc16_or16[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 16 counters of adc16 ORes
|-
| 0x440..0x45F || counters_adc32_or16[31:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 32 counters of adc32 ORes
|-
| 0x460..0x46F || counters_adc_selected[15:0] || ROL || 0x5bb7f6ae (05Oct18_16:41) || 16 counters for selected group of adcs, see conf_counter_adc_select
|-
| 0x470..0x4AF || counters_bsc64[63:0] || ROL || 0x5bc13541 (12Oct18_16:58) || 64 counters for the BSC bars
|-
|}

== additional registers ==

<pre>
reg | rw/ro | quartus name | firmware | description
0x60: param_out <= {2'h3, par_id, chan, cb_control_out
0x61: param_out <= {2'h3, par_id, chan, cb_status
0x62: param_out <= {2'h3, par_id, chan, cb_invert_a_out };
0x63: param_out <= {2'h3, par_id, chan, cb_invert_b_out };
0x64: param_out <= {2'h3, par_id, chan, cb_enable_le_a_out };
0x65: param_out <= {2'h3, par_id, chan, cb_enable_le_b_out };
0x66: param_out <= {2'h3, par_id, chan, cb_enable_te_a_out };
0x67: param_out <= {2'h3, par_id, chan, cb_enable_te_b_out };
0x6A | ro | cb_input_num | 0x618b790b | chronobox number of inputs
0x6B: param_out <= {2'h3, par_id, chan, cb_sync_mask_a_out };
0x6C: param_out <= {2'h3, par_id, chan, cb_sync_mask_b_out };
0x6D: param_out <= {2'h3, par_id, chan, cb_sync_reg_out };
0x6E: param_out <= {2'h3, par_id, chan, cb_sync_status };
0x6F: param_out <= {2'h3, par_id, chan, cb_latch_period_out };
0x70: param_out <= {2'h3, par_id, chan, cb_fifo_status };
0x71: begin param_out <= {2'h3, par_id, chan, cb_fifo_data }; cb_fifo_rdack_out <= 1; end
0x72: param_out <= {2'h3, par_id, chan, cb_udp_period_out };
0x73: param_out <= {2'h3, par_id, chan, cb_udp_threshold_out };
</pre>

== conf_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_clock_select || 0x5b3aa19f (02Jul18_15:05) || select 0=internal 62.5 MHz clock or 1=esata 62.5 MHz clock
|-
| 1 || conf_enable_aw_adc16 || 0x5baedfca (28Sep18_19:13) || select source of TPC AW aw16 bus, see [[#aw16 bus]]
|-
| 2 || conf_enable_aw_adc32a || 0x5baedfca (28Sep18_19:13) ||
|-
| 3 || conf_enable_aw_adc32b || 0x5baedfca (28Sep18_19:13) ||
|-
| 15..4 || || ||
|-
| 23..16 || conf_mlu_prompt || 0x5b3aa19f (02Jul18_15:05) || MLU trigger prompt window, see [[#aw16_mlu]]
|-
| 31..24 || conf_mlu_wait || 0x5b3aa19f (02Jul18_15:05) || MLU trigger wait window, see [[#aw16_mlu]]
|-
|}

== conf_mlu bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 31 || mlu_reset || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 30 || mlu_write || 0x5b3aa19f (02Jul18_15:05) || 1=write data bit into given address
|-
| 16 || mlu_data || 0x5b3aa19f (02Jul18_15:05) || data bit for writing to MLU RAM
|-
| 15..0 || mlu_write_addr || 0x5b3aa19f (02Jul18_15:05) || MLU RAM write address for writing the data bit
|-
|}

== conf_bsc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_bsc_adc_a || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 0..7
|-
| 1 || conf_bsc_adc_b || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 8..15
|-
| 2 || conf_bsc64_bot_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses bottom channels only
|-
| 3 || conf_bsc64_top_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses top channels only
|-
| 4 || conf_bsc64_bot_top_or || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "or" of top and bottom
|-
| 5 || conf_bsc64_bot_top_and || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "and" of top and bottom
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_bsc64_mult_min || 0x5bc13541 (12Oct18_16:58) || minimum bsc64 multiplicity
|-
| 23..16 || conf_bsc64_mult_max || 0x62c77f0b || maximum bsc64 multiplicity
|-
| 31..24 || conf_bsc64_mult_window || 0x62c77f0b || bsc64 multiplicity window length, 8 ns clocks
|-
|}

== conf_coinc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_coinc_required[0] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mult_1ormore
|-
| 0 || conf_coinc_required[0] || 0x62c77f0b || enable aw16_grand_or
|-
| 1 || conf_coinc_required[1] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mlu_trig
|-
| 2 || conf_coinc_required[2] || 0x5bc13541 (12Oct18_16:58) || enable bsc_grand_or_trig
|-
| 3 || conf_coinc_required[3] || 0x5bc13541 (12Oct18_16:58) || enable bsc_mult_trig
|-
| 3 || conf_coinc_required[3] || 0x62c77f0b || enable bsc64_mult_trig
|-
| 4 || conf_coinc_required[4] || 0x5bc13541 (12Oct18_16:58) || enable esata_nim_grand_or
|-
| 5 ||
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_coinc_window[7:0] || 0x5bc13541 (12Oct18_16:58) || coincidence window length in units of 125MHz clock (8 ns)
|-
| 23..16 || conf_coinc_start[7:0] || 0x5bc13541 (12Oct18_16:58) || start the coincidence window, same bits as "required"
|-
| 31..24 ||
|-
|}

== conf_trig_enable bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_enable_sw_trigger || || trigger on software trigger (how generated???)
|-
| 1 || conf_enable_pulser || || trigger on pulser
|-
| 2 || - || 0x5b120c9f (01Jun18_20:18) || not used
|-
| 3 || conf_pulser_run || || allow the pulser to run (frequency has to be set beforehand)
|-
| 4 || conf_output_pulser || 0x5bc8f90f || does nothing (top level ag_pulser_out is disconnected)
|-
| 4 || || 0x618b790b || not used
|-
| 5 || conf_enable_esata_nim || || trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand)
|-
| 6 || conf_enable_adc16 || || trigger on adc16_grand_or
|-
| 7 || conf_enable_adc32 || || trigger on adc32_grand_or
|-
| 8 || conf_enable_adc16_1ormore || || trigger on adc16_mult_1ormore "1 or more"
|-
| 9 || conf_enable_adc16_2ormore || || same, "2 or more"
|-
| 10 || conf_enable_adc16_3ormore || || same, "3 or more"
|-
| 11 || conf_enable_adc16_4ormore || || same, "4 or more"
|-
| 12 || - || 0x5b08938c (25May18_15:51) || not used
|-
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
|-
| 14 || - || 0x5bc8f90f || not used
|-
| 15 || conf_enable_adc || 0x5b120c9f (01Jun18_20:18) || trigger on adc_grand_or
|-
| 16 || conf_enable_aw16_coinc_a || 0x5bc8f90f || enable AW coincidence trigger, see [[#aw16_coinc]]
|-
| 16 || - || 0x62c77f0b || aw16_coinc_x removed
|-
| 17 || conf_enable_aw16_coinc_b || 0x5bc8f90f ||
|-
| 18 || conf_enable_aw16_coinc_c || 0x5bc8f90f ||
|-
| 19 || conf_enable_aw16_coinc_d || 0x5bc8f90f ||
|-
| 20 || - || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 20 || conf_enable_aw16_grand_or || 0x618b790b || enable trigger on aw16_grand_or
|-
| 21 || conf_enable_aw16_coinc || 0x5b3aa19f (02Jul18_15:05) || enable trigger on aw16_coinc_trig
|-
| 22 || conf_enable_aw16_mlu || 0x5b3aa19f (02Jul18_15:05) || enable AW MLU trigger
|-
| 23 || conf_enable_timeout_trig || 0x5bc8f90f (18Oct18_14:20) || enable trigger timeout trigger
|-
| 24 || conf_enable_aw16_1ormore || 0x5b3aa19f (02Jul18_15:05) || trigger on aw16_mult_1ormore "1 or more"
|-
| 24 || - || 0x62c77f0b || aw16_mult_xxx removed
|-
| 25 || conf_enable_aw16_2ormore || 0x5b3aa19f (02Jul18_15:05) || same, "2 or more"
|-
| 26 || conf_enable_aw16_3ormore || 0x5b3aa19f (02Jul18_15:05) || same, "3 or more"
|-
| 27 || conf_enable_aw16_4ormore || 0x5b3aa19f (02Jul18_15:05) || same, "4 or more"
|-
| 28 || conf_enable_bsc_grand_or || 0x5bc13541 (12Oct18_16:58) || trigger on BSC grand-or
|-
| 29 || conf_enable_bsc_mult || 0x5bc13541 (12Oct18_16:58) || trigger on BSC multiplicity
|-
| 30 || conf_enable_coinc || 0x5bc13541 (12Oct18_16:58) || trigger on TPC/BSC/ext coincidence trigger
|-
| 31 || - || || not used
|-
|}

== reg 0x2B bits ==

Write to this register will pulse corresponding fpga signals:

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || reset_out || 0x5b120c9f (01Jun18_20:18) || reset counters, etc
|-
| 1 || latch_out || 0x5b120c9f (01Jun18_20:18) || latch counters, sas bits, etc
|-
| 2 || trigger_out || 0x5b120c9f (01Jun18_20:18) || generate a software trigger
|-
|}

= UDP data format =

== firmware 0x5bc8f90f ==

{| cellpadding="10" cellspacing="0" border="1"
! Offset || Name || Quartus name || FwRev || Description
|-
| 0 || packet counter || none || all || 31-bit UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
|-
| 1 || 0x8 packet header || || all || 28 bits of counter_trig_out
|-
| 2 || trigger timestamp || trig_ts || all || 62.5MHz trigger timestamp
|-
| 3 || accepted triggers || counter_trig_out || all || counter of accepted triggers
|-
| 4 || input triggers || counter_trig_in || all || counter of trigger input
|-
| 5 || pulser triggers || counter_pulser || all || counter of pulser triggers
|-
| 6 || trigger bitmap || udp_trig_bits || 0x5a48448d (30Dec17_17:59) || bitmap of trigger information, see below
|-
| 7 || nim bits || udp_nim_bits_masked || ??? || 32 bits of ADC NIM inputs (2 bits per ADC)
|-
| 8 || esata bits || udp_esata_bits_masked || ??? || 32 bits of ADC ESATA inputs (2 bits per ADC)
|-
| 9 || mlu bits || aw16_prompt || 0x5b398983 (01Jul18_19:10) || 16 bits of MLU input, 1 bit per preamp
|-
| 10 || drift-blank-off counter || udp_drift_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the drift blank-off
|-
| 11 || scaledown counter || udp_scaledown_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the scaledown
|-
| X || || || ||
|-
| 12 || 0xE packet footer || || all || 28 bits of counter_trig_out
|-
|}

== firmware 0x618b790b (Nov 2021) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

== trigger bitmap ==

Firmware ??? (one of the very early revisions)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= adc16_coinc_top;
udp_trig_bits[5] <= adc16_coinc_bot;
udp_trig_bits[6] <= adc16_coinc;
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
udp_trig_bits[31:24] <= mult16[7:0];

</pre>

Firmware 0x5b08938c (25May18_15:51)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= 0; // not used
udp_trig_bits[31:24] <= mult16[7:0];
</pre>

Firmware 0x5b217dc4 (13Jun18_13:25)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5b3aa19f (02Jul18_15:05)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= udp_mlu_out;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5bc8f90f (18Oct18_14:20)

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_run_pulser
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = 0; // not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x618b790b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x62c77f0b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = 0; // aw16_coinc_a;
assign trig32_in[17] = 0; // aw16_coinc_b;
assign trig32_in[18] = 0; // aw16_coinc_c;
assign trig32_in[19] = 0; // aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = 0; // aw16_mult_1ormore;
assign trig32_in[25] = 0; // aw16_mult_2ormore;
assign trig32_in[26] = 0; // aw16_mult_3ormore;
assign trig32_in[27] = 0; // aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc64_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

= TRG chronobox inputs =

from trg_firmware/toplevel/grifc.v

<pre>
localparam CB_N = 23;
localparam CB_N1 = CB_N-1;

wire [CB_N1:0] cb_xinputs_async;

assign cb_xinputs_async[0] = ag_trig_out;
assign cb_xinputs_async[1] = ag_trig_scaledown_out;
assign cb_xinputs_async[2] = ag_trig_drift_out;
assign cb_xinputs_async[3] = ag_trig_received_out;

assign cb_xinputs_async[4] = ag_cb_sw_trig;
assign cb_xinputs_async[5] = ag_cb_pulser_trig;
assign cb_xinputs_async[6] = ag_cb_esata_nim_trig;
assign cb_xinputs_async[7] = ag_cb_adc16_grand_or_trig;
assign cb_xinputs_async[8] = ag_cb_adc32_grand_or_trig;

assign cb_xinputs_async[9] = ag_cb_aw16_grand_or_trig;
assign cb_xinputs_async[10] = ag_cb_aw16_mult_1ormore;
assign cb_xinputs_async[11] = ag_cb_aw16_mult_2ormore;
assign cb_xinputs_async[12] = ag_cb_aw16_mult_3ormore;
assign cb_xinputs_async[13] = ag_cb_aw16_mult_4ormore;
assign cb_xinputs_async[14] = ag_cb_aw16_mlu_trig;

assign cb_xinputs_async[15] = ag_cb_bsc64_grand_or_trig;
assign cb_xinputs_async[16] = ag_cb_bsc64_mult_1ormore;
assign cb_xinputs_async[17] = ag_cb_bsc64_mult_2ormore;
assign cb_xinputs_async[18] = ag_cb_bsc64_mult_3ormore;
assign cb_xinputs_async[19] = ag_cb_bsc64_mult_4ormore;
assign cb_xinputs_async[20] = ag_cb_bsc64_mult_trig;

assign cb_xinputs_async[21] = ag_cb_coinc_trig;

assign cb_xinputs_async[22] = ag_cb_timeout_trig;
</pre>

= Example UDP packets =

* trigger data, marker words 0x8

<pre>
ReadDataThread read 76
0: 0x003666ed -- UDP packet counter from UDP transmitter
1: 0x80000bf8 -- 0x8 is trigger data packet, 0xbf8 is the trigger counter from alphag.v
2: 0x2edf8b41 -- trigger data
3: 0x00000bf8
4: 0x00000bf8
5: 0x00000bee
6: 0x00000001
7: 0x00000000
8: 0x00000000
9: 0x00000003
10: 0x00000bf8
11: 0x00000bf8
12: 0x00000000
13: 0x00000000
14: 0x00000000
15: 0x00000000
16: 0x00000000
17: 0x00000000
18: 0xe0000bf8 -- 0xE is end of trigger data, counter 0xbf8 must match the counter in the 0x8 word.
ReadDataThread read 76 -- next packet
0: 0x003666ee -- UDP packet counter from UDP transmitter
...
</pre>

* chronobox fifo data, marker word 0xC, see [[Chronobox#FIFO_data_format]]

<pre>
ReadDataThread read 404
0: 0x003658ed -- UDP packet counter from UDP transmitter
1: 0xc000eacc -- 0xC is FIFO data, fifo packet counter 0xeacc from fifo_to_udp.v
2: 0x00000061 -- FIFO status, low bits the the word counter, so up to 0x61 fifo words are to follow
3: 0x87fb3d72 -- tsc hits
4: 0x8ffb3d74
5: 0x90fb3d74
6: 0x91fb3d74
7: 0x92fb3d74
8: 0x93fb3d74
9: 0x93fb3d75
10: 0x94fb3d74
11: 0x94fb3d77
12: 0x87fb3d77
13: 0x8ffb3d77
14: 0x90fb3d77
15: 0x91fb3d77
16: 0x92fb3d77
17: 0xfe000018 -- 0xFE scaler data starts, 0x18 words to follow
18: 0x00000000
19: 0x00000000
20: 0x00000000
21: 0x00000000
22: 0x00000000
23: 0x00000000
24: 0x00000000
25: 0x00000108
26: 0x00000000
27: 0x00000000
28: 0x00000000
29: 0x00000000
30: 0x00000000
31: 0x00000000
32: 0x00000000
33: 0x00000108
34: 0x00000108
35: 0x00000108
36: 0x00000108
37: 0x00000108
38: 0x00000108
39: 0x00000000
40: 0x00000000
41: 0xce56fa93 -- last word of scaler data is the sysclock counter (125 MHz)
42: 0xff800048 -- timestamp wraparound
43: 0x8f1f36e4 -- tsc hits
44: 0x901f36e4
45: 0x911f36e4
46: 0x921f36e4
47: 0x931f36e4
48: 0x941f36e4
49: 0x871f36e4
50: 0x871f36e7
51: 0x8f1f36e7
52: 0x901f36e9
53: 0x911f36e7
54: 0x921f36e9
55: 0x931f36e7
56: 0x941f36e9
57: 0x904330ac
58: 0x914330ac
59: 0x924330ac
60: 0x934330ac
61: 0x934330ad
62: 0x944330ac
63: 0x944330ad
64: 0x874330ac
65: 0x874330ad
66: 0x8f4330ac
67: 0x8f4330ad
68: 0x904330ad
69: 0x914330ad
70: 0x924330ad
71: 0x8f672a62
72: 0x90672a62
73: 0x91672a62
74: 0x92672a62
75: 0x93672a62
76: 0x94672a62
77: 0x87672a62
78: 0x87672a65
79: 0x8f672a65
80: 0x90672a65
81: 0x91672a65
82: 0x92672a65
83: 0x93672a65
84: 0x94672a65
85: 0xff000049
86: 0x878b2422
87: 0x8f8b2424
88: 0x908b2424
89: 0x918b2424
90: 0x928b2424
91: 0x938b2424
92: 0x938b2425
93: 0x948b2424
94: 0x948b2427
95: 0x878b2427
96: 0x8f8b2427
97: 0x908b2427
98: 0x918b2427
99: 0x928b2427
100: 0xe000eacc -- 0xE is end of fifo data, counter 0xeacc must match the counter in the 0xC word.
ReadDataThread read 344 -- next packet
...
</pre>

= TODO =

* DONE July 2022. add FwRev to the UDP data output
* RJ45 SFP: PROBLEM, D.A. CABLE: GOOD, Fiber SFP: ???. fix "write did not happen" (send udp write command, there is no reply, read returns old data as if write never happened). suspect udp "write" packet is lost?
* PROBLEM GONE Aug 2021. fix reply to wrong socket - udp packets should reply to same socket as they came from, udp data packets should be sent to same socket as requested them, not same socket as last command.
* DONE 2021jul30. add fixes from Chris P. for the auto-negotiation and dhcp (see email from him).
* DONE flash chip connected to FPGA. Aug 2021. implement ethernet flash programmer
* DONE Aug 2021. updated maxv firmware. implement FPGA reboot
* speed up programming the MLU by writing more than 1 bit at a time
* DONE Nov 2021. add 64-bit bitmap of BSC trigger bits
* DONE. add chronobox code
* DONE. add avalon mux for alphag and chronobox packets
* DONE. add chronobox fifo to udp packet sequencer
* check that TxReadyOut is correct and it is safe to send an avalon packet while previous packet is still transmitting.
* DONE. test fiber SFP is working
* complete the UDP flash programmer (parallel flash erase and write)

= End =

//KO

Daq

2022-07-15T19:57:03Z

Olchansk: /* /Equipment/CTRL/Settings/Pulser */

= Links =

* https://alphacpc05.cern.ch/agdaq/ -- midas daq page for the agdaq system at CERN
* https://daq16.triumf.ca -- midas daq page for the agmini system at TRIUMF
* https://daq.triumf.ca/elog-alphag/alphag/ -- elog
* https://daqstore.triumf.ca/AgWiki/index.php/Main_Page -- this wiki
* https://bitbucket.org/ttriumfdaq/agdaq - git repository for agdaq
* https://bitbucket.org/expalpha -- git repository on bitbucket
* https://edev-group.triumf.ca/fw/exp/alphag -- git repository on edev gitlab

= Inventory database =

* https://ladd00.triumf.ca/daqinv/frontend/list/170 - PWB inventory database
* https://ladd00.triumf.ca/daqinv/frontend/list/168 - ADC (GRIF-16) inventory, FMC-ADC32rev0,rev1 inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/176 - FMC-ADC32rev1.1 inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/174 - BSC RTM inventory
* https://ladd00.triumf.ca/daqinv/frontend/list/173 - BSC ASD inventory

= Hardware manuals =

* [[TRG]] - trigger board (GRIF-C) manual
* CDM - https://daq.triumf.ca/DaqWiki/index.php/VME-CDM -- clock VME-CDM manual
* ADC - https://daq.triumf.ca/DaqWiki/index.php/VME-GRIF-ADC16-Rev1 -- GRIF-16 ADC manual
* [[PWB]] - TPC Pad Wing Board manual
* TDC - https://daq.triumf.ca/DaqWiki/index.php/GSI_TRB3
* [[chronobox]] - chronobox manual
* [[ASD]] - BSC preamp board
* [[RTM]] - BSC VME rear transition board

= Performance =

Full system: (ADC fw rel-20201112-ko, PWB fw 20201005_ko)
* 1 Hz stable, ADC adc32 9 supp off rate 0.3 M/s, adc16 off, PWB udp_delay 25 supp off active 64 rate 6.6+4+6+4.6=21.2 M/s, TDC off, total rate 21 M/s
* 500 Hz stable, ADC adc32 9 supp 1500 rate 6 M/s, adc16 off, PWB udp_delay 10 supp 100 active 63 rate 3+4+3+3=13 M/s, TDC off, total rate 19 M/s

Single ADC: (fw rel-20201112-ko)

Fully suppressed data, sthreshold 5000
* 1 Hz: stable
* 500 Hz: stable (nominal max trigger rate)
* 6700 Hz: stable, 8 Mbytes/sec
* 6800 Hz: evb eventually confused
* 6850 Hz: evb confused, no lost triggers in the ADC, no crash in the ADC

All data, 510 samples/event, sthreshold 10 (fw rel-20201122-ko)
* 1 Hz: stable
* 100 Hz: stable, 3.4 Mbytes/sec
* 500 Hz: stable, 17 Mbytes/sec (nominal max trigger rate)
* 1000 Hz: stable, 32 Mbytes/sec
* 3100 Hz: stable, 106 M/s (approaching saturation of 1gige ethernet)
* 3200 Hz: stable, 110 M/s - TRG communication is in trouble
* 3300 Hz: stable, 116 M/s
* 3400 Hz: incomplete events, no ADC crash ("dropped due to full" counting, "dropped due to busy" are zero, this is as expected).

no suppression (different fpga data path)
* 1 Hz: stable
* 100 Hz: stable
* 500 Hz: stable, 17 M/s (nominal max trigger rate)
* 1000 Hz: stable, 32 M/s
* 3000 Hz: stable, 100 M/s (approaching saturation of 1gige ethernet)
* 3300 Hz: incomplete events, no ADC crash ("dropped due to full" counting, "dropped due to busy" are zero, this is as expected).

= Network connections =

The experiment private network number is: 192.168.1.x, gateway 192.168.1.1, netmask 255.255.255.0

network map:
<pre>
---- TRIUMF/CERN network --1gige-- alphagdaq --10gige-- juniper switch --1gige-- centrecom switch
</pre>

== alphagdaq network connections ==

on the rear of the machine:
<pre>
-----------------------------------------
| | rj45 | rj45 | | sfp | sfp |
-----------------------------------------

- left rj45 - copper 1gige - eno1 - spare (inactive)
- right rj45 - copper 1gige - eno2 - dhcp - cern/triumf network
- left sfp - 10gige - enp1s0f1 - spare (inactive)
- right sfp - 10gige - enp1s0f0 - static 192.168.1.1
</pre>

== connections between switches ==

* alphagdaq to juniper switch: direct attach (DAC) 10gige cable into any port of juniper switch
* juniper switch to centrecom switch: rj45 sfp in any port of juniper switch - cat5e/cat6 cable - to any port of centrecom switch
* cat5e/cat6 cable from any port of centrecom switch to the XXX port on the back of the juniper switch

== juniper switch ==

connected to juniper switch front is:

* everything that sends event data to alphagdaq, specifically:
** TRG (rj45 sfp)
** 16x ADC (fiber sfp)
** 64x PWB (fiber sfp)
* 10gige uplink to alphagdaq (10gige DAC cable)
* 1gige link to centrecom switch (rj45 sfp)
* 40gige ports are not used

connected to the juniper switch rear:

* CON is the serial console via RJ45-to-DB9 to USB-serial adapter to alphagdaq USB port (9600bps, 8N1, no flow control)
* C0 is the management ethernet interface port, connect to any port on the centrecom switch (juniper-private will ping)

== centrecom switch ==

* everything with copper rj45 connections, specifically:
** CDM boards
** HV, LV and VME power supplies
** RaspberryPi3 boards
** gas handling MFCs (algas)
** cooling system controller (moxa01)

= USB connections =

Note:
* alphagdaq has USB2 and USB3 connections. They are not the same, they are not generally interchangeable.
* USB3 connections and cables are generally blue coloured.

List of USB connections from alphagdaq:

* front USB3 port (blue): USB-A-to-B cable to USB blaster connected to the trigger board (front of rack)
* rear USB3 port (blue): USB3 short jumper to USB3 hub
* rear USB2 port (black): USB2 unpowered hub (Logiix) to USB-A-to-B cable to UPS USB connector
* rear USB2 port (black): USB-to-Serial adaper to DB9 to RJ45 adapter to Juniper switch console port

Note: UPS USB connection does not work with alphagdaq USB ports (both usb2 and usb3), but combination
using the unpowered USB2 hub seems to work ok.

List of USB connections from the USB hub:

* this is a powered USB3 hub
* USB-A-to-MicroUSB - to lvdb boards
* USB-A-to-Wiener interlock cable

= Clock and trigger distribution =

== Explanation ==

Trigger is generated by the trigger board (aka TRG, aka GRIF-C),
from the TRG eSATA output through the eSATA splitter it is fed into
the master CDM. The master CDM outputs the trigger on all MiniSAS output ports.
One of the master CDM MiniSAS outputs is connected to the CDM slave eSATA input.
The same as the master CDM, the slave CDM outputs the trigger on all MiniSAS output ports.

The master 62.5MHz clock is generated by the master CDM using the internal 10MHz oscillator
or the external 10MHz AD clock. Also on MiniSAS port 6 the master CDM generates
the 200MHz clock for the TDC. This clock is frequency-locked to the master 62.5MHz clock.

Master CDM clock selection (external CD 10MHz clock or internal oscillator 10MHz clock)
is done by a magic esper command (see below).

From the master CDM, the clock is fed to: the slave CDM, the TRG (via the eSATA splitter)
and to the TDC (via the RJ45 splitter).

The slave CDM sends the clock and the trigger to the ADCs and PWBs.

== Chronobox connections ==

Chronoboxes are synchronized with the daq using two signals: 10 MHz timestamp clock and TTL sync.

The sync signal used is the trigger signal - timestamps are reset by the 1st event - which is not a physics event, but the first trigger in the trigger sync sequence.

All chronoboxes are configured in "slave" and "chain" mode.

Slave mode: 10 MHz timestamp clock goes into the CLK_IN input (configured as NIM on the first chronobox and TTL on all others), sync signal goes into TTL input LEMO 4. (bank B direction set to "in").

Chain mode: 10 MHz timestamp clock is TTL output LEMO 0, sync is TTL output LEMO 1. (bank A direction set to "out"). These signals feed into CLK_IN (TTL mode) and TTL input LEMO 4 in the next chronobox in the chain.

The first chronobox receives the 10 MHz timestamp clock and sync signals from the master CDM per diagrams below.

* CDM 10 MHz clock output is NIM, feeds directly into the chronobox CLK_IN (NIM mode).
* CDM "trigger" ("sync") output is NIM, has to go through a NIM-to-TTL converter before feeding chronobox TTL input LEMO 4. I use a LeCroy 222 "gate and delay generator" module. NIM input goes into the "Start" input, TTL output is taken from the "TTL" output. Signal width is adjusted to around 100-1000 ns. Any other sutable NIM-to-TTL converter can also be used.
* "sync" output must be enabled in the master CDM:
<pre>
esper-tool cdm00
cd cdm
write multi_sync 2
</pre>

== Schematic ==

<pre>
TRG (GRIF-C)
------------
eSATA <------> eSATA splitter

eSATA splitter
--------------
trigger ---> eSATA ---> CDM-Master eSATA (trigger signal)
clock <--- (eSATA --- MiniSAS) <--- CDM MiniSAS (62.5MHz clock)
</pre>

<pre>
CDM-Master
----------
LEMO1B <----- 10 MHz AD clock (NIM)
LEMO2A --> (only if there is no external clock) 4ns lemo cable --> LEMO1B (62.5 MHz frequency monitor)
LEMO2B --> chronobox sync (NIM) --> NIM-to-TTL --> long lemo cable to chronobox sync input (TTL)
LEMO3B --> long lemo cable to chronobox clock input (NIM) (CLK_IN configured for NIM input)
eSATA <--- eSATA splitter <--- eSATA from TRG (trigger signal)
MiniSAS 1 --> (MiniSAS --- eSATA) --> CDM-Slave eSATA (62.5 MHz)
MiniSAS 6 --> (MiniSAS --- eSATA) --> eSATA splitter --> RJ45 --> TDC (200 MHz)
</pre>

<pre>
CDM-Slave
---------
LEMO2A --> 4ns lemo cable --> LEMO1B (62.5 MHz frequency monitor)
eSATA <--- trigger and 62.5MHz clock from CDM-Master
MiniSAS 1 --> ADC trigger and 62.5MHz clock
MiniSAS 2 --> same
MiniSAS 3 --> same
MiniSAS 4 --> same
MiniSAS 5 --> PWB trigger and 62.5MHz clock
MiniSAS 6 --> same
</pre>

[[File:VME_Crate_CERN.jpeg|800x450px|Layout of the VME crate at CERN.]]

Layout of the VME crate at CERN. The ALPHA-T module is in the rightmost slot. The Master CDM is next to it and it's labelled as #02. The Slave CDM is on the lefmost position and labelled by #03.

== Setup of CDM boards ==

ALPHA-g uses the Rev3 CDM boards. The 4 CDM boards that belong to ALPHA-g
have serial numbers 0, 1, 2 and 3 and are labeled cdm00, cdm01, cdm02, cdm03.

All the boards can be used as master and slave positions, but have to be
configured appropriately.

=== Slave setup ===

* install the board
* connect ethernet
* connect esata external clock
* esper-tool cdmNN ### i.e. esper-tool cdm01
* cd template
* write current_setup 4
* cd /cdm
* read
* observe clock frequency counters report correct values. "ext_clk" will only count if the lemo jumper is installed (see below)
<pre>
11 esata_clk uint32 R [62500246]
12 ext_clk uint32 R [62500246]
</pre>
* cd /lmk
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
156 ld1_counter uint32 RW [3]
157 ld2_counter uint32 RW [3]
</pre>

If needed, check correct operation of the pll lock monitoring:

* unplug the esata cable from the master CDM
* "red" light should go off
* read of lmk should report "pll1_ld" value 0 and "ld1_counter" and "ld2_counter" should increment
* reconnect the esata cable
* "red" light should return
* read of lmk should report both pll1_ld and pll2_ld locked (values "1").

=== Master setup ===

* install the board
* connect ethernet
* esper-tool cdmNN ### i.e. esper-tool cdm01
* cd template
* write current_setup 3
* cd /lmk
* write clkin_sel_mode 0
* cd /cdm
* read
* observe clock frequency counters report correct values. "ext_clk" will only count if the "clock loopback" lemo jumper is installed (see below)
<pre>
12 ext_clk uint32 R [62500189]
</pre>
* cd /lmk
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
156 ld1_counter uint32 RW [3]
157 ld2_counter uint32 RW [3]
</pre>

Check the 200MHz clock:
* connect MiniSAS-eSATA splitter cable to MiniSAS output 6, connect eSATA end to CDM eSATA input
* in esper-tool, read cdm: esata_clk should report 200MHz clock
<pre>
11 esata_clk uint32 R [200000603]
12 ext_clk uint32 R [62500188]
</pre>

=== Master setup with external 10 MHz clock ===

* setup master CDM as above (using internal clock)
* connect 10MHz external clock to LEMO1A
* esper-tool cdmNN
* cd /cdm
* write sel_nim 1 # if clock is NIM signal
* write sel_nim 0 # if clock is TTL signal (i.e. chronobox LEMO output)
* read ext_clk
<pre>
[http://cdm00:/cdm]> read ext_clk
9999556
</pre>
* if ext_clk reads 0 or does not read something close to 10MHz, stop here. debug the signal, try changing sel_nim, etc.
* cd /lmk
* write clkin_sel_mode 2 # select external clock
* read
* observe both PLL1 and PLL2 are locked: both values should be "1"
<pre>
150 clkin2_sel bool R [True]
144 pll1_ld uint8 R [1]
147 pll2_ld uint8 R [1]
</pre>
* on the MIDAS TRG page, observe that TRG measured external clock frequency is close to 62.5 MHz

== clkin_sel_mode positions ==

* 0 = 10MHz internal oscillator (use on master CDM in standalone mode)
* 1 = eSATA clock (use on slave CDM)
* 2 = external clock, should be 10MHz (use on master CDM to run from AD clock)

== LEMO connections ==

LEMO connectors:

<pre>
|
|LEMO1A|LEMO1B
|LEMO2A|LEMO2B
|LEMO3A|LEMO3B
|eSATA
|RJ45 ETH
|minisas
|
</pre>

* clock loopback jumper: to read the frequency of the generated 62.5MHz clock, connect LEMO cable from LEMO2B to LEMO1A
* 10MHz internal clock jumper: to feed 10MHz internal oscillator to the external clock, connect LEMO cable from LEMO3A to the LEMO1A
* 10MHz external clock: to feed 10MHz external clock, connect LEMO cable to LEMO1A

= MIDAS frontends =

== UDP ==

feudp receives udp packets from the ADC and PWB boards. For each udp packet 1 midas event is created,
with 1 data bank containing the udp data. Events are sent into the MIDAS event buffer BUFUDP. The names
of the data banks are assigned in ODB /eq/feudp/settings.

{ADC,PWB} --> 1gige --> switch --> 10gige --> alphagdaq --> feudp -> BUFUDP

== CTRL ==

fectrl controls all the ADC, PWB and trigger boards. It provides run start and stop sequencing,
runs the event synchronization sequence at the begin of the run, and records slow controls data (temperatures,
voltages, etc).

fectrl receives UDP data packets from the trigger board and sends them to the MIDAS event buffer BUFUDP.

fectrl receives commands from the control web pages (for ADC, PWB and trigger) to reboot, initialize, etc the boards.

fectrl configures the event builder via odb /eq/fectrl/evbconfig.

ADC <-> http esper <-> fectrl -> slow control data into midas history

PWB <-> http esper <-> fectrl -> slow control data into midas history

TRG <-> udp comm <-> fectrl -> BUFUDP, slow control and counters into midas history

fectrl <-> midas rpc <-> mhttpd <-> json rpc <-> control web pages for ADC, PWB and trigger

== EVB ==

feevb receives udp packet data from the MIDAS event buffer BUFUDP, inspects the packet timestamps
and collects the data with matching timestamps into physics events. feevb has provisions to do
data suppression, reduction and compression in addition to the data reduction done
in the ADC and PWB firmware.

feevb event synchronization relies on the event synchronization sequence done by fectrl when a run is started.

{ADC, PWB, TRG} -> BUFUDP -> feevb -> SYSTEM -> mlogger -> compression -> disk storage

=== internal structure ===

* event buffer readers, instances for BUFTRG, BUFTDC, BUFADC, BUFUDP
<pre>
BufferReader class - reads one midas event buffer:
- BufferReaderThread()
-- in batches of 1000 events
--- lock
--- TickLocked()
----- ReadEvent() -> bm_receive_event_alloc()
----- fHandler->HandleEvent()
-- fHandler->XMaybeFlushBank()
-- sleep 100 usec
</pre>
* event header decoder and intermediate buffer
<pre>
Handler class - accumulates events, sends them to the EVB in batches

- HandleEvent() <- BufferReaderThread() - receive incoming events
-- loop over all banks, examine bank name
--- call AddAdcBank(), AddPwbBank(), AddTrgBank(), AddTdcBank() according to bank name
---- AddXxxBank() -> XAddBank()
--- unknown banks go directly to evb->SendQueue
-- check if synchronization has completed

- XAddBank() - save BankBuf objects in a buffer

- XMaybeFlushBank(), XFlushBank() - send all accumulated data to the Evb class
-- evb->lock()
-- for each buffered BankBuf objects,
--- call evb->AddBankLocked()
-- buffer is now empty
</pre>
* event builder
<pre>
Evb class - assemble event fragments according to timestamps

- fEvents fifo (deque) - time sorted list of partially assembled events
-- new entries are added by FindEvent()
-- entries are modified by MergeSlot()
-- old entries are removed by GetLocked()

- AddBankLocked() <- XFlushBank() <- BufferReaderThread()
-- call fSync->Add()
-- transform BankBuf to EvbEventBuf
-- push it into per-module buffer fBuf[imodule]

- EvbThread()
-- EvbTickLocked()
--- BuildLocked()
---- in a loop, for no more than 1 sec
----- loop over all per-module buffers fBuf
------ pop first entry, pass it to BuildSlot()
------- call FindEvent()
------- call MergeSlot()
------- call CheckEvent()
--- in a loop
---- get all completed events via GetLocked() pass them to SendQueue->PushEvent()
-- if done nothing, sleep 100 usec, otherwise nominal sleep to free the evb lock

- GetNext() <- GetLocked() <- EvbThread() - get completed events
-- examine oldest EvbEvent entry in fEvents:
-- pop it if it is complete
-- pop it if it is too old (to prevent old incomplete events from stalling the evb) ("pop age" on the evb page)
-- pop it if a following event is complete ("pop following" on the evb page)
</pre>
* send queue
<pre>
SendQueue class - prepare events for writing to midas SYSTEM event buffer

- PushEvent() <- EvbThread()
-- push FragmentBuf into the queue

- SendQueueThread()
-- in a batch of 1000 events, call Tick()
--- pop FragmentBuf from the queue, call SendEvent()
--- compose midas event (memcpy()!)
--- TMFE fEq->SendEvent()
--- bm_send_event()
-- sleep 100 usec
</pre>
* equipment object
<pre>
EvbEq class - implements the midas equipment
- HandleBeginRun()
- HandleEndRun()
- HandlePeriodic()
</pre>

=== multithreading ===

* BufferReaderThread() one per midas event buffer
** high CPU use: bm_receive_event(), AddXxxBank()
** lock contention: midas event buffer lock, evb lock into XFlushBank->AddBankLocked()
* EvbThread()
** O(size of fEvents): FindEvent(), GetNext()
** lock contention: evb lock against XFlushBank(), SendQueue lock (1 per output event)
* SendQueueThread()
** high CPU use: memcpy() in SendEvent(), memcpy() in bm_send_event
** lock contention: event queue lock against EvbThread, midas event buffer lock
* main thread
** lock contention: evb lock in ReportEvb() and elsewhere

= ODB entries =

== /Equipment/CTRL/Settings ==
* TBW

== /Equipment/CTRL/Settings/Pulser ==

* ClockFreqHz - unit of 1/sec (Hz), set to 62500000, the TRG 62.5 MHz clock frequency (16 ns)
* PulseWidthClk - unit of 16 ns clocks, set to 25. (400 ns). width of internal pulser signal (used to go to a TRG external output, absent on GRIF-C boards)
* PulsePeriodClk - unit of 16 ns clocks, pulser in clock periods (+1), set to zero.
* PulseFreqHz - unit of 1/sec (Hz), requested pulser frequency, actual frequency is rounded to 16 ns clock granularity, change this value to select desired clock frequency
* BurstCtrl - enable burst of pulses 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses
* OutputEnable - enable TRG pulser external output (absent on GRIF-C boards)
* Enable - allow the pulser to run (bit 3 in TRG conf_trig_enable register)

== /Equipment/CTRL/Settings/TrigSrc - trigger source selection ==
* TrigPulser - trigger on the pulser
* TrigEsataNimGrandOr - trigger on external NIM inputs of GRIF-16 ADC modules
* TrigAdc16GrandOr - trigger on any adc16 signals (see adc16_masks)
* TrigAdc32GrandOr - trigger on any adc32 signals (see adc32_masks)
* Trig1ormore - trigger on adc16 multiplicity 1 or more
* Trig2ormore - ditto, 2 or more
* Trig3ormore - ditto, 3 or more
* Trig4ormore - ditto, 4 or more
* TrigAdcGrandOr - trigger on any ADC signal
* TrigAwCoincA - trigger on TPC AW coincidence (see [[TRG]] manual)
* TrigAwCoincB - ditto
* TrigAwCoincC - ditto
* TrigAwCoincD - ditto
* TrigAwCoinc - ditto
* TrigAw1ormore - trigger on TPC AW per-preamp multiplicity 1 or more (see [[TRG]] manual)
* TrigAw2ormore - ditto, 2 or more
* TrigAw3ormore - ditto, 3 or more
* TrigAw4ormore - ditto, 4 or more
* TrigAwMLU - trigger on TPC AW MLU signal (see [[TRG]] manual)
* TrigBscGrandOr - trigger on any BSC signal
* TrigBscMult - trigger on predefined BSC multiplicity (see [[TRG]] manual)
* TrigCoinc - trigger on predefined coincidence of TPC AW, BSC and external signal (see [[TRG]] manual)

== /Equipment/CTRL/Settings/TRG - trigger settings ==
* Enable - if set to "n", fectrl will not do anything with the trigger board. Normal value "y"
* Modules - hostnames of the trigger board. Normal value "alphat01"
* NimMask - 32-bit mask for the 32x NIM inputs (see TRG manual). Normal value 0, unless external trigger is in use.
* EsataMask - 32-bit mask for the 32x eSATA signals (see TRG manual). Normal value 0.
* adc16_mask[16] - 16x 16-bit mask for the 100MHz GRIF-16 onboard ADCs (see TRG manual). Normal value 0xFFFF for all 16 data links.
* adc32_mask[16] - 16x 32-bit mask for the 62.5MHz FMC-ADC32 ADCs (see TRG manual). Normal value 0xFFFFFFFF for all 16 data links.
* PassThrough - if set to "y", trigger is passed through the trigger module without generating any events and without causing deadtime.
* AwCoincA, B, C and D - 32-bit masks for the aw16 coincidence trigger (see TRG manual)
* Aw16FromAdc16 - route AW trigger (aw16) from adc16 (100MHz ADCs 0..15)
* Aw16FromAdc32a - route AW trigger (aw16) from adc32 group 15..0 (62.5MHz FMC-ADC32 in ADCs 0..7)
* Aw16FromAdc32b - route AW trigger (aw16) from adc32 group 31..16 (62.5MHz FMC-ADC32 in ADCs 8..15)
* MluDir, MluFiles - location of aw16 MLU bit patterns
* MluSelectedFile - currently selected/loaded MLU file. 0="grand or", 1="2 or more hit clusters", 2="2 or more hit clusters, with gap 2 or more", 3="3 or more hit clusters"
* MluPrompt - length of aw16_prompt_run gate in units of 8 ns clock, see [[TRG#aw16_mlu]]
* MluWait - length of aw_prompt_wait gate in units of 8 ns clock, see [[TRG#aw16_mlu]]
* MluTrigDelayClk - "TrigDelay" when triggered of aw16 MLU, in units of 16 ns clock
* (BSC settings, TBW)
* CoincStart - set same as CoincRequire
* CoincRequire - 0x5: (BSC grand or)*(TPC aw16_1ormore), 0x6: (BSC grand or)*(AW16 MLU), see [[TRG#Coincidence_trigger]] and [[TRG#conf_coinc_control bits]]
* CoincWindow - length of coincidence window in 8ns clocks.

== /Equipment/CTRL/Settings/PWB - PWB settings ==
* Enable - if set to "n", fectrl will not do anything with PWBs. Normal value "y".
* enable_boot_user_page - if set to "n", fectrl will not try to reboot PWBs into the user page firmware. Normal value "y".
* enable_trigger - if set to "n", all PWBs will be set to ignore the trigger. Normal value "y".
* enable_trigger_group_a - field wire pulser defeats the data suppression (every channel has a pulse) resulting in too much data overwhelming the DAQ (lost UDP packets). To permit correct data taking of field wire pulser data, PWBs are split into two groups (a and b), only one of the two groups should be enabled for field wire pulser runs. Both groups should be enabled for normal data taking. Normal value is "y"
* enable_trigger_group_b - see "enable_trigger_group_a". Normal value is "y".
* modules[64] - hostnames of PWB boards
* boot_user_page[64] - if set to "y" and enable_boot_user_page is "y", fectrl will reboot the corresponding PWB to the user page firmware.
* trigger[64] - if set to "y" and enable_trigget is "y", fectrl will set the PWB to accept the trigger.
* ch_enable - if set to "n" disables all PWB channels. Normal value is "y".
* ch_force - is set to "y" disables channel suppression (all PWB channels are read)
* suppress_reset - if set to "y" enables channel suppression for reset channels (threshold has to be set correctly)
* suppress_fpn - if set to "y" enables channel suppression for fpn channels (threshold has to be set correctly)
* suppress_pads - set to "y" enables channel suppression for TPC pad channels (threshold has to be set correctly)
* disable_reset1 - data suppression algorithm does not work for the channel "reset1" and it has to be suppressed explicitly by setting this value to "y". Normal value is "y".
* baseline_{reset,fpn,pads}[64] - waveform baseline for each PWB position
* threshold_{reset,fpn,pads} - waveform suppression threshold, see below:
* ch_threshold - PWB sca_N_ch_threshold, if set to 0, threshold is computed as "baseline_pads[seqpwb]-threshold_pads". Normal value is 0.
* test_mode - enable PWB test mode, the ADC data is replaced with a test pattern, see PWB esper variable signalproc/test_mode

== /Equipment/CTRL/Settings/TDC - TDC settings ==
* Enable - if set to "n", fectrl will tell the event builder that the TDC is not running. Normal value is "y".

== /Equipment/CTRL/Variables ==

* Scalers - TRG scalers and counters. from fectrl.cxx ReadTrgLocked()
<pre>
// 0..15 read the 16 base scalers at 0x100
// 16..31 read the adc16 scalers at 0x430
// 32..63 read the adc32 scalers at 0x440
// 64..79 read the 16 additional scalers at 0x110
// 80..95 read the 16 counters_adc_selected scalers at 0x460
// 96..159 read the 64 bar scalers at 0x470
// additional scalers should be appended at the end.
</pre>

== /Equipment/CTRL/EvbConfig - EVB configuration ==
All arrays have the same size corresponding to the number of EVB slots.
* name[] - slot name for the web page (trg01, adc01, adc01/adc32, pwb31/0, tdc01, etc)
* type[] - slot type: 1=TRG, 2=ADC16 and ADC32, 3=obsolete PWB, 4=obsolete PWB, 5=PWB, 6=TDC
* module[] - module number (adcNN, adcNN+100, pwbNN, etc)
* nbanks[] - number of expected banks (16 for ADC16, 32 for ADC32, not used, set to 1 for all others)
* tsfreq[] - timestamp frequency in Hz.

== /Equipment/ADC_UDP - ADC UDP configuration ==

* Common/Buffer - "BUFADC" - event buffer to use, name is hardwired in feevb.cxx
* Settings/udp_port - 50006 - UDP port number, also used by fectrl to configure the ADC modules
* Settings/rcv_bufsize - 209715200 - udp socket buffer size set by setsockopt(SOL_SOCKET, SO_RCVBUF). must have a corresponding command in /etc/rc.local to increase maximum system socket size: "/usr/sbin/sysctl -w net.core.rmem_max=200000000"
* Settings/packet_size - 1500 - non-jumbo-frame UDP packet maximum size
* Settings/max_buffered_packets - 40000 - maximum size of internal packet fifo. If it overflows, extra packets are discarded.
* Settings/max_packets_per_event - 8000 - how many UDP packets to pack into one midas event==

== /Equipment/PWB_X_UDP - PWB UDP configuration ==

For explanation see ADC_UDP above.

* Common/Buffer - "BUFUDP" - event buffer to use, name is hardwired in feevb.cxx
* Settings/udp_port - 50007, 50008, 50009, 50010 - for A, B, C and D UDP receivers respectively, also used by fectrl to configure the PWB modules
* Settings/rcv_bufsize - 209715200
* Settings/packet_size - 1500
* Settings/max_buffered_packets - 10000
* Settings/max_packets_per_event - 8000

= Trigger configuration =

These trigger modes are implemented:
* (manual trigger from web page)
* software pulser trigger (from fectrl)
* hardware pulser trigger (from the trigger board)
* NIM and eSATA trigger from ADC front panel inputs
* adc16 and adc32 discriminator triggers:
** adc16 grand-or trigger
** adc32 grand-or trigger
** adc (adc16+adc32) grand-or trigger
** adc16 multiplicity trigger (1ormore, 2ormore, 3ormore, 4ormore) for use with barrel scintillator
** anode wire multiplicity trigger (1ormore, 2ormore, 3ormore, 4ormore) (anode wire signals can be fed from adc16 or from adc32 signals)
** anode wire coincidence trigger
** anode wire MLU (memory lookup) trigger

== NIM trigger from ADC front panel ==

Trigger path:
<pre>
NIM signal --> LEMO input on ADC front panel --> data encoder --> data link to trigger board --> data decoder --> mask --> nim-esata-grand-or --> trigger
</pre>

To enable NIM trigger, do this:
* connect NIM signal to ADC front panel input
** Note1: NIM signal must be inverted
** Note2: LEMO connectors should be set to "NIM input" mode by ADC on-board jumpers (see ADC manual)
* observe correct bit goes to zero in the TRG web page: data link high work should change:
<pre>
0xNF00'0000 (N is the module id) to
0xN700'0000 (left lemo) or
0xNB00'0000 (right lemo)
</pre>
* Note3: if data link bits do not change, most likely the LEMO connectors are set to "DAC output" mode. Try to use LEMO inputs of a different ADC.
* compute the NIM mask: there are 32 bits, 2 bits per ADC data link. Bit 0x1 is right LEMO, bit 0x2 is left LEMO
* for example, to use left LEMO of ADC data link 12, set nim mask to (0x2)<<(2*12) = 0x02000000
* development branch of the git repository contains ''scripts/nim_mask.py'', which can compute forwards and backwards
* initialize the trigger board (on the TRG web page press button "initialize"), or start a new run
* on the history plot with "NIM grand or" counter, the rate should change from zero
* if a run is active, if one of the ADC LEMO outputs is set to output the trigger signal as a NIM pulse, one should see it fire use a scope. The delay or jitter between NIM trigger in and NIM trigger out should be around 100-200 ns (FIXME - measure this!)
* to set the DAQ to trigger on the NIM signal, on the run start page, check the box "TrigEsataNimGrandOr".
** Note: remember to set the scaledown to 0 if so desired.

= TPC field wire pulser =

The TPC field wire pulser input should be connected directly to the DAC output of ADC[0] (right lemo connector).

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for pulsing PWBs, baseline -1V, pulse height +2V (maximum possible pulse height in PWBs. Overdrives the AW ADC waveforms)
** dac_baseline: -8000
** dac_amplitude: 8000
** ramp_up_rate: 128
** ramp_down_rate: 70
** ramp_top_len: 128

* for pulsing AW, baseline -0.25V, pulse height +0.7V (AW ADC waveforms are in range. PWB waveforms are too small for goor time resolution)
** dac_baseline: -2000
** dac_amplitude: 4000
** ramp_up_rate: 20
** ramp_down_rate: 20
** ramp_top_len: 128

= BSC pulser =

The BSC pulser input on the BSC VME rear transition board (RTM) should be connected directly to the DAC output of ADC[4,5,6,7] (right lemo connector). (8 RTMs, but 4 ADCs, each signal is split using a LEMO "T" connector).

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for pulsing BSC, baseline -0.950V, pulse height +1.4V
** dac_baseline: -8000
** dac_amplitude: 4000
** ramp_up_rate: 64
** ramp_down_rate: 64
** ramp_top_len: 128

= NIM output =

To configure ADC analog output for NIM compatible pulse:

DAC settings in ODB /Equipment/CTRL/Settings/ADC/DAC/

* for output of NIM pulse: baseline 0V, pulse height -0.9V, pulse width 100 ns
** dac_baseline: 0
** dac_amplitude: 8000
** ramp_up_rate: 128
** ramp_down_rate: 128
** ramp_top_len: 4
** dac_xor: 1 (invert the signal)

= TDC connections =

* SFP8 - fiber SFP to Juniper switch
* right RJ45 - 200MHz clock
* left RJ45 - external trigger

= MIDAS Data banks =

* ATAT - fectrl - UDP packets from GRIF-C/TRG trigger board
* TRBA - fetdc - TDC data
* TRTM - fetdc - TDC FPGA temperatures, TID_FLOAT[5].
* AAnn - feudp - UDP packets from GRIF-16 ADC (before the event builder), "nn" is the ADC module number: adc01 is AA01 through adc20 is AA20.
* BBxx - feudp - UDP packets from PWB, obsolete
* Bnnm, Cnnm - feevb - EVB output banks: ADC data, "nn" is the ADC module number (1..20), "m" is the channel number (0..9,A..F), format is same as AAnn banks.
* PAnn - feudp - UDP packets from PWB, "nn" is the PWB module number (00..99), obsolete
* PBnn - feudp - UDP packets from PWB, "nn" is the PWB module number (00..99), PB01 is pwb01, PB78 is pwb78
* PCnn - feevb - EVB output banks: PWB data, "nn" is the PWB module number (00..99), same as above, format is same as PBnn banks

= ZZZ =

ZZZ

TRG

2022-07-15T19:49:30Z

Olchansk: /* Register addresses */

= TRG, the trigger control board for the ALPHA-g detector =

= Links =

* xxx
* https://bitbucket.org/expalpha/trg_firmware - firmware sources on bitbucket

= General characteristics =

== Photos ==

== Board schematics ==

* https://bitbucket.org/expalpha/trg_firmware/src/master/3xFMC_VME_Motherboard.pdf

== Available hardware ==

* Altera Stratix IV - main FPGA
* Altera Max V - boot FPGA
* boot flash: PC28F512M29EW - 512 Mbit parallel NOR flash.

= TRG front panel connections =

From top to bottom:

<pre>
|
| minisas-C - links 8-11
| minisas-D - links 12-15
|
| ethernet sfp - use copper sfp only
| minisas - not used, do not connect
| esata - clock in, trigger out
|
| minisas-A - links 0-3
| minisas-B - links 4-7
|
| LEDs
|
</pre>

MiniSAS and SATA flail cable connections:

<pre>
P1 <--> link 3
P2 <--> link 2
P3 <--> link 1
P4 <--> link 0
</pre>

LEDs:

<pre>
--PCB-- (left)
LED[0] - trigger out - ag_trig_out
LED[1] - network packet received - sfp_rx_data_valid
LED[2] - Xilinx FPGA boot ok - FMC1_CFG_DONE
LED[3] - not used
(right)
</pre>

= TRG onboard jumpers and switches =

* rotary switches: select IP address: 00=192.168.1.50, 11=.51, 22=.52, 33=.53, 44=.54, otherwire=.251

= Firmware update procedure =

* use quartus to generate the grifc.pof file (use grifc.cof)
* open quartus programmer
* attach grifc.pof to the 1st CFI_512 flash
* mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
* check that "initiate configuration after programming" is set in tools->options
* say "start"
* should take about 5 minutes
* grifc should reboot into the new firmware

If CFI_512 flash is not visible to the quartus programmer, load correct
code into the MaxV CPLD:

* open quartus programmer,
* say "auto detect"
* change file for the 5M2210 device
* use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
* say "program", it should finish in 10-15 seconds
* say "auto detect"
* CFI_512 flash should be visible now.

= Firmware revisions =

* 0x5bc8f90f - original firmware used for all data
* 0x6147c0f9 - added cbtrg, etc. installed at CERN on 20 Sep 2021.
* 0x618376ae - bigger cbtrg fifo, data rate tested up to 30 Mbytes/sec
* 0x6189c7f3 - fix loss of trigger packets. (missing fifo between alphag block and ethernet mux)
* 0x618b790b - fix loss of timestamps. (cbtrg inputs stretched to 100 ns long). installed at CERN 10 Nov 2021.

= Firmware build =

* use quartus 20.1
* see Makefile in the trg_firmware project

= Jtag remote connection =

* ssh agmini@daq16
* /opt/intelFPGA/16.1/quartus/bin/jtagd --config /home/agmini/.jtagd.conf
* netstat -an | grep 1309 ### note listen address is "0.0.0.0", NOT "127.0.0.1"
<pre>
tcp 0 0 0.0.0.0:1309 0.0.0.0:* LISTEN
</pre>
* opt/intelFPGA/16.1/quartus/bin/jtagconfig ### should work
* ssh olchansk@daq01
* cd git/trg_firmware
* /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
* jtagconfig ### should work
<pre>
daq01:trg_firmware$ jtagconfig
1) DE-SoC on daq16 [2-1.2.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) USB-Blaster on daq16 [2-1.3]
024090DD EP4SGX230(.|ES)
020A40DD 5M(1270ZF324|2210Z)/EPM2210

daq01:trg_firmware$
</pre>

= ALPHA-g trigger functions =

Trigger options:
* software trigger
* pulser trigger
* trigger on GRIF16 ADC NIM and ESATA inputs ("external trigger")
* adc16 grand-or
* adc32 grand-or
* adc16 wire multiplicity
* TPC anode wire per-preamp trigger (aw16 section)
** trigger on coincidences of preamps (removed fw 0x62c77f0b)
** trigger on multiplicity of preamps (removed fw 0x62c77f0b)
** trigger on specific topology of preamps (multiplicity of preamp clusters, etc) via the aw16_mlu trigger
* BSC trigger
** BSC grand_or
** BSC bar multiplicity
* coincidence trigger - select coincidence of external trigger, TPC AW grand-or, TPC AW MLU, BSC grand-or and BSC bar multiplicity triggers

== software trigger ==

to programmatically fire the trigger, one should:
* set the conf_enable_sw_trigger bit in conf_trig_enable, this will permit the software trigger to fire the trigger
* write value 0x4 to register 0x2B, this will cause the software trigger to fire

== pulser trigger ==

To use the pulser trigger, one should program:
* pulser period (in clocks)
* pulser width (in clocks, use value 5, the pulser no longer goes outside of the trigger board, so changing the width does not do anything)
* set the run_pulser bit in conf_trig_enable, this will cause the pulser to run
* set the enable_pulser bit in conf_trig_enable, this will cause the pulser to fire the trigger
* set the output_pulser bit in conf_trig_enable, this will cause the pulser to be output from the alphag firmware block (the pulser no longer goes outside of the trigger board, so changing the bit does not do anything)

== timeout trigger ==

The event builder uses event timestamps to assemble physics events. The timestamps
are usually 32 bit wide and run at 125 MHz (8 ns) or 62.5 MHz (16 ns). If
triggers are generated often (1 per second or more), timestamp wrap around
is easily detected by the event builder. If triggers come infrequently,
timestamp wrap around may occur while there are no triggers, not be seen
by the event builder causing loss of event synchronization.

To avoid this problem in the event builder, a timeout trigger should be generated
if no triggers were generated inside a 10 second interval.

The guaranties that even if all physics triggers temporarily stop for any reason,
the event builder will stay synchronized. (0.1 Hz timeout trigger frequency).

To enable the timeout trigger:
* program timeout trigger timeout in reg 0x43 in units of 8 ns clock
* enable it in bit 23 of [[#conf_trig_enable bits]]

== adc16 multiplicity trigger ==

This trigger is intended for use with the barrel scintillator signals connected to adc16 digitizers. It does not work well with TPC AW signals.

The 16 adc16 trigger bits (16x16=256) are added together to form the hit multiplicity value (adc16_mult, 16 bits, actual range 0 to 256).

Four threshold signals are computed: adc16_mult_1ormore = adc16_mult>=1, 2ormore, 3ormore, 4ormore.

There is a counter for each of these four signals.

Each of these four signals can fire the trigger, see [[#conf_trig_enable bits]].

== TPC anode wire triggers ==

=== aw16 bus ===

TPC Anode Wire trigger is based on the aw16[15:0] (xaw16) bus.

Each bit corresponds to one AW preamp. 16 preamps, 16 bits.

The aw16[15:0] bus can be fed by
* adc16_or16[15:0] - or16 of 100 MHz ADCs, 16 ADC sas links
* adc32_or16[15:0] - or16 of 62.5 MHz ADCs, FMC-ADC32 has 32 channels, so 2 bits per ADC: low 16 channels and high 16 channels, sas links 7..0
* adc32_or16[31:16] - or16 of 62.5 MHz ADCs, ditto, sas links 15..8
as selected by conf_enable_aw_adc16, conf_enable_aw_adc32a, conf_enable_aw_adc32b in [[#conf_control bits]]

<pre>
///////////////////////////////////////////////////////////
// TPC Anode Wire trigger logic (aw16)
///////////////////////////////////////////////////////////

// map adc signals into aw16

wire [15:0] aw16 = ({16{conf_enable_aw_adc16}} & adc16_or16[15:0]) |
({16{conf_enable_aw_adc32a}} & adc32_or16[15:0]) |
({16{conf_enable_aw_adc32b}} & adc32_or16[31:16]);
...
ag_conditioner cond_adc16_or16_0(.clk(clk), .in(aw16[0]), .out(xxaw16[0]));
...
xaw16 <= xxaw16;
</pre>

=== aw16_grand_or ===

TPC AW "grand or" trigger: use aw16_mult_1ormore (before fw 0x62c77f0b)

(256 anode wires, 16 wires per preamp, 16 preamps, 16 aw16 signals)

=== aw16_mlu ===

TPC AW preamp MLU trigger: the MLU (memory lookup
table) implements an arbitrary logical function
to map the 16 aw16 preamp signals into 1 aw16_mlu_trig trigger output.

Description of the aw16 mlu trigger.

In words:

* any aw16 signal starts the aw16_prompt_run gate
* aw16 signals are collected for the duration of conf_mlu_prompt (125MHz/8ns clock)
* this corresponds to time spread of TPC AW signals due to the drift time in the AW drift cell and to the variation in signal transmission time from the ADC to the TRG (digital trigger data link).
* when this prompt time expires, the MLU looks at the accumulated aw16_prompt bit pattern and makes the "yes/no" trigger decision
* after the trigger decision is made, we wait for the TPC to become quiet:
* we wait until all aw16 signals are empty (no timeout)
* we run the aw16_prompt_wait gate, length conf_mlu_wait (8ns clock), if any aw16 signals arrive, we wait for aw16 empty again, rinse, repeat.
* now, after TPC aw16 have been empty for conf_mlu_wait clocks (8ns clock), MLU trigger is ready for the next event.

In logic: (see alphag.v)

* aw16_or <= grand-or of 16 aw16 signals
* "aw16_or" starts the "aw16_prompt_cnt" counter, opens the aw16_prompt_run gate
* during the aw16_prompt_run gate, aw16_prompt collects (latches) the aw16 bits (aw16_prompt <= aw16_prompt | aw16)
* this is the time when we wait for all "prompt" signals from the TPC to arrive into the trigger
* at the end of the aw16_prompt_run gate, the signal aw16_prompt_out is pulsed, latching the output of the MLU into aw16_mlu_trig
* this is the MLU trigger "yes/no" trigger decision.
* after the MLU trigger decision is made, we wait for the arrival and passing of all TPC drift signals
* the aw16_prompt_wait_cnt and aw_prompt_wait gate opens
* if any new aw16 signals arrive (they are TPC drift signals at this time), the aw16_prompt_wait gate is restarted
* if no aw16 signals arrive during the full run of the aw16_prompt_wait gate ("TPC quiet time")
* the aw16_prompt_wait and aw16_prompt gates are cleared and the MLU trigger is ready for the next event.

Good settings are:
* conf_mlu_prompt: 64 (512 ns)
* conf_mlu_wait: 128 (1024 ns)

== BSC trigger ==

=== bsc_adc16 bus ===

The BSC trigger is based on the [15:0]bsc_adc16[7:0] bus: 16 trigger discriminator bits from 8 ADC sas links. (8*16 = 64+64 bars, top and bottom).

The bsc_adc16 bus can be fed from sas links 0..7 or 8..15, controlled by conf_bsc_adc16_a and conf_bsc_adc16_b bits on [[#conf_bsc_control bits]].

bsc_adc16 can be fed only from GRIF-16 100 MHz ADC trigger discriminators.

=== bsc64_top and bsc64_bot buses ===

* firmware 0x5bc8f90f: bsc_adc16 is remapped into 64 bits of top (bsc64_top) and bottom (bsc64_bot):
<pre>
ag_bsc_remap bsc_remap_a(.adc(bsc_adc16[0]), .bsc_bot(bsc64_bot[7:0]), .bsc_top(bsc64_top[7:0]));
ag_bsc_remap bsc_remap_b(.adc(bsc_adc16[1]), .bsc_bot(bsc64_bot[8+7:8+0]), .bsc_top(bsc64_top[8+7:8+0]));
ag_bsc_remap bsc_remap_c(.adc(bsc_adc16[2]), .bsc_bot(bsc64_bot[2*8+7:2*8+0]), .bsc_top(bsc64_top[2*8+7:2*8+0]));
ag_bsc_remap bsc_remap_d(.adc(bsc_adc16[3]), .bsc_bot(bsc64_bot[3*8+7:3*8+0]), .bsc_top(bsc64_top[3*8+7:3*8+0]));

ag_bsc_remap bsc_remap_e(.adc(bsc_adc16[4]), .bsc_bot(bsc64_bot[4*8+7:4*8+0]), .bsc_top(bsc64_top[4*8+7:4*8+0]));
ag_bsc_remap bsc_remap_f(.adc(bsc_adc16[5]), .bsc_bot(bsc64_bot[5*8+7:5*8+0]), .bsc_top(bsc64_top[5*8+7:5*8+0]));
ag_bsc_remap bsc_remap_g(.adc(bsc_adc16[6]), .bsc_bot(bsc64_bot[6*8+7:6*8+0]), .bsc_top(bsc64_top[6*8+7:6*8+0]));
ag_bsc_remap bsc_remap_h(.adc(bsc_adc16[7]), .bsc_bot(bsc64_bot[7*8+7:7*8+0]), .bsc_top(bsc64_top[7*8+7:7*8+0]));

module ag_bsc_remap
(
input wire [15:0] adc,
output wire [7:0] bsc_bot,
output wire [7:0] bsc_top
);

assign bsc_top[3] = adc[0];
assign bsc_top[2] = adc[1];
assign bsc_top[1] = adc[2];
assign bsc_top[0] = adc[3];

assign bsc_top[7] = adc[4];
assign bsc_top[6] = adc[5];
assign bsc_top[5] = adc[6];
assign bsc_top[4] = adc[7];

assign bsc_bot[0] = adc[8];
assign bsc_bot[1] = adc[9];
assign bsc_bot[2] = adc[10];
assign bsc_bot[3] = adc[11];

assign bsc_bot[4] = adc[12];
assign bsc_bot[5] = adc[13];
assign bsc_bot[6] = adc[14];
assign bsc_bot[7] = adc[15];

endmodule
</pre>

=== bsc64 bus ===

the bsc64 bus is the 64 bars used by the trigger, formed from bsc64_top and bsc64_bot:
<pre>
if (conf_bsc64_bot_only) begin
bsc64 <= bsc64_bot;
end else if (conf_bsc64_top_only) begin
bsc64 <= bsc64_top;
end else if (conf_bsc64_bot_top_or) begin
bsc64 <= bsc64_bot | bsc64_top;
end else if (conf_bsc64_bot_top_and) begin
bsc64 <= bsc64_bot & bsc64_top;
end else begin
bsc64 <= 64'b0;
end
</pre>

=== bsc_grand_or_trig ===

bsc_grand_or_trig is the grand-or of 64 bits of the bsc64 bus

to enable triggering on bsc_grand_or_trig, set corresponding bit in [[#conf_trig_enable bits]]

=== old bsc_mult_trig ===

(from fw 0x62c77f0b, old bsc_mult_trig was replaced by new bsc64 multiplicity trigger)

* bsc64_mult is computed as multiplicity of the bsc64 bus (number of 64 bsc64 bits that fired)
* bsc_mult_trig is computed:
<pre>
if (bsc64_mult >= conf_bsc64_mult) begin
bsc_mult_trig <= 1;
end else begin
bsc_mult_trig <= 0;
end
</pre>

to enable the bsc multiplicity trigger, set the multiplicity value conf_bsc64_mult in [[#conf_bsc_control bits]] and enable the corresponding bit in [[#conf_trig_enable bits]].

=== bsc64 multiplicity trigger ===

bsc64 BSC bar multiplicity trigger uses a time window. this time window is started by bsc64_grand_or and runs for conf_bsc64_mult_window clocks (8 nc clock). During this time, hits in bsc64_bus are accumulated (latched) and their multiplicity is computed. If multiplicity condition is satisfied (bigger or equal to conf_bsc64_mult_min), bsc64_mult_trig is fired and the bsc64 bit pattern is saved to the UDP packet. Then trigger waits for the bsc64_bus to be empty. Then trigger waits for conf_bsc64_empty_window clocks, if there is any bsc64 hits, we wait for empty again. So after bsc64 has been empty for conf_bsc64_empty_window clocks, multiplicity trigger is ready for the next event. This scheme cannot implement max multiplicity.

recommended values:
* conf_bsc64_mult_window (8 bits): slightly longer than 3 cycles of SAS link: 3*18 = 54 clocks, good value is 80 (640 ns).
* conf_bsc64_mult_min (8 bits): 2
* conf_bsc64_empty_window (8 bits): 80 (640 ns)

== Coincidence trigger ==

Coincidence trigger provides a combination of TPC, BSC and external scintillator (esata_nim_grand_or) signals:

<pre>
assign coinc_input[0] = aw16_grand_or; // was aw16_mult_1ormore;
assign coinc_input[1] = aw16_mlu_trig;
assign coinc_input[2] = bsc_grand_or_trig;
assign coinc_input[3] = bsc_mult_trig;
assign coinc_input[4] = esata_nim_grand_or;
assign coinc_input[5] = 0;
assign coinc_input[6] = 0;
assign coinc_input[7] = 0;
</pre>

Coincidence trigger "start" mask selects which of the inputs can start the coincidence window.

Coincidence trigger "require" mask selects which inputs must have a hits for the coincidence ot be satisfied.

Input hits are collected for the duration of the coincidence window, if all required inputs have hits, coinc_trig is fired.

Example settings:

* coincidence of external scintillator, BSC and TPC AW "grand or" signals: start 0x10, required 0x15
* coincidence of BSC and TPC AW "grand or" signals: start 0x4, required 0x5
* coincidence of BSC and TPC AW MLU triggers: start 0x4, required 0x6
* coincidence of BSC multiplicity and TPC AW MLU triggers: start 0x8, required 0xA

= Control registers =

== Register addresses ==

Note: all registers are 32 bits unless otherwise noted.

Note: RW means read-write register, RO means read-only, ROL means read-only, contents is latched by the "latch_out" bit

{| cellpadding="10" cellspacing="0" border="1"
! Address || Quartus Name || Access || FwRev || Description
|-
| 0x08 || num_sample || RW || GRIF-C || magic 16-bit register to control UDP packet size
|-
| 0x08 || scratch_reg || RW || 0x618b790b || 32-bit scratch register
|-
| 0x1F || compilation_time || RO || || Firmware revision
|-
| 0x20 || conf_trig_width || RW || || Trigger signal width, 16 ns clock
|-
| 0x21 || conf_busy_width || RW || || Busy signal width, 16 ns clock (not used)
|-
| 0x22 || conf_pulser_width || RW || || Pulser signal width, 16 ns clock
|-
| 0x23 || conf_pulser_period || RW || || Pulser signal period, 16 ns clock
|-
| 0x24 || conf_pulser_burst_ctrl || RW || 0x62d1bb19 || Generate bursts of pulses: 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses, 16 ns clocks
|-
| 0x25 || conf_trig_enable || RW || || see [[#conf_trig_enable bits]]
|-
| 0x26 || || || not used
|-
| 0x27 || || || not used
|-
| 0x28 || || || not used
|-
| 0x29 || conf_nim_mask || RW || || enable bits for ADC NIM inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2A || conf_esata_mask || RW || || enable bits for ADC eSATA inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2B || reset_out, latch_out, trigger_out || W || || see [[#reg 0x2B bits]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x5bc8f90f || configure AW coincidence trigger, see [[#aw16_coinc]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x62c77f0b || removed
|-
| 0x2D || conf_aw16_coinc_b || RW || 0x5bc8f90f ||
|-
| 0x2E || conf_aw16_coinc_c || RW || 0x5bc8f90f ||
|-
| 0x2F || conf_aw16_coinc_d || RW || 0x5bc8f90f ||
|-
| 0x30 || sas_sd[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect for each link
|-
| 0x31 || pll_625_status || ROL || 0x5b2057f5 (12Jun18_16:32) || 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter
|-
| 0x32 || clk_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the system 125 MHz clock
|-
| 0x33 || clk_625_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625)
|-
| 0x34 || conf_control || RW || 0x5b398983 (01Jul18_19:10) || see [[#conf_control bits]] below
|-
| 0x35 || conf_drift_width || RW || 0x5b398983 (01Jul18_19:10) || width of drift time blank-out in 16 ns clocks
|-
| 0x36 || conf_scaledown || RW || 0x5b398983 (01Jul18_19:10) || trigger scaledown, 0=no scaledown, 1=divide-by-2, 2=divide-by-3, etc
|-
| 0x37 || conf_mlu || RW || 0x5b398983 (01Jul18_19:10) || AW MLU control bits, see [[#conf_mlu bits]]
|-
| 0x38 || conf_trig_delay || RW || 0x5baedfca (28Sep18_19:13) || delay the trigger pulse, 16 ns clock
|-
| 0x39 || esata_clk_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the TRG 125 MHz clock
|-
| 0x3A || esata_clk_esata_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the external clock (eSATA 62.5 MHz clock)
|-
| 0x3B || conf_counter_adc_select || RW || 0x5bb7f6ae (05Oct18_16:41) || select which 16 ADCs are connected to the selected adc counters, 0..15 - connect the adc16 signals, 16..47 connect the adc32 signals
|-
| 0x3C || sysreset_ts || RO || 0x5bb7f6ae (05Oct18_16:41) || 125MHz counter of VME-SYSRESET
|-
| 0x3C || || || 0x618b790b || not used
|-
| 0x3D || GRIF-C csr || RW || GRIF-C || <= csr & ~par_value; // Selective clear
|-
| 0x3E || GRIF-C csr || RW || GRIF-C || <= csr | par_value; // Selective set
|-
| 0x3F || GRIF-C csr || RW || GRIF-C || <= par_value; // write
|-
| 0x3D || || || 0x618b790b || not used
|-
| 0x3E || || || 0x618b790b || not used
|-
| 0x3F || || || 0x618b790b || not used
|-
| 0x40 || conf_bsc_control || RW || 0x5bc13541 (12Oct18_16:58) || Barrel Scintillator trigger control, see [[#conf_bsc_control bits]]
|-
| 0x41 || conf_coinc_control || RW || 0x5bc13541 (12Oct18_16:58) || Coincidence trigger control, see [[#conf_coinc_control bits]]
|-
| 0x42 || reconfig_out || WO || 0x5bc13541 (12Oct18_16:58) || reserved for rebooting the FPGA (does not work)
|-
| 0x43 || conf_trigger_timeout || RW || 0x5bc8f90f (18Oct18_14:20) || Generate timeout trigger if there is no other trigger after given timeout, in 8 ns clocks, must be enabled by bit conf_enable_timeout_trig in [[#conf_trig_enable bits]]
|-
| 0x44 || eth_clk_counter || ROL || 0x618b790b ||
|-
| 0x45 || eth_clk_eth_counter || ROL || 0x618b790b ||
|-
| 0x100 || ts_625 || ROL || || latched timestamp
|-
| 0x101 || counter_trig_out || ROL || || counter of issued triggers
|-
| 0x102 || counter_trig_in || ROL || || counter of triggers
|-
| 0x103 || counter_pulser || ROL || || counter of pulser
|-
| 0x104 || counter_adc16_grand_or || ROL ||
|-
| 0x105 || counter_adc32_grand_or || ROL ||
|-
| 0x106 || counter_adc_grand_or || ROL ||
|-
| 0x107 || counter_esata_nim_grand_or || ROL ||
|-
| 0x108 || counter_adc16_mult_1ormore || ROL ||
|-
| 0x109 || counter_adc16_mult_2ormore || ROL ||
|-
| 0x10A || counter_adc16_mult_3ormore || ROL ||
|-
| 0x10B || counter_adc16_mult_4ormore || ROL ||
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x5bc8f90f || counter of AW coincidence triggers
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x62c77f0b || removed
|-
| 0x10D || counter_aw16_coinc_b || ROL || 0x5bc8f90f ||
|-
| 0x10E || counter_aw16_coinc_c || ROL || 0x5bc8f90f ||
|-
| 0x10F || counter_aw16_coinc_d || ROL || 0x5bc8f90f ||
|-
| 0x110 || counter_drift || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the drift time blank-out
|-
| 0x111 || counter_scaledown || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the scaledown
|-
| 0x112 || counter_aw16_coinc || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW coincidence triggers
|-
| 0x113 || counter_aw16_mlu || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW MLU triggers
|-
| 0x114 || counter_aw16_grand_or || ROL || 0x62c77f0b || counter of AW grand-or triggers
|-
| 0x114 || counter_aw16_mult_1ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 1ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 2ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x62c77f0b || removed
|-
| 0x116 || counter_aw16_mult_3ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 3ormore triggers
|-
| 0x117 || counter_aw16_mult_4ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 4ormore triggers
|-
| 0x118 || counter_bsc_grand_or || ROL || 0x5bc13541 (12Oct18_16:58) || counter of BSC grand-or triggers
|-
| 0x119 || counter_bsc_mult || ROL || 0x5bc13541 (12Oct18_16:58) || counter of old BSC multiplicity triggers
|-
| 0x11A || counter_coinc || ROL || 0x5bc13541 (12Oct18_16:58) || counter of coincidence triggers
|-
| 0x11B || counter_timeout || ROL || 0x618b790b || counter of timeout triggers
|-
| 0x11C || counter_bsc_mult_start || ROL || 0x62c77f0b || counter of BSC multiplicity windows
|-
| 0x11D || counter_bsc_mult_trig || ROL || 0x62c77f0b || counter of BSC multiplicity triggers
|-
| 0x11E || counter_coinc_start || ROL || 0x62d1b152 || counter of coincidence windows
|-
| 0x11F || counter_aw16_mlu_start || ROL || 0x62d1b152 || counter of TPC AW MLU windows
|-
| 0x200..0x207 || conf_adc16_masks || RW || all || adc16 enable bits
|-
| 0x300..0x30F || conf_adc32_masks || RW || all || adc32 enable bits
|-
| 0x400..0x41F || sas_bits[15:0][63:0] || ROL || all || sas data bits for each link
|-
| 0x420..0x42F || sas_sd_counters[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect counter for each link
|-
| 0x430..0x43F || counters_adc16_or16[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 16 counters of adc16 ORes
|-
| 0x440..0x45F || counters_adc32_or16[31:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 32 counters of adc32 ORes
|-
| 0x460..0x46F || counters_adc_selected[15:0] || ROL || 0x5bb7f6ae (05Oct18_16:41) || 16 counters for selected group of adcs, see conf_counter_adc_select
|-
| 0x470..0x4AF || counters_bsc64[63:0] || ROL || 0x5bc13541 (12Oct18_16:58) || 64 counters for the BSC bars
|-
|}

== additional registers ==

<pre>
reg | rw/ro | quartus name | firmware | description
0x60: param_out <= {2'h3, par_id, chan, cb_control_out
0x61: param_out <= {2'h3, par_id, chan, cb_status
0x62: param_out <= {2'h3, par_id, chan, cb_invert_a_out };
0x63: param_out <= {2'h3, par_id, chan, cb_invert_b_out };
0x64: param_out <= {2'h3, par_id, chan, cb_enable_le_a_out };
0x65: param_out <= {2'h3, par_id, chan, cb_enable_le_b_out };
0x66: param_out <= {2'h3, par_id, chan, cb_enable_te_a_out };
0x67: param_out <= {2'h3, par_id, chan, cb_enable_te_b_out };
0x6A | ro | cb_input_num | 0x618b790b | chronobox number of inputs
0x6B: param_out <= {2'h3, par_id, chan, cb_sync_mask_a_out };
0x6C: param_out <= {2'h3, par_id, chan, cb_sync_mask_b_out };
0x6D: param_out <= {2'h3, par_id, chan, cb_sync_reg_out };
0x6E: param_out <= {2'h3, par_id, chan, cb_sync_status };
0x6F: param_out <= {2'h3, par_id, chan, cb_latch_period_out };
0x70: param_out <= {2'h3, par_id, chan, cb_fifo_status };
0x71: begin param_out <= {2'h3, par_id, chan, cb_fifo_data }; cb_fifo_rdack_out <= 1; end
0x72: param_out <= {2'h3, par_id, chan, cb_udp_period_out };
0x73: param_out <= {2'h3, par_id, chan, cb_udp_threshold_out };
</pre>

== conf_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_clock_select || 0x5b3aa19f (02Jul18_15:05) || select 0=internal 62.5 MHz clock or 1=esata 62.5 MHz clock
|-
| 1 || conf_enable_aw_adc16 || 0x5baedfca (28Sep18_19:13) || select source of TPC AW aw16 bus, see [[#aw16 bus]]
|-
| 2 || conf_enable_aw_adc32a || 0x5baedfca (28Sep18_19:13) ||
|-
| 3 || conf_enable_aw_adc32b || 0x5baedfca (28Sep18_19:13) ||
|-
| 15..4 || || ||
|-
| 23..16 || conf_mlu_prompt || 0x5b3aa19f (02Jul18_15:05) || MLU trigger prompt window, see [[#aw16_mlu]]
|-
| 31..24 || conf_mlu_wait || 0x5b3aa19f (02Jul18_15:05) || MLU trigger wait window, see [[#aw16_mlu]]
|-
|}

== conf_mlu bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 31 || mlu_reset || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 30 || mlu_write || 0x5b3aa19f (02Jul18_15:05) || 1=write data bit into given address
|-
| 16 || mlu_data || 0x5b3aa19f (02Jul18_15:05) || data bit for writing to MLU RAM
|-
| 15..0 || mlu_write_addr || 0x5b3aa19f (02Jul18_15:05) || MLU RAM write address for writing the data bit
|-
|}

== conf_bsc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_bsc_adc_a || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 0..7
|-
| 1 || conf_bsc_adc_b || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 8..15
|-
| 2 || conf_bsc64_bot_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses bottom channels only
|-
| 3 || conf_bsc64_top_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses top channels only
|-
| 4 || conf_bsc64_bot_top_or || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "or" of top and bottom
|-
| 5 || conf_bsc64_bot_top_and || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "and" of top and bottom
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_bsc64_mult_min || 0x5bc13541 (12Oct18_16:58) || minimum bsc64 multiplicity
|-
| 23..16 || conf_bsc64_mult_max || 0x62c77f0b || maximum bsc64 multiplicity
|-
| 31..24 || conf_bsc64_mult_window || 0x62c77f0b || bsc64 multiplicity window length, 8 ns clocks
|-
|}

== conf_coinc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_coinc_required[0] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mult_1ormore
|-
| 0 || conf_coinc_required[0] || 0x62c77f0b || enable aw16_grand_or
|-
| 1 || conf_coinc_required[1] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mlu_trig
|-
| 2 || conf_coinc_required[2] || 0x5bc13541 (12Oct18_16:58) || enable bsc_grand_or_trig
|-
| 3 || conf_coinc_required[3] || 0x5bc13541 (12Oct18_16:58) || enable bsc_mult_trig
|-
| 3 || conf_coinc_required[3] || 0x62c77f0b || enable bsc64_mult_trig
|-
| 4 || conf_coinc_required[4] || 0x5bc13541 (12Oct18_16:58) || enable esata_nim_grand_or
|-
| 5 ||
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_coinc_window[7:0] || 0x5bc13541 (12Oct18_16:58) || coincidence window length in units of 125MHz clock (8 ns)
|-
| 23..16 || conf_coinc_start[7:0] || 0x5bc13541 (12Oct18_16:58) || start the coincidence window, same bits as "required"
|-
| 31..24 ||
|-
|}

== conf_trig_enable bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_enable_sw_trigger || || trigger on software trigger (how generated???)
|-
| 1 || conf_enable_pulser || || trigger on pulser
|-
| 2 || - || 0x5b120c9f (01Jun18_20:18) || not used
|-
| 3 || conf_pulser_run || || allow the pulser to run (frequency has to be set beforehand)
|-
| 4 || conf_output_pulser || 0x5bc8f90f || does nothing (top level ag_pulser_out is disconnected)
|-
| 4 || || 0x618b790b || not used
|-
| 5 || conf_enable_esata_nim || || trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand)
|-
| 6 || conf_enable_adc16 || || trigger on adc16_grand_or
|-
| 7 || conf_enable_adc32 || || trigger on adc32_grand_or
|-
| 8 || conf_enable_adc16_1ormore || || trigger on adc16_mult_1ormore "1 or more"
|-
| 9 || conf_enable_adc16_2ormore || || same, "2 or more"
|-
| 10 || conf_enable_adc16_3ormore || || same, "3 or more"
|-
| 11 || conf_enable_adc16_4ormore || || same, "4 or more"
|-
| 12 || - || 0x5b08938c (25May18_15:51) || not used
|-
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
|-
| 14 || - || 0x5bc8f90f || not used
|-
| 15 || conf_enable_adc || 0x5b120c9f (01Jun18_20:18) || trigger on adc_grand_or
|-
| 16 || conf_enable_aw16_coinc_a || 0x5bc8f90f || enable AW coincidence trigger, see [[#aw16_coinc]]
|-
| 16 || - || 0x62c77f0b || aw16_coinc_x removed
|-
| 17 || conf_enable_aw16_coinc_b || 0x5bc8f90f ||
|-
| 18 || conf_enable_aw16_coinc_c || 0x5bc8f90f ||
|-
| 19 || conf_enable_aw16_coinc_d || 0x5bc8f90f ||
|-
| 20 || - || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 20 || conf_enable_aw16_grand_or || 0x618b790b || enable trigger on aw16_grand_or
|-
| 21 || conf_enable_aw16_coinc || 0x5b3aa19f (02Jul18_15:05) || enable trigger on aw16_coinc_trig
|-
| 22 || conf_enable_aw16_mlu || 0x5b3aa19f (02Jul18_15:05) || enable AW MLU trigger
|-
| 23 || conf_enable_timeout_trig || 0x5bc8f90f (18Oct18_14:20) || enable trigger timeout trigger
|-
| 24 || conf_enable_aw16_1ormore || 0x5b3aa19f (02Jul18_15:05) || trigger on aw16_mult_1ormore "1 or more"
|-
| 24 || - || 0x62c77f0b || aw16_mult_xxx removed
|-
| 25 || conf_enable_aw16_2ormore || 0x5b3aa19f (02Jul18_15:05) || same, "2 or more"
|-
| 26 || conf_enable_aw16_3ormore || 0x5b3aa19f (02Jul18_15:05) || same, "3 or more"
|-
| 27 || conf_enable_aw16_4ormore || 0x5b3aa19f (02Jul18_15:05) || same, "4 or more"
|-
| 28 || conf_enable_bsc_grand_or || 0x5bc13541 (12Oct18_16:58) || trigger on BSC grand-or
|-
| 29 || conf_enable_bsc_mult || 0x5bc13541 (12Oct18_16:58) || trigger on BSC multiplicity
|-
| 30 || conf_enable_coinc || 0x5bc13541 (12Oct18_16:58) || trigger on TPC/BSC/ext coincidence trigger
|-
| 31 || - || || not used
|-
|}

== reg 0x2B bits ==

Write to this register will pulse corresponding fpga signals:

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || reset_out || 0x5b120c9f (01Jun18_20:18) || reset counters, etc
|-
| 1 || latch_out || 0x5b120c9f (01Jun18_20:18) || latch counters, sas bits, etc
|-
| 2 || trigger_out || 0x5b120c9f (01Jun18_20:18) || generate a software trigger
|-
|}

= UDP data format =

== firmware 0x5bc8f90f ==

{| cellpadding="10" cellspacing="0" border="1"
! Offset || Name || Quartus name || FwRev || Description
|-
| 0 || packet counter || none || all || 31-bit UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
|-
| 1 || 0x8 packet header || || all || 28 bits of counter_trig_out
|-
| 2 || trigger timestamp || trig_ts || all || 62.5MHz trigger timestamp
|-
| 3 || accepted triggers || counter_trig_out || all || counter of accepted triggers
|-
| 4 || input triggers || counter_trig_in || all || counter of trigger input
|-
| 5 || pulser triggers || counter_pulser || all || counter of pulser triggers
|-
| 6 || trigger bitmap || udp_trig_bits || 0x5a48448d (30Dec17_17:59) || bitmap of trigger information, see below
|-
| 7 || nim bits || udp_nim_bits_masked || ??? || 32 bits of ADC NIM inputs (2 bits per ADC)
|-
| 8 || esata bits || udp_esata_bits_masked || ??? || 32 bits of ADC ESATA inputs (2 bits per ADC)
|-
| 9 || mlu bits || aw16_prompt || 0x5b398983 (01Jul18_19:10) || 16 bits of MLU input, 1 bit per preamp
|-
| 10 || drift-blank-off counter || udp_drift_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the drift blank-off
|-
| 11 || scaledown counter || udp_scaledown_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the scaledown
|-
| X || || || ||
|-
| 12 || 0xE packet footer || || all || 28 bits of counter_trig_out
|-
|}

== firmware 0x618b790b (Nov 2021) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

== trigger bitmap ==

Firmware ??? (one of the very early revisions)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= adc16_coinc_top;
udp_trig_bits[5] <= adc16_coinc_bot;
udp_trig_bits[6] <= adc16_coinc;
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
udp_trig_bits[31:24] <= mult16[7:0];

</pre>

Firmware 0x5b08938c (25May18_15:51)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= 0; // not used
udp_trig_bits[31:24] <= mult16[7:0];
</pre>

Firmware 0x5b217dc4 (13Jun18_13:25)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5b3aa19f (02Jul18_15:05)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= udp_mlu_out;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5bc8f90f (18Oct18_14:20)

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_run_pulser
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = 0; // not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x618b790b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x62c77f0b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = 0; // aw16_coinc_a;
assign trig32_in[17] = 0; // aw16_coinc_b;
assign trig32_in[18] = 0; // aw16_coinc_c;
assign trig32_in[19] = 0; // aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = 0; // aw16_mult_1ormore;
assign trig32_in[25] = 0; // aw16_mult_2ormore;
assign trig32_in[26] = 0; // aw16_mult_3ormore;
assign trig32_in[27] = 0; // aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc64_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

= TRG chronobox inputs =

from trg_firmware/toplevel/grifc.v

<pre>
localparam CB_N = 23;
localparam CB_N1 = CB_N-1;

wire [CB_N1:0] cb_xinputs_async;

assign cb_xinputs_async[0] = ag_trig_out;
assign cb_xinputs_async[1] = ag_trig_scaledown_out;
assign cb_xinputs_async[2] = ag_trig_drift_out;
assign cb_xinputs_async[3] = ag_trig_received_out;

assign cb_xinputs_async[4] = ag_cb_sw_trig;
assign cb_xinputs_async[5] = ag_cb_pulser_trig;
assign cb_xinputs_async[6] = ag_cb_esata_nim_trig;
assign cb_xinputs_async[7] = ag_cb_adc16_grand_or_trig;
assign cb_xinputs_async[8] = ag_cb_adc32_grand_or_trig;

assign cb_xinputs_async[9] = ag_cb_aw16_grand_or_trig;
assign cb_xinputs_async[10] = ag_cb_aw16_mult_1ormore;
assign cb_xinputs_async[11] = ag_cb_aw16_mult_2ormore;
assign cb_xinputs_async[12] = ag_cb_aw16_mult_3ormore;
assign cb_xinputs_async[13] = ag_cb_aw16_mult_4ormore;
assign cb_xinputs_async[14] = ag_cb_aw16_mlu_trig;

assign cb_xinputs_async[15] = ag_cb_bsc64_grand_or_trig;
assign cb_xinputs_async[16] = ag_cb_bsc64_mult_1ormore;
assign cb_xinputs_async[17] = ag_cb_bsc64_mult_2ormore;
assign cb_xinputs_async[18] = ag_cb_bsc64_mult_3ormore;
assign cb_xinputs_async[19] = ag_cb_bsc64_mult_4ormore;
assign cb_xinputs_async[20] = ag_cb_bsc64_mult_trig;

assign cb_xinputs_async[21] = ag_cb_coinc_trig;

assign cb_xinputs_async[22] = ag_cb_timeout_trig;
</pre>

= Example UDP packets =

* trigger data, marker words 0x8

<pre>
ReadDataThread read 76
0: 0x003666ed -- UDP packet counter from UDP transmitter
1: 0x80000bf8 -- 0x8 is trigger data packet, 0xbf8 is the trigger counter from alphag.v
2: 0x2edf8b41 -- trigger data
3: 0x00000bf8
4: 0x00000bf8
5: 0x00000bee
6: 0x00000001
7: 0x00000000
8: 0x00000000
9: 0x00000003
10: 0x00000bf8
11: 0x00000bf8
12: 0x00000000
13: 0x00000000
14: 0x00000000
15: 0x00000000
16: 0x00000000
17: 0x00000000
18: 0xe0000bf8 -- 0xE is end of trigger data, counter 0xbf8 must match the counter in the 0x8 word.
ReadDataThread read 76 -- next packet
0: 0x003666ee -- UDP packet counter from UDP transmitter
...
</pre>

* chronobox fifo data, marker word 0xC, see [[Chronobox#FIFO_data_format]]

<pre>
ReadDataThread read 404
0: 0x003658ed -- UDP packet counter from UDP transmitter
1: 0xc000eacc -- 0xC is FIFO data, fifo packet counter 0xeacc from fifo_to_udp.v
2: 0x00000061 -- FIFO status, low bits the the word counter, so up to 0x61 fifo words are to follow
3: 0x87fb3d72 -- tsc hits
4: 0x8ffb3d74
5: 0x90fb3d74
6: 0x91fb3d74
7: 0x92fb3d74
8: 0x93fb3d74
9: 0x93fb3d75
10: 0x94fb3d74
11: 0x94fb3d77
12: 0x87fb3d77
13: 0x8ffb3d77
14: 0x90fb3d77
15: 0x91fb3d77
16: 0x92fb3d77
17: 0xfe000018 -- 0xFE scaler data starts, 0x18 words to follow
18: 0x00000000
19: 0x00000000
20: 0x00000000
21: 0x00000000
22: 0x00000000
23: 0x00000000
24: 0x00000000
25: 0x00000108
26: 0x00000000
27: 0x00000000
28: 0x00000000
29: 0x00000000
30: 0x00000000
31: 0x00000000
32: 0x00000000
33: 0x00000108
34: 0x00000108
35: 0x00000108
36: 0x00000108
37: 0x00000108
38: 0x00000108
39: 0x00000000
40: 0x00000000
41: 0xce56fa93 -- last word of scaler data is the sysclock counter (125 MHz)
42: 0xff800048 -- timestamp wraparound
43: 0x8f1f36e4 -- tsc hits
44: 0x901f36e4
45: 0x911f36e4
46: 0x921f36e4
47: 0x931f36e4
48: 0x941f36e4
49: 0x871f36e4
50: 0x871f36e7
51: 0x8f1f36e7
52: 0x901f36e9
53: 0x911f36e7
54: 0x921f36e9
55: 0x931f36e7
56: 0x941f36e9
57: 0x904330ac
58: 0x914330ac
59: 0x924330ac
60: 0x934330ac
61: 0x934330ad
62: 0x944330ac
63: 0x944330ad
64: 0x874330ac
65: 0x874330ad
66: 0x8f4330ac
67: 0x8f4330ad
68: 0x904330ad
69: 0x914330ad
70: 0x924330ad
71: 0x8f672a62
72: 0x90672a62
73: 0x91672a62
74: 0x92672a62
75: 0x93672a62
76: 0x94672a62
77: 0x87672a62
78: 0x87672a65
79: 0x8f672a65
80: 0x90672a65
81: 0x91672a65
82: 0x92672a65
83: 0x93672a65
84: 0x94672a65
85: 0xff000049
86: 0x878b2422
87: 0x8f8b2424
88: 0x908b2424
89: 0x918b2424
90: 0x928b2424
91: 0x938b2424
92: 0x938b2425
93: 0x948b2424
94: 0x948b2427
95: 0x878b2427
96: 0x8f8b2427
97: 0x908b2427
98: 0x918b2427
99: 0x928b2427
100: 0xe000eacc -- 0xE is end of fifo data, counter 0xeacc must match the counter in the 0xC word.
ReadDataThread read 344 -- next packet
...
</pre>

= TODO =

* DONE July 2022. add FwRev to the UDP data output
* RJ45 SFP: PROBLEM, D.A. CABLE: GOOD, Fiber SFP: ???. fix "write did not happen" (send udp write command, there is no reply, read returns old data as if write never happened). suspect udp "write" packet is lost?
* PROBLEM GONE Aug 2021. fix reply to wrong socket - udp packets should reply to same socket as they came from, udp data packets should be sent to same socket as requested them, not same socket as last command.
* DONE 2021jul30. add fixes from Chris P. for the auto-negotiation and dhcp (see email from him).
* DONE flash chip connected to FPGA. Aug 2021. implement ethernet flash programmer
* DONE Aug 2021. updated maxv firmware. implement FPGA reboot
* speed up programming the MLU by writing more than 1 bit at a time
* DONE Nov 2021. add 64-bit bitmap of BSC trigger bits
* DONE. add chronobox code
* DONE. add avalon mux for alphag and chronobox packets
* DONE. add chronobox fifo to udp packet sequencer
* check that TxReadyOut is correct and it is safe to send an avalon packet while previous packet is still transmitting.
* DONE. test fiber SFP is working
* complete the UDP flash programmer (parallel flash erase and write)

= End =

//KO

TRG

2022-07-15T19:47:11Z

Olchansk: /* TODO */

= TRG, the trigger control board for the ALPHA-g detector =

= Links =

* xxx
* https://bitbucket.org/expalpha/trg_firmware - firmware sources on bitbucket

= General characteristics =

== Photos ==

== Board schematics ==

* https://bitbucket.org/expalpha/trg_firmware/src/master/3xFMC_VME_Motherboard.pdf

== Available hardware ==

* Altera Stratix IV - main FPGA
* Altera Max V - boot FPGA
* boot flash: PC28F512M29EW - 512 Mbit parallel NOR flash.

= TRG front panel connections =

From top to bottom:

<pre>
|
| minisas-C - links 8-11
| minisas-D - links 12-15
|
| ethernet sfp - use copper sfp only
| minisas - not used, do not connect
| esata - clock in, trigger out
|
| minisas-A - links 0-3
| minisas-B - links 4-7
|
| LEDs
|
</pre>

MiniSAS and SATA flail cable connections:

<pre>
P1 <--> link 3
P2 <--> link 2
P3 <--> link 1
P4 <--> link 0
</pre>

LEDs:

<pre>
--PCB-- (left)
LED[0] - trigger out - ag_trig_out
LED[1] - network packet received - sfp_rx_data_valid
LED[2] - Xilinx FPGA boot ok - FMC1_CFG_DONE
LED[3] - not used
(right)
</pre>

= TRG onboard jumpers and switches =

* rotary switches: select IP address: 00=192.168.1.50, 11=.51, 22=.52, 33=.53, 44=.54, otherwire=.251

= Firmware update procedure =

* use quartus to generate the grifc.pof file (use grifc.cof)
* open quartus programmer
* attach grifc.pof to the 1st CFI_512 flash
* mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
* check that "initiate configuration after programming" is set in tools->options
* say "start"
* should take about 5 minutes
* grifc should reboot into the new firmware

If CFI_512 flash is not visible to the quartus programmer, load correct
code into the MaxV CPLD:

* open quartus programmer,
* say "auto detect"
* change file for the 5M2210 device
* use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
* say "program", it should finish in 10-15 seconds
* say "auto detect"
* CFI_512 flash should be visible now.

= Firmware revisions =

* 0x5bc8f90f - original firmware used for all data
* 0x6147c0f9 - added cbtrg, etc. installed at CERN on 20 Sep 2021.
* 0x618376ae - bigger cbtrg fifo, data rate tested up to 30 Mbytes/sec
* 0x6189c7f3 - fix loss of trigger packets. (missing fifo between alphag block and ethernet mux)
* 0x618b790b - fix loss of timestamps. (cbtrg inputs stretched to 100 ns long). installed at CERN 10 Nov 2021.

= Firmware build =

* use quartus 20.1
* see Makefile in the trg_firmware project

= Jtag remote connection =

* ssh agmini@daq16
* /opt/intelFPGA/16.1/quartus/bin/jtagd --config /home/agmini/.jtagd.conf
* netstat -an | grep 1309 ### note listen address is "0.0.0.0", NOT "127.0.0.1"
<pre>
tcp 0 0 0.0.0.0:1309 0.0.0.0:* LISTEN
</pre>
* opt/intelFPGA/16.1/quartus/bin/jtagconfig ### should work
* ssh olchansk@daq01
* cd git/trg_firmware
* /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
* jtagconfig ### should work
<pre>
daq01:trg_firmware$ jtagconfig
1) DE-SoC on daq16 [2-1.2.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) USB-Blaster on daq16 [2-1.3]
024090DD EP4SGX230(.|ES)
020A40DD 5M(1270ZF324|2210Z)/EPM2210

daq01:trg_firmware$
</pre>

= ALPHA-g trigger functions =

Trigger options:
* software trigger
* pulser trigger
* trigger on GRIF16 ADC NIM and ESATA inputs ("external trigger")
* adc16 grand-or
* adc32 grand-or
* adc16 wire multiplicity
* TPC anode wire per-preamp trigger (aw16 section)
** trigger on coincidences of preamps (removed fw 0x62c77f0b)
** trigger on multiplicity of preamps (removed fw 0x62c77f0b)
** trigger on specific topology of preamps (multiplicity of preamp clusters, etc) via the aw16_mlu trigger
* BSC trigger
** BSC grand_or
** BSC bar multiplicity
* coincidence trigger - select coincidence of external trigger, TPC AW grand-or, TPC AW MLU, BSC grand-or and BSC bar multiplicity triggers

== software trigger ==

to programmatically fire the trigger, one should:
* set the conf_enable_sw_trigger bit in conf_trig_enable, this will permit the software trigger to fire the trigger
* write value 0x4 to register 0x2B, this will cause the software trigger to fire

== pulser trigger ==

To use the pulser trigger, one should program:
* pulser period (in clocks)
* pulser width (in clocks, use value 5, the pulser no longer goes outside of the trigger board, so changing the width does not do anything)
* set the run_pulser bit in conf_trig_enable, this will cause the pulser to run
* set the enable_pulser bit in conf_trig_enable, this will cause the pulser to fire the trigger
* set the output_pulser bit in conf_trig_enable, this will cause the pulser to be output from the alphag firmware block (the pulser no longer goes outside of the trigger board, so changing the bit does not do anything)

== timeout trigger ==

The event builder uses event timestamps to assemble physics events. The timestamps
are usually 32 bit wide and run at 125 MHz (8 ns) or 62.5 MHz (16 ns). If
triggers are generated often (1 per second or more), timestamp wrap around
is easily detected by the event builder. If triggers come infrequently,
timestamp wrap around may occur while there are no triggers, not be seen
by the event builder causing loss of event synchronization.

To avoid this problem in the event builder, a timeout trigger should be generated
if no triggers were generated inside a 10 second interval.

The guaranties that even if all physics triggers temporarily stop for any reason,
the event builder will stay synchronized. (0.1 Hz timeout trigger frequency).

To enable the timeout trigger:
* program timeout trigger timeout in reg 0x43 in units of 8 ns clock
* enable it in bit 23 of [[#conf_trig_enable bits]]

== adc16 multiplicity trigger ==

This trigger is intended for use with the barrel scintillator signals connected to adc16 digitizers. It does not work well with TPC AW signals.

The 16 adc16 trigger bits (16x16=256) are added together to form the hit multiplicity value (adc16_mult, 16 bits, actual range 0 to 256).

Four threshold signals are computed: adc16_mult_1ormore = adc16_mult>=1, 2ormore, 3ormore, 4ormore.

There is a counter for each of these four signals.

Each of these four signals can fire the trigger, see [[#conf_trig_enable bits]].

== TPC anode wire triggers ==

=== aw16 bus ===

TPC Anode Wire trigger is based on the aw16[15:0] (xaw16) bus.

Each bit corresponds to one AW preamp. 16 preamps, 16 bits.

The aw16[15:0] bus can be fed by
* adc16_or16[15:0] - or16 of 100 MHz ADCs, 16 ADC sas links
* adc32_or16[15:0] - or16 of 62.5 MHz ADCs, FMC-ADC32 has 32 channels, so 2 bits per ADC: low 16 channels and high 16 channels, sas links 7..0
* adc32_or16[31:16] - or16 of 62.5 MHz ADCs, ditto, sas links 15..8
as selected by conf_enable_aw_adc16, conf_enable_aw_adc32a, conf_enable_aw_adc32b in [[#conf_control bits]]

<pre>
///////////////////////////////////////////////////////////
// TPC Anode Wire trigger logic (aw16)
///////////////////////////////////////////////////////////

// map adc signals into aw16

wire [15:0] aw16 = ({16{conf_enable_aw_adc16}} & adc16_or16[15:0]) |
({16{conf_enable_aw_adc32a}} & adc32_or16[15:0]) |
({16{conf_enable_aw_adc32b}} & adc32_or16[31:16]);
...
ag_conditioner cond_adc16_or16_0(.clk(clk), .in(aw16[0]), .out(xxaw16[0]));
...
xaw16 <= xxaw16;
</pre>

=== aw16_grand_or ===

TPC AW "grand or" trigger: use aw16_mult_1ormore (before fw 0x62c77f0b)

(256 anode wires, 16 wires per preamp, 16 preamps, 16 aw16 signals)

=== aw16_mlu ===

TPC AW preamp MLU trigger: the MLU (memory lookup
table) implements an arbitrary logical function
to map the 16 aw16 preamp signals into 1 aw16_mlu_trig trigger output.

Description of the aw16 mlu trigger.

In words:

* any aw16 signal starts the aw16_prompt_run gate
* aw16 signals are collected for the duration of conf_mlu_prompt (125MHz/8ns clock)
* this corresponds to time spread of TPC AW signals due to the drift time in the AW drift cell and to the variation in signal transmission time from the ADC to the TRG (digital trigger data link).
* when this prompt time expires, the MLU looks at the accumulated aw16_prompt bit pattern and makes the "yes/no" trigger decision
* after the trigger decision is made, we wait for the TPC to become quiet:
* we wait until all aw16 signals are empty (no timeout)
* we run the aw16_prompt_wait gate, length conf_mlu_wait (8ns clock), if any aw16 signals arrive, we wait for aw16 empty again, rinse, repeat.
* now, after TPC aw16 have been empty for conf_mlu_wait clocks (8ns clock), MLU trigger is ready for the next event.

In logic: (see alphag.v)

* aw16_or <= grand-or of 16 aw16 signals
* "aw16_or" starts the "aw16_prompt_cnt" counter, opens the aw16_prompt_run gate
* during the aw16_prompt_run gate, aw16_prompt collects (latches) the aw16 bits (aw16_prompt <= aw16_prompt | aw16)
* this is the time when we wait for all "prompt" signals from the TPC to arrive into the trigger
* at the end of the aw16_prompt_run gate, the signal aw16_prompt_out is pulsed, latching the output of the MLU into aw16_mlu_trig
* this is the MLU trigger "yes/no" trigger decision.
* after the MLU trigger decision is made, we wait for the arrival and passing of all TPC drift signals
* the aw16_prompt_wait_cnt and aw_prompt_wait gate opens
* if any new aw16 signals arrive (they are TPC drift signals at this time), the aw16_prompt_wait gate is restarted
* if no aw16 signals arrive during the full run of the aw16_prompt_wait gate ("TPC quiet time")
* the aw16_prompt_wait and aw16_prompt gates are cleared and the MLU trigger is ready for the next event.

Good settings are:
* conf_mlu_prompt: 64 (512 ns)
* conf_mlu_wait: 128 (1024 ns)

== BSC trigger ==

=== bsc_adc16 bus ===

The BSC trigger is based on the [15:0]bsc_adc16[7:0] bus: 16 trigger discriminator bits from 8 ADC sas links. (8*16 = 64+64 bars, top and bottom).

The bsc_adc16 bus can be fed from sas links 0..7 or 8..15, controlled by conf_bsc_adc16_a and conf_bsc_adc16_b bits on [[#conf_bsc_control bits]].

bsc_adc16 can be fed only from GRIF-16 100 MHz ADC trigger discriminators.

=== bsc64_top and bsc64_bot buses ===

* firmware 0x5bc8f90f: bsc_adc16 is remapped into 64 bits of top (bsc64_top) and bottom (bsc64_bot):
<pre>
ag_bsc_remap bsc_remap_a(.adc(bsc_adc16[0]), .bsc_bot(bsc64_bot[7:0]), .bsc_top(bsc64_top[7:0]));
ag_bsc_remap bsc_remap_b(.adc(bsc_adc16[1]), .bsc_bot(bsc64_bot[8+7:8+0]), .bsc_top(bsc64_top[8+7:8+0]));
ag_bsc_remap bsc_remap_c(.adc(bsc_adc16[2]), .bsc_bot(bsc64_bot[2*8+7:2*8+0]), .bsc_top(bsc64_top[2*8+7:2*8+0]));
ag_bsc_remap bsc_remap_d(.adc(bsc_adc16[3]), .bsc_bot(bsc64_bot[3*8+7:3*8+0]), .bsc_top(bsc64_top[3*8+7:3*8+0]));

ag_bsc_remap bsc_remap_e(.adc(bsc_adc16[4]), .bsc_bot(bsc64_bot[4*8+7:4*8+0]), .bsc_top(bsc64_top[4*8+7:4*8+0]));
ag_bsc_remap bsc_remap_f(.adc(bsc_adc16[5]), .bsc_bot(bsc64_bot[5*8+7:5*8+0]), .bsc_top(bsc64_top[5*8+7:5*8+0]));
ag_bsc_remap bsc_remap_g(.adc(bsc_adc16[6]), .bsc_bot(bsc64_bot[6*8+7:6*8+0]), .bsc_top(bsc64_top[6*8+7:6*8+0]));
ag_bsc_remap bsc_remap_h(.adc(bsc_adc16[7]), .bsc_bot(bsc64_bot[7*8+7:7*8+0]), .bsc_top(bsc64_top[7*8+7:7*8+0]));

module ag_bsc_remap
(
input wire [15:0] adc,
output wire [7:0] bsc_bot,
output wire [7:0] bsc_top
);

assign bsc_top[3] = adc[0];
assign bsc_top[2] = adc[1];
assign bsc_top[1] = adc[2];
assign bsc_top[0] = adc[3];

assign bsc_top[7] = adc[4];
assign bsc_top[6] = adc[5];
assign bsc_top[5] = adc[6];
assign bsc_top[4] = adc[7];

assign bsc_bot[0] = adc[8];
assign bsc_bot[1] = adc[9];
assign bsc_bot[2] = adc[10];
assign bsc_bot[3] = adc[11];

assign bsc_bot[4] = adc[12];
assign bsc_bot[5] = adc[13];
assign bsc_bot[6] = adc[14];
assign bsc_bot[7] = adc[15];

endmodule
</pre>

=== bsc64 bus ===

the bsc64 bus is the 64 bars used by the trigger, formed from bsc64_top and bsc64_bot:
<pre>
if (conf_bsc64_bot_only) begin
bsc64 <= bsc64_bot;
end else if (conf_bsc64_top_only) begin
bsc64 <= bsc64_top;
end else if (conf_bsc64_bot_top_or) begin
bsc64 <= bsc64_bot | bsc64_top;
end else if (conf_bsc64_bot_top_and) begin
bsc64 <= bsc64_bot & bsc64_top;
end else begin
bsc64 <= 64'b0;
end
</pre>

=== bsc_grand_or_trig ===

bsc_grand_or_trig is the grand-or of 64 bits of the bsc64 bus

to enable triggering on bsc_grand_or_trig, set corresponding bit in [[#conf_trig_enable bits]]

=== old bsc_mult_trig ===

(from fw 0x62c77f0b, old bsc_mult_trig was replaced by new bsc64 multiplicity trigger)

* bsc64_mult is computed as multiplicity of the bsc64 bus (number of 64 bsc64 bits that fired)
* bsc_mult_trig is computed:
<pre>
if (bsc64_mult >= conf_bsc64_mult) begin
bsc_mult_trig <= 1;
end else begin
bsc_mult_trig <= 0;
end
</pre>

to enable the bsc multiplicity trigger, set the multiplicity value conf_bsc64_mult in [[#conf_bsc_control bits]] and enable the corresponding bit in [[#conf_trig_enable bits]].

=== bsc64 multiplicity trigger ===

bsc64 BSC bar multiplicity trigger uses a time window. this time window is started by bsc64_grand_or and runs for conf_bsc64_mult_window clocks (8 nc clock). During this time, hits in bsc64_bus are accumulated (latched) and their multiplicity is computed. If multiplicity condition is satisfied (bigger or equal to conf_bsc64_mult_min), bsc64_mult_trig is fired and the bsc64 bit pattern is saved to the UDP packet. Then trigger waits for the bsc64_bus to be empty. Then trigger waits for conf_bsc64_empty_window clocks, if there is any bsc64 hits, we wait for empty again. So after bsc64 has been empty for conf_bsc64_empty_window clocks, multiplicity trigger is ready for the next event. This scheme cannot implement max multiplicity.

recommended values:
* conf_bsc64_mult_window (8 bits): slightly longer than 3 cycles of SAS link: 3*18 = 54 clocks, good value is 80 (640 ns).
* conf_bsc64_mult_min (8 bits): 2
* conf_bsc64_empty_window (8 bits): 80 (640 ns)

== Coincidence trigger ==

Coincidence trigger provides a combination of TPC, BSC and external scintillator (esata_nim_grand_or) signals:

<pre>
assign coinc_input[0] = aw16_grand_or; // was aw16_mult_1ormore;
assign coinc_input[1] = aw16_mlu_trig;
assign coinc_input[2] = bsc_grand_or_trig;
assign coinc_input[3] = bsc_mult_trig;
assign coinc_input[4] = esata_nim_grand_or;
assign coinc_input[5] = 0;
assign coinc_input[6] = 0;
assign coinc_input[7] = 0;
</pre>

Coincidence trigger "start" mask selects which of the inputs can start the coincidence window.

Coincidence trigger "require" mask selects which inputs must have a hits for the coincidence ot be satisfied.

Input hits are collected for the duration of the coincidence window, if all required inputs have hits, coinc_trig is fired.

Example settings:

* coincidence of external scintillator, BSC and TPC AW "grand or" signals: start 0x10, required 0x15
* coincidence of BSC and TPC AW "grand or" signals: start 0x4, required 0x5
* coincidence of BSC and TPC AW MLU triggers: start 0x4, required 0x6
* coincidence of BSC multiplicity and TPC AW MLU triggers: start 0x8, required 0xA

= Control registers =

== Register addresses ==

Note: all registers are 32 bits unless otherwise noted.

Note: RW means read-write register, RO means read-only, ROL means read-only, contents is latched by the "latch_out" bit

{| cellpadding="10" cellspacing="0" border="1"
! Address || Quartus Name || Access || FwRev || Description
|-
| 0x08 || num_sample || RW || GRIF-C || magic 16-bit register to control UDP packet size
|-
| 0x08 || scratch_reg || RW || 0x618b790b || 32-bit scratch register
|-
| 0x1F || compilation_time || RO || || Firmware revision
|-
| 0x20 || conf_trig_width || RW || || Trigger signal width, 16 ns clock
|-
| 0x21 || conf_busy_width || RW || || Busy signal width, 16 ns clock (not used)
|-
| 0x22 || conf_pulser_width || RW || || Pulser signal width, 16 ns clock
|-
| 0x23 || conf_pulser_period || RW || || Pulser signal period, 16 ns clock
|-
| 0x24 || || || || not used
|-
| 0x25 || conf_trig_enable || RW || || see [[#conf_trig_enable bits]]
|-
| 0x26 || || || not used
|-
| 0x27 || || || not used
|-
| 0x28 || || || not used
|-
| 0x29 || conf_nim_mask || RW || || enable bits for ADC NIM inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2A || conf_esata_mask || RW || || enable bits for ADC eSATA inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2B || reset_out, latch_out, trigger_out || W || || see [[#reg 0x2B bits]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x5bc8f90f || configure AW coincidence trigger, see [[#aw16_coinc]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x62c77f0b || removed
|-
| 0x2D || conf_aw16_coinc_b || RW || 0x5bc8f90f ||
|-
| 0x2E || conf_aw16_coinc_c || RW || 0x5bc8f90f ||
|-
| 0x2F || conf_aw16_coinc_d || RW || 0x5bc8f90f ||
|-
| 0x30 || sas_sd[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect for each link
|-
| 0x31 || pll_625_status || ROL || 0x5b2057f5 (12Jun18_16:32) || 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter
|-
| 0x32 || clk_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the system 125 MHz clock
|-
| 0x33 || clk_625_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625)
|-
| 0x34 || conf_control || RW || 0x5b398983 (01Jul18_19:10) || see [[#conf_control bits]] below
|-
| 0x35 || conf_drift_width || RW || 0x5b398983 (01Jul18_19:10) || width of drift time blank-out in 16 ns clocks
|-
| 0x36 || conf_scaledown || RW || 0x5b398983 (01Jul18_19:10) || trigger scaledown, 0=no scaledown, 1=divide-by-2, 2=divide-by-3, etc
|-
| 0x37 || conf_mlu || RW || 0x5b398983 (01Jul18_19:10) || AW MLU control bits, see [[#conf_mlu bits]]
|-
| 0x38 || conf_trig_delay || RW || 0x5baedfca (28Sep18_19:13) || delay the trigger pulse, 16 ns clock
|-
| 0x39 || esata_clk_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the TRG 125 MHz clock
|-
| 0x3A || esata_clk_esata_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the external clock (eSATA 62.5 MHz clock)
|-
| 0x3B || conf_counter_adc_select || RW || 0x5bb7f6ae (05Oct18_16:41) || select which 16 ADCs are connected to the selected adc counters, 0..15 - connect the adc16 signals, 16..47 connect the adc32 signals
|-
| 0x3C || sysreset_ts || RO || 0x5bb7f6ae (05Oct18_16:41) || 125MHz counter of VME-SYSRESET
|-
| 0x3C || || || 0x618b790b || not used
|-
| 0x3D || GRIF-C csr || RW || GRIF-C || <= csr & ~par_value; // Selective clear
|-
| 0x3E || GRIF-C csr || RW || GRIF-C || <= csr | par_value; // Selective set
|-
| 0x3F || GRIF-C csr || RW || GRIF-C || <= par_value; // write
|-
| 0x3D || || || 0x618b790b || not used
|-
| 0x3E || || || 0x618b790b || not used
|-
| 0x3F || || || 0x618b790b || not used
|-
| 0x40 || conf_bsc_control || RW || 0x5bc13541 (12Oct18_16:58) || Barrel Scintillator trigger control, see [[#conf_bsc_control bits]]
|-
| 0x41 || conf_coinc_control || RW || 0x5bc13541 (12Oct18_16:58) || Coincidence trigger control, see [[#conf_coinc_control bits]]
|-
| 0x42 || reconfig_out || WO || 0x5bc13541 (12Oct18_16:58) || reserved for rebooting the FPGA (does not work)
|-
| 0x43 || conf_trigger_timeout || RW || 0x5bc8f90f (18Oct18_14:20) || Generate timeout trigger if there is no other trigger after given timeout, in 8 ns clocks, must be enabled by bit conf_enable_timeout_trig in [[#conf_trig_enable bits]]
|-
| 0x44 || eth_clk_counter || ROL || 0x618b790b ||
|-
| 0x45 || eth_clk_eth_counter || ROL || 0x618b790b ||
|-
| 0x100 || ts_625 || ROL || || latched timestamp
|-
| 0x101 || counter_trig_out || ROL || || counter of issued triggers
|-
| 0x102 || counter_trig_in || ROL || || counter of triggers
|-
| 0x103 || counter_pulser || ROL || || counter of pulser
|-
| 0x104 || counter_adc16_grand_or || ROL ||
|-
| 0x105 || counter_adc32_grand_or || ROL ||
|-
| 0x106 || counter_adc_grand_or || ROL ||
|-
| 0x107 || counter_esata_nim_grand_or || ROL ||
|-
| 0x108 || counter_adc16_mult_1ormore || ROL ||
|-
| 0x109 || counter_adc16_mult_2ormore || ROL ||
|-
| 0x10A || counter_adc16_mult_3ormore || ROL ||
|-
| 0x10B || counter_adc16_mult_4ormore || ROL ||
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x5bc8f90f || counter of AW coincidence triggers
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x62c77f0b || removed
|-
| 0x10D || counter_aw16_coinc_b || ROL || 0x5bc8f90f ||
|-
| 0x10E || counter_aw16_coinc_c || ROL || 0x5bc8f90f ||
|-
| 0x10F || counter_aw16_coinc_d || ROL || 0x5bc8f90f ||
|-
| 0x110 || counter_drift || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the drift time blank-out
|-
| 0x111 || counter_scaledown || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the scaledown
|-
| 0x112 || counter_aw16_coinc || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW coincidence triggers
|-
| 0x113 || counter_aw16_mlu || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW MLU triggers
|-
| 0x114 || counter_aw16_grand_or || ROL || 0x62c77f0b || counter of AW grand-or triggers
|-
| 0x114 || counter_aw16_mult_1ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 1ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 2ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x62c77f0b || removed
|-
| 0x116 || counter_aw16_mult_3ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 3ormore triggers
|-
| 0x117 || counter_aw16_mult_4ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 4ormore triggers
|-
| 0x118 || counter_bsc_grand_or || ROL || 0x5bc13541 (12Oct18_16:58) || counter of BSC grand-or triggers
|-
| 0x119 || counter_bsc_mult || ROL || 0x5bc13541 (12Oct18_16:58) || counter of old BSC multiplicity triggers
|-
| 0x11A || counter_coinc || ROL || 0x5bc13541 (12Oct18_16:58) || counter of coincidence triggers
|-
| 0x11B || counter_timeout || ROL || 0x618b790b || counter of timeout triggers
|-
| 0x11C || counter_bsc_mult_start || ROL || 0x62c77f0b || counter of BSC multiplicity windows
|-
| 0x11D || counter_bsc_mult_trig || ROL || 0x62c77f0b || counter of BSC multiplicity triggers
|-
| 0x11E || counter_coinc_start || ROL || 0x62d1b152 || counter of coincidence windows
|-
| 0x11F || counter_aw16_mlu_start || ROL || 0x62d1b152 || counter of TPC AW MLU windows
|-
| 0x200..0x207 || conf_adc16_masks || RW || all || adc16 enable bits
|-
| 0x300..0x30F || conf_adc32_masks || RW || all || adc32 enable bits
|-
| 0x400..0x41F || sas_bits[15:0][63:0] || ROL || all || sas data bits for each link
|-
| 0x420..0x42F || sas_sd_counters[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect counter for each link
|-
| 0x430..0x43F || counters_adc16_or16[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 16 counters of adc16 ORes
|-
| 0x440..0x45F || counters_adc32_or16[31:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 32 counters of adc32 ORes
|-
| 0x460..0x46F || counters_adc_selected[15:0] || ROL || 0x5bb7f6ae (05Oct18_16:41) || 16 counters for selected group of adcs, see conf_counter_adc_select
|-
| 0x470..0x4AF || counters_bsc64[63:0] || ROL || 0x5bc13541 (12Oct18_16:58) || 64 counters for the BSC bars
|-
|}

== additional registers ==

<pre>
reg | rw/ro | quartus name | firmware | description
0x60: param_out <= {2'h3, par_id, chan, cb_control_out
0x61: param_out <= {2'h3, par_id, chan, cb_status
0x62: param_out <= {2'h3, par_id, chan, cb_invert_a_out };
0x63: param_out <= {2'h3, par_id, chan, cb_invert_b_out };
0x64: param_out <= {2'h3, par_id, chan, cb_enable_le_a_out };
0x65: param_out <= {2'h3, par_id, chan, cb_enable_le_b_out };
0x66: param_out <= {2'h3, par_id, chan, cb_enable_te_a_out };
0x67: param_out <= {2'h3, par_id, chan, cb_enable_te_b_out };
0x6A | ro | cb_input_num | 0x618b790b | chronobox number of inputs
0x6B: param_out <= {2'h3, par_id, chan, cb_sync_mask_a_out };
0x6C: param_out <= {2'h3, par_id, chan, cb_sync_mask_b_out };
0x6D: param_out <= {2'h3, par_id, chan, cb_sync_reg_out };
0x6E: param_out <= {2'h3, par_id, chan, cb_sync_status };
0x6F: param_out <= {2'h3, par_id, chan, cb_latch_period_out };
0x70: param_out <= {2'h3, par_id, chan, cb_fifo_status };
0x71: begin param_out <= {2'h3, par_id, chan, cb_fifo_data }; cb_fifo_rdack_out <= 1; end
0x72: param_out <= {2'h3, par_id, chan, cb_udp_period_out };
0x73: param_out <= {2'h3, par_id, chan, cb_udp_threshold_out };
</pre>

== conf_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_clock_select || 0x5b3aa19f (02Jul18_15:05) || select 0=internal 62.5 MHz clock or 1=esata 62.5 MHz clock
|-
| 1 || conf_enable_aw_adc16 || 0x5baedfca (28Sep18_19:13) || select source of TPC AW aw16 bus, see [[#aw16 bus]]
|-
| 2 || conf_enable_aw_adc32a || 0x5baedfca (28Sep18_19:13) ||
|-
| 3 || conf_enable_aw_adc32b || 0x5baedfca (28Sep18_19:13) ||
|-
| 15..4 || || ||
|-
| 23..16 || conf_mlu_prompt || 0x5b3aa19f (02Jul18_15:05) || MLU trigger prompt window, see [[#aw16_mlu]]
|-
| 31..24 || conf_mlu_wait || 0x5b3aa19f (02Jul18_15:05) || MLU trigger wait window, see [[#aw16_mlu]]
|-
|}

== conf_mlu bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 31 || mlu_reset || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 30 || mlu_write || 0x5b3aa19f (02Jul18_15:05) || 1=write data bit into given address
|-
| 16 || mlu_data || 0x5b3aa19f (02Jul18_15:05) || data bit for writing to MLU RAM
|-
| 15..0 || mlu_write_addr || 0x5b3aa19f (02Jul18_15:05) || MLU RAM write address for writing the data bit
|-
|}

== conf_bsc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_bsc_adc_a || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 0..7
|-
| 1 || conf_bsc_adc_b || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 8..15
|-
| 2 || conf_bsc64_bot_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses bottom channels only
|-
| 3 || conf_bsc64_top_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses top channels only
|-
| 4 || conf_bsc64_bot_top_or || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "or" of top and bottom
|-
| 5 || conf_bsc64_bot_top_and || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "and" of top and bottom
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_bsc64_mult_min || 0x5bc13541 (12Oct18_16:58) || minimum bsc64 multiplicity
|-
| 23..16 || conf_bsc64_mult_max || 0x62c77f0b || maximum bsc64 multiplicity
|-
| 31..24 || conf_bsc64_mult_window || 0x62c77f0b || bsc64 multiplicity window length, 8 ns clocks
|-
|}

== conf_coinc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_coinc_required[0] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mult_1ormore
|-
| 0 || conf_coinc_required[0] || 0x62c77f0b || enable aw16_grand_or
|-
| 1 || conf_coinc_required[1] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mlu_trig
|-
| 2 || conf_coinc_required[2] || 0x5bc13541 (12Oct18_16:58) || enable bsc_grand_or_trig
|-
| 3 || conf_coinc_required[3] || 0x5bc13541 (12Oct18_16:58) || enable bsc_mult_trig
|-
| 3 || conf_coinc_required[3] || 0x62c77f0b || enable bsc64_mult_trig
|-
| 4 || conf_coinc_required[4] || 0x5bc13541 (12Oct18_16:58) || enable esata_nim_grand_or
|-
| 5 ||
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_coinc_window[7:0] || 0x5bc13541 (12Oct18_16:58) || coincidence window length in units of 125MHz clock (8 ns)
|-
| 23..16 || conf_coinc_start[7:0] || 0x5bc13541 (12Oct18_16:58) || start the coincidence window, same bits as "required"
|-
| 31..24 ||
|-
|}

== conf_trig_enable bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_enable_sw_trigger || || trigger on software trigger (how generated???)
|-
| 1 || conf_enable_pulser || || trigger on pulser
|-
| 2 || - || 0x5b120c9f (01Jun18_20:18) || not used
|-
| 3 || conf_pulser_run || || allow the pulser to run (frequency has to be set beforehand)
|-
| 4 || conf_output_pulser || 0x5bc8f90f || does nothing (top level ag_pulser_out is disconnected)
|-
| 4 || || 0x618b790b || not used
|-
| 5 || conf_enable_esata_nim || || trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand)
|-
| 6 || conf_enable_adc16 || || trigger on adc16_grand_or
|-
| 7 || conf_enable_adc32 || || trigger on adc32_grand_or
|-
| 8 || conf_enable_adc16_1ormore || || trigger on adc16_mult_1ormore "1 or more"
|-
| 9 || conf_enable_adc16_2ormore || || same, "2 or more"
|-
| 10 || conf_enable_adc16_3ormore || || same, "3 or more"
|-
| 11 || conf_enable_adc16_4ormore || || same, "4 or more"
|-
| 12 || - || 0x5b08938c (25May18_15:51) || not used
|-
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
|-
| 14 || - || 0x5bc8f90f || not used
|-
| 15 || conf_enable_adc || 0x5b120c9f (01Jun18_20:18) || trigger on adc_grand_or
|-
| 16 || conf_enable_aw16_coinc_a || 0x5bc8f90f || enable AW coincidence trigger, see [[#aw16_coinc]]
|-
| 16 || - || 0x62c77f0b || aw16_coinc_x removed
|-
| 17 || conf_enable_aw16_coinc_b || 0x5bc8f90f ||
|-
| 18 || conf_enable_aw16_coinc_c || 0x5bc8f90f ||
|-
| 19 || conf_enable_aw16_coinc_d || 0x5bc8f90f ||
|-
| 20 || - || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 20 || conf_enable_aw16_grand_or || 0x618b790b || enable trigger on aw16_grand_or
|-
| 21 || conf_enable_aw16_coinc || 0x5b3aa19f (02Jul18_15:05) || enable trigger on aw16_coinc_trig
|-
| 22 || conf_enable_aw16_mlu || 0x5b3aa19f (02Jul18_15:05) || enable AW MLU trigger
|-
| 23 || conf_enable_timeout_trig || 0x5bc8f90f (18Oct18_14:20) || enable trigger timeout trigger
|-
| 24 || conf_enable_aw16_1ormore || 0x5b3aa19f (02Jul18_15:05) || trigger on aw16_mult_1ormore "1 or more"
|-
| 24 || - || 0x62c77f0b || aw16_mult_xxx removed
|-
| 25 || conf_enable_aw16_2ormore || 0x5b3aa19f (02Jul18_15:05) || same, "2 or more"
|-
| 26 || conf_enable_aw16_3ormore || 0x5b3aa19f (02Jul18_15:05) || same, "3 or more"
|-
| 27 || conf_enable_aw16_4ormore || 0x5b3aa19f (02Jul18_15:05) || same, "4 or more"
|-
| 28 || conf_enable_bsc_grand_or || 0x5bc13541 (12Oct18_16:58) || trigger on BSC grand-or
|-
| 29 || conf_enable_bsc_mult || 0x5bc13541 (12Oct18_16:58) || trigger on BSC multiplicity
|-
| 30 || conf_enable_coinc || 0x5bc13541 (12Oct18_16:58) || trigger on TPC/BSC/ext coincidence trigger
|-
| 31 || - || || not used
|-
|}

== reg 0x2B bits ==

Write to this register will pulse corresponding fpga signals:

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || reset_out || 0x5b120c9f (01Jun18_20:18) || reset counters, etc
|-
| 1 || latch_out || 0x5b120c9f (01Jun18_20:18) || latch counters, sas bits, etc
|-
| 2 || trigger_out || 0x5b120c9f (01Jun18_20:18) || generate a software trigger
|-
|}

= UDP data format =

== firmware 0x5bc8f90f ==

{| cellpadding="10" cellspacing="0" border="1"
! Offset || Name || Quartus name || FwRev || Description
|-
| 0 || packet counter || none || all || 31-bit UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
|-
| 1 || 0x8 packet header || || all || 28 bits of counter_trig_out
|-
| 2 || trigger timestamp || trig_ts || all || 62.5MHz trigger timestamp
|-
| 3 || accepted triggers || counter_trig_out || all || counter of accepted triggers
|-
| 4 || input triggers || counter_trig_in || all || counter of trigger input
|-
| 5 || pulser triggers || counter_pulser || all || counter of pulser triggers
|-
| 6 || trigger bitmap || udp_trig_bits || 0x5a48448d (30Dec17_17:59) || bitmap of trigger information, see below
|-
| 7 || nim bits || udp_nim_bits_masked || ??? || 32 bits of ADC NIM inputs (2 bits per ADC)
|-
| 8 || esata bits || udp_esata_bits_masked || ??? || 32 bits of ADC ESATA inputs (2 bits per ADC)
|-
| 9 || mlu bits || aw16_prompt || 0x5b398983 (01Jul18_19:10) || 16 bits of MLU input, 1 bit per preamp
|-
| 10 || drift-blank-off counter || udp_drift_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the drift blank-off
|-
| 11 || scaledown counter || udp_scaledown_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the scaledown
|-
| X || || || ||
|-
| 12 || 0xE packet footer || || all || 28 bits of counter_trig_out
|-
|}

== firmware 0x618b790b (Nov 2021) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

== trigger bitmap ==

Firmware ??? (one of the very early revisions)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= adc16_coinc_top;
udp_trig_bits[5] <= adc16_coinc_bot;
udp_trig_bits[6] <= adc16_coinc;
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
udp_trig_bits[31:24] <= mult16[7:0];

</pre>

Firmware 0x5b08938c (25May18_15:51)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= 0; // not used
udp_trig_bits[31:24] <= mult16[7:0];
</pre>

Firmware 0x5b217dc4 (13Jun18_13:25)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5b3aa19f (02Jul18_15:05)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= udp_mlu_out;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5bc8f90f (18Oct18_14:20)

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_run_pulser
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = 0; // not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x618b790b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x62c77f0b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = 0; // aw16_coinc_a;
assign trig32_in[17] = 0; // aw16_coinc_b;
assign trig32_in[18] = 0; // aw16_coinc_c;
assign trig32_in[19] = 0; // aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = 0; // aw16_mult_1ormore;
assign trig32_in[25] = 0; // aw16_mult_2ormore;
assign trig32_in[26] = 0; // aw16_mult_3ormore;
assign trig32_in[27] = 0; // aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc64_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

= TRG chronobox inputs =

from trg_firmware/toplevel/grifc.v

<pre>
localparam CB_N = 23;
localparam CB_N1 = CB_N-1;

wire [CB_N1:0] cb_xinputs_async;

assign cb_xinputs_async[0] = ag_trig_out;
assign cb_xinputs_async[1] = ag_trig_scaledown_out;
assign cb_xinputs_async[2] = ag_trig_drift_out;
assign cb_xinputs_async[3] = ag_trig_received_out;

assign cb_xinputs_async[4] = ag_cb_sw_trig;
assign cb_xinputs_async[5] = ag_cb_pulser_trig;
assign cb_xinputs_async[6] = ag_cb_esata_nim_trig;
assign cb_xinputs_async[7] = ag_cb_adc16_grand_or_trig;
assign cb_xinputs_async[8] = ag_cb_adc32_grand_or_trig;

assign cb_xinputs_async[9] = ag_cb_aw16_grand_or_trig;
assign cb_xinputs_async[10] = ag_cb_aw16_mult_1ormore;
assign cb_xinputs_async[11] = ag_cb_aw16_mult_2ormore;
assign cb_xinputs_async[12] = ag_cb_aw16_mult_3ormore;
assign cb_xinputs_async[13] = ag_cb_aw16_mult_4ormore;
assign cb_xinputs_async[14] = ag_cb_aw16_mlu_trig;

assign cb_xinputs_async[15] = ag_cb_bsc64_grand_or_trig;
assign cb_xinputs_async[16] = ag_cb_bsc64_mult_1ormore;
assign cb_xinputs_async[17] = ag_cb_bsc64_mult_2ormore;
assign cb_xinputs_async[18] = ag_cb_bsc64_mult_3ormore;
assign cb_xinputs_async[19] = ag_cb_bsc64_mult_4ormore;
assign cb_xinputs_async[20] = ag_cb_bsc64_mult_trig;

assign cb_xinputs_async[21] = ag_cb_coinc_trig;

assign cb_xinputs_async[22] = ag_cb_timeout_trig;
</pre>

= Example UDP packets =

* trigger data, marker words 0x8

<pre>
ReadDataThread read 76
0: 0x003666ed -- UDP packet counter from UDP transmitter
1: 0x80000bf8 -- 0x8 is trigger data packet, 0xbf8 is the trigger counter from alphag.v
2: 0x2edf8b41 -- trigger data
3: 0x00000bf8
4: 0x00000bf8
5: 0x00000bee
6: 0x00000001
7: 0x00000000
8: 0x00000000
9: 0x00000003
10: 0x00000bf8
11: 0x00000bf8
12: 0x00000000
13: 0x00000000
14: 0x00000000
15: 0x00000000
16: 0x00000000
17: 0x00000000
18: 0xe0000bf8 -- 0xE is end of trigger data, counter 0xbf8 must match the counter in the 0x8 word.
ReadDataThread read 76 -- next packet
0: 0x003666ee -- UDP packet counter from UDP transmitter
...
</pre>

* chronobox fifo data, marker word 0xC, see [[Chronobox#FIFO_data_format]]

<pre>
ReadDataThread read 404
0: 0x003658ed -- UDP packet counter from UDP transmitter
1: 0xc000eacc -- 0xC is FIFO data, fifo packet counter 0xeacc from fifo_to_udp.v
2: 0x00000061 -- FIFO status, low bits the the word counter, so up to 0x61 fifo words are to follow
3: 0x87fb3d72 -- tsc hits
4: 0x8ffb3d74
5: 0x90fb3d74
6: 0x91fb3d74
7: 0x92fb3d74
8: 0x93fb3d74
9: 0x93fb3d75
10: 0x94fb3d74
11: 0x94fb3d77
12: 0x87fb3d77
13: 0x8ffb3d77
14: 0x90fb3d77
15: 0x91fb3d77
16: 0x92fb3d77
17: 0xfe000018 -- 0xFE scaler data starts, 0x18 words to follow
18: 0x00000000
19: 0x00000000
20: 0x00000000
21: 0x00000000
22: 0x00000000
23: 0x00000000
24: 0x00000000
25: 0x00000108
26: 0x00000000
27: 0x00000000
28: 0x00000000
29: 0x00000000
30: 0x00000000
31: 0x00000000
32: 0x00000000
33: 0x00000108
34: 0x00000108
35: 0x00000108
36: 0x00000108
37: 0x00000108
38: 0x00000108
39: 0x00000000
40: 0x00000000
41: 0xce56fa93 -- last word of scaler data is the sysclock counter (125 MHz)
42: 0xff800048 -- timestamp wraparound
43: 0x8f1f36e4 -- tsc hits
44: 0x901f36e4
45: 0x911f36e4
46: 0x921f36e4
47: 0x931f36e4
48: 0x941f36e4
49: 0x871f36e4
50: 0x871f36e7
51: 0x8f1f36e7
52: 0x901f36e9
53: 0x911f36e7
54: 0x921f36e9
55: 0x931f36e7
56: 0x941f36e9
57: 0x904330ac
58: 0x914330ac
59: 0x924330ac
60: 0x934330ac
61: 0x934330ad
62: 0x944330ac
63: 0x944330ad
64: 0x874330ac
65: 0x874330ad
66: 0x8f4330ac
67: 0x8f4330ad
68: 0x904330ad
69: 0x914330ad
70: 0x924330ad
71: 0x8f672a62
72: 0x90672a62
73: 0x91672a62
74: 0x92672a62
75: 0x93672a62
76: 0x94672a62
77: 0x87672a62
78: 0x87672a65
79: 0x8f672a65
80: 0x90672a65
81: 0x91672a65
82: 0x92672a65
83: 0x93672a65
84: 0x94672a65
85: 0xff000049
86: 0x878b2422
87: 0x8f8b2424
88: 0x908b2424
89: 0x918b2424
90: 0x928b2424
91: 0x938b2424
92: 0x938b2425
93: 0x948b2424
94: 0x948b2427
95: 0x878b2427
96: 0x8f8b2427
97: 0x908b2427
98: 0x918b2427
99: 0x928b2427
100: 0xe000eacc -- 0xE is end of fifo data, counter 0xeacc must match the counter in the 0xC word.
ReadDataThread read 344 -- next packet
...
</pre>

= TODO =

* DONE July 2022. add FwRev to the UDP data output
* RJ45 SFP: PROBLEM, D.A. CABLE: GOOD, Fiber SFP: ???. fix "write did not happen" (send udp write command, there is no reply, read returns old data as if write never happened). suspect udp "write" packet is lost?
* PROBLEM GONE Aug 2021. fix reply to wrong socket - udp packets should reply to same socket as they came from, udp data packets should be sent to same socket as requested them, not same socket as last command.
* DONE 2021jul30. add fixes from Chris P. for the auto-negotiation and dhcp (see email from him).
* DONE flash chip connected to FPGA. Aug 2021. implement ethernet flash programmer
* DONE Aug 2021. updated maxv firmware. implement FPGA reboot
* speed up programming the MLU by writing more than 1 bit at a time
* DONE Nov 2021. add 64-bit bitmap of BSC trigger bits
* DONE. add chronobox code
* DONE. add avalon mux for alphag and chronobox packets
* DONE. add chronobox fifo to udp packet sequencer
* check that TxReadyOut is correct and it is safe to send an avalon packet while previous packet is still transmitting.
* DONE. test fiber SFP is working
* complete the UDP flash programmer (parallel flash erase and write)

= End =

//KO

TRG

2022-07-15T19:06:13Z

Olchansk: /* TODO */

= TRG, the trigger control board for the ALPHA-g detector =

= Links =

* xxx
* https://bitbucket.org/expalpha/trg_firmware - firmware sources on bitbucket

= General characteristics =

== Photos ==

== Board schematics ==

* https://bitbucket.org/expalpha/trg_firmware/src/master/3xFMC_VME_Motherboard.pdf

== Available hardware ==

* Altera Stratix IV - main FPGA
* Altera Max V - boot FPGA
* boot flash: PC28F512M29EW - 512 Mbit parallel NOR flash.

= TRG front panel connections =

From top to bottom:

<pre>
|
| minisas-C - links 8-11
| minisas-D - links 12-15
|
| ethernet sfp - use copper sfp only
| minisas - not used, do not connect
| esata - clock in, trigger out
|
| minisas-A - links 0-3
| minisas-B - links 4-7
|
| LEDs
|
</pre>

MiniSAS and SATA flail cable connections:

<pre>
P1 <--> link 3
P2 <--> link 2
P3 <--> link 1
P4 <--> link 0
</pre>

LEDs:

<pre>
--PCB-- (left)
LED[0] - trigger out - ag_trig_out
LED[1] - network packet received - sfp_rx_data_valid
LED[2] - Xilinx FPGA boot ok - FMC1_CFG_DONE
LED[3] - not used
(right)
</pre>

= TRG onboard jumpers and switches =

* rotary switches: select IP address: 00=192.168.1.50, 11=.51, 22=.52, 33=.53, 44=.54, otherwire=.251

= Firmware update procedure =

* use quartus to generate the grifc.pof file (use grifc.cof)
* open quartus programmer
* attach grifc.pof to the 1st CFI_512 flash
* mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
* check that "initiate configuration after programming" is set in tools->options
* say "start"
* should take about 5 minutes
* grifc should reboot into the new firmware

If CFI_512 flash is not visible to the quartus programmer, load correct
code into the MaxV CPLD:

* open quartus programmer,
* say "auto detect"
* change file for the 5M2210 device
* use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
* say "program", it should finish in 10-15 seconds
* say "auto detect"
* CFI_512 flash should be visible now.

= Firmware revisions =

* 0x5bc8f90f - original firmware used for all data
* 0x6147c0f9 - added cbtrg, etc. installed at CERN on 20 Sep 2021.
* 0x618376ae - bigger cbtrg fifo, data rate tested up to 30 Mbytes/sec
* 0x6189c7f3 - fix loss of trigger packets. (missing fifo between alphag block and ethernet mux)
* 0x618b790b - fix loss of timestamps. (cbtrg inputs stretched to 100 ns long). installed at CERN 10 Nov 2021.

= Firmware build =

* use quartus 20.1
* see Makefile in the trg_firmware project

= Jtag remote connection =

* ssh agmini@daq16
* /opt/intelFPGA/16.1/quartus/bin/jtagd --config /home/agmini/.jtagd.conf
* netstat -an | grep 1309 ### note listen address is "0.0.0.0", NOT "127.0.0.1"
<pre>
tcp 0 0 0.0.0.0:1309 0.0.0.0:* LISTEN
</pre>
* opt/intelFPGA/16.1/quartus/bin/jtagconfig ### should work
* ssh olchansk@daq01
* cd git/trg_firmware
* /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
* jtagconfig ### should work
<pre>
daq01:trg_firmware$ jtagconfig
1) DE-SoC on daq16 [2-1.2.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) USB-Blaster on daq16 [2-1.3]
024090DD EP4SGX230(.|ES)
020A40DD 5M(1270ZF324|2210Z)/EPM2210

daq01:trg_firmware$
</pre>

= ALPHA-g trigger functions =

Trigger options:
* software trigger
* pulser trigger
* trigger on GRIF16 ADC NIM and ESATA inputs ("external trigger")
* adc16 grand-or
* adc32 grand-or
* adc16 wire multiplicity
* TPC anode wire per-preamp trigger (aw16 section)
** trigger on coincidences of preamps (removed fw 0x62c77f0b)
** trigger on multiplicity of preamps (removed fw 0x62c77f0b)
** trigger on specific topology of preamps (multiplicity of preamp clusters, etc) via the aw16_mlu trigger
* BSC trigger
** BSC grand_or
** BSC bar multiplicity
* coincidence trigger - select coincidence of external trigger, TPC AW grand-or, TPC AW MLU, BSC grand-or and BSC bar multiplicity triggers

== software trigger ==

to programmatically fire the trigger, one should:
* set the conf_enable_sw_trigger bit in conf_trig_enable, this will permit the software trigger to fire the trigger
* write value 0x4 to register 0x2B, this will cause the software trigger to fire

== pulser trigger ==

To use the pulser trigger, one should program:
* pulser period (in clocks)
* pulser width (in clocks, use value 5, the pulser no longer goes outside of the trigger board, so changing the width does not do anything)
* set the run_pulser bit in conf_trig_enable, this will cause the pulser to run
* set the enable_pulser bit in conf_trig_enable, this will cause the pulser to fire the trigger
* set the output_pulser bit in conf_trig_enable, this will cause the pulser to be output from the alphag firmware block (the pulser no longer goes outside of the trigger board, so changing the bit does not do anything)

== timeout trigger ==

The event builder uses event timestamps to assemble physics events. The timestamps
are usually 32 bit wide and run at 125 MHz (8 ns) or 62.5 MHz (16 ns). If
triggers are generated often (1 per second or more), timestamp wrap around
is easily detected by the event builder. If triggers come infrequently,
timestamp wrap around may occur while there are no triggers, not be seen
by the event builder causing loss of event synchronization.

To avoid this problem in the event builder, a timeout trigger should be generated
if no triggers were generated inside a 10 second interval.

The guaranties that even if all physics triggers temporarily stop for any reason,
the event builder will stay synchronized. (0.1 Hz timeout trigger frequency).

To enable the timeout trigger:
* program timeout trigger timeout in reg 0x43 in units of 8 ns clock
* enable it in bit 23 of [[#conf_trig_enable bits]]

== adc16 multiplicity trigger ==

This trigger is intended for use with the barrel scintillator signals connected to adc16 digitizers. It does not work well with TPC AW signals.

The 16 adc16 trigger bits (16x16=256) are added together to form the hit multiplicity value (adc16_mult, 16 bits, actual range 0 to 256).

Four threshold signals are computed: adc16_mult_1ormore = adc16_mult>=1, 2ormore, 3ormore, 4ormore.

There is a counter for each of these four signals.

Each of these four signals can fire the trigger, see [[#conf_trig_enable bits]].

== TPC anode wire triggers ==

=== aw16 bus ===

TPC Anode Wire trigger is based on the aw16[15:0] (xaw16) bus.

Each bit corresponds to one AW preamp. 16 preamps, 16 bits.

The aw16[15:0] bus can be fed by
* adc16_or16[15:0] - or16 of 100 MHz ADCs, 16 ADC sas links
* adc32_or16[15:0] - or16 of 62.5 MHz ADCs, FMC-ADC32 has 32 channels, so 2 bits per ADC: low 16 channels and high 16 channels, sas links 7..0
* adc32_or16[31:16] - or16 of 62.5 MHz ADCs, ditto, sas links 15..8
as selected by conf_enable_aw_adc16, conf_enable_aw_adc32a, conf_enable_aw_adc32b in [[#conf_control bits]]

<pre>
///////////////////////////////////////////////////////////
// TPC Anode Wire trigger logic (aw16)
///////////////////////////////////////////////////////////

// map adc signals into aw16

wire [15:0] aw16 = ({16{conf_enable_aw_adc16}} & adc16_or16[15:0]) |
({16{conf_enable_aw_adc32a}} & adc32_or16[15:0]) |
({16{conf_enable_aw_adc32b}} & adc32_or16[31:16]);
...
ag_conditioner cond_adc16_or16_0(.clk(clk), .in(aw16[0]), .out(xxaw16[0]));
...
xaw16 <= xxaw16;
</pre>

=== aw16_grand_or ===

TPC AW "grand or" trigger: use aw16_mult_1ormore (before fw 0x62c77f0b)

(256 anode wires, 16 wires per preamp, 16 preamps, 16 aw16 signals)

=== aw16_mlu ===

TPC AW preamp MLU trigger: the MLU (memory lookup
table) implements an arbitrary logical function
to map the 16 aw16 preamp signals into 1 aw16_mlu_trig trigger output.

Description of the aw16 mlu trigger.

In words:

* any aw16 signal starts the aw16_prompt_run gate
* aw16 signals are collected for the duration of conf_mlu_prompt (125MHz/8ns clock)
* this corresponds to time spread of TPC AW signals due to the drift time in the AW drift cell and to the variation in signal transmission time from the ADC to the TRG (digital trigger data link).
* when this prompt time expires, the MLU looks at the accumulated aw16_prompt bit pattern and makes the "yes/no" trigger decision
* after the trigger decision is made, we wait for the TPC to become quiet:
* we wait until all aw16 signals are empty (no timeout)
* we run the aw16_prompt_wait gate, length conf_mlu_wait (8ns clock), if any aw16 signals arrive, we wait for aw16 empty again, rinse, repeat.
* now, after TPC aw16 have been empty for conf_mlu_wait clocks (8ns clock), MLU trigger is ready for the next event.

In logic: (see alphag.v)

* aw16_or <= grand-or of 16 aw16 signals
* "aw16_or" starts the "aw16_prompt_cnt" counter, opens the aw16_prompt_run gate
* during the aw16_prompt_run gate, aw16_prompt collects (latches) the aw16 bits (aw16_prompt <= aw16_prompt | aw16)
* this is the time when we wait for all "prompt" signals from the TPC to arrive into the trigger
* at the end of the aw16_prompt_run gate, the signal aw16_prompt_out is pulsed, latching the output of the MLU into aw16_mlu_trig
* this is the MLU trigger "yes/no" trigger decision.
* after the MLU trigger decision is made, we wait for the arrival and passing of all TPC drift signals
* the aw16_prompt_wait_cnt and aw_prompt_wait gate opens
* if any new aw16 signals arrive (they are TPC drift signals at this time), the aw16_prompt_wait gate is restarted
* if no aw16 signals arrive during the full run of the aw16_prompt_wait gate ("TPC quiet time")
* the aw16_prompt_wait and aw16_prompt gates are cleared and the MLU trigger is ready for the next event.

Good settings are:
* conf_mlu_prompt: 64 (512 ns)
* conf_mlu_wait: 128 (1024 ns)

== BSC trigger ==

=== bsc_adc16 bus ===

The BSC trigger is based on the [15:0]bsc_adc16[7:0] bus: 16 trigger discriminator bits from 8 ADC sas links. (8*16 = 64+64 bars, top and bottom).

The bsc_adc16 bus can be fed from sas links 0..7 or 8..15, controlled by conf_bsc_adc16_a and conf_bsc_adc16_b bits on [[#conf_bsc_control bits]].

bsc_adc16 can be fed only from GRIF-16 100 MHz ADC trigger discriminators.

=== bsc64_top and bsc64_bot buses ===

* firmware 0x5bc8f90f: bsc_adc16 is remapped into 64 bits of top (bsc64_top) and bottom (bsc64_bot):
<pre>
ag_bsc_remap bsc_remap_a(.adc(bsc_adc16[0]), .bsc_bot(bsc64_bot[7:0]), .bsc_top(bsc64_top[7:0]));
ag_bsc_remap bsc_remap_b(.adc(bsc_adc16[1]), .bsc_bot(bsc64_bot[8+7:8+0]), .bsc_top(bsc64_top[8+7:8+0]));
ag_bsc_remap bsc_remap_c(.adc(bsc_adc16[2]), .bsc_bot(bsc64_bot[2*8+7:2*8+0]), .bsc_top(bsc64_top[2*8+7:2*8+0]));
ag_bsc_remap bsc_remap_d(.adc(bsc_adc16[3]), .bsc_bot(bsc64_bot[3*8+7:3*8+0]), .bsc_top(bsc64_top[3*8+7:3*8+0]));

ag_bsc_remap bsc_remap_e(.adc(bsc_adc16[4]), .bsc_bot(bsc64_bot[4*8+7:4*8+0]), .bsc_top(bsc64_top[4*8+7:4*8+0]));
ag_bsc_remap bsc_remap_f(.adc(bsc_adc16[5]), .bsc_bot(bsc64_bot[5*8+7:5*8+0]), .bsc_top(bsc64_top[5*8+7:5*8+0]));
ag_bsc_remap bsc_remap_g(.adc(bsc_adc16[6]), .bsc_bot(bsc64_bot[6*8+7:6*8+0]), .bsc_top(bsc64_top[6*8+7:6*8+0]));
ag_bsc_remap bsc_remap_h(.adc(bsc_adc16[7]), .bsc_bot(bsc64_bot[7*8+7:7*8+0]), .bsc_top(bsc64_top[7*8+7:7*8+0]));

module ag_bsc_remap
(
input wire [15:0] adc,
output wire [7:0] bsc_bot,
output wire [7:0] bsc_top
);

assign bsc_top[3] = adc[0];
assign bsc_top[2] = adc[1];
assign bsc_top[1] = adc[2];
assign bsc_top[0] = adc[3];

assign bsc_top[7] = adc[4];
assign bsc_top[6] = adc[5];
assign bsc_top[5] = adc[6];
assign bsc_top[4] = adc[7];

assign bsc_bot[0] = adc[8];
assign bsc_bot[1] = adc[9];
assign bsc_bot[2] = adc[10];
assign bsc_bot[3] = adc[11];

assign bsc_bot[4] = adc[12];
assign bsc_bot[5] = adc[13];
assign bsc_bot[6] = adc[14];
assign bsc_bot[7] = adc[15];

endmodule
</pre>

=== bsc64 bus ===

the bsc64 bus is the 64 bars used by the trigger, formed from bsc64_top and bsc64_bot:
<pre>
if (conf_bsc64_bot_only) begin
bsc64 <= bsc64_bot;
end else if (conf_bsc64_top_only) begin
bsc64 <= bsc64_top;
end else if (conf_bsc64_bot_top_or) begin
bsc64 <= bsc64_bot | bsc64_top;
end else if (conf_bsc64_bot_top_and) begin
bsc64 <= bsc64_bot & bsc64_top;
end else begin
bsc64 <= 64'b0;
end
</pre>

=== bsc_grand_or_trig ===

bsc_grand_or_trig is the grand-or of 64 bits of the bsc64 bus

to enable triggering on bsc_grand_or_trig, set corresponding bit in [[#conf_trig_enable bits]]

=== old bsc_mult_trig ===

(from fw 0x62c77f0b, old bsc_mult_trig was replaced by new bsc64 multiplicity trigger)

* bsc64_mult is computed as multiplicity of the bsc64 bus (number of 64 bsc64 bits that fired)
* bsc_mult_trig is computed:
<pre>
if (bsc64_mult >= conf_bsc64_mult) begin
bsc_mult_trig <= 1;
end else begin
bsc_mult_trig <= 0;
end
</pre>

to enable the bsc multiplicity trigger, set the multiplicity value conf_bsc64_mult in [[#conf_bsc_control bits]] and enable the corresponding bit in [[#conf_trig_enable bits]].

=== bsc64 multiplicity trigger ===

bsc64 BSC bar multiplicity trigger uses a time window. this time window is started by bsc64_grand_or and runs for conf_bsc64_mult_window clocks (8 nc clock). During this time, hits in bsc64_bus are accumulated (latched) and their multiplicity is computed. If multiplicity condition is satisfied (bigger or equal to conf_bsc64_mult_min), bsc64_mult_trig is fired and the bsc64 bit pattern is saved to the UDP packet. Then trigger waits for the bsc64_bus to be empty. Then trigger waits for conf_bsc64_empty_window clocks, if there is any bsc64 hits, we wait for empty again. So after bsc64 has been empty for conf_bsc64_empty_window clocks, multiplicity trigger is ready for the next event. This scheme cannot implement max multiplicity.

recommended values:
* conf_bsc64_mult_window (8 bits): slightly longer than 3 cycles of SAS link: 3*18 = 54 clocks, good value is 80 (640 ns).
* conf_bsc64_mult_min (8 bits): 2
* conf_bsc64_empty_window (8 bits): 80 (640 ns)

== Coincidence trigger ==

Coincidence trigger provides a combination of TPC, BSC and external scintillator (esata_nim_grand_or) signals:

<pre>
assign coinc_input[0] = aw16_grand_or; // was aw16_mult_1ormore;
assign coinc_input[1] = aw16_mlu_trig;
assign coinc_input[2] = bsc_grand_or_trig;
assign coinc_input[3] = bsc_mult_trig;
assign coinc_input[4] = esata_nim_grand_or;
assign coinc_input[5] = 0;
assign coinc_input[6] = 0;
assign coinc_input[7] = 0;
</pre>

Coincidence trigger "start" mask selects which of the inputs can start the coincidence window.

Coincidence trigger "require" mask selects which inputs must have a hits for the coincidence ot be satisfied.

Input hits are collected for the duration of the coincidence window, if all required inputs have hits, coinc_trig is fired.

Example settings:

* coincidence of external scintillator, BSC and TPC AW "grand or" signals: start 0x10, required 0x15
* coincidence of BSC and TPC AW "grand or" signals: start 0x4, required 0x5
* coincidence of BSC and TPC AW MLU triggers: start 0x4, required 0x6
* coincidence of BSC multiplicity and TPC AW MLU triggers: start 0x8, required 0xA

= Control registers =

== Register addresses ==

Note: all registers are 32 bits unless otherwise noted.

Note: RW means read-write register, RO means read-only, ROL means read-only, contents is latched by the "latch_out" bit

{| cellpadding="10" cellspacing="0" border="1"
! Address || Quartus Name || Access || FwRev || Description
|-
| 0x08 || num_sample || RW || GRIF-C || magic 16-bit register to control UDP packet size
|-
| 0x08 || scratch_reg || RW || 0x618b790b || 32-bit scratch register
|-
| 0x1F || compilation_time || RO || || Firmware revision
|-
| 0x20 || conf_trig_width || RW || || Trigger signal width, 16 ns clock
|-
| 0x21 || conf_busy_width || RW || || Busy signal width, 16 ns clock (not used)
|-
| 0x22 || conf_pulser_width || RW || || Pulser signal width, 16 ns clock
|-
| 0x23 || conf_pulser_period || RW || || Pulser signal period, 16 ns clock
|-
| 0x24 || || || || not used
|-
| 0x25 || conf_trig_enable || RW || || see [[#conf_trig_enable bits]]
|-
| 0x26 || || || not used
|-
| 0x27 || || || not used
|-
| 0x28 || || || not used
|-
| 0x29 || conf_nim_mask || RW || || enable bits for ADC NIM inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2A || conf_esata_mask || RW || || enable bits for ADC eSATA inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2B || reset_out, latch_out, trigger_out || W || || see [[#reg 0x2B bits]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x5bc8f90f || configure AW coincidence trigger, see [[#aw16_coinc]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x62c77f0b || removed
|-
| 0x2D || conf_aw16_coinc_b || RW || 0x5bc8f90f ||
|-
| 0x2E || conf_aw16_coinc_c || RW || 0x5bc8f90f ||
|-
| 0x2F || conf_aw16_coinc_d || RW || 0x5bc8f90f ||
|-
| 0x30 || sas_sd[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect for each link
|-
| 0x31 || pll_625_status || ROL || 0x5b2057f5 (12Jun18_16:32) || 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter
|-
| 0x32 || clk_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the system 125 MHz clock
|-
| 0x33 || clk_625_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625)
|-
| 0x34 || conf_control || RW || 0x5b398983 (01Jul18_19:10) || see [[#conf_control bits]] below
|-
| 0x35 || conf_drift_width || RW || 0x5b398983 (01Jul18_19:10) || width of drift time blank-out in 16 ns clocks
|-
| 0x36 || conf_scaledown || RW || 0x5b398983 (01Jul18_19:10) || trigger scaledown, 0=no scaledown, 1=divide-by-2, 2=divide-by-3, etc
|-
| 0x37 || conf_mlu || RW || 0x5b398983 (01Jul18_19:10) || AW MLU control bits, see [[#conf_mlu bits]]
|-
| 0x38 || conf_trig_delay || RW || 0x5baedfca (28Sep18_19:13) || delay the trigger pulse, 16 ns clock
|-
| 0x39 || esata_clk_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the TRG 125 MHz clock
|-
| 0x3A || esata_clk_esata_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the external clock (eSATA 62.5 MHz clock)
|-
| 0x3B || conf_counter_adc_select || RW || 0x5bb7f6ae (05Oct18_16:41) || select which 16 ADCs are connected to the selected adc counters, 0..15 - connect the adc16 signals, 16..47 connect the adc32 signals
|-
| 0x3C || sysreset_ts || RO || 0x5bb7f6ae (05Oct18_16:41) || 125MHz counter of VME-SYSRESET
|-
| 0x3C || || || 0x618b790b || not used
|-
| 0x3D || GRIF-C csr || RW || GRIF-C || <= csr & ~par_value; // Selective clear
|-
| 0x3E || GRIF-C csr || RW || GRIF-C || <= csr | par_value; // Selective set
|-
| 0x3F || GRIF-C csr || RW || GRIF-C || <= par_value; // write
|-
| 0x3D || || || 0x618b790b || not used
|-
| 0x3E || || || 0x618b790b || not used
|-
| 0x3F || || || 0x618b790b || not used
|-
| 0x40 || conf_bsc_control || RW || 0x5bc13541 (12Oct18_16:58) || Barrel Scintillator trigger control, see [[#conf_bsc_control bits]]
|-
| 0x41 || conf_coinc_control || RW || 0x5bc13541 (12Oct18_16:58) || Coincidence trigger control, see [[#conf_coinc_control bits]]
|-
| 0x42 || reconfig_out || WO || 0x5bc13541 (12Oct18_16:58) || reserved for rebooting the FPGA (does not work)
|-
| 0x43 || conf_trigger_timeout || RW || 0x5bc8f90f (18Oct18_14:20) || Generate timeout trigger if there is no other trigger after given timeout, in 8 ns clocks, must be enabled by bit conf_enable_timeout_trig in [[#conf_trig_enable bits]]
|-
| 0x44 || eth_clk_counter || ROL || 0x618b790b ||
|-
| 0x45 || eth_clk_eth_counter || ROL || 0x618b790b ||
|-
| 0x100 || ts_625 || ROL || || latched timestamp
|-
| 0x101 || counter_trig_out || ROL || || counter of issued triggers
|-
| 0x102 || counter_trig_in || ROL || || counter of triggers
|-
| 0x103 || counter_pulser || ROL || || counter of pulser
|-
| 0x104 || counter_adc16_grand_or || ROL ||
|-
| 0x105 || counter_adc32_grand_or || ROL ||
|-
| 0x106 || counter_adc_grand_or || ROL ||
|-
| 0x107 || counter_esata_nim_grand_or || ROL ||
|-
| 0x108 || counter_adc16_mult_1ormore || ROL ||
|-
| 0x109 || counter_adc16_mult_2ormore || ROL ||
|-
| 0x10A || counter_adc16_mult_3ormore || ROL ||
|-
| 0x10B || counter_adc16_mult_4ormore || ROL ||
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x5bc8f90f || counter of AW coincidence triggers
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x62c77f0b || removed
|-
| 0x10D || counter_aw16_coinc_b || ROL || 0x5bc8f90f ||
|-
| 0x10E || counter_aw16_coinc_c || ROL || 0x5bc8f90f ||
|-
| 0x10F || counter_aw16_coinc_d || ROL || 0x5bc8f90f ||
|-
| 0x110 || counter_drift || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the drift time blank-out
|-
| 0x111 || counter_scaledown || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the scaledown
|-
| 0x112 || counter_aw16_coinc || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW coincidence triggers
|-
| 0x113 || counter_aw16_mlu || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW MLU triggers
|-
| 0x114 || counter_aw16_grand_or || ROL || 0x62c77f0b || counter of AW grand-or triggers
|-
| 0x114 || counter_aw16_mult_1ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 1ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 2ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x62c77f0b || removed
|-
| 0x116 || counter_aw16_mult_3ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 3ormore triggers
|-
| 0x117 || counter_aw16_mult_4ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 4ormore triggers
|-
| 0x118 || counter_bsc_grand_or || ROL || 0x5bc13541 (12Oct18_16:58) || counter of BSC grand-or triggers
|-
| 0x119 || counter_bsc_mult || ROL || 0x5bc13541 (12Oct18_16:58) || counter of old BSC multiplicity triggers
|-
| 0x11A || counter_coinc || ROL || 0x5bc13541 (12Oct18_16:58) || counter of coincidence triggers
|-
| 0x11B || counter_timeout || ROL || 0x618b790b || counter of timeout triggers
|-
| 0x11C || counter_bsc_mult_start || ROL || 0x62c77f0b || counter of BSC multiplicity windows
|-
| 0x11D || counter_bsc_mult_trig || ROL || 0x62c77f0b || counter of BSC multiplicity triggers
|-
| 0x11E || counter_coinc_start || ROL || 0x62d1b152 || counter of coincidence windows
|-
| 0x11F || counter_aw16_mlu_start || ROL || 0x62d1b152 || counter of TPC AW MLU windows
|-
| 0x200..0x207 || conf_adc16_masks || RW || all || adc16 enable bits
|-
| 0x300..0x30F || conf_adc32_masks || RW || all || adc32 enable bits
|-
| 0x400..0x41F || sas_bits[15:0][63:0] || ROL || all || sas data bits for each link
|-
| 0x420..0x42F || sas_sd_counters[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect counter for each link
|-
| 0x430..0x43F || counters_adc16_or16[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 16 counters of adc16 ORes
|-
| 0x440..0x45F || counters_adc32_or16[31:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 32 counters of adc32 ORes
|-
| 0x460..0x46F || counters_adc_selected[15:0] || ROL || 0x5bb7f6ae (05Oct18_16:41) || 16 counters for selected group of adcs, see conf_counter_adc_select
|-
| 0x470..0x4AF || counters_bsc64[63:0] || ROL || 0x5bc13541 (12Oct18_16:58) || 64 counters for the BSC bars
|-
|}

== additional registers ==

<pre>
reg | rw/ro | quartus name | firmware | description
0x60: param_out <= {2'h3, par_id, chan, cb_control_out
0x61: param_out <= {2'h3, par_id, chan, cb_status
0x62: param_out <= {2'h3, par_id, chan, cb_invert_a_out };
0x63: param_out <= {2'h3, par_id, chan, cb_invert_b_out };
0x64: param_out <= {2'h3, par_id, chan, cb_enable_le_a_out };
0x65: param_out <= {2'h3, par_id, chan, cb_enable_le_b_out };
0x66: param_out <= {2'h3, par_id, chan, cb_enable_te_a_out };
0x67: param_out <= {2'h3, par_id, chan, cb_enable_te_b_out };
0x6A | ro | cb_input_num | 0x618b790b | chronobox number of inputs
0x6B: param_out <= {2'h3, par_id, chan, cb_sync_mask_a_out };
0x6C: param_out <= {2'h3, par_id, chan, cb_sync_mask_b_out };
0x6D: param_out <= {2'h3, par_id, chan, cb_sync_reg_out };
0x6E: param_out <= {2'h3, par_id, chan, cb_sync_status };
0x6F: param_out <= {2'h3, par_id, chan, cb_latch_period_out };
0x70: param_out <= {2'h3, par_id, chan, cb_fifo_status };
0x71: begin param_out <= {2'h3, par_id, chan, cb_fifo_data }; cb_fifo_rdack_out <= 1; end
0x72: param_out <= {2'h3, par_id, chan, cb_udp_period_out };
0x73: param_out <= {2'h3, par_id, chan, cb_udp_threshold_out };
</pre>

== conf_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_clock_select || 0x5b3aa19f (02Jul18_15:05) || select 0=internal 62.5 MHz clock or 1=esata 62.5 MHz clock
|-
| 1 || conf_enable_aw_adc16 || 0x5baedfca (28Sep18_19:13) || select source of TPC AW aw16 bus, see [[#aw16 bus]]
|-
| 2 || conf_enable_aw_adc32a || 0x5baedfca (28Sep18_19:13) ||
|-
| 3 || conf_enable_aw_adc32b || 0x5baedfca (28Sep18_19:13) ||
|-
| 15..4 || || ||
|-
| 23..16 || conf_mlu_prompt || 0x5b3aa19f (02Jul18_15:05) || MLU trigger prompt window, see [[#aw16_mlu]]
|-
| 31..24 || conf_mlu_wait || 0x5b3aa19f (02Jul18_15:05) || MLU trigger wait window, see [[#aw16_mlu]]
|-
|}

== conf_mlu bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 31 || mlu_reset || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 30 || mlu_write || 0x5b3aa19f (02Jul18_15:05) || 1=write data bit into given address
|-
| 16 || mlu_data || 0x5b3aa19f (02Jul18_15:05) || data bit for writing to MLU RAM
|-
| 15..0 || mlu_write_addr || 0x5b3aa19f (02Jul18_15:05) || MLU RAM write address for writing the data bit
|-
|}

== conf_bsc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_bsc_adc_a || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 0..7
|-
| 1 || conf_bsc_adc_b || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 8..15
|-
| 2 || conf_bsc64_bot_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses bottom channels only
|-
| 3 || conf_bsc64_top_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses top channels only
|-
| 4 || conf_bsc64_bot_top_or || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "or" of top and bottom
|-
| 5 || conf_bsc64_bot_top_and || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "and" of top and bottom
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_bsc64_mult_min || 0x5bc13541 (12Oct18_16:58) || minimum bsc64 multiplicity
|-
| 23..16 || conf_bsc64_mult_max || 0x62c77f0b || maximum bsc64 multiplicity
|-
| 31..24 || conf_bsc64_mult_window || 0x62c77f0b || bsc64 multiplicity window length, 8 ns clocks
|-
|}

== conf_coinc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_coinc_required[0] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mult_1ormore
|-
| 0 || conf_coinc_required[0] || 0x62c77f0b || enable aw16_grand_or
|-
| 1 || conf_coinc_required[1] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mlu_trig
|-
| 2 || conf_coinc_required[2] || 0x5bc13541 (12Oct18_16:58) || enable bsc_grand_or_trig
|-
| 3 || conf_coinc_required[3] || 0x5bc13541 (12Oct18_16:58) || enable bsc_mult_trig
|-
| 3 || conf_coinc_required[3] || 0x62c77f0b || enable bsc64_mult_trig
|-
| 4 || conf_coinc_required[4] || 0x5bc13541 (12Oct18_16:58) || enable esata_nim_grand_or
|-
| 5 ||
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_coinc_window[7:0] || 0x5bc13541 (12Oct18_16:58) || coincidence window length in units of 125MHz clock (8 ns)
|-
| 23..16 || conf_coinc_start[7:0] || 0x5bc13541 (12Oct18_16:58) || start the coincidence window, same bits as "required"
|-
| 31..24 ||
|-
|}

== conf_trig_enable bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_enable_sw_trigger || || trigger on software trigger (how generated???)
|-
| 1 || conf_enable_pulser || || trigger on pulser
|-
| 2 || - || 0x5b120c9f (01Jun18_20:18) || not used
|-
| 3 || conf_pulser_run || || allow the pulser to run (frequency has to be set beforehand)
|-
| 4 || conf_output_pulser || 0x5bc8f90f || does nothing (top level ag_pulser_out is disconnected)
|-
| 4 || || 0x618b790b || not used
|-
| 5 || conf_enable_esata_nim || || trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand)
|-
| 6 || conf_enable_adc16 || || trigger on adc16_grand_or
|-
| 7 || conf_enable_adc32 || || trigger on adc32_grand_or
|-
| 8 || conf_enable_adc16_1ormore || || trigger on adc16_mult_1ormore "1 or more"
|-
| 9 || conf_enable_adc16_2ormore || || same, "2 or more"
|-
| 10 || conf_enable_adc16_3ormore || || same, "3 or more"
|-
| 11 || conf_enable_adc16_4ormore || || same, "4 or more"
|-
| 12 || - || 0x5b08938c (25May18_15:51) || not used
|-
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
|-
| 14 || - || 0x5bc8f90f || not used
|-
| 15 || conf_enable_adc || 0x5b120c9f (01Jun18_20:18) || trigger on adc_grand_or
|-
| 16 || conf_enable_aw16_coinc_a || 0x5bc8f90f || enable AW coincidence trigger, see [[#aw16_coinc]]
|-
| 16 || - || 0x62c77f0b || aw16_coinc_x removed
|-
| 17 || conf_enable_aw16_coinc_b || 0x5bc8f90f ||
|-
| 18 || conf_enable_aw16_coinc_c || 0x5bc8f90f ||
|-
| 19 || conf_enable_aw16_coinc_d || 0x5bc8f90f ||
|-
| 20 || - || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 20 || conf_enable_aw16_grand_or || 0x618b790b || enable trigger on aw16_grand_or
|-
| 21 || conf_enable_aw16_coinc || 0x5b3aa19f (02Jul18_15:05) || enable trigger on aw16_coinc_trig
|-
| 22 || conf_enable_aw16_mlu || 0x5b3aa19f (02Jul18_15:05) || enable AW MLU trigger
|-
| 23 || conf_enable_timeout_trig || 0x5bc8f90f (18Oct18_14:20) || enable trigger timeout trigger
|-
| 24 || conf_enable_aw16_1ormore || 0x5b3aa19f (02Jul18_15:05) || trigger on aw16_mult_1ormore "1 or more"
|-
| 24 || - || 0x62c77f0b || aw16_mult_xxx removed
|-
| 25 || conf_enable_aw16_2ormore || 0x5b3aa19f (02Jul18_15:05) || same, "2 or more"
|-
| 26 || conf_enable_aw16_3ormore || 0x5b3aa19f (02Jul18_15:05) || same, "3 or more"
|-
| 27 || conf_enable_aw16_4ormore || 0x5b3aa19f (02Jul18_15:05) || same, "4 or more"
|-
| 28 || conf_enable_bsc_grand_or || 0x5bc13541 (12Oct18_16:58) || trigger on BSC grand-or
|-
| 29 || conf_enable_bsc_mult || 0x5bc13541 (12Oct18_16:58) || trigger on BSC multiplicity
|-
| 30 || conf_enable_coinc || 0x5bc13541 (12Oct18_16:58) || trigger on TPC/BSC/ext coincidence trigger
|-
| 31 || - || || not used
|-
|}

== reg 0x2B bits ==

Write to this register will pulse corresponding fpga signals:

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || reset_out || 0x5b120c9f (01Jun18_20:18) || reset counters, etc
|-
| 1 || latch_out || 0x5b120c9f (01Jun18_20:18) || latch counters, sas bits, etc
|-
| 2 || trigger_out || 0x5b120c9f (01Jun18_20:18) || generate a software trigger
|-
|}

= UDP data format =

== firmware 0x5bc8f90f ==

{| cellpadding="10" cellspacing="0" border="1"
! Offset || Name || Quartus name || FwRev || Description
|-
| 0 || packet counter || none || all || 31-bit UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
|-
| 1 || 0x8 packet header || || all || 28 bits of counter_trig_out
|-
| 2 || trigger timestamp || trig_ts || all || 62.5MHz trigger timestamp
|-
| 3 || accepted triggers || counter_trig_out || all || counter of accepted triggers
|-
| 4 || input triggers || counter_trig_in || all || counter of trigger input
|-
| 5 || pulser triggers || counter_pulser || all || counter of pulser triggers
|-
| 6 || trigger bitmap || udp_trig_bits || 0x5a48448d (30Dec17_17:59) || bitmap of trigger information, see below
|-
| 7 || nim bits || udp_nim_bits_masked || ??? || 32 bits of ADC NIM inputs (2 bits per ADC)
|-
| 8 || esata bits || udp_esata_bits_masked || ??? || 32 bits of ADC ESATA inputs (2 bits per ADC)
|-
| 9 || mlu bits || aw16_prompt || 0x5b398983 (01Jul18_19:10) || 16 bits of MLU input, 1 bit per preamp
|-
| 10 || drift-blank-off counter || udp_drift_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the drift blank-off
|-
| 11 || scaledown counter || udp_scaledown_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the scaledown
|-
| X || || || ||
|-
| 12 || 0xE packet footer || || all || 28 bits of counter_trig_out
|-
|}

== firmware 0x618b790b (Nov 2021) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

== trigger bitmap ==

Firmware ??? (one of the very early revisions)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= adc16_coinc_top;
udp_trig_bits[5] <= adc16_coinc_bot;
udp_trig_bits[6] <= adc16_coinc;
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
udp_trig_bits[31:24] <= mult16[7:0];

</pre>

Firmware 0x5b08938c (25May18_15:51)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= 0; // not used
udp_trig_bits[31:24] <= mult16[7:0];
</pre>

Firmware 0x5b217dc4 (13Jun18_13:25)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5b3aa19f (02Jul18_15:05)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= udp_mlu_out;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5bc8f90f (18Oct18_14:20)

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_run_pulser
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = 0; // not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x618b790b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x62c77f0b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = 0; // aw16_coinc_a;
assign trig32_in[17] = 0; // aw16_coinc_b;
assign trig32_in[18] = 0; // aw16_coinc_c;
assign trig32_in[19] = 0; // aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = 0; // aw16_mult_1ormore;
assign trig32_in[25] = 0; // aw16_mult_2ormore;
assign trig32_in[26] = 0; // aw16_mult_3ormore;
assign trig32_in[27] = 0; // aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc64_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

= TRG chronobox inputs =

from trg_firmware/toplevel/grifc.v

<pre>
localparam CB_N = 23;
localparam CB_N1 = CB_N-1;

wire [CB_N1:0] cb_xinputs_async;

assign cb_xinputs_async[0] = ag_trig_out;
assign cb_xinputs_async[1] = ag_trig_scaledown_out;
assign cb_xinputs_async[2] = ag_trig_drift_out;
assign cb_xinputs_async[3] = ag_trig_received_out;

assign cb_xinputs_async[4] = ag_cb_sw_trig;
assign cb_xinputs_async[5] = ag_cb_pulser_trig;
assign cb_xinputs_async[6] = ag_cb_esata_nim_trig;
assign cb_xinputs_async[7] = ag_cb_adc16_grand_or_trig;
assign cb_xinputs_async[8] = ag_cb_adc32_grand_or_trig;

assign cb_xinputs_async[9] = ag_cb_aw16_grand_or_trig;
assign cb_xinputs_async[10] = ag_cb_aw16_mult_1ormore;
assign cb_xinputs_async[11] = ag_cb_aw16_mult_2ormore;
assign cb_xinputs_async[12] = ag_cb_aw16_mult_3ormore;
assign cb_xinputs_async[13] = ag_cb_aw16_mult_4ormore;
assign cb_xinputs_async[14] = ag_cb_aw16_mlu_trig;

assign cb_xinputs_async[15] = ag_cb_bsc64_grand_or_trig;
assign cb_xinputs_async[16] = ag_cb_bsc64_mult_1ormore;
assign cb_xinputs_async[17] = ag_cb_bsc64_mult_2ormore;
assign cb_xinputs_async[18] = ag_cb_bsc64_mult_3ormore;
assign cb_xinputs_async[19] = ag_cb_bsc64_mult_4ormore;
assign cb_xinputs_async[20] = ag_cb_bsc64_mult_trig;

assign cb_xinputs_async[21] = ag_cb_coinc_trig;

assign cb_xinputs_async[22] = ag_cb_timeout_trig;
</pre>

= Example UDP packets =

* trigger data, marker words 0x8

<pre>
ReadDataThread read 76
0: 0x003666ed -- UDP packet counter from UDP transmitter
1: 0x80000bf8 -- 0x8 is trigger data packet, 0xbf8 is the trigger counter from alphag.v
2: 0x2edf8b41 -- trigger data
3: 0x00000bf8
4: 0x00000bf8
5: 0x00000bee
6: 0x00000001
7: 0x00000000
8: 0x00000000
9: 0x00000003
10: 0x00000bf8
11: 0x00000bf8
12: 0x00000000
13: 0x00000000
14: 0x00000000
15: 0x00000000
16: 0x00000000
17: 0x00000000
18: 0xe0000bf8 -- 0xE is end of trigger data, counter 0xbf8 must match the counter in the 0x8 word.
ReadDataThread read 76 -- next packet
0: 0x003666ee -- UDP packet counter from UDP transmitter
...
</pre>

* chronobox fifo data, marker word 0xC, see [[Chronobox#FIFO_data_format]]

<pre>
ReadDataThread read 404
0: 0x003658ed -- UDP packet counter from UDP transmitter
1: 0xc000eacc -- 0xC is FIFO data, fifo packet counter 0xeacc from fifo_to_udp.v
2: 0x00000061 -- FIFO status, low bits the the word counter, so up to 0x61 fifo words are to follow
3: 0x87fb3d72 -- tsc hits
4: 0x8ffb3d74
5: 0x90fb3d74
6: 0x91fb3d74
7: 0x92fb3d74
8: 0x93fb3d74
9: 0x93fb3d75
10: 0x94fb3d74
11: 0x94fb3d77
12: 0x87fb3d77
13: 0x8ffb3d77
14: 0x90fb3d77
15: 0x91fb3d77
16: 0x92fb3d77
17: 0xfe000018 -- 0xFE scaler data starts, 0x18 words to follow
18: 0x00000000
19: 0x00000000
20: 0x00000000
21: 0x00000000
22: 0x00000000
23: 0x00000000
24: 0x00000000
25: 0x00000108
26: 0x00000000
27: 0x00000000
28: 0x00000000
29: 0x00000000
30: 0x00000000
31: 0x00000000
32: 0x00000000
33: 0x00000108
34: 0x00000108
35: 0x00000108
36: 0x00000108
37: 0x00000108
38: 0x00000108
39: 0x00000000
40: 0x00000000
41: 0xce56fa93 -- last word of scaler data is the sysclock counter (125 MHz)
42: 0xff800048 -- timestamp wraparound
43: 0x8f1f36e4 -- tsc hits
44: 0x901f36e4
45: 0x911f36e4
46: 0x921f36e4
47: 0x931f36e4
48: 0x941f36e4
49: 0x871f36e4
50: 0x871f36e7
51: 0x8f1f36e7
52: 0x901f36e9
53: 0x911f36e7
54: 0x921f36e9
55: 0x931f36e7
56: 0x941f36e9
57: 0x904330ac
58: 0x914330ac
59: 0x924330ac
60: 0x934330ac
61: 0x934330ad
62: 0x944330ac
63: 0x944330ad
64: 0x874330ac
65: 0x874330ad
66: 0x8f4330ac
67: 0x8f4330ad
68: 0x904330ad
69: 0x914330ad
70: 0x924330ad
71: 0x8f672a62
72: 0x90672a62
73: 0x91672a62
74: 0x92672a62
75: 0x93672a62
76: 0x94672a62
77: 0x87672a62
78: 0x87672a65
79: 0x8f672a65
80: 0x90672a65
81: 0x91672a65
82: 0x92672a65
83: 0x93672a65
84: 0x94672a65
85: 0xff000049
86: 0x878b2422
87: 0x8f8b2424
88: 0x908b2424
89: 0x918b2424
90: 0x928b2424
91: 0x938b2424
92: 0x938b2425
93: 0x948b2424
94: 0x948b2427
95: 0x878b2427
96: 0x8f8b2427
97: 0x908b2427
98: 0x918b2427
99: 0x928b2427
100: 0xe000eacc -- 0xE is end of fifo data, counter 0xeacc must match the counter in the 0xC word.
ReadDataThread read 344 -- next packet
...
</pre>

= TODO =

* add FwRev to the UDP data output
* RJ45 SFP: PROBLEM, D.A. CABLE: GOOD, Fiber SFP: ???. fix "write did not happen" (send udp write command, there is no reply, read returns old data as if write never happened). suspect udp "write" packet is lost?
* PROBLEM GONE Aug 2021. fix reply to wrong socket - udp packets should reply to same socket as they came from, udp data packets should be sent to same socket as requested them, not same socket as last command.
* DONE 2021jul30. add fixes from Chris P. for the auto-negotiation and dhcp (see email from him).
* DONE flash chip connected to FPGA. Aug 2021. implement ethernet flash programmer
* DONE Aug 2021. updated maxv firmware. implement FPGA reboot
* speed up programming the MLU by writing more than 1 bit at a time
* DONE Nov 2021. add 64-bit bitmap of BSC trigger bits
* DONE. add chronobox code
* DONE. add avalon mux for alphag and chronobox packets
* DONE. add chronobox fifo to udp packet sequencer
* check that TxReadyOut is correct and it is safe to send an avalon packet while previous packet is still transmitting.
* DONE. test fiber SFP is working
* complete the UDP flash programmer (parallel flash erase and write)

= End =

//KO

TRG

2022-07-15T19:05:12Z

Olchansk: /* firmware 0x618b790b */

= TRG, the trigger control board for the ALPHA-g detector =

= Links =

* xxx
* https://bitbucket.org/expalpha/trg_firmware - firmware sources on bitbucket

= General characteristics =

== Photos ==

== Board schematics ==

* https://bitbucket.org/expalpha/trg_firmware/src/master/3xFMC_VME_Motherboard.pdf

== Available hardware ==

* Altera Stratix IV - main FPGA
* Altera Max V - boot FPGA
* boot flash: PC28F512M29EW - 512 Mbit parallel NOR flash.

= TRG front panel connections =

From top to bottom:

<pre>
|
| minisas-C - links 8-11
| minisas-D - links 12-15
|
| ethernet sfp - use copper sfp only
| minisas - not used, do not connect
| esata - clock in, trigger out
|
| minisas-A - links 0-3
| minisas-B - links 4-7
|
| LEDs
|
</pre>

MiniSAS and SATA flail cable connections:

<pre>
P1 <--> link 3
P2 <--> link 2
P3 <--> link 1
P4 <--> link 0
</pre>

LEDs:

<pre>
--PCB-- (left)
LED[0] - trigger out - ag_trig_out
LED[1] - network packet received - sfp_rx_data_valid
LED[2] - Xilinx FPGA boot ok - FMC1_CFG_DONE
LED[3] - not used
(right)
</pre>

= TRG onboard jumpers and switches =

* rotary switches: select IP address: 00=192.168.1.50, 11=.51, 22=.52, 33=.53, 44=.54, otherwire=.251

= Firmware update procedure =

* use quartus to generate the grifc.pof file (use grifc.cof)
* open quartus programmer
* attach grifc.pof to the 1st CFI_512 flash
* mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
* check that "initiate configuration after programming" is set in tools->options
* say "start"
* should take about 5 minutes
* grifc should reboot into the new firmware

If CFI_512 flash is not visible to the quartus programmer, load correct
code into the MaxV CPLD:

* open quartus programmer,
* say "auto detect"
* change file for the 5M2210 device
* use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
* say "program", it should finish in 10-15 seconds
* say "auto detect"
* CFI_512 flash should be visible now.

= Firmware revisions =

* 0x5bc8f90f - original firmware used for all data
* 0x6147c0f9 - added cbtrg, etc. installed at CERN on 20 Sep 2021.
* 0x618376ae - bigger cbtrg fifo, data rate tested up to 30 Mbytes/sec
* 0x6189c7f3 - fix loss of trigger packets. (missing fifo between alphag block and ethernet mux)
* 0x618b790b - fix loss of timestamps. (cbtrg inputs stretched to 100 ns long). installed at CERN 10 Nov 2021.

= Firmware build =

* use quartus 20.1
* see Makefile in the trg_firmware project

= Jtag remote connection =

* ssh agmini@daq16
* /opt/intelFPGA/16.1/quartus/bin/jtagd --config /home/agmini/.jtagd.conf
* netstat -an | grep 1309 ### note listen address is "0.0.0.0", NOT "127.0.0.1"
<pre>
tcp 0 0 0.0.0.0:1309 0.0.0.0:* LISTEN
</pre>
* opt/intelFPGA/16.1/quartus/bin/jtagconfig ### should work
* ssh olchansk@daq01
* cd git/trg_firmware
* /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
* jtagconfig ### should work
<pre>
daq01:trg_firmware$ jtagconfig
1) DE-SoC on daq16 [2-1.2.3]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

2) USB-Blaster on daq16 [2-1.3]
024090DD EP4SGX230(.|ES)
020A40DD 5M(1270ZF324|2210Z)/EPM2210

daq01:trg_firmware$
</pre>

= ALPHA-g trigger functions =

Trigger options:
* software trigger
* pulser trigger
* trigger on GRIF16 ADC NIM and ESATA inputs ("external trigger")
* adc16 grand-or
* adc32 grand-or
* adc16 wire multiplicity
* TPC anode wire per-preamp trigger (aw16 section)
** trigger on coincidences of preamps (removed fw 0x62c77f0b)
** trigger on multiplicity of preamps (removed fw 0x62c77f0b)
** trigger on specific topology of preamps (multiplicity of preamp clusters, etc) via the aw16_mlu trigger
* BSC trigger
** BSC grand_or
** BSC bar multiplicity
* coincidence trigger - select coincidence of external trigger, TPC AW grand-or, TPC AW MLU, BSC grand-or and BSC bar multiplicity triggers

== software trigger ==

to programmatically fire the trigger, one should:
* set the conf_enable_sw_trigger bit in conf_trig_enable, this will permit the software trigger to fire the trigger
* write value 0x4 to register 0x2B, this will cause the software trigger to fire

== pulser trigger ==

To use the pulser trigger, one should program:
* pulser period (in clocks)
* pulser width (in clocks, use value 5, the pulser no longer goes outside of the trigger board, so changing the width does not do anything)
* set the run_pulser bit in conf_trig_enable, this will cause the pulser to run
* set the enable_pulser bit in conf_trig_enable, this will cause the pulser to fire the trigger
* set the output_pulser bit in conf_trig_enable, this will cause the pulser to be output from the alphag firmware block (the pulser no longer goes outside of the trigger board, so changing the bit does not do anything)

== timeout trigger ==

The event builder uses event timestamps to assemble physics events. The timestamps
are usually 32 bit wide and run at 125 MHz (8 ns) or 62.5 MHz (16 ns). If
triggers are generated often (1 per second or more), timestamp wrap around
is easily detected by the event builder. If triggers come infrequently,
timestamp wrap around may occur while there are no triggers, not be seen
by the event builder causing loss of event synchronization.

To avoid this problem in the event builder, a timeout trigger should be generated
if no triggers were generated inside a 10 second interval.

The guaranties that even if all physics triggers temporarily stop for any reason,
the event builder will stay synchronized. (0.1 Hz timeout trigger frequency).

To enable the timeout trigger:
* program timeout trigger timeout in reg 0x43 in units of 8 ns clock
* enable it in bit 23 of [[#conf_trig_enable bits]]

== adc16 multiplicity trigger ==

This trigger is intended for use with the barrel scintillator signals connected to adc16 digitizers. It does not work well with TPC AW signals.

The 16 adc16 trigger bits (16x16=256) are added together to form the hit multiplicity value (adc16_mult, 16 bits, actual range 0 to 256).

Four threshold signals are computed: adc16_mult_1ormore = adc16_mult>=1, 2ormore, 3ormore, 4ormore.

There is a counter for each of these four signals.

Each of these four signals can fire the trigger, see [[#conf_trig_enable bits]].

== TPC anode wire triggers ==

=== aw16 bus ===

TPC Anode Wire trigger is based on the aw16[15:0] (xaw16) bus.

Each bit corresponds to one AW preamp. 16 preamps, 16 bits.

The aw16[15:0] bus can be fed by
* adc16_or16[15:0] - or16 of 100 MHz ADCs, 16 ADC sas links
* adc32_or16[15:0] - or16 of 62.5 MHz ADCs, FMC-ADC32 has 32 channels, so 2 bits per ADC: low 16 channels and high 16 channels, sas links 7..0
* adc32_or16[31:16] - or16 of 62.5 MHz ADCs, ditto, sas links 15..8
as selected by conf_enable_aw_adc16, conf_enable_aw_adc32a, conf_enable_aw_adc32b in [[#conf_control bits]]

<pre>
///////////////////////////////////////////////////////////
// TPC Anode Wire trigger logic (aw16)
///////////////////////////////////////////////////////////

// map adc signals into aw16

wire [15:0] aw16 = ({16{conf_enable_aw_adc16}} & adc16_or16[15:0]) |
({16{conf_enable_aw_adc32a}} & adc32_or16[15:0]) |
({16{conf_enable_aw_adc32b}} & adc32_or16[31:16]);
...
ag_conditioner cond_adc16_or16_0(.clk(clk), .in(aw16[0]), .out(xxaw16[0]));
...
xaw16 <= xxaw16;
</pre>

=== aw16_grand_or ===

TPC AW "grand or" trigger: use aw16_mult_1ormore (before fw 0x62c77f0b)

(256 anode wires, 16 wires per preamp, 16 preamps, 16 aw16 signals)

=== aw16_mlu ===

TPC AW preamp MLU trigger: the MLU (memory lookup
table) implements an arbitrary logical function
to map the 16 aw16 preamp signals into 1 aw16_mlu_trig trigger output.

Description of the aw16 mlu trigger.

In words:

* any aw16 signal starts the aw16_prompt_run gate
* aw16 signals are collected for the duration of conf_mlu_prompt (125MHz/8ns clock)
* this corresponds to time spread of TPC AW signals due to the drift time in the AW drift cell and to the variation in signal transmission time from the ADC to the TRG (digital trigger data link).
* when this prompt time expires, the MLU looks at the accumulated aw16_prompt bit pattern and makes the "yes/no" trigger decision
* after the trigger decision is made, we wait for the TPC to become quiet:
* we wait until all aw16 signals are empty (no timeout)
* we run the aw16_prompt_wait gate, length conf_mlu_wait (8ns clock), if any aw16 signals arrive, we wait for aw16 empty again, rinse, repeat.
* now, after TPC aw16 have been empty for conf_mlu_wait clocks (8ns clock), MLU trigger is ready for the next event.

In logic: (see alphag.v)

* aw16_or <= grand-or of 16 aw16 signals
* "aw16_or" starts the "aw16_prompt_cnt" counter, opens the aw16_prompt_run gate
* during the aw16_prompt_run gate, aw16_prompt collects (latches) the aw16 bits (aw16_prompt <= aw16_prompt | aw16)
* this is the time when we wait for all "prompt" signals from the TPC to arrive into the trigger
* at the end of the aw16_prompt_run gate, the signal aw16_prompt_out is pulsed, latching the output of the MLU into aw16_mlu_trig
* this is the MLU trigger "yes/no" trigger decision.
* after the MLU trigger decision is made, we wait for the arrival and passing of all TPC drift signals
* the aw16_prompt_wait_cnt and aw_prompt_wait gate opens
* if any new aw16 signals arrive (they are TPC drift signals at this time), the aw16_prompt_wait gate is restarted
* if no aw16 signals arrive during the full run of the aw16_prompt_wait gate ("TPC quiet time")
* the aw16_prompt_wait and aw16_prompt gates are cleared and the MLU trigger is ready for the next event.

Good settings are:
* conf_mlu_prompt: 64 (512 ns)
* conf_mlu_wait: 128 (1024 ns)

== BSC trigger ==

=== bsc_adc16 bus ===

The BSC trigger is based on the [15:0]bsc_adc16[7:0] bus: 16 trigger discriminator bits from 8 ADC sas links. (8*16 = 64+64 bars, top and bottom).

The bsc_adc16 bus can be fed from sas links 0..7 or 8..15, controlled by conf_bsc_adc16_a and conf_bsc_adc16_b bits on [[#conf_bsc_control bits]].

bsc_adc16 can be fed only from GRIF-16 100 MHz ADC trigger discriminators.

=== bsc64_top and bsc64_bot buses ===

* firmware 0x5bc8f90f: bsc_adc16 is remapped into 64 bits of top (bsc64_top) and bottom (bsc64_bot):
<pre>
ag_bsc_remap bsc_remap_a(.adc(bsc_adc16[0]), .bsc_bot(bsc64_bot[7:0]), .bsc_top(bsc64_top[7:0]));
ag_bsc_remap bsc_remap_b(.adc(bsc_adc16[1]), .bsc_bot(bsc64_bot[8+7:8+0]), .bsc_top(bsc64_top[8+7:8+0]));
ag_bsc_remap bsc_remap_c(.adc(bsc_adc16[2]), .bsc_bot(bsc64_bot[2*8+7:2*8+0]), .bsc_top(bsc64_top[2*8+7:2*8+0]));
ag_bsc_remap bsc_remap_d(.adc(bsc_adc16[3]), .bsc_bot(bsc64_bot[3*8+7:3*8+0]), .bsc_top(bsc64_top[3*8+7:3*8+0]));

ag_bsc_remap bsc_remap_e(.adc(bsc_adc16[4]), .bsc_bot(bsc64_bot[4*8+7:4*8+0]), .bsc_top(bsc64_top[4*8+7:4*8+0]));
ag_bsc_remap bsc_remap_f(.adc(bsc_adc16[5]), .bsc_bot(bsc64_bot[5*8+7:5*8+0]), .bsc_top(bsc64_top[5*8+7:5*8+0]));
ag_bsc_remap bsc_remap_g(.adc(bsc_adc16[6]), .bsc_bot(bsc64_bot[6*8+7:6*8+0]), .bsc_top(bsc64_top[6*8+7:6*8+0]));
ag_bsc_remap bsc_remap_h(.adc(bsc_adc16[7]), .bsc_bot(bsc64_bot[7*8+7:7*8+0]), .bsc_top(bsc64_top[7*8+7:7*8+0]));

module ag_bsc_remap
(
input wire [15:0] adc,
output wire [7:0] bsc_bot,
output wire [7:0] bsc_top
);

assign bsc_top[3] = adc[0];
assign bsc_top[2] = adc[1];
assign bsc_top[1] = adc[2];
assign bsc_top[0] = adc[3];

assign bsc_top[7] = adc[4];
assign bsc_top[6] = adc[5];
assign bsc_top[5] = adc[6];
assign bsc_top[4] = adc[7];

assign bsc_bot[0] = adc[8];
assign bsc_bot[1] = adc[9];
assign bsc_bot[2] = adc[10];
assign bsc_bot[3] = adc[11];

assign bsc_bot[4] = adc[12];
assign bsc_bot[5] = adc[13];
assign bsc_bot[6] = adc[14];
assign bsc_bot[7] = adc[15];

endmodule
</pre>

=== bsc64 bus ===

the bsc64 bus is the 64 bars used by the trigger, formed from bsc64_top and bsc64_bot:
<pre>
if (conf_bsc64_bot_only) begin
bsc64 <= bsc64_bot;
end else if (conf_bsc64_top_only) begin
bsc64 <= bsc64_top;
end else if (conf_bsc64_bot_top_or) begin
bsc64 <= bsc64_bot | bsc64_top;
end else if (conf_bsc64_bot_top_and) begin
bsc64 <= bsc64_bot & bsc64_top;
end else begin
bsc64 <= 64'b0;
end
</pre>

=== bsc_grand_or_trig ===

bsc_grand_or_trig is the grand-or of 64 bits of the bsc64 bus

to enable triggering on bsc_grand_or_trig, set corresponding bit in [[#conf_trig_enable bits]]

=== old bsc_mult_trig ===

(from fw 0x62c77f0b, old bsc_mult_trig was replaced by new bsc64 multiplicity trigger)

* bsc64_mult is computed as multiplicity of the bsc64 bus (number of 64 bsc64 bits that fired)
* bsc_mult_trig is computed:
<pre>
if (bsc64_mult >= conf_bsc64_mult) begin
bsc_mult_trig <= 1;
end else begin
bsc_mult_trig <= 0;
end
</pre>

to enable the bsc multiplicity trigger, set the multiplicity value conf_bsc64_mult in [[#conf_bsc_control bits]] and enable the corresponding bit in [[#conf_trig_enable bits]].

=== bsc64 multiplicity trigger ===

bsc64 BSC bar multiplicity trigger uses a time window. this time window is started by bsc64_grand_or and runs for conf_bsc64_mult_window clocks (8 nc clock). During this time, hits in bsc64_bus are accumulated (latched) and their multiplicity is computed. If multiplicity condition is satisfied (bigger or equal to conf_bsc64_mult_min), bsc64_mult_trig is fired and the bsc64 bit pattern is saved to the UDP packet. Then trigger waits for the bsc64_bus to be empty. Then trigger waits for conf_bsc64_empty_window clocks, if there is any bsc64 hits, we wait for empty again. So after bsc64 has been empty for conf_bsc64_empty_window clocks, multiplicity trigger is ready for the next event. This scheme cannot implement max multiplicity.

recommended values:
* conf_bsc64_mult_window (8 bits): slightly longer than 3 cycles of SAS link: 3*18 = 54 clocks, good value is 80 (640 ns).
* conf_bsc64_mult_min (8 bits): 2
* conf_bsc64_empty_window (8 bits): 80 (640 ns)

== Coincidence trigger ==

Coincidence trigger provides a combination of TPC, BSC and external scintillator (esata_nim_grand_or) signals:

<pre>
assign coinc_input[0] = aw16_grand_or; // was aw16_mult_1ormore;
assign coinc_input[1] = aw16_mlu_trig;
assign coinc_input[2] = bsc_grand_or_trig;
assign coinc_input[3] = bsc_mult_trig;
assign coinc_input[4] = esata_nim_grand_or;
assign coinc_input[5] = 0;
assign coinc_input[6] = 0;
assign coinc_input[7] = 0;
</pre>

Coincidence trigger "start" mask selects which of the inputs can start the coincidence window.

Coincidence trigger "require" mask selects which inputs must have a hits for the coincidence ot be satisfied.

Input hits are collected for the duration of the coincidence window, if all required inputs have hits, coinc_trig is fired.

Example settings:

* coincidence of external scintillator, BSC and TPC AW "grand or" signals: start 0x10, required 0x15
* coincidence of BSC and TPC AW "grand or" signals: start 0x4, required 0x5
* coincidence of BSC and TPC AW MLU triggers: start 0x4, required 0x6
* coincidence of BSC multiplicity and TPC AW MLU triggers: start 0x8, required 0xA

= Control registers =

== Register addresses ==

Note: all registers are 32 bits unless otherwise noted.

Note: RW means read-write register, RO means read-only, ROL means read-only, contents is latched by the "latch_out" bit

{| cellpadding="10" cellspacing="0" border="1"
! Address || Quartus Name || Access || FwRev || Description
|-
| 0x08 || num_sample || RW || GRIF-C || magic 16-bit register to control UDP packet size
|-
| 0x08 || scratch_reg || RW || 0x618b790b || 32-bit scratch register
|-
| 0x1F || compilation_time || RO || || Firmware revision
|-
| 0x20 || conf_trig_width || RW || || Trigger signal width, 16 ns clock
|-
| 0x21 || conf_busy_width || RW || || Busy signal width, 16 ns clock (not used)
|-
| 0x22 || conf_pulser_width || RW || || Pulser signal width, 16 ns clock
|-
| 0x23 || conf_pulser_period || RW || || Pulser signal period, 16 ns clock
|-
| 0x24 || || || || not used
|-
| 0x25 || conf_trig_enable || RW || || see [[#conf_trig_enable bits]]
|-
| 0x26 || || || not used
|-
| 0x27 || || || not used
|-
| 0x28 || || || not used
|-
| 0x29 || conf_nim_mask || RW || || enable bits for ADC NIM inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2A || conf_esata_mask || RW || || enable bits for ADC eSATA inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2B || reset_out, latch_out, trigger_out || W || || see [[#reg 0x2B bits]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x5bc8f90f || configure AW coincidence trigger, see [[#aw16_coinc]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x62c77f0b || removed
|-
| 0x2D || conf_aw16_coinc_b || RW || 0x5bc8f90f ||
|-
| 0x2E || conf_aw16_coinc_c || RW || 0x5bc8f90f ||
|-
| 0x2F || conf_aw16_coinc_d || RW || 0x5bc8f90f ||
|-
| 0x30 || sas_sd[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect for each link
|-
| 0x31 || pll_625_status || ROL || 0x5b2057f5 (12Jun18_16:32) || 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter
|-
| 0x32 || clk_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the system 125 MHz clock
|-
| 0x33 || clk_625_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625)
|-
| 0x34 || conf_control || RW || 0x5b398983 (01Jul18_19:10) || see [[#conf_control bits]] below
|-
| 0x35 || conf_drift_width || RW || 0x5b398983 (01Jul18_19:10) || width of drift time blank-out in 16 ns clocks
|-
| 0x36 || conf_scaledown || RW || 0x5b398983 (01Jul18_19:10) || trigger scaledown, 0=no scaledown, 1=divide-by-2, 2=divide-by-3, etc
|-
| 0x37 || conf_mlu || RW || 0x5b398983 (01Jul18_19:10) || AW MLU control bits, see [[#conf_mlu bits]]
|-
| 0x38 || conf_trig_delay || RW || 0x5baedfca (28Sep18_19:13) || delay the trigger pulse, 16 ns clock
|-
| 0x39 || esata_clk_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the TRG 125 MHz clock
|-
| 0x3A || esata_clk_esata_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the external clock (eSATA 62.5 MHz clock)
|-
| 0x3B || conf_counter_adc_select || RW || 0x5bb7f6ae (05Oct18_16:41) || select which 16 ADCs are connected to the selected adc counters, 0..15 - connect the adc16 signals, 16..47 connect the adc32 signals
|-
| 0x3C || sysreset_ts || RO || 0x5bb7f6ae (05Oct18_16:41) || 125MHz counter of VME-SYSRESET
|-
| 0x3C || || || 0x618b790b || not used
|-
| 0x3D || GRIF-C csr || RW || GRIF-C || <= csr & ~par_value; // Selective clear
|-
| 0x3E || GRIF-C csr || RW || GRIF-C || <= csr | par_value; // Selective set
|-
| 0x3F || GRIF-C csr || RW || GRIF-C || <= par_value; // write
|-
| 0x3D || || || 0x618b790b || not used
|-
| 0x3E || || || 0x618b790b || not used
|-
| 0x3F || || || 0x618b790b || not used
|-
| 0x40 || conf_bsc_control || RW || 0x5bc13541 (12Oct18_16:58) || Barrel Scintillator trigger control, see [[#conf_bsc_control bits]]
|-
| 0x41 || conf_coinc_control || RW || 0x5bc13541 (12Oct18_16:58) || Coincidence trigger control, see [[#conf_coinc_control bits]]
|-
| 0x42 || reconfig_out || WO || 0x5bc13541 (12Oct18_16:58) || reserved for rebooting the FPGA (does not work)
|-
| 0x43 || conf_trigger_timeout || RW || 0x5bc8f90f (18Oct18_14:20) || Generate timeout trigger if there is no other trigger after given timeout, in 8 ns clocks, must be enabled by bit conf_enable_timeout_trig in [[#conf_trig_enable bits]]
|-
| 0x44 || eth_clk_counter || ROL || 0x618b790b ||
|-
| 0x45 || eth_clk_eth_counter || ROL || 0x618b790b ||
|-
| 0x100 || ts_625 || ROL || || latched timestamp
|-
| 0x101 || counter_trig_out || ROL || || counter of issued triggers
|-
| 0x102 || counter_trig_in || ROL || || counter of triggers
|-
| 0x103 || counter_pulser || ROL || || counter of pulser
|-
| 0x104 || counter_adc16_grand_or || ROL ||
|-
| 0x105 || counter_adc32_grand_or || ROL ||
|-
| 0x106 || counter_adc_grand_or || ROL ||
|-
| 0x107 || counter_esata_nim_grand_or || ROL ||
|-
| 0x108 || counter_adc16_mult_1ormore || ROL ||
|-
| 0x109 || counter_adc16_mult_2ormore || ROL ||
|-
| 0x10A || counter_adc16_mult_3ormore || ROL ||
|-
| 0x10B || counter_adc16_mult_4ormore || ROL ||
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x5bc8f90f || counter of AW coincidence triggers
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x62c77f0b || removed
|-
| 0x10D || counter_aw16_coinc_b || ROL || 0x5bc8f90f ||
|-
| 0x10E || counter_aw16_coinc_c || ROL || 0x5bc8f90f ||
|-
| 0x10F || counter_aw16_coinc_d || ROL || 0x5bc8f90f ||
|-
| 0x110 || counter_drift || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the drift time blank-out
|-
| 0x111 || counter_scaledown || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the scaledown
|-
| 0x112 || counter_aw16_coinc || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW coincidence triggers
|-
| 0x113 || counter_aw16_mlu || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW MLU triggers
|-
| 0x114 || counter_aw16_grand_or || ROL || 0x62c77f0b || counter of AW grand-or triggers
|-
| 0x114 || counter_aw16_mult_1ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 1ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 2ormore triggers
|-
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x62c77f0b || removed
|-
| 0x116 || counter_aw16_mult_3ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 3ormore triggers
|-
| 0x117 || counter_aw16_mult_4ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 4ormore triggers
|-
| 0x118 || counter_bsc_grand_or || ROL || 0x5bc13541 (12Oct18_16:58) || counter of BSC grand-or triggers
|-
| 0x119 || counter_bsc_mult || ROL || 0x5bc13541 (12Oct18_16:58) || counter of old BSC multiplicity triggers
|-
| 0x11A || counter_coinc || ROL || 0x5bc13541 (12Oct18_16:58) || counter of coincidence triggers
|-
| 0x11B || counter_timeout || ROL || 0x618b790b || counter of timeout triggers
|-
| 0x11C || counter_bsc_mult_start || ROL || 0x62c77f0b || counter of BSC multiplicity windows
|-
| 0x11D || counter_bsc_mult_trig || ROL || 0x62c77f0b || counter of BSC multiplicity triggers
|-
| 0x11E || counter_coinc_start || ROL || 0x62d1b152 || counter of coincidence windows
|-
| 0x11F || counter_aw16_mlu_start || ROL || 0x62d1b152 || counter of TPC AW MLU windows
|-
| 0x200..0x207 || conf_adc16_masks || RW || all || adc16 enable bits
|-
| 0x300..0x30F || conf_adc32_masks || RW || all || adc32 enable bits
|-
| 0x400..0x41F || sas_bits[15:0][63:0] || ROL || all || sas data bits for each link
|-
| 0x420..0x42F || sas_sd_counters[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect counter for each link
|-
| 0x430..0x43F || counters_adc16_or16[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 16 counters of adc16 ORes
|-
| 0x440..0x45F || counters_adc32_or16[31:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 32 counters of adc32 ORes
|-
| 0x460..0x46F || counters_adc_selected[15:0] || ROL || 0x5bb7f6ae (05Oct18_16:41) || 16 counters for selected group of adcs, see conf_counter_adc_select
|-
| 0x470..0x4AF || counters_bsc64[63:0] || ROL || 0x5bc13541 (12Oct18_16:58) || 64 counters for the BSC bars
|-
|}

== additional registers ==

<pre>
reg | rw/ro | quartus name | firmware | description
0x60: param_out <= {2'h3, par_id, chan, cb_control_out
0x61: param_out <= {2'h3, par_id, chan, cb_status
0x62: param_out <= {2'h3, par_id, chan, cb_invert_a_out };
0x63: param_out <= {2'h3, par_id, chan, cb_invert_b_out };
0x64: param_out <= {2'h3, par_id, chan, cb_enable_le_a_out };
0x65: param_out <= {2'h3, par_id, chan, cb_enable_le_b_out };
0x66: param_out <= {2'h3, par_id, chan, cb_enable_te_a_out };
0x67: param_out <= {2'h3, par_id, chan, cb_enable_te_b_out };
0x6A | ro | cb_input_num | 0x618b790b | chronobox number of inputs
0x6B: param_out <= {2'h3, par_id, chan, cb_sync_mask_a_out };
0x6C: param_out <= {2'h3, par_id, chan, cb_sync_mask_b_out };
0x6D: param_out <= {2'h3, par_id, chan, cb_sync_reg_out };
0x6E: param_out <= {2'h3, par_id, chan, cb_sync_status };
0x6F: param_out <= {2'h3, par_id, chan, cb_latch_period_out };
0x70: param_out <= {2'h3, par_id, chan, cb_fifo_status };
0x71: begin param_out <= {2'h3, par_id, chan, cb_fifo_data }; cb_fifo_rdack_out <= 1; end
0x72: param_out <= {2'h3, par_id, chan, cb_udp_period_out };
0x73: param_out <= {2'h3, par_id, chan, cb_udp_threshold_out };
</pre>

== conf_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_clock_select || 0x5b3aa19f (02Jul18_15:05) || select 0=internal 62.5 MHz clock or 1=esata 62.5 MHz clock
|-
| 1 || conf_enable_aw_adc16 || 0x5baedfca (28Sep18_19:13) || select source of TPC AW aw16 bus, see [[#aw16 bus]]
|-
| 2 || conf_enable_aw_adc32a || 0x5baedfca (28Sep18_19:13) ||
|-
| 3 || conf_enable_aw_adc32b || 0x5baedfca (28Sep18_19:13) ||
|-
| 15..4 || || ||
|-
| 23..16 || conf_mlu_prompt || 0x5b3aa19f (02Jul18_15:05) || MLU trigger prompt window, see [[#aw16_mlu]]
|-
| 31..24 || conf_mlu_wait || 0x5b3aa19f (02Jul18_15:05) || MLU trigger wait window, see [[#aw16_mlu]]
|-
|}

== conf_mlu bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 31 || mlu_reset || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 30 || mlu_write || 0x5b3aa19f (02Jul18_15:05) || 1=write data bit into given address
|-
| 16 || mlu_data || 0x5b3aa19f (02Jul18_15:05) || data bit for writing to MLU RAM
|-
| 15..0 || mlu_write_addr || 0x5b3aa19f (02Jul18_15:05) || MLU RAM write address for writing the data bit
|-
|}

== conf_bsc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_bsc_adc_a || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 0..7
|-
| 1 || conf_bsc_adc_b || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 8..15
|-
| 2 || conf_bsc64_bot_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses bottom channels only
|-
| 3 || conf_bsc64_top_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses top channels only
|-
| 4 || conf_bsc64_bot_top_or || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "or" of top and bottom
|-
| 5 || conf_bsc64_bot_top_and || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "and" of top and bottom
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_bsc64_mult_min || 0x5bc13541 (12Oct18_16:58) || minimum bsc64 multiplicity
|-
| 23..16 || conf_bsc64_mult_max || 0x62c77f0b || maximum bsc64 multiplicity
|-
| 31..24 || conf_bsc64_mult_window || 0x62c77f0b || bsc64 multiplicity window length, 8 ns clocks
|-
|}

== conf_coinc_control bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_coinc_required[0] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mult_1ormore
|-
| 0 || conf_coinc_required[0] || 0x62c77f0b || enable aw16_grand_or
|-
| 1 || conf_coinc_required[1] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mlu_trig
|-
| 2 || conf_coinc_required[2] || 0x5bc13541 (12Oct18_16:58) || enable bsc_grand_or_trig
|-
| 3 || conf_coinc_required[3] || 0x5bc13541 (12Oct18_16:58) || enable bsc_mult_trig
|-
| 3 || conf_coinc_required[3] || 0x62c77f0b || enable bsc64_mult_trig
|-
| 4 || conf_coinc_required[4] || 0x5bc13541 (12Oct18_16:58) || enable esata_nim_grand_or
|-
| 5 ||
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_coinc_window[7:0] || 0x5bc13541 (12Oct18_16:58) || coincidence window length in units of 125MHz clock (8 ns)
|-
| 23..16 || conf_coinc_start[7:0] || 0x5bc13541 (12Oct18_16:58) || start the coincidence window, same bits as "required"
|-
| 31..24 ||
|-
|}

== conf_trig_enable bits ==

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_enable_sw_trigger || || trigger on software trigger (how generated???)
|-
| 1 || conf_enable_pulser || || trigger on pulser
|-
| 2 || - || 0x5b120c9f (01Jun18_20:18) || not used
|-
| 3 || conf_pulser_run || || allow the pulser to run (frequency has to be set beforehand)
|-
| 4 || conf_output_pulser || 0x5bc8f90f || does nothing (top level ag_pulser_out is disconnected)
|-
| 4 || || 0x618b790b || not used
|-
| 5 || conf_enable_esata_nim || || trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand)
|-
| 6 || conf_enable_adc16 || || trigger on adc16_grand_or
|-
| 7 || conf_enable_adc32 || || trigger on adc32_grand_or
|-
| 8 || conf_enable_adc16_1ormore || || trigger on adc16_mult_1ormore "1 or more"
|-
| 9 || conf_enable_adc16_2ormore || || same, "2 or more"
|-
| 10 || conf_enable_adc16_3ormore || || same, "3 or more"
|-
| 11 || conf_enable_adc16_4ormore || || same, "4 or more"
|-
| 12 || - || 0x5b08938c (25May18_15:51) || not used
|-
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
|-
| 14 || - || 0x5bc8f90f || not used
|-
| 15 || conf_enable_adc || 0x5b120c9f (01Jun18_20:18) || trigger on adc_grand_or
|-
| 16 || conf_enable_aw16_coinc_a || 0x5bc8f90f || enable AW coincidence trigger, see [[#aw16_coinc]]
|-
| 16 || - || 0x62c77f0b || aw16_coinc_x removed
|-
| 17 || conf_enable_aw16_coinc_b || 0x5bc8f90f ||
|-
| 18 || conf_enable_aw16_coinc_c || 0x5bc8f90f ||
|-
| 19 || conf_enable_aw16_coinc_d || 0x5bc8f90f ||
|-
| 20 || - || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 20 || conf_enable_aw16_grand_or || 0x618b790b || enable trigger on aw16_grand_or
|-
| 21 || conf_enable_aw16_coinc || 0x5b3aa19f (02Jul18_15:05) || enable trigger on aw16_coinc_trig
|-
| 22 || conf_enable_aw16_mlu || 0x5b3aa19f (02Jul18_15:05) || enable AW MLU trigger
|-
| 23 || conf_enable_timeout_trig || 0x5bc8f90f (18Oct18_14:20) || enable trigger timeout trigger
|-
| 24 || conf_enable_aw16_1ormore || 0x5b3aa19f (02Jul18_15:05) || trigger on aw16_mult_1ormore "1 or more"
|-
| 24 || - || 0x62c77f0b || aw16_mult_xxx removed
|-
| 25 || conf_enable_aw16_2ormore || 0x5b3aa19f (02Jul18_15:05) || same, "2 or more"
|-
| 26 || conf_enable_aw16_3ormore || 0x5b3aa19f (02Jul18_15:05) || same, "3 or more"
|-
| 27 || conf_enable_aw16_4ormore || 0x5b3aa19f (02Jul18_15:05) || same, "4 or more"
|-
| 28 || conf_enable_bsc_grand_or || 0x5bc13541 (12Oct18_16:58) || trigger on BSC grand-or
|-
| 29 || conf_enable_bsc_mult || 0x5bc13541 (12Oct18_16:58) || trigger on BSC multiplicity
|-
| 30 || conf_enable_coinc || 0x5bc13541 (12Oct18_16:58) || trigger on TPC/BSC/ext coincidence trigger
|-
| 31 || - || || not used
|-
|}

== reg 0x2B bits ==

Write to this register will pulse corresponding fpga signals:

{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || reset_out || 0x5b120c9f (01Jun18_20:18) || reset counters, etc
|-
| 1 || latch_out || 0x5b120c9f (01Jun18_20:18) || latch counters, sas bits, etc
|-
| 2 || trigger_out || 0x5b120c9f (01Jun18_20:18) || generate a software trigger
|-
|}

= UDP data format =

== firmware 0x5bc8f90f ==

{| cellpadding="10" cellspacing="0" border="1"
! Offset || Name || Quartus name || FwRev || Description
|-
| 0 || packet counter || none || all || 31-bit UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
|-
| 1 || 0x8 packet header || || all || 28 bits of counter_trig_out
|-
| 2 || trigger timestamp || trig_ts || all || 62.5MHz trigger timestamp
|-
| 3 || accepted triggers || counter_trig_out || all || counter of accepted triggers
|-
| 4 || input triggers || counter_trig_in || all || counter of trigger input
|-
| 5 || pulser triggers || counter_pulser || all || counter of pulser triggers
|-
| 6 || trigger bitmap || udp_trig_bits || 0x5a48448d (30Dec17_17:59) || bitmap of trigger information, see below
|-
| 7 || nim bits || udp_nim_bits_masked || ??? || 32 bits of ADC NIM inputs (2 bits per ADC)
|-
| 8 || esata bits || udp_esata_bits_masked || ??? || 32 bits of ADC ESATA inputs (2 bits per ADC)
|-
| 9 || mlu bits || aw16_prompt || 0x5b398983 (01Jul18_19:10) || 16 bits of MLU input, 1 bit per preamp
|-
| 10 || drift-blank-off counter || udp_drift_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the drift blank-off
|-
| 11 || scaledown counter || udp_scaledown_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the scaledown
|-
| X || || || ||
|-
| 12 || 0xE packet footer || || all || 28 bits of counter_trig_out
|-
|}

== firmware 0x618b790b (Nov 2021) ==

<pre>
0 udp_data_out <= {4'h8,udp_counter_trig_out[27:0]};
1 udp_data_out <= udp_trig_ts_625;
2 udp_data_out <= udp_counter_trig_out;
3 udp_data_out <= udp_counter_trig_in;
4 udp_data_out <= udp_counter_pulser;
5 udp_data_out <= udp_trig_bits;
6 udp_data_out <= udp_nim_bits;
7 udp_data_out <= udp_esata_bits;
8 udp_data_out <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
9 udp_data_out <= udp_counter_drift;
10 udp_data_out <= udp_counter_scaledown;
11 udp_data_out <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
12 udp_data_out <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
13 udp_data_out <= { udp_bsc64_bus[31:0]};
14 udp_data_out <= { udp_bsc64_bus[63:32]};
15 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
16 udp_data_out <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
17 udp_data_out <= {4'hE,udp_counter_trig_out[27:0]};
</pre>

== trigger bitmap ==

Firmware ??? (one of the very early revisions)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= adc16_coinc_top;
udp_trig_bits[5] <= adc16_coinc_bot;
udp_trig_bits[6] <= adc16_coinc;
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
udp_trig_bits[31:24] <= mult16[7:0];

</pre>

Firmware 0x5b08938c (25May18_15:51)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= 0; // not used
udp_trig_bits[31:24] <= mult16[7:0];
</pre>

Firmware 0x5b217dc4 (13Jun18_13:25)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5b3aa19f (02Jul18_15:05)

<pre>
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= udp_mlu_out;
udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>

Firmware 0x5bc8f90f (18Oct18_14:20)

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_run_pulser
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = 0; // not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x618b790b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = aw16_coinc_a;
assign trig32_in[17] = aw16_coinc_b;
assign trig32_in[18] = aw16_coinc_c;
assign trig32_in[19] = aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = aw16_mult_1ormore;
assign trig32_in[25] = aw16_mult_2ormore;
assign trig32_in[26] = aw16_mult_3ormore;
assign trig32_in[27] = aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

Firmware 0x62c77f0b

<pre>
udp_trig_bits <= trig32_in;
assign trig32_in[0] = sw_trigger; // software trigger
assign trig32_in[1] = 0; // not used pulser trigger
assign trig32_in[2] = 0; // not used conf_enable_sas_or
assign trig32_in[3] = 0; // not used conf_pulser_run
assign trig32_in[4] = 0; // not used conf_output_pulser
assign trig32_in[5] = esata_nim_grand_or;
assign trig32_in[6] = adc16_grand_or;
assign trig32_in[7] = adc32_grand_or;
assign trig32_in[8] = adc16_mult_1ormore;
assign trig32_in[9] = adc16_mult_2ormore;
assign trig32_in[10] = adc16_mult_3ormore;
assign trig32_in[11] = adc16_mult_4ormore;
assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
assign trig32_in[13] = 0; // not used conf_enable_udp
assign trig32_in[14] = 0; // not used conf_enable_busy
assign trig32_in[15] = adc_grand_or;
assign trig32_in[16] = 0; // aw16_coinc_a;
assign trig32_in[17] = 0; // aw16_coinc_b;
assign trig32_in[18] = 0; // aw16_coinc_c;
assign trig32_in[19] = 0; // aw16_coinc_d;
assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
assign trig32_in[21] = aw16_coinc_trig;
assign trig32_in[22] = aw16_mlu_trig;
assign trig32_in[23] = timeout_trig;
assign trig32_in[24] = 0; // aw16_mult_1ormore;
assign trig32_in[25] = 0; // aw16_mult_2ormore;
assign trig32_in[26] = 0; // aw16_mult_3ormore;
assign trig32_in[27] = 0; // aw16_mult_4ormore;
assign trig32_in[28] = bsc_grand_or_trig;
assign trig32_in[29] = bsc64_mult_trig;
assign trig32_in[30] = coinc_trig;
assign trig32_in[31] = 0; // not used
</pre>

= TRG chronobox inputs =

from trg_firmware/toplevel/grifc.v

<pre>
localparam CB_N = 23;
localparam CB_N1 = CB_N-1;

wire [CB_N1:0] cb_xinputs_async;

assign cb_xinputs_async[0] = ag_trig_out;
assign cb_xinputs_async[1] = ag_trig_scaledown_out;
assign cb_xinputs_async[2] = ag_trig_drift_out;
assign cb_xinputs_async[3] = ag_trig_received_out;

assign cb_xinputs_async[4] = ag_cb_sw_trig;
assign cb_xinputs_async[5] = ag_cb_pulser_trig;
assign cb_xinputs_async[6] = ag_cb_esata_nim_trig;
assign cb_xinputs_async[7] = ag_cb_adc16_grand_or_trig;
assign cb_xinputs_async[8] = ag_cb_adc32_grand_or_trig;

assign cb_xinputs_async[9] = ag_cb_aw16_grand_or_trig;
assign cb_xinputs_async[10] = ag_cb_aw16_mult_1ormore;
assign cb_xinputs_async[11] = ag_cb_aw16_mult_2ormore;
assign cb_xinputs_async[12] = ag_cb_aw16_mult_3ormore;
assign cb_xinputs_async[13] = ag_cb_aw16_mult_4ormore;
assign cb_xinputs_async[14] = ag_cb_aw16_mlu_trig;

assign cb_xinputs_async[15] = ag_cb_bsc64_grand_or_trig;
assign cb_xinputs_async[16] = ag_cb_bsc64_mult_1ormore;
assign cb_xinputs_async[17] = ag_cb_bsc64_mult_2ormore;
assign cb_xinputs_async[18] = ag_cb_bsc64_mult_3ormore;
assign cb_xinputs_async[19] = ag_cb_bsc64_mult_4ormore;
assign cb_xinputs_async[20] = ag_cb_bsc64_mult_trig;

assign cb_xinputs_async[21] = ag_cb_coinc_trig;

assign cb_xinputs_async[22] = ag_cb_timeout_trig;
</pre>

= Example UDP packets =

* trigger data, marker words 0x8

<pre>
ReadDataThread read 76
0: 0x003666ed -- UDP packet counter from UDP transmitter
1: 0x80000bf8 -- 0x8 is trigger data packet, 0xbf8 is the trigger counter from alphag.v
2: 0x2edf8b41 -- trigger data
3: 0x00000bf8
4: 0x00000bf8
5: 0x00000bee
6: 0x00000001
7: 0x00000000
8: 0x00000000
9: 0x00000003
10: 0x00000bf8
11: 0x00000bf8
12: 0x00000000
13: 0x00000000
14: 0x00000000
15: 0x00000000
16: 0x00000000
17: 0x00000000
18: 0xe0000bf8 -- 0xE is end of trigger data, counter 0xbf8 must match the counter in the 0x8 word.
ReadDataThread read 76 -- next packet
0: 0x003666ee -- UDP packet counter from UDP transmitter
...
</pre>

* chronobox fifo data, marker word 0xC, see [[Chronobox#FIFO_data_format]]

<pre>
ReadDataThread read 404
0: 0x003658ed -- UDP packet counter from UDP transmitter
1: 0xc000eacc -- 0xC is FIFO data, fifo packet counter 0xeacc from fifo_to_udp.v
2: 0x00000061 -- FIFO status, low bits the the word counter, so up to 0x61 fifo words are to follow
3: 0x87fb3d72 -- tsc hits
4: 0x8ffb3d74
5: 0x90fb3d74
6: 0x91fb3d74
7: 0x92fb3d74
8: 0x93fb3d74
9: 0x93fb3d75
10: 0x94fb3d74
11: 0x94fb3d77
12: 0x87fb3d77
13: 0x8ffb3d77
14: 0x90fb3d77
15: 0x91fb3d77
16: 0x92fb3d77
17: 0xfe000018 -- 0xFE scaler data starts, 0x18 words to follow
18: 0x00000000
19: 0x00000000
20: 0x00000000
21: 0x00000000
22: 0x00000000
23: 0x00000000
24: 0x00000000
25: 0x00000108
26: 0x00000000
27: 0x00000000
28: 0x00000000
29: 0x00000000
30: 0x00000000
31: 0x00000000
32: 0x00000000
33: 0x00000108
34: 0x00000108
35: 0x00000108
36: 0x00000108
37: 0x00000108
38: 0x00000108
39: 0x00000000
40: 0x00000000
41: 0xce56fa93 -- last word of scaler data is the sysclock counter (125 MHz)
42: 0xff800048 -- timestamp wraparound
43: 0x8f1f36e4 -- tsc hits
44: 0x901f36e4
45: 0x911f36e4
46: 0x921f36e4
47: 0x931f36e4
48: 0x941f36e4
49: 0x871f36e4
50: 0x871f36e7
51: 0x8f1f36e7
52: 0x901f36e9
53: 0x911f36e7
54: 0x921f36e9
55: 0x931f36e7
56: 0x941f36e9
57: 0x904330ac
58: 0x914330ac
59: 0x924330ac
60: 0x934330ac
61: 0x934330ad
62: 0x944330ac
63: 0x944330ad
64: 0x874330ac
65: 0x874330ad
66: 0x8f4330ac
67: 0x8f4330ad
68: 0x904330ad
69: 0x914330ad
70: 0x924330ad
71: 0x8f672a62
72: 0x90672a62
73: 0x91672a62
74: 0x92672a62
75: 0x93672a62
76: 0x94672a62
77: 0x87672a62
78: 0x87672a65
79: 0x8f672a65
80: 0x90672a65
81: 0x91672a65
82: 0x92672a65
83: 0x93672a65
84: 0x94672a65
85: 0xff000049
86: 0x878b2422
87: 0x8f8b2424
88: 0x908b2424
89: 0x918b2424
90: 0x928b2424
91: 0x938b2424
92: 0x938b2425
93: 0x948b2424
94: 0x948b2427
95: 0x878b2427
96: 0x8f8b2427
97: 0x908b2427
98: 0x918b2427
99: 0x928b2427
100: 0xe000eacc -- 0xE is end of fifo data, counter 0xeacc must match the counter in the 0xC word.
ReadDataThread read 344 -- next packet
...
</pre>

= TODO =

* add FwRev to the UDP data output
* RJ45 SFP: PROBLEM, D.A. CABLE: GOOD, Fiber SFP: ???. fix "write did not happen" (send udp write command, there is no reply, read returns old data as if write never happened). suspect udp "write" packet is lost?
* PROBLEM GONE Aug 2021. fix reply to wrong socket - udp packets should reply to same socket as they came from, udp data packets should be sent to same socket as requested them, not same socket as last command.
* DONE 2021jul30. add fixes from Chris P. for the auto-negotiation and dhcp (see email from him).
* DONE flash chip connected to FPGA. Aug 2021. implement ethernet flash programmer
* DONE Aug 2021. updated maxv firmware. implement FPGA reboot
* speed up programming the MLU by writing more than 1 bit at a time
* add 64-bit bitmap of BSC trigger bits
* DONE. add chronobox code
* DONE. add avalon mux for alphag and chronobox packets
* DONE. add chronobox fifo to udp packet sequencer
* check that TxReadyOut is correct and it is safe to send an avalon packet while previous packet is still transmitting.
* test fiber SFP is working
* complete the UDP flash programmer (parallel flash erase and write)

= End =

//KO