View source for PWB

= Links =

* https://bitbucket.org/expalpha/pwb_rev1_firmware
* https://edev-group.triumf.ca/fw/exp/alphag/feam/rev1
* https://edev-group.triumf.ca/hw/alphag/feam/rev1
* https://ladd00.triumf.ca/daqinv/frontend/list/170 - PWB inventory database

= Schematics =

* [[Image:pwb_rev0.pdf]]
* [[Image:Pwb-rev1-after.pdf]]
* [[Image:AlphaG Rev1.pdf]]

= Manuals =

* [[Image:AFTER_MANUAL_V1.pdf]] AFTER SCA manual v1
* [[Image:AFTER_DataSheet1_1.pdf]] AFTER SCA manual v1.1
* [[Image:AFTER_SCA_table2.pdf]] AFTER SCA channel map

= Hardware =

== Power distribution and monitoring ==

External power supply is:
* +5V
* +2V

Central board:

* Ext_5V - F1 - RS1 (0.1R) - Fuse_5V
* Ext_2V - F2/F3 - RS2 (0.1R) - Idig2-
* LDO3 - Fuse_5V - DIG_3.3V - selfenable - ADM7154
* LDO5 - Fuse_5V - DIG_2.5V - selfenable - ADM7154
* LDO_CLN - Fuse5V - CLN_3.3V - selfenable - 
* VREG - DIG_3.3V - -2.5V SCA BIAS - selfenable - LTC1983ES6-3#TRMPBF
* LDO7 - DIG_2.5V - DDR3_VRef - enable DDR3_1P5V, DDR3_PG, DDR3_VttEN
* LDO2 - Idig2V- - DIG_1.1V - enable DIG_3.3V - LT3071
* LDO6 - Idig2V- - DDR3_1P5V - enable DIG_3.3V - LT3083

SCA Wing:

* Ext_5V - F1 - RS1 (0.3R) - Isca- - SCA_Fuse5V
* LDO1 - SCA_Fuse5V - SCA3.3V - enable ADC_PWR_EN - ADM7154
* LDO2 - SCA3.3V - ADC1.8V - selfenable - ADM7154
* LDO3 - SCA3.3V - TRN2.5V - selfenable - LT1761
* REF - SCA3.3V - 1.45V Vicm - selfenable - LM4121

esper variables:

* board/i_sca12, i_sca34, v_sca12, v_sca34: voltage and current into LDO1, after fuse F1 (wing board)
* board/i_p2, v_p2: voltage and current on 2V bus after fuses F2/F3
* board/i_p5, v_p5: voltage and current on 5V bus after fuse F1 (central board)

== Trigger and Clock distribution ==

Clock (62.5MHz) and trigger are distributed to the PWB columns via the [https://edev-group.triumf.ca/hw/alphag/trigger-card-sata-adapter/rev1 trigger SATA adapter].

The two miniSAS cables from cdm03 port 5 and 6 are connected to a miniSAS-SATA splitter 1-to-4 (CS Electronics "iSAS SATA adapter" ADP-887P-1X). Since there are only 8 columns and the clock and trigger signals are daisy-chained across the 8 rows, this scheme is sufficient to provide the necessary inputs to all 64 PWBs.

[https://www.techcable.com/sas-mini-sas-cables/sata-cables/ SATA 6Gb/s Cable with Latching Clip. Straight Pinout 1-1 247726-L  40in]

== Optical Link ==

Main data uplink.

SFP (Small Form Pluggable) Avago Technologies AFBR-57M5APZ [[File:AVAGO SFP specs.pdf|SFP (Small Form Pluggable) Avago Technologies AFBR-57M5APZ]]

Fiber optic Tripp Lite N820 - 10 m [[File:FiberOptic TrippLite specs.pdf|Fiber optic Tripp Lite N820 - 10 m]]

== SATA Link ==

Secondary data uplink, capable also to deliver clock and trigger.

The SATA link connects PWB from adjacent columuns on the same row.

The SATA cable is a "crossed cable".

= Firmware =

== Firmware update ==

PWB firmware update is done using "esper-tool".

<pre>
esper-tool -v upload -f file.rpd http://pwbNN update factory_rpd
esper-tool -v upload -f file.rpd http://pwbNN update file_rpd
</pre>

As of PWB firmware pwb_rev1_20200706_ko:

Permission to write into the flash memory is controlled by esper variables:

* allow_write set to "false": "esper-tool upload" does a "verify": successful upload means epcq flash content is same as rpd file, error means content is not the same.
* allow_write set to "true": "esper-tool upload" updates the epcq flash from the rpd file: for each data block, read the epcq flash, compare to rpd data, if different, erase the flash block, write the flash, read the flash, if there is a mismatch (bad write), return an error.
* allow_factory_write set to "true" to enable writing to the "factory_rpd". DO NOT SET IT TO "true" UNLESS YOU MEAN TO UPDATE THE PWB BOOTLOADER. IF YOU FLASH BUM FIRMWARE or IF THERE IS A POWER OUTAGE WHILE UPDATING, THE PWB WILL BE BRICKED and has to be recovered by connecting a USB blaster.

To update firmware of multiple boards to correct version, recommended is the script "update_pwb.perl":
<pre>
cd ~/online/src
./update_pwb.perl pwb12 pwb06 pwb78
</pre>

== Factory page and user page firmware boot ==

Each PWB board has 2 firmware images: boot loader (factory page)
and data acquisition (user page). On power up, the FPGA loads and runs
the boot loader firmware from the factory page, later the control
software reboots the FPGA into the data acquisition firmware from
the user page.

Because loading defective firmware can brick https://en.wikipedia.org/wiki/Brick_(electronics)
the PWB, new firmware images are loaded into the user page, if anything is wrong,
the PWB can still boot from the factory page and one can use the firmware update
function to load a good firmware image into the user page.

The boot loader firmware in the factory page is not intended for data acquisition, it is only meant to provide three functions:
* boot enough hardware and software to communicate via the ethernet and the sata link
* firmware update (both factory page and user page)
* reboot into the user page

The boot loader firmware in the factory page is usually never updated unless absolutely
needed to fix a problem with these three functions (i.e. compatibility with sata link communications).

If factory image is corrupted or the contains defective firmware and the PWB does not boot (no dhcp, no ping, no esper),
the only way to unbrick it is by loading good firmware using a jtag flash programmer (usb-blaster). Connecting it requires
physical access to the jtag connector on the PWB board. It is impossible when the detector is fully assembled in the experiment.

The PWB has a 32 Mbyte EPCQ flash memory chip, it is divided into 2 pages 16 Mbytes of factory page and 16 Mbytes of user page.

A complete firmware image generally contains 3 pieces:
* FPGA firmware and NIOS "feam_bootloader" software RAM image (sof file)
* NIOS "feam" software RAM image (feam.elf.flash.hex) - all the C code for esper communications and PWB data acquisition
* NIOS filesystem image (feam.webpkg.hex) - esper web pages

This is the boot sequence:
* on power-up the FPGA automatically loads the sof file from address 0 of the EPCQ flash (this is the factory image sof file)
* the FPGA is "started"
* the NIOS CPU starts executing the "feam_bootloader" C code embedded in the sof file (NIOS project hdl/software/feam_bootloader)
* feam_bootloader initializes the hardware (clocks, DDR memory, etc)
* feam_bootloader write-protects the EPCQ flash memory
* feam_bootloader copies the "feam" software from EPCQ flash to the DDR memory (after checking for correct checkum)
* feam_bootloader restarts the NIOS CPU
* the NIOS CPU starts running from DDR memory, executes the "feam" software (NIOS project hdl/software/feam)
* call main() in hdl/software/feam/src/task_init.c
* call task_init() in the same file
* infinite loop waiting for IP address via DHCP
* after have IP address, call task_esper() from hdl/software/feam/src/task_esper.c
* task_esper() creates all the esper modules, esper variables, etc,
* mod_http.c starts the mongoose web server
* PWB is open for business

This is the protection against booting corrupted firmware:
* FPGA hardware loads the sof file from epcq flash and checks for correct checksum before "starting" it
* NIOS CPU is part of the sof file, protected by sof file checksum
* NIOS feam_bootloader C code is part of the sof file, protected by the sof checksum
* feam_bootloader checks for correct signatures and checksums of the DDR memory image
* "feam" C code is protected by the checksum of the DDR memory image

== NIOS terminal ==

<pre>
$ ssh agmini@daq16
$ /opt/intelFPGA/16.1/quartus/bin/jtagconfig
1) USB-Blaster [2-1.2]
  02B030DD   5CGTFD7(B5|C5|D5)/5CGXBC7B6/..
$ /opt/intelFPGA/17.0/quartus/bin/nios2-terminal
nios2-terminal: connected to hardware target using JTAG UART on cable
nios2-terminal: "USB-Blaster [2-1.2]", device 1, instance 0
nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)
PWB Revision 1 Boot Loader
Ver 2.0  Build 357 - Wed Jun  6 15:05:35 PDT 2018
...
</pre>

== Flash boot loader firmware via jtag ==

<pre>
$ ssh agmini@daq16
$ /opt/intelFPGA/16.1/quartus/bin/jtagconfig
1) USB-Blaster [2-1.2]
  02B030DD   5CGTFD7(B5|C5|D5)/5CGXBC7B6/..
$ cd ~/online/firmware/pwb_rev1
$ ls -l
$ /opt/intelFPGA/17.1/quartus/bin/quartus_pgmw
... auto detect
... load the jic file
... in menu tools->programmer, enable "unprotect device"
... start program/configure operation
</pre>

== Flash user page firmware via esper-tool ==

<pre>
$ ssh agmini@daq16
$ cd online/src
$ more update_pwb.perl ### check that $fw is set to the desired firmware file
$ ./update_pwb.perl pwb06 ### or give more PWB names or give "all"
</pre>

== Build firmware ==

=== quartus version to use ===

* quartus 16.1 should be used for jtag (jtagconfig and jtagd)
* quartus 17.0 should be used to build the PWB firmware (17.1 is not compatible)

=== start license server ===

<pre>
ssh agmini@daq16
/opt/intelFPGA/17.0/quartus/linux64/lmgrd -c ~agmini/online/license-daq16.dat
</pre>

=== prepare the build environment ===

<pre>
$ ssh agmini@daq16
$ /opt/intelFPGA/17.0/nios2eds/nios2_command_shell.sh
</pre>

=== get latest version of the code and build it ===

<pre>
$ cd online/firmware/git/pwb_rev1_firmware
$ git pull
$ git checkout alphag
$ git pull
$ ./scripts/compile_project.sh
... about 30-40 minutes ...
$ ls -l bin/*.sof bin/*.jic bin/*.rpd
-rw-r--r-- 1 agmini alpha 12727389 Jan 24  2018 bin/feam_rev1_auto.rpd
-rw-r--r-- 1 agmini alpha 33554661 Jan 24  2018 bin/feam_rev1.jic
-rw-r--r-- 1 agmini alpha  6974754 Jan 24  2018 bin/rev1.sof
$ ### feam.jic is loaded via jtag
$ ### feam_auto.rpd is loaded via esper
$ ### feam.sof is used to attach the quartus signal tap logic analyzer
</pre>

=== firmware build order and sequence ===

* erase previous build
* regenerate qsys
* regenerate NIOS BSP "feam_bootloader_bsp" and "feam_bsp"
* build NIOS projects "feam_bootloader" and "feam"
* build quartus sof file (with the "feam_bootloader" nios project inside)
* build jic and rpd files (with the quartus sof file and the "feam" nios project inside)
* load sof file into the FPGA using jtag (be careful about compatible "feam" nios project already in the epcq flash)
* load jic file into the epcq factory page using jtag (cycle power for them to take effect)
* load rpd file into the epcq factory or user page using esper

=== scripts for building the firmware ===

* scripts/compile_project.sh - build everything from scratch:
* scripts/compile_qsys.sh - regenerate the main qsys component
* scripts/compile_nios.sh - regenerate the BSPs, then same as compile_elf.sh
* scripts/compile_elf.sh - build the BSPs, "feam_bootloader" and "feam" NIOS projects
* scripts/update_elf.sh - regenerate the rpd and jic files to include the new "feam" NIOS build (keeps the old "feam_bootloader" in the sof file)
* scripts/update_bootloader.sh - also regenerate the sof file to include the new "feam_bootloader" build
* scripts/clean_quartus.sh - prepare quartus fpga sof file to build from scratch
* scripts/compile_quartus.sh - build the quartus fpga sof file incrementally (run clean_quartus.sh to build from scratch).
* scripts/load_jtag_sof.pl bin/rev1.sof - load sof file into the FPGA. this will boot the new fpga firmware, the new feam_bootloader (if update_bootloader.sh was run), but with the old "feam" already in epcq flash. (beware of incompatible sof, "feam_bootloader" and "feam" builds!)
* scripts/load_jtag_jic.pl bin/feam_rev1.jic - load jic file into the EPCQ flash, same as using the graphical flash programmer tool. (this will leave the FPGA running the quartus jtag flash loader firmware, not the PWB firmware. Cycle power for new jic file to take effect).

== ESPER Variables ==

* Board
** invert_ext_trig - invert trigger signal from CDM before it drives any logic (to undo incorrect signal polarity)
** reset_nios - goggle up, them down to reset NIOS subsystem

* Signalproc
** test_mode - ADC data is replaced with a test pattern, see test mode bits in sca_x_ch_ctrl.
** sca_a_ch_ctrl, sca_b_ch_ctrl, sca_c_ch_ctrl, sca_d_ch_ctrl - channel control bits:
<pre>
11..0 - threshold - channel suppression threshold
14..12 - ctrl_test_mode - test mode:
         0=fixed patter 0xa5a,
         1=time bin counter,
         2=time bin counter with channel number,
         3=sequential adc sample counter,
         4={ch_crossed_out,trig_pos,trig_neg,adc[8:0]},
         5={trig,adc[10:0]},
         6={ch_crossed_min,adc[10:0]}
15 - ctrl_supp_mode - channel suppression mode: 0=adc<=(baseline-threshold), 1=adc<=threshold
</pre>

* Link
** link_ctrl - sata link control. The bits are:
<pre>
0 - sata_link_udp_stream_in_enable - permit data flow from sata link to OFFLOAD_SATA
1 - udp_stream_out_enable - permit sca data flow to sata link
2 - sata_to_eth_enable - permit ethernet data flow from sata link to TSE_MAC
3 - eth_to_sata_enable - permit ethernet data flow from TSE MAC to sata link
4 - enable_stop_our_tx - enable flow control: allow stop_tx
#5 - stop_our_tx - manually activate the flow control signal into link_tx
6 - enable_stop_remote_tx - enable flow control: allow send "stop_tx"
#7 - stop_remote_tx - manually activate the flow control signal into link_tx
8 - tx_test_pattern_udp - udp data is replaced by test pattern 0x11111111, 0x22222222, etc.
9 - tx_test_pattern_eth - nios-to-sata data is replaced by test pattern 0x11111111, 0x22222222, etc.
10 - udp_delay_enable - delay between udp packets, see udp_delay_value below
11 - reboot_tx - send K_REBOOT command to the sata link mate, where it has same effect as board/reset_nios.
12 - sata_to_nios_disable
13 - nios_to_sata_disable
14 - 
15 - 
16 -
24..31 - udp_delay_value - delay between udp packets (top 8 bits of a 20-bit counter)
</pre>

== Firmware data path ==

Main data path:
<pre>
feam_top
|
sca_sigproc
|
sca_event_control
4 * sca_control (sca_channel.sv)
4 * channel_fifo (1024 samples)
</pre>
<pre>
sca_control (sca_channel.sv)
|
state machine to control SCA read and write enables
|
sca_write_control (what does it do?!?)
sca_read_control
</pre>
<pre>
sca_read_control
|
state machine to store ADC samples into per-channel FIFOs (channel_fifo)
selector to replace ADC samples with a test pattern
79*sca_trig_one -> ch_crossed_out - channel hit detector
</pre>
<pre>
sca_event_control
|
event_fifo (hdl/mf/event_descriptor_fifo)
state machine to take ADC data from 4 per-channel FIFOs (channel_fifo) and store it into DDR memory (write addr increment is 510*8 (number of samples)*8 = 4080).
state machine to read transposed ADC data from DDR memory (read addr increment is 8+8=16 - 2 samples * 2 bytes * 4 sca = 16) and create 4 per-sca data streams
</pre>
<pre>
data stream:
4 per-sca data streams from sca_event_control -> sca_sigproc(event_dat)
|
packet_chunker (hdl/lib/packet_chunker.sv) (4*event_dat -> event_segment_dat) - multiplex 4 data streams into 1 stream of UDP-sized packets
|
packet_length_prepender (hdl/lib/packet_length_prepender.sv)  (event_segment_dat -> udp_event_val_out)
|
udp_event_val -> info qsys (udp_stream_sca) and into sata link (mux channel 2).
</pre>

== Firmware build instructions from Bryerton (obsolete) ==

This is the old README.md file from the firmware git repository.

These instructions are not used to build the firmware (use scrips/compile_project.sh).

They are still useful for figuring out which buttons to push in the altera gui programs.

<pre>
# ALPHAg FrontEnd Acquisition Module (FEAM) - REV0

Welcome to the ALPHAg FEAM Project 

# Table of Contents

* [Overview](#overview)
* [Inital Setup](#initial-setup)
    * [Quartus Setup](#quartus-setup)
        * [Create the .cdf](#create-the-cdf)
    * [NIOS Setup](#nios-Setup)
        * [Create the project files](#create-the-project-files) 
* [Build Instructions](#build-instructions)
    * [Building from Quartus GUI](#building-from-quartus-gui)
        * [Generate the QSys File](#generate-the-qsys-file)
        * [Compile the NIOSII Project](#compile-the-niosii-project)
        * [Compile the Quartus Project](#compile-the-quartus-project)
    * [Building from Scripts](#building-from-scripts)
    * [Installing from JTAG](#installing-from-jtag)
    * [Installing from ESPER](#installing-from-esper)

# Overview

The FEAM is a digitizer located on the ALPHAg detector. Each FEAM consists of 4 AFTER SCAs for a total of 288 channels.

# Initial Setup

## Quartus Setup

### Create the .cdf
1. Open Quartus Prime Standard Edition
2. Click on **Tools -> Programmer**. The **Programmer** window will appear
3. In the **Programmer** window, click **Auto Detect**. A **Select Device** dialog box will appear
    1. (Optional) If **Auto Detect** is greyed out, click on **Hardware Setup**. The **Hardware Setup** dialog box will appear
    2. Under **Hardware Settings**, double-click on the USB JTAG hardware you wish to use
    3. Click **Close**. The **Hardware Setup** dialog box will close
5. Click on **File -> Save As**. The **Save As** dialog box will appear
6. In the **Save As** dialog box, browse to the **/\<project_dir\>/bin/** directory
7. Make sure the **Add file to current project** checkbox is checked
7. In the **File name** input box, type "alphag_feam.cdf" and click **Save**
8. Close the **Programmer** window
9. Done!

## NIOS Setup

### Create the project files
1. Open Quartus Prime Standard Edition
2. Open the NIOS II Software Build Tools by clicking **Tools -> NIOS II Software Build Tools for Eclipse**
3. The **Workspace Launcher** window will appear, click *OK* to accept the default workspace.
4. Click **File -> Import...**. The **Import** dialog box will appear
5. Click on **General -> Existing Projects into Workspace**
6. Click **Next \>**
7. Next to **Select root directory** click **Browse...**. A **Browse for Folder** dialog box will appear
8. Browse to **/\<project_dir\>/hdl/software** and click **OK**
8. Four Projects should appear in the **Projects** panel: 
    * alphag_feam
    * alphag\_feam\_bsp 
    * alphag\_feam\_bootloader
    * alphag\_feam\_bootloader\_bsp
9. Click **Select All**
10. Click **Finish**
11. Done!
 
# Build Instructions

## Building from Quartus GUI

**Warning: Please use Quartus Prime Standard Edition 16.1**
### Generate the QSys File
1. Open Quartus Standard Edition 16.1
1. Open QSys by clicking **Tools -> QSys**
2. Click on **File -> Open** (CTRL+O). An **Open File** dialog box should appear.
3. Select the **alphag_feam.qsys** file from the **/\<project_dir\>/hdl** directory and click **Open**
4. Modify as necessary. NOTE: Any change to the QSys, even cosmetic such as expanding or collapsing components will cause the QSys to desire a re-generate. 
5. Click **File -> Save** (CTRL+S)
6. Click **Generate HDL**. A **Generation** dialog box will appear 
7. Select the settings you desire to be changed, if any
8. Click **Generate**
9. Wait for the generation to complete.
10. Done!

### Compile the NIOSII Project
1. Open the NIOS II Software Build Tools by clicking **Tools -> NIOS II Software Build Tools for Eclipse**
2. (Optional) If the QSys file has been re-generated performing the following
    1. Right-click on **alphag\_feam\_bsp** and select **NIOS II -> Generate BSP**. The BSP will regenerate
    2. Right-click on **alphag\_feam\_bootloader\_bsp** and select **NIOS II -> Generate BSP**. The BSP will regenerate
3. Modify files as needed. WARNING: Do not modify any BSP files by hand! All changes will be lost on next generate.
4. Click **Project -> Build All** (CTRL+B). If your workspace as multiple projects, it is recommend to close all but the ones related to the FEAM.
5. Right-click on **alphag\_feam\_bootloader** and select **Make Targets -> Build...**. The **Make Targets** dialog box will appear
6. In the **Make Targets** dialog box, select **mem\_init\_generate** and click **Build**
7. Done!

### Compile the Quartus Project
1. Open Quartus Standard Edition 16.1
1. Under **Processing** click **Start Compilation** (CTRL+L)
2. Wait about 16-30 minutes.
3. Done!
  
**Note:** If Quartus crashed while compiling, delete the **\<project_dir\>/hdl/db** and **\<project_dir\>/hdl/incremental_db** directories and try again
  
## Installing from JTAG
1. Generate the .jic file using the provided /bin/alphag\_feam\_jic.cof
    1. In the main Quartus window, click **File -> Convert Programming Files**, A **Convert Programming Files** window will appear
    2. In the **Convert Programming Files** window, click **Open Conversion Setup Data**. An **Open** dialog box will appear
    3. In the **Open** dialog box, select the **alphag_feam.cof** file located in **/bin/**
    4. Click **Open**. The **Open dialog box will close
        * Note the **File name** field, it should display /\<project\_dir\>/bin/alphag\_feam.jic
    5. In the **Convert Programming Files** window, click **Generate**
    6. When the .jic is done being generated, a small dialog box will appear, click **OK**
    7. In the **Convert Programming Files** window, click **Close**
2. Load the .JIC file using the Programmer
    1. In the main Quartus window in the **Project Navigator** drop-down input select **Files**.
    2. Scroll down the window and find the **alphag_feam.cdf**, and double-click it. The **Programmer** window will open
    3. Click on the icon labelled **5CGXFC4C6**
    4. Click on the **Change File** button. The **Select New Programming File** dialog box will appear
    5. Browse to **/\<project_dir\>/bin/** and select **alphag\_feam.jic**
    6. Click Open. The **Select New Programming File** dialog box will close
    7. In the main panel, check the **Program/Configure** box on the line that starts **./bin/alphag\_feam.jic**
    8. Click the **Start** button
    9. Wait for the **Progress** bar to go to 100% and stop
    10. Done!
</pre>

= Internal test pulser =

Documentation from Bryerton:

<pre>
---------- Forwarded message ---------
From: Bryerton Shaw <bryerton@triumf.ca>
Date: Tue, 24 Apr 2018 at 16:18
Subject: RE: PWB/FEAM internal test pulse
To: Lars Martin <lmartin@triumf.ca>
Cc: Andrea Capra <acapra@triumf.ca>


Hi Lars (and Andrea),

In the new(er) firmware the test pulse code has been modified slightly to
fit in better with the upgraded trigger system. I can add an option to
allow it to be triggered by the external trigger (currently it has an
interval option, or you can hit the manual trigger to fire it, if it’s
enabled)

The *options for the test pulser* are under the *signalproc module*:

*test_pulse_ena*

An array of four booleans, that control turning on the test pulse for each
SCA. If this is False, the other options below will do nothings for that SCA



*test_pulse_interval_ena*

An array of four booleans, that control turning on the interval trigger for
each SCA



*test_pulse_interval*

An unsigned 32-bit value that marks how many 16ns clock cycles occur
between interval triggers. Only one value, as there is only one interval
timer.



*test_pulse_wdt*

An array of four 16-bit unsigned integers that control the width of the
pulse for each SCA when the trigger occurs.



Now, there is a second set of options to control the delay of the *test
pulse interval trigger*. These options are located under the *trigger
module*




*intp_trig_ena*

Boolean value enabling/disabling the interval test pulse trigger.



*intp_trig_delay*

Unsigned 32-bit integer controlling the trigger delay, which is the time
between when the trigger is requested, and when the trigger actually fires.



You can setup the interval trigger and use that to create event packets
with the test pulse on set intervals. If the interval trigger is
insufficient, I can create another option, which is to fire the test pulse
for enabled SCAs when the external trigger goes. If so, I’ll add this
option in the *signalproc *module for you:



*test_pulse_on_ext*

An array of four Booleans, that control if the test pulse for that SCA
fires on external trigger.




Remember, in order to use the SCA test pulse at all, you must also set the
SCA to test mode. You can do this by going into the *sca0-3 modules* and
setting *test* to *functionality *(the value is *3* if you want to set it
via esper-tool)



Btw currently the SCAs are hard-coded to have all 72 channels receive the
test pulse on firing, and the option to de-select/select which channels to
fire is not offered. Would you like this ability? And if so do you want it
to set all four SCAs the same, or have an option for all 288 channels?



The waveform viewer on the webpage was removed for technical reasons, and
so all viewing is done via the MIDAS DAQ. There are some preliminary tools
I’ve created to verify the event packets and their waveforms, but I
wouldn’t call them easy to setup or use at the moment. (Or very  useful for
fine comparisons). If KO doesn’t have a way of saving the events to disk, I
could deliver something that captured and saved waveforms quite quickly.

Regards,
Bryerton


*From:* Lars Martin
*Sent:* April 23, 2018 5:10 PM
*To:* Bryerton Shaw <bryerton@triumf.ca>
*Cc:* Andrea Capra <acapra@triumf.ca>
*Subject:* PWB/FEAM internal test pulse



Hi Bryerton,

Andrea and I would like to check the response function of the PWBs. For
that Daryl suggested to first look at the internal test pulse.

Can you point us to what settings are required to make that go? And to use
the external trigger if we want to acquire the data?

Ideally we would acquire Midas data from that, but it's unclear if KO's
frontend allows for that right now. Can we access the data with Esper
instead?

Finally, we haven't had the waveform display on the web page for a while,
but Daryl said you guys use it. Are we using a different page somehow?



Hope all is well with the baby, cheers,

Lars
</pre>

= TODO =

* IMPOSSIBLE (ext clock only connected to clock cleaner) add frequency counter for the external clock (62.5 MHz)
* DONE add random delay before memtest
* DONE add 4 more bits to udp_delay
* DONE fix crash on boot if run is active and triggers arrive (check that trigger is off on boot) (do not set trigger/enable_all, ext_trig_ena, inp_trig_ena, signal_proc/force_run to 1 after boot)
* DONE (kludge jtag uart write()) increase size of jtag uart output buffer, make it unlimited if possible.
* DONE (kludge jtag uart write()) on dhcp timeout, reboot the fpga - reboot of nios does not clear the jtag uart, which becomes full and nios stops.
* DONE add NIOS watchdog timeout for fectrl
* DONE do not use external clock until instructed by fectrl (clock cleaner default is pin select mode, default pin mode is input with pull down, so clock 0 is selected, this is the ext clock. but we can drive clock select pins from the fpga).
* DONE change clock cleaner power up: use the 2 lines status_clkin0 and status_clkin1 to tell clock cleaner to use the internal clock (clkin2) - from the FPGA drive first line low, second line high. Also change all NIOS code that programs the clock cleaner to keep these two lines in the "input" mode. Current code switches them to "output" mode.
* DONE clock cleaner power up state is wrong for both choices of clock: 62.5 MHz ext clock and 125 MHz internal clock, see explanation in feam_top.sv. It looks like I need to drive status_clkin0 and status_clkin1 to "holdover" mode, both logic level 1. Currently status_clkin0 is used as SPI read line, this has to be moved to a different line first.
* add watchdog timeout that works in factory mode ("remote update" watchdog only works in user mode)
* enable HTTP pipelining - copy changes on mongoose from ADC project.
* reset everything if it looks like NIOS TCP/IP code has crashed, but enough code is still running to prevent tripping of the fpga-remote-update watchdog timer. such crash tends to happens when the sata link mate is rebooted and incomplete data arrives from the disrupted ethernet data path.
* DONE when loading AFTER ASIC do not go into infinite loop if read-back is broken (always mismatch).
* read and report error status information bits for 2983fc.pdf voltages, currents and temperatures chip
* add provisions for coded trigger
* DONE verify readout of MV2 Hall magnetometer (all registers and bits from device are visible in esper)

= ZZZ =

ZZZ