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{| cellpadding="10" cellspacing="0" border="1" | {| cellpadding="10" cellspacing="0" border="1" | ||
! Address || Quartus Name || Access || FwRev || Description | ! Address || Quartus Name || Access || FwRev || Description | ||
|- | |||
| 0x08 || num_sample || RW || GRIF-C || magic register to control UDP packet size | |||
|- | |- | ||
| 0x1F || compilation_time || RO || || Firmware revision | | 0x1F || compilation_time || RO || || Firmware revision | ||
| Line 131: | Line 133: | ||
| 0x33 || clk_625_counter || RO || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625) | | 0x33 || clk_625_counter || RO || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625) | ||
|- | |- | ||
| 0x3D || GRIF-C csr || <= csr & ~par_value; // Selective clear | | 0x3D || GRIF-C csr || RW || GRIF-C || <= csr & ~par_value; // Selective clear | ||
|- | |- | ||
| 0x3E || GRIF-C csr || <= csr | par_value; // Selective set | | 0x3E || GRIF-C csr || RW || GRIF-C || <= csr | par_value; // Selective set | ||
|- | |- | ||
| 0x3F || GRIF-C csr || <= par_value; // write | | 0x3F || GRIF-C csr || RW || GRIF-C || <= par_value; // write | ||
|- | |- | ||
| 0x100 || ts_625 || RO || || latched timestamp | | 0x100 || ts_625 || RO || || latched timestamp | ||
Revision as of 16:23, 22 June 2018
ALPHAT, the trigger control board for the ALPHA-g detector
Links
- xxx
- https://bitbucket.org/teamalphag/alphat_firmware - firmware sources on bitbucket
General characteristics
Photos
Board schematics
Available hardware
ALPHA-T front panel connections
From top to bottom:
| | minisas-C - links 8-11 | minisas-D - links 12-15 | | ethernet sfp - use copper sfp only | minisas - not used, do not connect | esata - clock in, trigger out | | minisas-A - links 0-3 | minisas-B - links 4-7 | | LEDs |
MiniSAS flail cable connections:
P1 <--> link 3 P2 <--> link 2 P3 <--> link 1 P4 <--> link 0
Firmware update procedure
- use quartus to generate the grifc.pof file (use grifc.cof)
- open quartus programmer
- attach grifc.pof to the 1st CFI_512 flash
- mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
- check that "initiate configuration after programming" is set in tools->options
- say "start"
- should take about 5 minutes
- grifc should reboot into the new firmware
If CFI_512 flash is not visible to the quartus programmer, load correct code into the MaxV CPLD:
- open quartus programmer,
- say "auto detect"
- change file for the 5M2210 device
- use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
- say "program", it should finish in 10-15 seconds
- say "auto detect"
- CFI_512 flash should be visible now.
Firmware revisions
ALPHA-g trigger functions
Trigger modes:
- software trigger
- pulser trigger
- trigger on GRIF16 ADC NIM and ESATA inputs
- adc16 grand-or
- adc32 grand-or
- adc16 multiplicity (plus adc32 multiplicity?!?)
- trigger on coincidences of ADC links
Control registers
Register addresses
Note: all registers are 32 bits unless otherwise noted.
| Address | Quartus Name | Access | FwRev | Description |
|---|---|---|---|---|
| 0x08 | num_sample | RW | GRIF-C | magic register to control UDP packet size |
| 0x1F | compilation_time | RO | Firmware revision | |
| 0x20 | conf_trig_width <= par_value; | |||
| 0x21 | conf_busy_width <= par_value; | |||
| 0x22 | conf_pulser_width <= par_value; | |||
| 0x23 | conf_pulser_period <= par_value; | |||
| 0x24 | sw_trigger_counter <= 10; | |||
| 0x24 | - | 0x5b120c9f (01Jun18_20:18) | not used | |
| 0x25 | conf_trig_enable <= par_value; | |||
| 0x26 | conf_sas_trig_mask <= par_value; | obsolete | ||
| 0x27 | conf_sas_trig_mask_a <= par_value; | obsolete | ||
| 0x28 | conf_sas_trig_mask_b <= par_value; | obsolete | ||
| 0x29 | conf_nim_mask <= par_value; | |||
| 0x2A | conf_esata_mask <= par_value; | |||
| 0x2B | reset_out, latch_out, trigger_out | pulsed | 0x5b120c9f (01Jun18_20:18) | see reg 0x2B bits |
| 0x2C | conf_coinc_a <= par_value; | |||
| 0x2D | conf_coinc_b <= par_value; | |||
| 0x2E | conf_coinc_c <= par_value; | |||
| 0x2F | conf_coinc_d <= par_value; | |||
| 0x30 | sas_sd[15:0] | RO | 0x5b120c9f (01Jun18_20:18) | sas signal detect for each link |
| 0x31 | pll_625_status | RO | 0x5b2057f5 (12Jun18_16:32) | 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter |
| 0x32 | clk_counter | RO | 0x5b2057f5 (12Jun18_16:32) | frequency counter of the system 125 MHz clock |
| 0x33 | clk_625_counter | RO | 0x5b2057f5 (12Jun18_16:32) | frequency counter of the currently selected 62.5 MHz clock (my_clk_625) |
| 0x3D | GRIF-C csr | RW | GRIF-C | <= csr & ~par_value; // Selective clear |
| 0x3E | GRIF-C csr | RW | GRIF-C | par_value; // Selective set |
| 0x3F | GRIF-C csr | RW | GRIF-C | <= par_value; // write |
| 0x100 | ts_625 | RO | latched timestamp | |
| 0x101 | counter_trig_out | RO | counter of issued triggers | |
| 0x102 | counter_trig_in | RO | counter of triggers | |
| 0x103 | counter_pulser | RO | counter of pulser | |
| 0x104 | counter_adc16_grand_or | |||
| 0x105 | counter_adc32_grand_or | |||
| 0x106 | counter_adc_grand_or | |||
| 0x107 | counter_esata_nim_grand_or | |||
| 0x108 | counter_adc16_mult_1ormore | |||
| 0x109 | counter_adc16_mult_2ormore | |||
| 0x10A | counter_adc16_mult_3ormore | |||
| 0x10B | counter_adc16_mult_4ormore | |||
| 0x10C | counter_cc01 | |||
| 0x10D | counter_cc23 | |||
| 0x10E | counter_cc45 | |||
| 0x10F | counter_cc67 | |||
| 0x200..0x207 | conf_adc16_masks | |||
| 0x300..0x30F | conf_adc32_masks | |||
| 0x400..0x41F | sas_bits[15:0][63:0] | RO | sas data bits for each link | |
| 0x420..0x42F | sas_sd_counters[15:0] | RO | 0x5b120c9f (01Jun18_20:18) | sas signal detect counter for each link |
| 0x430..0x43F | counters_adc16_or16[15:0] | RO | 0x5b120c9f (01Jun18_20:18) | 16 counters of adc16 ORes |
| 0x440..0x45F | counters_adc32_or16[31:0] | RO | 0x5b120c9f (01Jun18_20:18) | 32 counters of adc32 ORes |
remaining GRIF-C registers
14'h001: param_out <= {2'h3, par_id, chan, 16'h0, threshold };
14'h002: param_out <= {2'h3, par_id, chan, pulser_ctrl };
14'h003: param_out <= {2'h3, par_id, chan, 31'h0, polarity };
14'h004: param_out <= {2'h3, par_id, chan, 16'h0, diff_const };
14'h005: param_out <= {2'h3, par_id, chan, 16'h0, integ_const };
14'h006: param_out <= {2'h3, par_id, chan, 22'h0, decimation };
14'h007: param_out <= {2'h3, par_id, chan, 16'h0, num_pretrig };
14'h008: param_out <= {2'h3, par_id, chan, 16'h0, num_sample };
14'h009: param_out <= {2'h3, par_id, chan, 16'h0, pole_corn };
14'h00A: param_out <= {2'h3, par_id, chan, 16'h0, hitdet_integ };
14'h00B: param_out <= {2'h3, par_id, chan, 16'h0, hitdet_diff };
14'h00C: param_out <= {2'h3, par_id, chan, 16'h0, integ_delay };
14'h00D: param_out <= {2'h3, par_id, chan, 30'h0, wavebuf_mode };
14'h00E: param_out <= {2'h3, par_id, chan, trig_deadtime};
14'h00F: param_out <= {2'h3, par_id, chan, 31'h0, enable_adc };
14'h010: param_out <= {2'h3, par_id, chan, 28'h0, detectortype };
14'h011: param_out <= {2'h3, par_id, chan, sync_livetime};
14'h012: param_out <= {2'h3, par_id, chan, sync_deadtime};
conf_trig_enable bits
| Bit | Quartus Name | FwRev | Description |
|---|---|---|---|
| 0 | conf_enable_sw_trigger | trigger on software trigger (how generated???) | |
| 1 | conf_enable_pulser | trigger on pulser | |
| 2 | conf_enable_sas_or | obsolete | |
| 2 | - | 0x5b120c9f (01Jun18_20:18) | not used |
| 3 | conf_run_pulser | let the pulser run (frequency has to be set beforehand) | |
| 4 | conf_output_pulser | enable external output of pulser signal | |
| 5 | conf_enable_esata_nim | trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand) | |
| 6 | conf_enable_adc16 | trigger on adc16 grand-or | |
| 7 | conf_enable_adc32 | trigger on adc32 grand-or | |
| 8 | conf_enable_adc16_1ormore | trigger on adc16 grand multiplicity "1 or more" | |
| 9 | conf_enable_adc16_2ormore | same, "2 or more" | |
| 10 | conf_enable_adc16_3ormore | same, "3 or more" | |
| 11 | conf_enable_adc16_4ormore | same, "4 or more" | |
| 12 | conf_enable_adc16_coinc | trigger on special coincidence of adc16 links | |
| 12 | - | 0x5b08938c (25May18_15:51) | not used |
| 13 | conf_enable_udp | 0x5a7a3fbd (06Feb18_15:52) | enable sending UDP packets |
| 14 | conf_enable_busy | 0x5a7a3fbd (06Feb18_15:52) | enable activation of busy counter |
| 15 | conf_enable_adc | 0x5b120c9f (01Jun18_20:18) | trigger on adc grand-or |
| 16 | conf_enable_coinc_a | ||
| 17 | conf_enable_coinc_b | ||
| 18 | conf_enable_coinc_c | ||
| 19 | conf_enable_coinc_d | ||
| 20 | conf_clock_select | 0x5b2057f5 (12Jun18_16:32) | select internal 62.5 MHz clock or esata 62.5 MHz clock |
| 24 | conf_enable_xadc_1ormore | NEXT | trigger on AW preamp multiplicity "1 or more" |
| 25 | conf_enable_xadc_2ormore | same, "2 or more" | |
| 26 | conf_enable_xadc_3ormore | same, "3 or more" | |
| 27 | conf_enable_xadc_4ormore | same, "4 or more" |
reg 0x2B bits
| Bit | Quartus Name | FwRev | Description |
|---|---|---|---|
| 0 | reset_out | 0x5b120c9f (01Jun18_20:18) | reset counters, etc |
| 1 | latch_out | 0x5b120c9f (01Jun18_20:18) | latch counters, sas bits, etc |
| 2 | trigger_out | 0x5b120c9f (01Jun18_20:18) | generate a trigger |
UDP data format
| Offset | Name | Quartus name | FwRev | Description |
|---|---|---|---|---|
| 0 | packet counter | none | all | UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware |
| 1 | 0x8 packet header | all | 28 bits of counter_trig_out | |
| 2 | trigger timestamp | trig_ts | all | 62.5MHz trigger timestamp |
| 3 | accepted triggers | counter_trig_out | all | counter of accepted triggers |
| 4 | input triggers | counter_trig_in | all | counter of trigger input |
| 5 | pulser triggers | counter_pulser | all | counter of pulser triggers |
| 6 | trigger bitmap | udp_trig_bits | 0x5a48448d (30Dec17_17:59) | bitmap of trigger information, see below |
| 7 | nim bits | udp_nim_bits_masked | ??? | 32 bits of ADC NIM inputs (2 bits per ADC) |
| 8 | esata bits | udp_esata_bits_masked | ??? | 32 bits of ADC ESATA inputs (2 bits per ADC) |
| X | ||||
| 9 | 0x9 packet footer | all | 28 bits of counter_trig_out |
trigger bitmap
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= adc16_coinc_top;
udp_trig_bits[5] <= adc16_coinc_bot;
udp_trig_bits[6] <= adc16_coinc;
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
udp_trig_bits[31:24] <= mult16[7:0];
Firmware 0x5b08938c (25May18_15:51)
udp_trig_bits[0] <= adc16_grand_or;
udp_trig_bits[1] <= adc32_grand_or;
udp_trig_bits[2] <= adc_grand_or;
udp_trig_bits[3] <= esata_nim_grand_or;
udp_trig_bits[4] <= 0; // not used
udp_trig_bits[5] <= 0; // not used
udp_trig_bits[6] <= 0; // not used
udp_trig_bits[7] <= 0;
udp_trig_bits[23:8] <= 0; // not used
udp_trig_bits[31:24] <= mult16[7:0];
TODO
- add FwRev to the UDP data output
End
//KO