Chronobox

Links

• https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano
• https://bitbucket.org/teamalphag/chronobox_firmware
• https://bitbucket.org/teamalphag/chronobox_software

Input channel mapping

• 0+16 : first ECL connector
• 16+16 : second ECL connector
• 32+8 : LEMO inputs (TTL)
• 40+18 : GPIO inputs (FPGA pins)
• 58 : external clock (10 MHz nominal)
• 59 : internal clock (100 MHz)

Install chronobox software

git clone https://bitbucket.org/teamalphag/chronobox_software.git
cd chronobox_software
make clean
make
ls -l *.exe
-rwxr-xr-x 1 olchansk users 18808 Aug 16 15:26 reboot_cb.exe
-rwxr-xr-x 1 olchansk users 47256 Aug 16 15:26 srunner_cb.exe
-rwxr-xr-x 1 olchansk users 20732 Aug 16 15:26 test_cb.exe

Install chronobox quartus firmware project

cd online/git
git clone https://bitbucket.org/teamalphag/chronobox_firmware.git
cd chronobox_firmware
cat timestamp.v
ls -l output_files/*.jic

Firmware revisions

• 0x5aceaed2 - April 2018 - all inputs connected to counters (except ext clock), 58 inputs, 50 MHz clock
• 0x5b6de806 - August 2018 - added fpga boot flash programmer and fpga reboot
• 0x5b7c827d - August 2018 - bshaw added debounce on GPIO inputs (for flow meters), 100 MHz clock
• 0x5b873169 - August 2018 - rebuilt, no changes
• 0x5b89e4b4 - August 2018 - added external clock signal, 59 inputs, 100 MHz clock
• 0x5b8de2b0 - September 2018 - added data fifo and timestamp counters (TSCs) for the first 4 inputs
• 0x5b906c56 - September 2018 - improved overflow markers, added scalers readout into the data fifo

Firmware update

If FPGA is not running compatible firmware srunner_cb will not work. To proceed, load the correct SOF file via JTAG (https://daq.triumf.ca/DaqWiki/index.php/DE10-Nano#JTAG_load_sof_file), then srunner_cb should work and will be able to load the jic or rpd file into the FPGA boot flash memory.

Different revisions of the DE10-Nano board have different FPGA boot flash chips, some have EPCQ128 (use the "-128" option), some have the EPCQ64 chip (use the "-64" option). Use "srunner_cb -id" per example below to identify which flash chip is present on each specific chronobox. Note that the DE10-Nano documentation and the firmware quartus project generally refer to the EPCS64/EPCQ64 chip. The only practical difference is the use of "-128" or "-64" srunner_cb options.

./srunner_cb.exe -id -64 /dev/null # identify EPCS64 flash
./srunner_cb.exe -id -128 /dev/null # identify EPCQ128 flash
./srunner_cb.exe -read -128 test.rpd # read flash contents into a file
#./srunner_cb.exe -program -128 /home/olchansk/git/chronobox_firmware/output_files/DE10_NANO_SoC_GHRD_auto.rpd # write firmware rpd file into flash
./srunner_cb.exe -program -128 ~agmini/online/firmware/git/chronobox_firmware/output_files/DE10_NANO_SoC_GHRD_auto.rpd
./reboot_cb.exe # reboot the fpga into the new firmware

Chronobox firmware registers

reg | rw/ro | quartus name | firmware | description
0 | ro | sof_revision_in | all | firmware revision timestamp code
0 | wo | latch_scalers_out, zero_scalers_out | all | write bit 0: latch_scalers, bit 1: zero scalers
1 | rw | reg1_led_out | all | DE10-Nano LED output
2 | ro | switches_in | all | read DE10-Nano switches
3 | ro | buttons_in | all | read DE10-Nano buttons
4 | rw | reg4_test | all | 32-bit read-write test register
5 | rw | flash_programmer_in, reg5_flash_programmer_out | 0x5b6de806 | 0xABCD srunner flash programmer
6 | ro | ecl_in | all | read state of ECL inputs
7 | ro | reg7_test_in | all | ???
8 | rw | scaler_addr_out, reg8_scaler_data_in | all | top 16 bits of address becomes scaler bus address, 32 bit read is the corresponding scaler data
9 | ro | lemo_in | all | read state of LEMO inputs
A | ro | gpio_in | all | read state of GPIO inputs
B | rw | regB_lemo_out | all | LEMO output data
C | rw | regC_gpio_out | all | GPIO output data
D | rw | regD_out_enable_out | all | enable output tristates: [31:24] - LEMO_OUT, [17:0] - GPIO_OUT
E | rw | regE, reconfig_out | 0x5b6de806 | FPGA reboot: write inverted firmware revision (reg0) to reboot the FPGA
F | ro | regF_input_num_in | 0x5b89e4b4 | number of chronobox inputs (to read scalers, add 1 for the clock counter)
10 | ro | reg10_fifo_status | 0x5b8de2b0 | data fifo status, see below
11 | ro | reg11_fifo_data | 0x5b8de2b0 | data fifo data, see below

reg 0x10

Data FIFO status bits:

31: fifo_full
30: fifo_empty
29: 0
28: 0
24+4: 0
0+24: fifo_usedw

FIFO data format

• 0x8ntttttt: TSC data, 24 bits "tttttt" of timestamp, 7 bits "nn" of channel number, top bit set to 1
• 0xffTTmmmm: timestamp wrap around marker: "TT" is the top 8 bits of the timestamp, "mmmm" increments for each marker
• 0xfe00nnnn: scaler data, following "nnnn" words are the latched scalers

timestamp wrap around marker

The timestamp data is only 24 bits, to allow timestamping with longer time range, wrap around markers are added to the data stream.

For input signals that arrive close to the time of timestamp wrap around, there is ambiguity in the ordering of the data fifo: does the wrap around marker or the signal timestamp show up first? For example for rare signals, one can see this:

wrap 1
wrap 2
timestamp 0x00000003
wrap 3
wrap 4

does the hit belong with wrap marker 2 (written to the fifo just after wrap marker 2) or with marker 3 (written to the fifo just before wrap marker 3)?

To remove this ambiguity, additional markers are written to the data stream half way between the wrap arounds, making it obvious that the signal arrived right after wrap marker 3 (but was written to the FIFO before the marker):

wrap 1 0x00
wrap 1 0x80
wrap 2 0x00
wrap 2 0x80
timestamp 0x00000003
wrap 3 0x00
wrap 3 0x80

test_cb.exe

test_cb.exe is the general test program for the chronobox.

• test_cb.exe 0 # read chronobox register 0
• test_cb.exe 4 0x1234 # write to chronobox register 4
• test_cb.exe reboot # reboot the FPGA (the ARM CPU keeps running)
• test_cb.exe scalers # read all scalers in a loop