PWB: Difference between revisions

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= Firmware =
= Firmware =


== General information ==
== Factory page and user page firmware ==


AAA
Each PWB board has 2 firmware images: boot loader (factory page)
and data acquisition (user page). On power up, the FPGA loads and runs
the boot loader firmware from the factory page, later the control
software reboots the FPGA into the data acquisition firmware from
the user page.
 
Because loading defective firmware can brick https://en.wikipedia.org/wiki/Brick_(electronics)
the PWB, new firmware images are loaded into the user page, if anything is wrong,
the PWB can still boot from the factory page and one can use the firmware update
function to load a good firmware image into the user page.
 
The boot loader firmware in the factory page is not intended for data acquisition, it is only meant to provide three functions:
* boot enough hardware and software to communicate via the ethernet and the sata link
* firmware update (both factory page and user page)
* reboot into the user page
 
The boot loader firmware in the factory page is usually let alone, never updated unless absolutely
needed to fix a problem with these three functions (i.e. compatibility with sata link communications).
 
The PWB has a 32 Mbyte EPCQ flash memory chip, it is divided into 2 pages 16 Mbytes of factory page and 16 Mbytes of user page.


== NIOS terminal ==
== NIOS terminal ==

Revision as of 18:57, 5 February 2020

Links

Schematics

Manuals

Firmware

Factory page and user page firmware

Each PWB board has 2 firmware images: boot loader (factory page) and data acquisition (user page). On power up, the FPGA loads and runs the boot loader firmware from the factory page, later the control software reboots the FPGA into the data acquisition firmware from the user page.

Because loading defective firmware can brick https://en.wikipedia.org/wiki/Brick_(electronics) the PWB, new firmware images are loaded into the user page, if anything is wrong, the PWB can still boot from the factory page and one can use the firmware update function to load a good firmware image into the user page.

The boot loader firmware in the factory page is not intended for data acquisition, it is only meant to provide three functions:

  • boot enough hardware and software to communicate via the ethernet and the sata link
  • firmware update (both factory page and user page)
  • reboot into the user page

The boot loader firmware in the factory page is usually let alone, never updated unless absolutely needed to fix a problem with these three functions (i.e. compatibility with sata link communications).

The PWB has a 32 Mbyte EPCQ flash memory chip, it is divided into 2 pages 16 Mbytes of factory page and 16 Mbytes of user page.

NIOS terminal

$ ssh agmini@daq16
$ /opt/intelFPGA/16.1/quartus/bin/jtagconfig
1) USB-Blaster [2-1.2]
  02B030DD   5CGTFD7(B5|C5|D5)/5CGXBC7B6/..
$ /opt/intelFPGA/17.0/quartus/bin/nios2-terminal
nios2-terminal: connected to hardware target using JTAG UART on cable
nios2-terminal: "USB-Blaster [2-1.2]", device 1, instance 0
nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)
PWB Revision 1 Boot Loader
Ver 2.0  Build 357 - Wed Jun  6 15:05:35 PDT 2018
...

Flash boot loader firmware via jtag

$ ssh agmini@daq16
$ /opt/intelFPGA/16.1/quartus/bin/jtagconfig
1) USB-Blaster [2-1.2]
  02B030DD   5CGTFD7(B5|C5|D5)/5CGXBC7B6/..
$ cd ~/online/firmware/pwb_rev1
$ ls -l
$ /opt/intelFPGA/17.1/quartus/bin/quartus_pgmw
... auto detect
... load the jic file
... in menu tools->programmer, enable "unprotect device"
... start program/configure operation

Flash user page firmware via esper-tool

$ ssh agmini@daq16
$ cd online/src
$ more update_pwb.perl ### check that $fw is set to the desired firmware file
$ ./update_pwb.perl pwb06 ### or give more PWB names or give "all"

Build firmware

NOTE: quartus 16.1 should be used for jtag (jtagconfig and jtagd)

NOTE: quartus 17.0 should be used to build the PWB firmware (17.1 is not compatible) 

$ ssh agmini@daq16
$ /opt/intelFPGA/17.0/nios2eds/nios2_command_shell.sh
------------------------------------------------
Altera Nios2 Command Shell [GCC 4]

Version 17.0, Build 602
------------------------------------------------
$ cd online/firmware/git/pwb_rev1_firmware
$ git pull
$ git checkout alphag
$ git pull
$ ./scripts/compile_project.sh
$ ls -l bin/*.sof bin/*.jic bin/*.rpd
-rw-r--r-- 1 agmini alpha 12727389 Jan 24  2018 bin/feam_auto.rpd
-rw-r--r-- 1 agmini alpha 33554661 Jan 24  2018 bin/feam.jic
-rw-r--r-- 1 agmini alpha  6974754 Jan 24  2018 bin/feam.sof
$ ### feam.jic is loaded via jtag
$ ### feam_auto.rpd is loaded via esper
$ ### feam.sof is used to attach the signal tap

ESPER Variables

  • Board
    • invert external trigger - invert trigger signal from CDM before it drives any logic (to undo incorrect signal polarity)
  • Signalproc
    • test_mode - ADC data is replaced with a test pattern: {row_cnt[2:0], samples_read[8:0]}. row_count is the sca readout index 1..79 minus 1 (reset1 is 0, last waveform is 78), samples_read is the sca bin count from 0 to 509 minus 1: bin 0 is 509, bin 1 is 0, bin 2 is 1, bin 509 is 508.
  • Link
    • link_ctrl - sata link control. The bits are:
0 - sata_link_udp_stream_in_enable - permit data flow from sata link to OFFLOAD_SATA
1 - udp_stream_out_enable - permit sca data flow to sata link
2 - sata_to_eth_enable - permit ethernet data flow from sata link to TSE_MAC
3 - eth_to_sata_enable - permit ethernet data flow from TSE MAC to sata link
4 - enable_stop_our_tx - enable flow control: allow stop_tx
#5 - stop_our_tx - manually activate the flow control signal into link_tx
6 - enable_stop_remote_tx - enable flow control: allow send "stop_tx"
#7 - stop_remote_tx - manually activate the flow control signal into link_tx
8 - tx_test_pattern_udp - udp data is replaced by test pattern 0x11111111, 0x22222222, etc.
9 - tx_test_pattern_eth - nios-to-sata data is replaced by test pattern 0x11111111, 0x22222222, etc.
10 - 
11 - 
12 - sata_to_nios_disable
13 - nios_to_sata_disable
14 - 
15 -

ZZZ

ZZZ

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