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= ALPHAT, the trigger control board for the ALPHA-g detector =
= TRG, the trigger control board for the ALPHA-g detector =


== References ==
= Links =


* xxx
* xxx
* https://bitbucket.org/expalpha/trg_firmware - firmware sources on bitbucket


== General characteristics ==
= General characteristics =


=== Photos ===
== Photos ==


=== Board schematics ===
== Board schematics ==


=== Available hardware ===
* https://bitbucket.org/expalpha/trg_firmware/src/master/3xFMC_VME_Motherboard.pdf


== Firmware update procedure ==
== Available hardware ==


== Firmware revisions ==
* Altera Stratix IV - main FPGA
* Altera Max V - boot FPGA
* boot flash: PC28F512M29EW - 512 Mbit parallel NOR flash.


== ALPHA-g trigger functions ==
= TRG front panel connections =


== Control registers ==
From top to bottom:


=== Register addresses ===
<pre>
|
| minisas-C - links 8-11
| minisas-D - links 12-15
|
| ethernet sfp - use copper sfp only
| minisas - not used, do not connect
| esata - clock in, trigger out
|
| minisas-A - links 0-3
| minisas-B - links 4-7
|
| LEDs
|
</pre>
 
MiniSAS and SATA flail cable connections:
 
<pre>
P1 <--> link 3
P2 <--> link 2
P3 <--> link 1
P4 <--> link 0
</pre>
 
LEDs:
 
<pre>
--PCB-- (left)
LED[0] - trigger out - ag_trig_out
LED[1] - network packet received - sfp_rx_data_valid
LED[2] - Xilinx FPGA boot ok - FMC1_CFG_DONE
LED[3] - not used
(right)
</pre>
 
= TRG onboard jumpers and switches =
 
* rotary switches: select IP address: 00=192.168.1.50, 11=.51, 22=.52, 33=.53, 44=.54, otherwire=.251
 
= Firmware update procedure =
 
* use quartus to generate the grifc.pof file (use grifc.cof)
* open quartus programmer
* attach grifc.pof to the 1st CFI_512 flash
* mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
* check that "initiate configuration after programming" is set in tools->options
* say "start"
* should take about 5 minutes
* grifc should reboot into the new firmware
 
If CFI_512 flash is not visible to the quartus programmer, load correct
code into the MaxV CPLD:
 
* open quartus programmer,
* say "auto detect"
* change file for the 5M2210 device
* use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
* say "program", it should finish in 10-15 seconds
* say "auto detect"
* CFI_512 flash should be visible now.
 
= Firmware revisions =
 
* 0x5bc8f90f - original firmware used for all data
* 0x6147c0f9 - added cbtrg, etc. installed at CERN on 20 Sep 2021.
* 0x618376ae - bigger cbtrg fifo, data rate tested up to 30 Mbytes/sec
* 0x6189c7f3 - fix loss of trigger packets. (missing fifo between alphag block and ethernet mux)
* 0x618b790b - fix loss of timestamps. (cbtrg inputs stretched to 100 ns long). installed at CERN 10 Nov 2021.
* 0x62d32d95 - updated cbtrg, switched to edge-triggered cbtrg inputs, improved BSC multiplicity trigger, improved coinc trigger, added burst pulser. installed at CERN 19 Jul 2022.
* 0x62ded109 - fix cbtrg fifo data corruption, 1st fifo word was missing, 2nd fifo word sent twice.
 
= Firmware build =
 
* use quartus 20.1
* see Makefile in the trg_firmware project
 
= Jtag remote connection =
 
* ssh agmini@daq16
* /opt/intelFPGA/16.1/quartus/bin/jtagd --config /home/agmini/.jtagd.conf
* netstat -an | grep 1309 ### note listen address is "0.0.0.0", NOT "127.0.0.1"
<pre>
tcp        0      0 0.0.0.0:1309            0.0.0.0:*              LISTEN   
</pre>
* opt/intelFPGA/16.1/quartus/bin/jtagconfig ### should work
* ssh olchansk@daq01
* cd git/trg_firmware
* /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
* jtagconfig ### should work
<pre>
daq01:trg_firmware$ jtagconfig
1) DE-SoC on daq16 [2-1.2.3]
  4BA00477  SOCVHPS
  02D020DD  5CSEBA6(.|ES)/5CSEMA6/..
 
2) USB-Blaster on daq16 [2-1.3]
  024090DD  EP4SGX230(.|ES)
  020A40DD  5M(1270ZF324|2210Z)/EPM2210
 
daq01:trg_firmware$
</pre>
 
= ALPHA-g trigger functions =
 
Trigger options:
* software trigger
* pulser trigger
* trigger on GRIF16 ADC NIM and ESATA inputs ("external trigger")
* adc16 grand-or
* adc32 grand-or
* adc16 wire multiplicity
* TPC anode wire per-preamp trigger (aw16 section)
** trigger on coincidences of preamps (removed fw 0x62c77f0b)
** trigger on multiplicity of preamps (removed fw 0x62c77f0b)
** trigger on specific topology of preamps (multiplicity of preamp clusters, etc) via the aw16_mlu trigger
* BSC trigger
** BSC grand_or
** BSC bar multiplicity
* coincidence trigger - select coincidence of external trigger, TPC AW grand-or, TPC AW MLU, BSC grand-or and BSC bar multiplicity triggers
 
== software trigger ==
 
to programmatically fire the trigger, one should:
* set the conf_enable_sw_trigger bit in conf_trig_enable, this will permit the software trigger to fire the trigger
* write value 0x4 to register 0x2B, this will cause the software trigger to fire
 
== pulser trigger ==
 
To use the pulser trigger, one should program:
* pulser period (in clocks)
* pulser width (in clocks, use value 5, the pulser no longer goes outside of the trigger board, so changing the width does not do anything)
* set the run_pulser bit in conf_trig_enable, this will cause the pulser to run
* set the enable_pulser bit in conf_trig_enable, this will cause the pulser to fire the trigger
* set the output_pulser bit in conf_trig_enable, this will cause the pulser to be output from the alphag firmware block (the pulser no longer goes outside of the trigger board, so changing the bit does not do anything)
 
== timeout trigger ==
 
The event builder uses event timestamps to assemble physics events. The timestamps
are usually 32 bit wide and run at 125 MHz (8 ns) or 62.5 MHz (16 ns). If
triggers are generated often (1 per second or more), timestamp wrap around
is easily detected by the event builder. If triggers come infrequently,
timestamp wrap around may occur while there are no triggers, not be seen
by the event builder causing loss of event synchronization.
 
To avoid this problem in the event builder, a timeout trigger should be generated
if no triggers were generated inside a 10 second interval.
 
The guaranties that even if all physics triggers temporarily stop for any reason,
the event builder will stay synchronized. (0.1 Hz timeout trigger frequency).
 
To enable the timeout trigger:
* program timeout trigger timeout in reg 0x43 in units of 8 ns clock
* enable it in bit 23 of [[#conf_trig_enable bits]]
 
== adc16 multiplicity trigger ==
 
This trigger is intended for use with the barrel scintillator signals connected to adc16 digitizers. It does not work well with TPC AW signals.
 
The 16 adc16 trigger bits (16x16=256) are added together to form the hit multiplicity value (adc16_mult, 16 bits, actual range 0 to 256).
 
Four threshold signals are computed: adc16_mult_1ormore = adc16_mult>=1, 2ormore, 3ormore, 4ormore.
 
There is a counter for each of these four signals.
 
Each of these four signals can fire the trigger, see [[#conf_trig_enable bits]].
 
== TPC anode wire triggers ==
 
=== aw16 bus ===
 
TPC Anode Wire trigger is based on the aw16[15:0] (xaw16) bus.
 
Each bit corresponds to one AW preamp. 16 preamps, 16 bits.
 
The aw16[15:0] bus can be fed by
* adc16_or16[15:0] - or16 of 100 MHz ADCs, 16 ADC sas links
* adc32_or16[15:0] - or16 of 62.5 MHz ADCs, FMC-ADC32 has 32 channels, so 2 bits per ADC: low 16 channels and high 16 channels, sas links 7..0
* adc32_or16[31:16] - or16 of 62.5 MHz ADCs, ditto, sas links 15..8
as selected by conf_enable_aw_adc16, conf_enable_aw_adc32a, conf_enable_aw_adc32b in [[#conf_control bits]]
 
<pre>
  ///////////////////////////////////////////////////////////
  //          TPC Anode Wire trigger logic (aw16)
  ///////////////////////////////////////////////////////////
 
  // map adc signals into aw16
 
  wire [15:0]   aw16 = ({16{conf_enable_aw_adc16}} & adc16_or16[15:0]) |
  ({16{conf_enable_aw_adc32a}} & adc32_or16[15:0]) |
  ({16{conf_enable_aw_adc32b}} & adc32_or16[31:16]);
  ...
  ag_conditioner cond_adc16_or16_0(.clk(clk), .in(aw16[0]), .out(xxaw16[0]));
  ...
  xaw16 <= xxaw16;
</pre>
 
=== aw16_grand_or ===
 
TPC AW "grand or" trigger: use aw16_mult_1ormore (before fw 0x62c77f0b)
 
(256 anode wires, 16 wires per preamp, 16 preamps, 16 aw16 signals)
 
=== aw16_mlu ===
 
TPC AW preamp MLU trigger: the MLU (memory lookup
table) implements an arbitrary logical function
to map the 16 aw16 preamp signals into 1 aw16_mlu_trig trigger output.
 
Description of the aw16 mlu trigger.
 
In words:
 
* any aw16 signal starts the aw16_prompt_run gate
* aw16 signals are collected for the duration of conf_mlu_prompt (125MHz/8ns clock)
* this corresponds to time spread of TPC AW signals due to the drift time in the AW drift cell and to the variation in signal transmission time from the ADC to the TRG (digital trigger data link).
* when this prompt time expires, the MLU looks at the accumulated aw16_prompt bit pattern and makes the "yes/no" trigger decision
* after the trigger decision is made, we wait for the TPC to become quiet:
* we wait until all aw16 signals are empty (no timeout)
* we run the aw16_prompt_wait gate, length conf_mlu_wait (8ns clock), if any aw16 signals arrive, we wait for aw16 empty again, rinse, repeat.
* now, after TPC aw16 have been empty for conf_mlu_wait clocks (8ns clock), MLU trigger is ready for the next event.
 
In logic: (see alphag.v)
 
* aw16_or <= grand-or of 16 aw16 signals
* "aw16_or" starts the "aw16_prompt_cnt" counter, opens the aw16_prompt_run gate
* during the aw16_prompt_run gate, aw16_prompt collects (latches) the aw16 bits (aw16_prompt <= aw16_prompt | aw16)
* this is the time when we wait for all "prompt" signals from the TPC to arrive into the trigger
* at the end of the aw16_prompt_run gate, the signal aw16_prompt_out is pulsed, latching the output of the MLU into aw16_mlu_trig
* this is the MLU trigger "yes/no" trigger decision.
* after the MLU trigger decision is made, we wait for the arrival and passing of all TPC drift signals
* the aw16_prompt_wait_cnt and aw_prompt_wait gate opens
* if any new aw16 signals arrive (they are TPC drift signals at this time), the aw16_prompt_wait gate is restarted
* if no aw16 signals arrive during the full run of the aw16_prompt_wait gate ("TPC quiet time")
* the aw16_prompt_wait and aw16_prompt gates are cleared and the MLU trigger is ready for the next event.
 
Good settings are:
* conf_mlu_prompt: 64 (512 ns)
* conf_mlu_wait: 128 (1024 ns)
 
== BSC trigger ==
 
=== bsc_adc16 bus ===
 
The BSC trigger is based on the [15:0]bsc_adc16[7:0] bus: 16 trigger discriminator bits from 8 ADC sas links. (8*16 = 64+64 bars, top and bottom).
 
The bsc_adc16 bus can be fed from sas links 0..7 or 8..15, controlled by conf_bsc_adc16_a and conf_bsc_adc16_b bits on [[#conf_bsc_control bits]].
 
bsc_adc16 can be fed only from GRIF-16 100 MHz ADC trigger discriminators.
 
=== bsc64_top and bsc64_bot buses ===
 
* firmware 0x5bc8f90f: bsc_adc16 is remapped into 64 bits of top (bsc64_top) and bottom (bsc64_bot):
<pre>
ag_bsc_remap bsc_remap_a(.adc(bsc_adc16[0]), .bsc_bot(bsc64_bot[7:0]), .bsc_top(bsc64_top[7:0]));
  ag_bsc_remap bsc_remap_b(.adc(bsc_adc16[1]), .bsc_bot(bsc64_bot[8+7:8+0]), .bsc_top(bsc64_top[8+7:8+0]));
  ag_bsc_remap bsc_remap_c(.adc(bsc_adc16[2]), .bsc_bot(bsc64_bot[2*8+7:2*8+0]), .bsc_top(bsc64_top[2*8+7:2*8+0]));
  ag_bsc_remap bsc_remap_d(.adc(bsc_adc16[3]), .bsc_bot(bsc64_bot[3*8+7:3*8+0]), .bsc_top(bsc64_top[3*8+7:3*8+0]));
 
  ag_bsc_remap bsc_remap_e(.adc(bsc_adc16[4]), .bsc_bot(bsc64_bot[4*8+7:4*8+0]), .bsc_top(bsc64_top[4*8+7:4*8+0]));
  ag_bsc_remap bsc_remap_f(.adc(bsc_adc16[5]), .bsc_bot(bsc64_bot[5*8+7:5*8+0]), .bsc_top(bsc64_top[5*8+7:5*8+0]));
  ag_bsc_remap bsc_remap_g(.adc(bsc_adc16[6]), .bsc_bot(bsc64_bot[6*8+7:6*8+0]), .bsc_top(bsc64_top[6*8+7:6*8+0]));
  ag_bsc_remap bsc_remap_h(.adc(bsc_adc16[7]), .bsc_bot(bsc64_bot[7*8+7:7*8+0]), .bsc_top(bsc64_top[7*8+7:7*8+0]));
 
module ag_bsc_remap
  (
  input wire [15:0]  adc,
  output wire [7:0]  bsc_bot,
  output wire [7:0]  bsc_top
  );
 
  assign bsc_top[3] = adc[0];
  assign bsc_top[2] = adc[1];
  assign bsc_top[1] = adc[2];
  assign bsc_top[0] = adc[3];
 
  assign bsc_top[7] = adc[4];
  assign bsc_top[6] = adc[5];
  assign bsc_top[5] = adc[6];
  assign bsc_top[4] = adc[7];
 
  assign bsc_bot[0] = adc[8];
  assign bsc_bot[1] = adc[9];
  assign bsc_bot[2] = adc[10];
  assign bsc_bot[3] = adc[11];
 
  assign bsc_bot[4] = adc[12];
  assign bsc_bot[5] = adc[13];
  assign bsc_bot[6] = adc[14];
  assign bsc_bot[7] = adc[15];
 
endmodule
</pre>
 
=== bsc64 bus ===
 
the bsc64 bus is the 64 bars used by the trigger, formed from bsc64_top and bsc64_bot:
<pre>
      if (conf_bsc64_bot_only) begin
bsc64 <= bsc64_bot;
      end else if (conf_bsc64_top_only) begin
bsc64 <= bsc64_top;
      end else if (conf_bsc64_bot_top_or) begin
bsc64 <= bsc64_bot | bsc64_top;
      end else if (conf_bsc64_bot_top_and) begin
bsc64 <= bsc64_bot & bsc64_top;
      end else begin
bsc64 <= 64'b0;
      end
</pre>
 
=== bsc_grand_or_trig ===
 
bsc_grand_or_trig is the grand-or of 64 bits of the bsc64 bus
 
to enable triggering on bsc_grand_or_trig, set corresponding bit in [[#conf_trig_enable bits]]
 
=== old bsc_mult_trig ===
 
(from fw 0x62c77f0b, old bsc_mult_trig was replaced by new bsc64 multiplicity trigger)
 
* bsc64_mult is computed as multiplicity of the bsc64 bus (number of 64 bsc64 bits that fired)
* bsc_mult_trig is computed:
<pre>
      if (bsc64_mult >= conf_bsc64_mult) begin
bsc_mult_trig <= 1;
      end else begin
bsc_mult_trig <= 0;
      end
</pre>
 
to enable the bsc multiplicity trigger, set the multiplicity value conf_bsc64_mult in [[#conf_bsc_control bits]] and enable the corresponding bit in [[#conf_trig_enable bits]].
 
=== bsc64 multiplicity trigger ===
 
bsc64 BSC bar multiplicity trigger uses a time window. this time window is started by bsc64_grand_or and runs for conf_bsc64_mult_window clocks (8 nc clock). During this time, hits in bsc64_bus are accumulated (latched) and their multiplicity is computed. If multiplicity condition is satisfied (bigger or equal to conf_bsc64_mult_min), bsc64_mult_trig is fired and the bsc64 bit pattern is saved to the UDP packet. Then trigger waits for the bsc64_bus to be empty. Then trigger waits for conf_bsc64_empty_window clocks, if there is any bsc64 hits, we wait for empty again. So after bsc64 has been empty for conf_bsc64_empty_window clocks, multiplicity trigger is ready for the next event. This scheme cannot implement max multiplicity.
 
recommended values:
* conf_bsc64_mult_window (8 bits): slightly longer than 3 cycles of SAS link: 3*18 = 54 clocks, good value is 80 (640 ns).
* conf_bsc64_mult_min (8 bits): 2
* conf_bsc64_empty_window (8 bits): 80 (640 ns)
 
== Coincidence trigger ==
 
Coincidence trigger provides a combination of TPC, BSC and external scintillator (esata_nim_grand_or) signals:
 
<pre>
  assign coinc_input[0] = aw16_grand_or; // was aw16_mult_1ormore;
  assign coinc_input[1] = aw16_mlu_trig;
  assign coinc_input[2] = bsc_grand_or_trig;
  assign coinc_input[3] = bsc_mult_trig;
  assign coinc_input[4] = esata_nim_grand_or;
  assign coinc_input[5] = 0;
  assign coinc_input[6] = 0;
  assign coinc_input[7] = 0;
</pre>
 
Coincidence trigger "start" mask selects which of the inputs can start the coincidence window.
 
Coincidence trigger "require" mask selects which inputs must have a hits for the coincidence to be satisfied.
 
Input hits are collected for the duration of the coincidence window, if all required inputs have hits, coinc_trig is fired.
 
Example settings:
 
* coincidence of external scintillator, BSC and TPC AW "grand or" signals: start 0x10, required 0x15
* coincidence of BSC grand-or and TPC AW grand-or signals: start 0x5, required 0x5
* coincidence of BSC multiplicity and TPC AW grand-or triggers: start 0x9, required 0x9
 
= Control registers =
 
== Register addresses ==


Note: all registers are 32 bits unless otherwise noted.
Note: all registers are 32 bits unless otherwise noted.
Note: RW means read-write register, RO means read-only, ROL means read-only, contents is latched by the "latch_out" bit


{| cellpadding="10" cellspacing="0" border="1"
{| cellpadding="10" cellspacing="0" border="1"
! Address || Quartus Name || Access || FwRev || Description
! Address || Quartus Name || Access || FwRev || Description
|-
| 0x08 || num_sample || RW || GRIF-C || magic 16-bit register to control UDP packet size
|-
| 0x08 || scratch_reg || RW || 0x618b790b || 32-bit scratch register
|-
|-
| 0x1F || compilation_time || RO || || Firmware revision
| 0x1F || compilation_time || RO || || Firmware revision
|-
|-
| 0x20 || conf_trig_width     <= par_value;
| 0x20 || conf_trig_width || RW || || Trigger signal width, 16 ns clock
|-
| 0x21 || conf_busy_width || RW || || Busy signal width, 16 ns clock (not used)
|-
| 0x22 || conf_pulser_width || RW || || Pulser signal width, 16 ns clock
|-
| 0x23 || conf_pulser_period || RW || || Pulser signal period, 16 ns clock
|-
| 0x24 || conf_pulser_burst_ctrl || RW || 0x62d1c47e || Generate bursts of pulses: 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses, 16 ns clocks
|-
| 0x25 || conf_trig_enable || RW || || see [[#conf_trig_enable bits]]
|-
| 0x26 || || || not used
|-
| 0x27 || || || not used
|-
| 0x28 || || || not used
|-
| 0x29 || conf_nim_mask || RW || || enable bits for ADC NIM inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2A || conf_esata_mask || RW || || enable bits for ADC eSATA inputs, 2 bits per ADC sas link, 16 links
|-
| 0x2B || reset_out, latch_out, trigger_out || W || || see [[#reg 0x2B bits]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x5bc8f90f || configure AW coincidence trigger, see [[#aw16_coinc]]
|-
| 0x2C || conf_aw16_coinc_a || RW || 0x62c77f0b || removed
|-
| 0x2D || conf_aw16_coinc_b || RW || 0x5bc8f90f ||
|-
| 0x2E || conf_aw16_coinc_c || RW || 0x5bc8f90f ||
|-
| 0x2F || conf_aw16_coinc_d || RW || 0x5bc8f90f ||
|-
| 0x30 || sas_sd[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect for each link
|-
| 0x31 || pll_625_status || ROL || 0x5b2057f5 (12Jun18_16:32) || 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter
|-
| 0x32 || clk_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the system 125 MHz clock
|-
| 0x33 || clk_625_counter || ROL || 0x5b2057f5 (12Jun18_16:32) || frequency counter of the currently selected 62.5 MHz clock (my_clk_625)
|-
| 0x34 || conf_control || RW || 0x5b398983 (01Jul18_19:10) || see [[#conf_control bits]] below
|-
| 0x35 || conf_drift_width || RW || 0x5b398983 (01Jul18_19:10) || width of drift time blank-out in 16 ns clocks
|-
| 0x36 || conf_scaledown || RW || 0x5b398983 (01Jul18_19:10) || trigger scaledown, 0=no scaledown, 1=divide-by-2, 2=divide-by-3, etc
|-
| 0x37 || conf_mlu || RW || 0x5b398983 (01Jul18_19:10) || AW MLU control bits, see [[#conf_mlu bits]]
|-
| 0x38 || conf_trig_delay || RW || 0x5baedfca (28Sep18_19:13) || delay the trigger pulse, 16 ns clock
|-
| 0x39 || esata_clk_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the TRG 125 MHz clock
|-
| 0x3A || esata_clk_esata_counter || ROL || 0x5baedfca (28Sep18_19:13) || frequency counter of the external clock (eSATA 62.5 MHz clock)
|-
| 0x3B || conf_counter_adc_select || RW || 0x5bb7f6ae (05Oct18_16:41) || select which 16 ADCs are connected to the selected adc counters, 0..15 - connect the adc16 signals, 16..47 connect the adc32 signals
|-
| 0x3C || sysreset_ts || RO || 0x5bb7f6ae (05Oct18_16:41) || 125MHz counter of VME-SYSRESET
|-
| 0x3C || || || 0x618b790b || not used
|-
| 0x3D || GRIF-C csr || RW || GRIF-C || <= csr & ~par_value; // Selective clear
|-
| 0x3E || GRIF-C csr || RW || GRIF-C || <= csr |  par_value; // Selective set
|-
| 0x3F || GRIF-C csr || RW || GRIF-C || <= par_value; // write
|-
| 0x3D ||  ||  || 0x618b790b || not used
|-
| 0x3E ||  ||  || 0x618b790b || not used
|-
| 0x3F ||  ||  || 0x618b790b || not used
|-
| 0x40 || conf_bsc_control || RW || 0x5bc13541 (12Oct18_16:58) || Barrel Scintillator trigger control, see [[#conf_bsc_control bits]]
|-
| 0x41 || conf_coinc_control || RW || 0x5bc13541 (12Oct18_16:58) || Coincidence trigger control, see [[#conf_coinc_control bits]]
|-
| 0x42 || reconfig_out || WO || 0x5bc13541 (12Oct18_16:58) || reserved for rebooting the FPGA (does not work)
|-
| 0x43 || conf_trigger_timeout || RW || 0x5bc8f90f (18Oct18_14:20) || Generate timeout trigger if there is no other trigger after given timeout, in 8 ns clocks, must be enabled by bit conf_enable_timeout_trig in [[#conf_trig_enable bits]]
|-
| 0x44 || eth_clk_counter || ROL || 0x618b790b ||
|-
| 0x45 || eth_clk_eth_counter || ROL || 0x618b790b ||
|-
| 0x100 || ts_625 || ROL || || latched timestamp
|-
| 0x101 || counter_trig_out || ROL || || counter of issued triggers
|-
| 0x102 || counter_trig_in || ROL || || counter of triggers
|-
| 0x103 || counter_pulser || ROL || || counter of pulser
|-
| 0x104 || counter_adc16_grand_or || ROL ||
|-
| 0x105 || counter_adc32_grand_or || ROL ||
|-
| 0x106 || counter_adc_grand_or || ROL ||
|-
| 0x107 || counter_esata_nim_grand_or || ROL ||
|-
| 0x108 || counter_adc16_mult_1ormore || ROL ||
|-
| 0x109 || counter_adc16_mult_2ormore || ROL ||
|-
| 0x10A || counter_adc16_mult_3ormore || ROL ||
|-
| 0x10B || counter_adc16_mult_4ormore || ROL ||
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x5bc8f90f || counter of AW coincidence triggers
|-
| 0x10C || counter_aw16_coinc_a || ROL || 0x62c77f0b || removed
|-
|-
| 0x21 || conf_busy_width    <= par_value;
| 0x10D || counter_aw16_coinc_b || ROL || 0x5bc8f90f ||
|-
|-
| 0x22 || conf_pulser_width  <= par_value;
| 0x10E || counter_aw16_coinc_c || ROL || 0x5bc8f90f ||
|-
|-
| 0x23 || conf_pulser_period  <= par_value;
| 0x10F || counter_aw16_coinc_d || ROL || 0x5bc8f90f ||
|-
|-
| 0x24 || sw_trigger_counter <= 10;
| 0x110 || counter_drift || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the drift time blank-out
|-
|-
| 0x25 || conf_trig_enable  <= par_value;
| 0x111 || counter_scaledown || ROL || 0x5b398983 (01Jul18_19:10) || counter of triggers that passed the scaledown
|-
|-
| 0x26 || conf_sas_trig_mask <= par_value; || obsolete
| 0x112 || counter_aw16_coinc || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW coincidence triggers
|-
|-
| 0x27 || conf_sas_trig_mask_a <= par_value; || obsolete
| 0x113 || counter_aw16_mlu || ROL || 0x5b398983 (01Jul18_19:10) || counter of AW MLU triggers
|-
|-
| 0x28 || conf_sas_trig_mask_b <= par_value; || obsolete
| 0x114 || counter_aw16_grand_or || ROL || 0x62c77f0b || counter of AW grand-or triggers
|-
|-
| 0x29 || conf_nim_mask <= par_value;
| 0x114 || counter_aw16_mult_1ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 1ormore triggers
|-
|-
| 0x2A || conf_esata_mask <= par_value;
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 2ormore triggers
|-
|-
| 0x2B || conf_latch <= 1;
| 0x115 || counter_aw16_mult_2ormore || ROL || 0x62c77f0b || removed
|-
|-
| 0x2C || conf_coinc_a <= par_value;
| 0x116 || counter_aw16_mult_3ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 3ormore triggers
|-
|-
| 0x2D || conf_coinc_b <= par_value;
| 0x117 || counter_aw16_mult_4ormore || ROL || 0x5bb7f6ae (05Oct18_16:41) || counter of AW 4ormore triggers
|-
|-
| 0x2E || conf_coinc_c <= par_value;
| 0x118 || counter_bsc_grand_or || ROL || 0x5bc13541 (12Oct18_16:58) || counter of BSC grand-or triggers
|-
|-
| 0x2F || conf_coinc_d <= par_value;
| 0x119 || counter_bsc_mult || ROL || 0x5bc13541 (12Oct18_16:58) || counter of old BSC multiplicity triggers
|-
|-
| 0x100..0x11F || scaler_data[1023..0]
| 0x11A || counter_coinc || ROL || 0x5bc13541 (12Oct18_16:58) || counter of coincidence triggers
|-
|-
| 0x200..0x207 || conf_adc16_masks
| 0x11B || counter_timeout || ROL || 0x618b790b || counter of timeout triggers
|-
|-
| 0x300..0x30F || conf_adc32_masks
| 0x11C || counter_bsc_mult_start || ROL || 0x62c77f0b || counter of BSC multiplicity windows
|-
|-
| 0x400..0x41F || ag_sas_bits[1023..0]
| 0x11D || counter_bsc_mult_trig || ROL || 0x62c77f0b || counter of BSC multiplicity triggers
|-
| 0x11E || counter_coinc_start || ROL || 0x62d1b152 || counter of coincidence windows
|-
| 0x11F || counter_aw16_mlu_start || ROL || 0x62d1b152 || counter of TPC AW MLU windows
|-
| 0x200..0x207 || conf_adc16_masks || RW || all || adc16 enable bits
|-
| 0x300..0x30F || conf_adc32_masks || RW || all || adc32 enable bits
|-
| 0x400..0x41F || sas_bits[15:0][63:0] || ROL || all || sas data bits for each link
|-
| 0x420..0x42F || sas_sd_counters[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || sas signal detect counter for each link
|-
| 0x430..0x43F || counters_adc16_or16[15:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 16 counters of adc16 ORes
|-
| 0x440..0x45F || counters_adc32_or16[31:0] || ROL || 0x5b120c9f (01Jun18_20:18) || 32 counters of adc32 ORes
|-
| 0x460..0x46F || counters_adc_selected[15:0] || ROL || 0x5bb7f6ae (05Oct18_16:41) || 16 counters for selected group of adcs, see conf_counter_adc_select
|-
| 0x470..0x4AF || counters_bsc64[63:0] || ROL || 0x5bc13541 (12Oct18_16:58) || 64 counters for the BSC bars
|-
|-
|}
|}


<pre>
== additional registers ==
remaining GRIF-C registers


            14'h001:  param_out <= {2'h3, par_id, chan, 16'h0,  threshold    };
            14'h002:  param_out <= {2'h3, par_id, chan,        pulser_ctrl  };
            14'h003:  param_out <= {2'h3, par_id, chan, 31'h0,  polarity    };
            14'h004:  param_out <= {2'h3, par_id, chan, 16'h0,  diff_const  };
            14'h005:  param_out <= {2'h3, par_id, chan, 16'h0,  integ_const  };
    14'h006:  param_out <= {2'h3, par_id, chan, 22'h0,  decimation  };
            14'h007:  param_out <= {2'h3, par_id, chan, 16'h0,  num_pretrig  };
            14'h008:  param_out <= {2'h3, par_id, chan, 16'h0,  num_sample  };
            14'h009:  param_out <= {2'h3, par_id, chan, 16'h0,  pole_corn    };
            14'h00A:  param_out <= {2'h3, par_id, chan, 16'h0,  hitdet_integ };
            14'h00B:  param_out <= {2'h3, par_id, chan, 16'h0,  hitdet_diff  };
            14'h00C:  param_out <= {2'h3, par_id, chan, 16'h0,  integ_delay  };
            14'h00D:  param_out <= {2'h3, par_id, chan, 30'h0,  wavebuf_mode };
            14'h00E:  param_out <= {2'h3, par_id, chan,        trig_deadtime};
            14'h00F:  param_out <= {2'h3, par_id, chan, 31'h0,  enable_adc  };
            14'h010:  param_out <= {2'h3, par_id, chan, 28'h0,  detectortype };
            14'h011:  param_out <= {2'h3, par_id, chan,        sync_livetime};
            14'h012:  param_out <= {2'h3, par_id, chan,        sync_deadtime};
</pre>
<pre>
<pre>
GRIF-C CSR register
reg  | rw/ro/rol | quartus name  | firmware  | description
              14'h3D: csr                  <= csr & ~par_value; // Selective clear
-----------------------------------------------------------------
      14'h3E: csr                  <= csr |  par_value; // Selective set
0x60 | rw | cb_control_out      | 0x618b790b | chronobox control
      14'h3F: csr                  <= par_value;
0x61 | rw | cb_status            | 0x618b790b |  chronobox status
0x62 | rw | cb_invert_a_out      | 0x618b790b | chronobox input invert
0x63 | rw | cb_invert_b_out      | 0x618b790b |
0x64 | rw | cb_enable_le_a_out  | 0x618b790b | timestamp enable leading edge
0x65 | rw | cb_enable_le_b_out  | 0x618b790b |
0x66 | rw | cb_enable_te_a_out  | 0x618b790b | timestamp enable traiing edge
0x67 | rw | cb_enable_te_b_out  | 0x618b790b |
0x6A | ro | cb_input_num        | 0x618b790b | chronobox number of inputs
0x6B | rw | cb_sync_mask_a_out  | 0x618b790b | chronobox sync signal source
0x6C | rw | cb_sync_mask_b_out  | 0x618b790b |
0x6D | rw | cb_sync_reg_out      | 0x618b790b | chronobox sync register
0x6E | ro | cb_sync_status      | 0x618b790b | chronobox sync status
0x6F | rw | cb_latch_period_out | 0x618b790b | chronobox scalers latch period
0x70 | ro | cb_fifo_status      | 0x618b790b | chronobox data fifo status
0x71 | ro | cb_fifo_data        | 0x618b790b | read chronobox data fifo (cb_fifo_rdack_out <= 1)
0x72 | rw | cb_udp_period_out    | 0x618b790b | period for flushing fifo to UDP
0x73 | rw | cb_udp_threshold_out | 0x618b790b | byte threshold for flushing fifo to UDP
</pre>
</pre>


=== map of scaler_data ===
== conf_control bits ==
 
{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_clock_select || 0x5b3aa19f (02Jul18_15:05) || select 0=internal 62.5 MHz clock or 1=esata 62.5 MHz clock
|-
| 1 || conf_enable_aw_adc16 || 0x5baedfca (28Sep18_19:13) || select source of TPC AW aw16 bus, see [[#aw16 bus]]
|-
| 2 || conf_enable_aw_adc32a || 0x5baedfca (28Sep18_19:13) ||
|-
| 3 || conf_enable_aw_adc32b || 0x5baedfca (28Sep18_19:13) ||
|-
| 15..4 || || ||
|-
| 23..16 || conf_mlu_prompt || 0x5b3aa19f (02Jul18_15:05) || MLU trigger prompt window, see [[#aw16_mlu]]
|-
| 31..24 || conf_mlu_wait || 0x5b3aa19f (02Jul18_15:05) || MLU trigger wait window, see [[#aw16_mlu]]
|-
|}
 
== conf_mlu bits ==
 
{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 31 || mlu_reset || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 30 || mlu_write || 0x5b3aa19f (02Jul18_15:05) || 1=write data bit into given address
|-
| 16 || mlu_data || 0x5b3aa19f (02Jul18_15:05) || data bit for writing to MLU RAM
|-
| 15..0 || mlu_write_addr || 0x5b3aa19f (02Jul18_15:05) || MLU RAM write address for writing the data bit
|-
|}
 
== conf_bsc_control bits ==
 
{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || conf_bsc_adc_a || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 0..7
|-
| 1 || conf_bsc_adc_b || 0x5bc13541 (12Oct18_16:58) || enable mapping of BSC ADCs to ADC links 8..15
|-
| 2 || conf_bsc64_bot_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses bottom channels only
|-
| 3 || conf_bsc64_top_only || 0x5bc13541 (12Oct18_16:58) || bsc64 uses top channels only
|-
| 4 || conf_bsc64_bot_top_or || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "or" of top and bottom
|-
| 5 || conf_bsc64_bot_top_and || 0x5bc13541 (12Oct18_16:58) || bsc64 uses "and" of top and bottom
|-
| 6 ||
|-
| 7 ||
|-
| 15..8 || conf_bsc64_mult_min || 0x5bc13541 (12Oct18_16:58) || minimum bsc64 multiplicity
|-
| 23..16 || conf_bsc64_empty_wondow || 0x62d1c47e || bsc64 empty window length, 8 ns clocks
|-
| 31..24 || conf_bsc64_mult_window || 0x62c77f0b || bsc64 multiplicity window length, 8 ns clocks
|-
|}


<pre>
== conf_coinc_control bits ==
map of scaler_data:


        if (i==0)
{| cellpadding="10" cellspacing="0" border="1"
  assign scaler_data_wire[i*32+31:i*32] = ts_625;
! Bit || Quartus Name || FwRev || Description
else if (i==1)
|-
  assign scaler_data_wire[i*32+31:i*32] = counter_trig_out;
| 0 || conf_coinc_required[0] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mult_1ormore
else if (i==2)
|-
  assign scaler_data_wire[i*32+31:i*32] = counter_trig_in;
| 0 || conf_coinc_required[0] || 0x62c77f0b || enable aw16_grand_or
else if (i==3)
|-
  assign scaler_data_wire[i*32+31:i*32] = counter_pulser;
| 1 || conf_coinc_required[1] || 0x5bc13541 (12Oct18_16:58) || enable aw16_mlu_trig
else if (i==4)
|-
  assign scaler_data_wire[i*32+31:i*32] = counter_adc16_grand_or;
| 2 || conf_coinc_required[2] || 0x5bc13541 (12Oct18_16:58) || enable bsc_grand_or_trig
else if (i==5)
|-
  assign scaler_data_wire[i*32+31:i*32] = counter_adc32_grand_or;
| 3 || conf_coinc_required[3] || 0x5bc13541 (12Oct18_16:58) || enable bsc_mult_trig
else if (i==6)
|-
  assign scaler_data_wire[i*32+31:i*32] = counter_adc_grand_or;
| 3 || conf_coinc_required[3] || 0x62c77f0b || enable bsc64_mult_trig
else if (i==7)
|-
  assign scaler_data_wire[i*32+31:i*32] = counter_esata_nim_grand_or;
| 4 || conf_coinc_required[4] || 0x5bc13541 (12Oct18_16:58) || enable esata_nim_grand_or
else if (i==8)
|-
  assign scaler_data_wire[i*32+31:i*32] = counter_mult16_1ormore;
| 5 || conf_coinc_required[5]
else if (i==9)
|-
  assign scaler_data_wire[i*32+31:i*32] = counter_mult16_2ormore;
| 6 || conf_coinc_required[6]
else if (i==10)
|-
  assign scaler_data_wire[i*32+31:i*32] = counter_mult16_3ormore;
| 7 || conf_coinc_required[7]
else if (i==11)
|-
  assign scaler_data_wire[i*32+31:i*32] = counter_mult16_4ormore;
| 15..8 || conf_coinc_window[7:0] || 0x5bc13541 (12Oct18_16:58) || coincidence window length in units of 125MHz clock (8 ns)
else if (i==12)
|-
  assign scaler_data_wire[i*32+31:i*32] = counter_cc01;
| 23..16 || conf_coinc_start[7:0] || 0x5bc13541 (12Oct18_16:58) || start the coincidence window, same bits as "required"
else if (i==13)
|-
  assign scaler_data_wire[i*32+31:i*32] = counter_cc23;
| 31..24 ||
else if (i==14)
|-
  assign scaler_data_wire[i*32+31:i*32] = counter_cc45;
|}
else if (i==15)
  assign scaler_data_wire[i*32+31:i*32] = counter_cc67;
else if (i==16)
  assign scaler_data_wire[i*32+31:i*32] = { counter_adc16_or16[1][15:0], counter_adc16_or16[0][15:0] };
else if (i==17)
  assign scaler_data_wire[i*32+31:i*32] = { counter_adc16_or16[3][15:0], counter_adc16_or16[2][15:0] };
else if (i==18)
  assign scaler_data_wire[i*32+31:i*32] = { counter_adc16_or16[5][15:0], counter_adc16_or16[4][15:0] };
else if (i==19)
  assign scaler_data_wire[i*32+31:i*32] = { counter_adc16_or16[7][15:0], counter_adc16_or16[6][15:0] };
else if (i==20)
  assign scaler_data_wire[i*32+31:i*32] = { counter_adc16_or16[9][15:0], counter_adc16_or16[8][15:0] };
else if (i==21)
  assign scaler_data_wire[i*32+31:i*32] = { counter_adc16_or16[11][15:0], counter_adc16_or16[10][15:0] };
else if (i==22)
  assign scaler_data_wire[i*32+31:i*32] = { counter_adc16_or16[13][15:0], counter_adc16_or16[12][15:0] };
else if (i==23)
  assign scaler_data_wire[i*32+31:i*32] = { counter_adc16_or16[15][15:0], counter_adc16_or16[14][15:0] };
else
  assign scaler_data_wire[1023:i*32] = 0;
</pre>


=== conf_trig_enable bits ===
== conf_trig_enable bits ==


{| cellpadding="10" cellspacing="0" border="1"
{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
! Bit || Quartus Name || FwRev || Description
|-
|-
| 0 || conf_enable_sw_trigger || init || ???
| 0 || conf_enable_sw_trigger || || trigger on software trigger (how generated???)
|-
|-
| 1 || conf_enable_pulser = conf_trig_enable[1];
| 1 || conf_enable_pulser || || trigger on pulser
|-
|-
| 2 || conf_enable_sas_or = conf_trig_enable[2];
| 2 || - || 0x5b120c9f (01Jun18_20:18) || not used
|-
|-
| 3 || conf_run_pulser = conf_trig_enable[3];
| 3 || conf_pulser_run || || allow the pulser to run (frequency has to be set beforehand)
|-
|-
| 4 || conf_output_pulser = conf_trig_enable[4];
| 4 || conf_output_pulser || 0x5bc8f90f || does nothing (top level ag_pulser_out is disconnected)
|-
|-
| 5 || conf_enable_esata_nim = conf_trig_enable[5];
| 4 || || 0x618b790b || not used
|-
|-
| 6 || wire conf_enable_adc16 = conf_trig_enable[6];
| 5 || conf_enable_esata_nim || || trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand)
|-
|-
| 7 || wire conf_enable_adc32 = conf_trig_enable[7];
| 6 || conf_enable_adc16 || || trigger on adc16_grand_or
|-
|-
| 8 || wire conf_enable_1ormore = conf_trig_enable[8];
| 7 || conf_enable_adc32 || || trigger on adc32_grand_or
|-
|-
| 9 || wire conf_enable_2ormore = conf_trig_enable[9];
| 8 || conf_enable_adc16_1ormore || || trigger on adc16_mult_1ormore "1 or more"
|-
|-
| 10 || wire conf_enable_3ormore = conf_trig_enable[10];
| 9 || conf_enable_adc16_2ormore || || same, "2 or more"
|-
|-
| 11 || wire conf_enable_4ormore = conf_trig_enable[11];
| 10 || conf_enable_adc16_3ormore || || same, "3 or more"
|-
|-
| 12 || wire conf_enable_adc16_coinc = conf_trig_enable[12];
| 11 || conf_enable_adc16_4ormore || || same, "4 or more"
|-
| 12 || - || 0x5b08938c (25May18_15:51) || not used
|-
|-
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
|-
|-
| 14 || conf_enable_busy || 0x5a7a3fbd (06Feb18_15:52) || enable activation of busy counter
| 14 || - || 0x5bc8f90f || not used
|-
| 15 || conf_enable_adc || 0x5b120c9f (01Jun18_20:18) || trigger on adc_grand_or
|-
| 16 || conf_enable_aw16_coinc_a || 0x5bc8f90f || enable AW coincidence trigger, see [[#aw16_coinc]]
|-
| 16 || - || 0x62c77f0b || aw16_coinc_x removed
|-
| 17 || conf_enable_aw16_coinc_b || 0x5bc8f90f ||
|-
| 18 || conf_enable_aw16_coinc_c || 0x5bc8f90f ||
|-
| 19 || conf_enable_aw16_coinc_d || 0x5bc8f90f ||
|-
| 20 || - || 0x5b3aa19f (02Jul18_15:05) || not used
|-
| 20 || conf_enable_aw16_grand_or || 0x618b790b || enable trigger on aw16_grand_or
|-
| 21 || conf_enable_aw16_coinc || 0x5b3aa19f (02Jul18_15:05) || enable trigger on aw16_coinc_trig
|-
| 22 || conf_enable_aw16_mlu || 0x5b3aa19f (02Jul18_15:05) || enable AW MLU trigger
|-
| 23 || conf_enable_timeout_trig || 0x5bc8f90f (18Oct18_14:20) || enable trigger timeout trigger
|-
| 24 || conf_enable_aw16_1ormore || 0x5b3aa19f (02Jul18_15:05) || trigger on aw16_mult_1ormore "1 or more"
|-
| 24 || - || 0x62c77f0b || aw16_mult_xxx removed
|-
| 25 || conf_enable_aw16_2ormore || 0x5b3aa19f (02Jul18_15:05) || same, "2 or more"
|-
| 26 || conf_enable_aw16_3ormore || 0x5b3aa19f (02Jul18_15:05) || same, "3 or more"
|-
|-
| 15 || - || - || not used
| 27 || conf_enable_aw16_4ormore || 0x5b3aa19f (02Jul18_15:05) || same, "4 or more"
|-
|-
| 16 || conf_enable_coinc_a = conf_trig_enable[16];
| 28 || conf_enable_bsc_grand_or || 0x5bc13541 (12Oct18_16:58) || trigger on BSC grand-or
|-
|-
| 17 || conf_enable_coinc_b = conf_trig_enable[17];
| 29 || conf_enable_bsc_mult || 0x5bc13541 (12Oct18_16:58) || trigger on BSC multiplicity
|-
|-
| 18 || conf_enable_coinc_c = conf_trig_enable[18];
| 30 || conf_enable_coinc || 0x5bc13541 (12Oct18_16:58) || trigger on TPC/BSC/ext coincidence trigger
|-
|-
| 19 || conf_enable_coinc_d = conf_trig_enable[19];
| 31 || - || || not used
|-
|-
|}
|}


== UDP data format ==
== reg 0x2B bits ==
 
Write to this register will pulse corresponding fpga signals:
 
{| cellpadding="10" cellspacing="0" border="1"
! Bit || Quartus Name || FwRev || Description
|-
| 0 || reset_out || 0x5b120c9f (01Jun18_20:18) || reset counters, etc
|-
| 1 || latch_out || 0x5b120c9f (01Jun18_20:18) || latch counters, sas bits, etc
|-
| 2 || trigger_out || 0x5b120c9f (01Jun18_20:18) || generate a software trigger
|-
|}
 
= UDP data format =
 
== general format ==
 
<pre>
trigger packet:
 
[0] udp packet counter
[1] 0x8ccccccc
...
[N] 0xEccccccc
 
different versions of trigger packets should be decoded according to packet length:
40 bytes: initial firmware
76 bytes: firmware 0x618b790b (Nov 2021)
80 bytes: firmware 0x62d1c47e (Jul 2022)
 
chronobox fifo packet, firmware 0x618b790b (Nov 2021)
 
[0] udp packet counter
[1] 0xCccccccc
[2] fifo status
[3] fifo data
...
[N] 0xEccccccc
 
0x0ccccccc is the 28 bit fifo packet counter
 
chronobox fifo packet, firmware 0x618b790b (Nov 2021)
 
[0] udp packet counter
[1] 0xDccccccc
[2] 0xDEADBEEF
[3] fifo status
[4] fifo data
...
[N] 0xEccccccc
 
0x0ccccccc is the 28 bit fifo packet counter
</pre>
 
== firmware 0x5bc8f90f ==


{| cellpadding="10" cellspacing="0" border="1"
{| cellpadding="10" cellspacing="0" border="1"
! Offset || Name || Quartus name || FwRev || Description
! Offset || Name || Quartus name || FwRev || Description
|-
|-
| 0 || packet counter || none || all || UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
| 0 || packet counter || none || all || 31-bit UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
|-
|-
| 1 || 0x8 packet header || || all || 28 bits of counter_trig_out
| 1 || 0x8 packet header || || all || 28 bits of counter_trig_out
Line 227: Line 864:
|-
|-
| 8 || esata bits || udp_esata_bits_masked || ??? || 32 bits of ADC ESATA inputs (2 bits per ADC)
| 8 || esata bits || udp_esata_bits_masked || ??? || 32 bits of ADC ESATA inputs (2 bits per ADC)
|-
| 9 || mlu bits || aw16_prompt || 0x5b398983 (01Jul18_19:10) || 16 bits of MLU input, 1 bit per preamp
|-
| 10 || drift-blank-off counter || udp_drift_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the drift blank-off
|-
| 11 || scaledown counter || udp_scaledown_counter || 0x5b3aa19f (02Jul18_15:05) || counter of triggers that passed the scaledown
|-
|-
| X ||  ||  ||  ||  
| X ||  ||  ||  ||  
|-
|-
| 9 || 0x9 packet footer ||  || all || 28 bits of counter_trig_out
| 12 || 0xE packet footer ||  || all || 28 bits of counter_trig_out
|-
|-
|}
|}


=== trigger bitmap ===
== firmware 0x618b790b (Nov 2021) ==
 
packet size 76 bytes
 
<pre>
0 udp packet counter
1   udp_data_out  <= {4'h8,udp_counter_trig_out[27:0]};
2   udp_data_out <= udp_trig_ts_625;
3   udp_data_out  <= udp_counter_trig_out;
4   udp_data_out  <= udp_counter_trig_in;
5   udp_data_out  <= udp_counter_pulser;
6   udp_data_out  <= udp_trig_bits;
7   udp_data_out  <= udp_nim_bits;
8   udp_data_out  <= udp_esata_bits;
9   udp_data_out  <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
10   udp_data_out  <= udp_counter_drift;
11   udp_data_out  <= udp_counter_scaledown;
12   udp_data_out  <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
13   udp_data_out  <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
14   udp_data_out  <= { udp_bsc64_bus[31:0]};
15   udp_data_out  <= { udp_bsc64_bus[63:32]};
16   udp_data_out  <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
17   udp_data_out  <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
18   udp_data_out  <= {4'hE,udp_counter_trig_out[27:0]};
</pre>
 
== firmware 0x62d1c47e (Jul 2022) ==
 
packet size 80 bytes
 
<pre>
0 udp packet counter
1   udp_data_out  <= {4'h8,udp_counter_trig_out[27:0]};
2   udp_data_out <= udp_trig_ts_625;
3   udp_data_out  <= udp_counter_trig_out;
4   udp_data_out  <= udp_counter_trig_in;
5   udp_data_out  <= udp_counter_pulser;
6   udp_data_out  <= udp_trig_bits;
7   udp_data_out  <= udp_nim_bits;
8   udp_data_out  <= udp_esata_bits;
9   udp_data_out  <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
10   udp_data_out  <= udp_counter_drift;
11   udp_data_out  <= udp_counter_scaledown;
12   udp_data_out  <= { 8'h00, 8'h00, 16'h0000 };
13   udp_data_out  <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
14   udp_data_out  <= { udp_bsc64_bus[31:0]};
15   udp_data_out  <= { udp_bsc64_bus[63:32]};
16   udp_data_out  <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
17   udp_data_out  <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
18        udp_data_out  <= conf_fw_rev;
19   udp_data_out  <= {4'hE,udp_counter_trig_out[27:0]};
</pre>
 
Values of udp_coinc_latch[7:0]:
* aaa
 
Values of udp_aw16_mult[7:0] and udp_aw16_bus[15:0]:
* aaa
 
Values of udp_bsc64_mult[7:0] and udp_bsc64_bus[63:0]
* aaa
 
== trigger bitmap ==
 
Firmware ??? (one of the very early revisions)
 
<pre>
<pre>
               udp_trig_bits[0] <= adc16_grand_or;
               udp_trig_bits[0] <= adc16_grand_or;
Line 249: Line 957:
</pre>
</pre>


== TODO ==
Firmware 0x5b08938c (25May18_15:51)
 
<pre>
              udp_trig_bits[0] <= adc16_grand_or;
              udp_trig_bits[1] <= adc32_grand_or;
              udp_trig_bits[2] <= adc_grand_or;
              udp_trig_bits[3] <= esata_nim_grand_or;
              udp_trig_bits[4] <= 0; // not used
              udp_trig_bits[5] <= 0; // not used
              udp_trig_bits[6] <= 0; // not used
              udp_trig_bits[7] <= 0;
              udp_trig_bits[23:8] <= 0; // not used
              udp_trig_bits[31:24] <= mult16[7:0];
</pre>
 
Firmware 0x5b217dc4 (13Jun18_13:25)
 
<pre>
              udp_trig_bits[0] <= adc16_grand_or;
              udp_trig_bits[1] <= adc32_grand_or;
              udp_trig_bits[2] <= adc_grand_or;
              udp_trig_bits[3] <= esata_nim_grand_or;
              udp_trig_bits[4] <= 0; // not used
              udp_trig_bits[5] <= 0; // not used
              udp_trig_bits[6] <= 0; // not used
              udp_trig_bits[7] <= 0;
              udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
              udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>
 
Firmware 0x5b3aa19f (02Jul18_15:05)
 
<pre>
              udp_trig_bits[0] <= adc16_grand_or;
              udp_trig_bits[1] <= adc32_grand_or;
              udp_trig_bits[2] <= adc_grand_or;
              udp_trig_bits[3] <= esata_nim_grand_or;
              udp_trig_bits[4] <= 0; // not used
              udp_trig_bits[5] <= 0; // not used
              udp_trig_bits[6] <= 0; // not used
              udp_trig_bits[7] <= udp_mlu_out;
              udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
              udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)
</pre>
 
Firmware 0x5bc8f90f (18Oct18_14:20)
 
<pre>
  udp_trig_bits  <= trig32_in;
  assign trig32_in[0]  = trigger; // software trigger
  assign trig32_in[1]  = 0; // not used pulser trigger
  assign trig32_in[2]  = 0; // not used conf_enable_sas_or
  assign trig32_in[3]  = 0; // not used conf_run_pulser
  assign trig32_in[4]  = 0; // not used conf_output_pulser
  assign trig32_in[5]  = esata_nim_grand_or;
  assign trig32_in[6]  = adc16_grand_or;
  assign trig32_in[7]  = adc32_grand_or;
  assign trig32_in[8]  = adc16_mult_1ormore;
  assign trig32_in[9]  = adc16_mult_2ormore;
  assign trig32_in[10] = adc16_mult_3ormore;
  assign trig32_in[11] = adc16_mult_4ormore;
  assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
  assign trig32_in[13] = 0; // not used conf_enable_udp
  assign trig32_in[14] = 0; // not used conf_enable_busy
  assign trig32_in[15] = adc_grand_or;
  assign trig32_in[16] = aw16_coinc_a;
  assign trig32_in[17] = aw16_coinc_b;
  assign trig32_in[18] = aw16_coinc_c;
  assign trig32_in[19] = aw16_coinc_d;
  assign trig32_in[20] = 0; // not used conf_clock_select
  assign trig32_in[21] = aw16_coinc_trig;
  assign trig32_in[22] = aw16_mlu_trig;
  assign trig32_in[23] = timeout_trig;
  assign trig32_in[24] = aw16_mult_1ormore;
  assign trig32_in[25] = aw16_mult_2ormore;
  assign trig32_in[26] = aw16_mult_3ormore;
  assign trig32_in[27] = aw16_mult_4ormore;
  assign trig32_in[28] = bsc_grand_or_trig;
  assign trig32_in[29] = bsc_mult_trig;
  assign trig32_in[30] = coinc_trig;
  assign trig32_in[31] = 0; // not used
</pre>
 
Firmware 0x618b790b
 
<pre>
  udp_trig_bits  <= trig32_in;
  assign trig32_in[0]  = sw_trigger; // software trigger
  assign trig32_in[1]  = 0; // not used pulser trigger
  assign trig32_in[2]  = 0; // not used conf_enable_sas_or
  assign trig32_in[3]  = 0; // not used conf_pulser_run
  assign trig32_in[4]  = 0; // not used conf_output_pulser
  assign trig32_in[5]  = esata_nim_grand_or;
  assign trig32_in[6]  = adc16_grand_or;
  assign trig32_in[7]  = adc32_grand_or;
  assign trig32_in[8]  = adc16_mult_1ormore;
  assign trig32_in[9]  = adc16_mult_2ormore;
  assign trig32_in[10] = adc16_mult_3ormore;
  assign trig32_in[11] = adc16_mult_4ormore;
  assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
  assign trig32_in[13] = 0; // not used conf_enable_udp
  assign trig32_in[14] = 0; // not used conf_enable_busy
  assign trig32_in[15] = adc_grand_or;
  assign trig32_in[16] = aw16_coinc_a;
  assign trig32_in[17] = aw16_coinc_b;
  assign trig32_in[18] = aw16_coinc_c;
  assign trig32_in[19] = aw16_coinc_d;
  assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
  assign trig32_in[21] = aw16_coinc_trig;
  assign trig32_in[22] = aw16_mlu_trig;
  assign trig32_in[23] = timeout_trig;
  assign trig32_in[24] = aw16_mult_1ormore;
  assign trig32_in[25] = aw16_mult_2ormore;
  assign trig32_in[26] = aw16_mult_3ormore;
  assign trig32_in[27] = aw16_mult_4ormore;
  assign trig32_in[28] = bsc_grand_or_trig;
  assign trig32_in[29] = bsc_mult_trig;
  assign trig32_in[30] = coinc_trig;
  assign trig32_in[31] = 0; // not used
</pre>
 
Firmware 0x62c77f0b
 
<pre>
  udp_trig_bits  <= trig32_in;
  assign trig32_in[0]  = sw_trigger; // software trigger
  assign trig32_in[1]  = 0; // not used pulser trigger
  assign trig32_in[2]  = 0; // not used conf_enable_sas_or
  assign trig32_in[3]  = 0; // not used conf_pulser_run
  assign trig32_in[4]  = 0; // not used conf_output_pulser
  assign trig32_in[5]  = esata_nim_grand_or;
  assign trig32_in[6]  = adc16_grand_or;
  assign trig32_in[7]  = adc32_grand_or;
  assign trig32_in[8]  = adc16_mult_1ormore;
  assign trig32_in[9]  = adc16_mult_2ormore;
  assign trig32_in[10] = adc16_mult_3ormore;
  assign trig32_in[11] = adc16_mult_4ormore;
  assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
  assign trig32_in[13] = 0; // not used conf_enable_udp
  assign trig32_in[14] = 0; // not used conf_enable_busy
  assign trig32_in[15] = adc_grand_or;
  assign trig32_in[16] = 0; // aw16_coinc_a;
  assign trig32_in[17] = 0; // aw16_coinc_b;
  assign trig32_in[18] = 0; // aw16_coinc_c;
  assign trig32_in[19] = 0; // aw16_coinc_d;
  assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
  assign trig32_in[21] = aw16_coinc_trig;
  assign trig32_in[22] = aw16_mlu_trig;
  assign trig32_in[23] = timeout_trig;
  assign trig32_in[24] = 0; // aw16_mult_1ormore;
  assign trig32_in[25] = 0; // aw16_mult_2ormore;
  assign trig32_in[26] = 0; // aw16_mult_3ormore;
  assign trig32_in[27] = 0; // aw16_mult_4ormore;
  assign trig32_in[28] = bsc_grand_or_trig;
  assign trig32_in[29] = bsc64_mult_trig;
  assign trig32_in[30] = coinc_trig;
  assign trig32_in[31] = 0; // not used
</pre>
 
= TRG chronobox inputs =
 
from trg_firmware/toplevel/grifc.v
 
<pre>
  localparam CB_N = 23;
  localparam CB_N1 = CB_N-1;
 
  wire [CB_N1:0]    cb_xinputs_async;
 
  assign cb_xinputs_async[0] = ag_trig_out;
  assign cb_xinputs_async[1] = ag_trig_scaledown_out;
  assign cb_xinputs_async[2] = ag_trig_drift_out;
  assign cb_xinputs_async[3] = ag_trig_received_out;
 
  assign cb_xinputs_async[4] = ag_cb_sw_trig;
  assign cb_xinputs_async[5] = ag_cb_pulser_trig;
  assign cb_xinputs_async[6] = ag_cb_esata_nim_trig;
  assign cb_xinputs_async[7] = ag_cb_adc16_grand_or_trig;
  assign cb_xinputs_async[8] = ag_cb_adc32_grand_or_trig;
 
  assign cb_xinputs_async[9] = ag_cb_aw16_grand_or_trig;
  assign cb_xinputs_async[10] = ag_cb_aw16_mult_1ormore;
  assign cb_xinputs_async[11] = ag_cb_aw16_mult_2ormore;
  assign cb_xinputs_async[12] = ag_cb_aw16_mult_3ormore;
  assign cb_xinputs_async[13] = ag_cb_aw16_mult_4ormore;
  assign cb_xinputs_async[14] = ag_cb_aw16_mlu_trig;
 
  assign cb_xinputs_async[15] = ag_cb_bsc64_grand_or_trig;
  assign cb_xinputs_async[16] = ag_cb_bsc64_mult_1ormore;
  assign cb_xinputs_async[17] = ag_cb_bsc64_mult_2ormore;
  assign cb_xinputs_async[18] = ag_cb_bsc64_mult_3ormore;
  assign cb_xinputs_async[19] = ag_cb_bsc64_mult_4ormore;
  assign cb_xinputs_async[20] = ag_cb_bsc64_mult_trig;
 
  assign cb_xinputs_async[21] = ag_cb_coinc_trig;
 
  assign cb_xinputs_async[22] = ag_cb_timeout_trig;
</pre>
 
= Example UDP packets =
 
* trigger data, marker words 0x8
 
<pre>
ReadDataThread read 76
  0: 0x003666ed -- UDP packet counter from UDP transmitter
  1: 0x80000bf8 -- 0x8 is trigger data packet, 0xbf8 is the trigger counter from alphag.v
  2: 0x2edf8b41 -- trigger data
  3: 0x00000bf8
  4: 0x00000bf8
  5: 0x00000bee
  6: 0x00000001
  7: 0x00000000
  8: 0x00000000
  9: 0x00000003
10: 0x00000bf8
11: 0x00000bf8
12: 0x00000000
13: 0x00000000
14: 0x00000000
15: 0x00000000
16: 0x00000000
17: 0x00000000
18: 0xe0000bf8 -- 0xE is end of trigger data, counter 0xbf8 must match the counter in the 0x8 word.
ReadDataThread read 76 -- next packet
  0: 0x003666ee -- UDP packet counter from UDP transmitter
...
</pre>
 
* chronobox fifo data, marker word 0xC, see [[Chronobox#FIFO_data_format]]
 
<pre>
ReadDataThread read 404
  0: 0x003658ed -- UDP packet counter from UDP transmitter
  1: 0xc000eacc -- 0xC is FIFO data, fifo packet counter 0xeacc from fifo_to_udp.v
  2: 0x00000061 -- FIFO status, low bits the the word counter, so up to 0x61 fifo words are to follow
  3: 0x87fb3d72 -- tsc hits
  4: 0x8ffb3d74
  5: 0x90fb3d74
  6: 0x91fb3d74
  7: 0x92fb3d74
  8: 0x93fb3d74
  9: 0x93fb3d75
10: 0x94fb3d74
11: 0x94fb3d77
12: 0x87fb3d77
13: 0x8ffb3d77
14: 0x90fb3d77
15: 0x91fb3d77
16: 0x92fb3d77
17: 0xfe000018 -- 0xFE scaler data starts, 0x18 words to follow
18: 0x00000000
19: 0x00000000
20: 0x00000000
21: 0x00000000
22: 0x00000000
23: 0x00000000
24: 0x00000000
25: 0x00000108
26: 0x00000000
27: 0x00000000
28: 0x00000000
29: 0x00000000
30: 0x00000000
31: 0x00000000
32: 0x00000000
33: 0x00000108
34: 0x00000108
35: 0x00000108
36: 0x00000108
37: 0x00000108
38: 0x00000108
39: 0x00000000
40: 0x00000000
41: 0xce56fa93 -- last word of scaler data is the sysclock counter (125 MHz)
42: 0xff800048 -- timestamp wraparound
43: 0x8f1f36e4 -- tsc hits
44: 0x901f36e4
45: 0x911f36e4
46: 0x921f36e4
47: 0x931f36e4
48: 0x941f36e4
49: 0x871f36e4
50: 0x871f36e7
51: 0x8f1f36e7
52: 0x901f36e9
53: 0x911f36e7
54: 0x921f36e9
55: 0x931f36e7
56: 0x941f36e9
57: 0x904330ac
58: 0x914330ac
59: 0x924330ac
60: 0x934330ac
61: 0x934330ad
62: 0x944330ac
63: 0x944330ad
64: 0x874330ac
65: 0x874330ad
66: 0x8f4330ac
67: 0x8f4330ad
68: 0x904330ad
69: 0x914330ad
70: 0x924330ad
71: 0x8f672a62
72: 0x90672a62
73: 0x91672a62
74: 0x92672a62
75: 0x93672a62
76: 0x94672a62
77: 0x87672a62
78: 0x87672a65
79: 0x8f672a65
80: 0x90672a65
81: 0x91672a65
82: 0x92672a65
83: 0x93672a65
84: 0x94672a65
85: 0xff000049
86: 0x878b2422
87: 0x8f8b2424
88: 0x908b2424
89: 0x918b2424
90: 0x928b2424
91: 0x938b2424
92: 0x938b2425
93: 0x948b2424
94: 0x948b2427
95: 0x878b2427
96: 0x8f8b2427
97: 0x908b2427
98: 0x918b2427
99: 0x928b2427
100: 0xe000eacc -- 0xE is end of fifo data, counter 0xeacc must match the counter in the 0xC word.
ReadDataThread read 344 -- next packet
...
</pre>
 
= TODO =


* add FwRev to the UDP data output
* DONE July 2022. add FwRev to the UDP data output
* RJ45 SFP: PROBLEM, D.A. CABLE: GOOD, Fiber SFP: ???. fix "write did not happen" (send udp write command, there is no reply, read returns old data as if write never happened). suspect udp "write" packet is lost?
* PROBLEM GONE Aug 2021. fix reply to wrong socket - udp packets should reply to same socket as they came from, udp data packets should be sent to same socket as requested them, not same socket as last command.
* DONE 2021jul30. add fixes from Chris P. for the auto-negotiation and dhcp (see email from him).
* DONE flash chip connected to FPGA. Aug 2021. implement ethernet flash programmer
* DONE Aug 2021. updated maxv firmware. implement FPGA reboot
* speed up programming the MLU by writing more than 1 bit at a time
* DONE Nov 2021. add 64-bit bitmap of BSC trigger bits
* DONE. add chronobox code
* DONE. add avalon mux for alphag and chronobox packets
* DONE. add chronobox fifo to udp packet sequencer
* check that TxReadyOut is correct and it is safe to send an avalon packet while previous packet is still transmitting.
* DONE. test fiber SFP is working
* complete the UDP flash programmer (parallel flash erase and write)


== End ==
= End =


//KO
//KO

Latest revision as of 10:06, 25 July 2022

TRG, the trigger control board for the ALPHA-g detector

Links

General characteristics

Photos

Board schematics

Available hardware

  • Altera Stratix IV - main FPGA
  • Altera Max V - boot FPGA
  • boot flash: PC28F512M29EW - 512 Mbit parallel NOR flash.

TRG front panel connections

From top to bottom: 

|
| minisas-C - links 8-11
| minisas-D - links 12-15
|
| ethernet sfp - use copper sfp only
| minisas - not used, do not connect
| esata - clock in, trigger out
|
| minisas-A - links 0-3
| minisas-B - links 4-7
|
| LEDs
|

MiniSAS and SATA flail cable connections: 

P1 <--> link 3
P2 <--> link 2
P3 <--> link 1
P4 <--> link 0

LEDs: 

--PCB-- (left)
LED[0] - trigger out - ag_trig_out
LED[1] - network packet received - sfp_rx_data_valid
LED[2] - Xilinx FPGA boot ok - FMC1_CFG_DONE
LED[3] - not used
(right)

TRG onboard jumpers and switches

  • rotary switches: select IP address: 00=192.168.1.50, 11=.51, 22=.52, 33=.53, 44=.54, otherwire=.251

Firmware update procedure

  • use quartus to generate the grifc.pof file (use grifc.cof)
  • open quartus programmer
  • attach grifc.pof to the 1st CFI_512 flash
  • mark program/configure for the same flash (3 marks: pof, page_0 and OPTION_BITS
  • check that "initiate configuration after programming" is set in tools->options
  • say "start"
  • should take about 5 minutes
  • grifc should reboot into the new firmware

If CFI_512 flash is not visible to the quartus programmer, load correct code into the MaxV CPLD:

  • open quartus programmer,
  • say "auto detect"
  • change file for the 5M2210 device
  • use .../boot/maxv_3xfmc_normal.pof from the firmware git repository
  • say "program", it should finish in 10-15 seconds
  • say "auto detect"
  • CFI_512 flash should be visible now.

Firmware revisions

  • 0x5bc8f90f - original firmware used for all data
  • 0x6147c0f9 - added cbtrg, etc. installed at CERN on 20 Sep 2021.
  • 0x618376ae - bigger cbtrg fifo, data rate tested up to 30 Mbytes/sec
  • 0x6189c7f3 - fix loss of trigger packets. (missing fifo between alphag block and ethernet mux)
  • 0x618b790b - fix loss of timestamps. (cbtrg inputs stretched to 100 ns long). installed at CERN 10 Nov 2021.
  • 0x62d32d95 - updated cbtrg, switched to edge-triggered cbtrg inputs, improved BSC multiplicity trigger, improved coinc trigger, added burst pulser. installed at CERN 19 Jul 2022.
  • 0x62ded109 - fix cbtrg fifo data corruption, 1st fifo word was missing, 2nd fifo word sent twice.

Firmware build

  • use quartus 20.1
  • see Makefile in the trg_firmware project

Jtag remote connection

  • ssh agmini@daq16
  • /opt/intelFPGA/16.1/quartus/bin/jtagd --config /home/agmini/.jtagd.conf
  • netstat -an | grep 1309 ### note listen address is "0.0.0.0", NOT "127.0.0.1"
tcp        0      0 0.0.0.0:1309            0.0.0.0:*               LISTEN
  • opt/intelFPGA/16.1/quartus/bin/jtagconfig ### should work
  • ssh olchansk@daq01
  • cd git/trg_firmware
  • /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
  • jtagconfig ### should work
daq01:trg_firmware$ jtagconfig
1) DE-SoC on daq16 [2-1.2.3]
  4BA00477   SOCVHPS
  02D020DD   5CSEBA6(.|ES)/5CSEMA6/..

2) USB-Blaster on daq16 [2-1.3]
  024090DD   EP4SGX230(.|ES)
  020A40DD   5M(1270ZF324|2210Z)/EPM2210

daq01:trg_firmware$

ALPHA-g trigger functions

Trigger options:

  • software trigger
  • pulser trigger
  • trigger on GRIF16 ADC NIM and ESATA inputs ("external trigger")
  • adc16 grand-or
  • adc32 grand-or
  • adc16 wire multiplicity
  • TPC anode wire per-preamp trigger (aw16 section)
    • trigger on coincidences of preamps (removed fw 0x62c77f0b)
    • trigger on multiplicity of preamps (removed fw 0x62c77f0b)
    • trigger on specific topology of preamps (multiplicity of preamp clusters, etc) via the aw16_mlu trigger
  • BSC trigger
    • BSC grand_or
    • BSC bar multiplicity
  • coincidence trigger - select coincidence of external trigger, TPC AW grand-or, TPC AW MLU, BSC grand-or and BSC bar multiplicity triggers

software trigger

to programmatically fire the trigger, one should:

  • set the conf_enable_sw_trigger bit in conf_trig_enable, this will permit the software trigger to fire the trigger
  • write value 0x4 to register 0x2B, this will cause the software trigger to fire

pulser trigger

To use the pulser trigger, one should program:

  • pulser period (in clocks)
  • pulser width (in clocks, use value 5, the pulser no longer goes outside of the trigger board, so changing the width does not do anything)
  • set the run_pulser bit in conf_trig_enable, this will cause the pulser to run
  • set the enable_pulser bit in conf_trig_enable, this will cause the pulser to fire the trigger
  • set the output_pulser bit in conf_trig_enable, this will cause the pulser to be output from the alphag firmware block (the pulser no longer goes outside of the trigger board, so changing the bit does not do anything)

timeout trigger

The event builder uses event timestamps to assemble physics events. The timestamps are usually 32 bit wide and run at 125 MHz (8 ns) or 62.5 MHz (16 ns). If triggers are generated often (1 per second or more), timestamp wrap around is easily detected by the event builder. If triggers come infrequently, timestamp wrap around may occur while there are no triggers, not be seen by the event builder causing loss of event synchronization.

To avoid this problem in the event builder, a timeout trigger should be generated if no triggers were generated inside a 10 second interval.

The guaranties that even if all physics triggers temporarily stop for any reason, the event builder will stay synchronized. (0.1 Hz timeout trigger frequency).

To enable the timeout trigger:

  • program timeout trigger timeout in reg 0x43 in units of 8 ns clock
  • enable it in bit 23 of #conf_trig_enable bits

adc16 multiplicity trigger

This trigger is intended for use with the barrel scintillator signals connected to adc16 digitizers. It does not work well with TPC AW signals.

The 16 adc16 trigger bits (16x16=256) are added together to form the hit multiplicity value (adc16_mult, 16 bits, actual range 0 to 256).

Four threshold signals are computed: adc16_mult_1ormore = adc16_mult>=1, 2ormore, 3ormore, 4ormore.

There is a counter for each of these four signals.

Each of these four signals can fire the trigger, see #conf_trig_enable bits.

TPC anode wire triggers

aw16 bus

TPC Anode Wire trigger is based on the aw16[15:0] (xaw16) bus.

Each bit corresponds to one AW preamp. 16 preamps, 16 bits.

The aw16[15:0] bus can be fed by

  • adc16_or16[15:0] - or16 of 100 MHz ADCs, 16 ADC sas links
  • adc32_or16[15:0] - or16 of 62.5 MHz ADCs, FMC-ADC32 has 32 channels, so 2 bits per ADC: low 16 channels and high 16 channels, sas links 7..0
  • adc32_or16[31:16] - or16 of 62.5 MHz ADCs, ditto, sas links 15..8

as selected by conf_enable_aw_adc16, conf_enable_aw_adc32a, conf_enable_aw_adc32b in #conf_control bits 

   ///////////////////////////////////////////////////////////
   //           TPC Anode Wire trigger logic (aw16)
   ///////////////////////////////////////////////////////////

   // map adc signals into aw16

   wire [15:0] 		   aw16 = ({16{conf_enable_aw_adc16}} & adc16_or16[15:0]) |
			   ({16{conf_enable_aw_adc32a}} & adc32_or16[15:0]) |
			   ({16{conf_enable_aw_adc32b}} & adc32_or16[31:16]);
   ...
   ag_conditioner cond_adc16_or16_0(.clk(clk), .in(aw16[0]), .out(xxaw16[0]));
   ...
   xaw16 <= xxaw16;

aw16_grand_or

TPC AW "grand or" trigger: use aw16_mult_1ormore (before fw 0x62c77f0b)

(256 anode wires, 16 wires per preamp, 16 preamps, 16 aw16 signals)

aw16_mlu

TPC AW preamp MLU trigger: the MLU (memory lookup table) implements an arbitrary logical function to map the 16 aw16 preamp signals into 1 aw16_mlu_trig trigger output.

Description of the aw16 mlu trigger.

In words:

  • any aw16 signal starts the aw16_prompt_run gate
  • aw16 signals are collected for the duration of conf_mlu_prompt (125MHz/8ns clock)
  • this corresponds to time spread of TPC AW signals due to the drift time in the AW drift cell and to the variation in signal transmission time from the ADC to the TRG (digital trigger data link).
  • when this prompt time expires, the MLU looks at the accumulated aw16_prompt bit pattern and makes the "yes/no" trigger decision
  • after the trigger decision is made, we wait for the TPC to become quiet:
  • we wait until all aw16 signals are empty (no timeout)
  • we run the aw16_prompt_wait gate, length conf_mlu_wait (8ns clock), if any aw16 signals arrive, we wait for aw16 empty again, rinse, repeat.
  • now, after TPC aw16 have been empty for conf_mlu_wait clocks (8ns clock), MLU trigger is ready for the next event.

In logic: (see alphag.v)

  • aw16_or <= grand-or of 16 aw16 signals
  • "aw16_or" starts the "aw16_prompt_cnt" counter, opens the aw16_prompt_run gate
  • during the aw16_prompt_run gate, aw16_prompt collects (latches) the aw16 bits (aw16_prompt <= aw16_prompt | aw16)
  • this is the time when we wait for all "prompt" signals from the TPC to arrive into the trigger
  • at the end of the aw16_prompt_run gate, the signal aw16_prompt_out is pulsed, latching the output of the MLU into aw16_mlu_trig
  • this is the MLU trigger "yes/no" trigger decision.
  • after the MLU trigger decision is made, we wait for the arrival and passing of all TPC drift signals
  • the aw16_prompt_wait_cnt and aw_prompt_wait gate opens
  • if any new aw16 signals arrive (they are TPC drift signals at this time), the aw16_prompt_wait gate is restarted
  • if no aw16 signals arrive during the full run of the aw16_prompt_wait gate ("TPC quiet time")
  • the aw16_prompt_wait and aw16_prompt gates are cleared and the MLU trigger is ready for the next event.

Good settings are:

  • conf_mlu_prompt: 64 (512 ns)
  • conf_mlu_wait: 128 (1024 ns)

BSC trigger

bsc_adc16 bus

The BSC trigger is based on the [15:0]bsc_adc16[7:0] bus: 16 trigger discriminator bits from 8 ADC sas links. (8*16 = 64+64 bars, top and bottom).

The bsc_adc16 bus can be fed from sas links 0..7 or 8..15, controlled by conf_bsc_adc16_a and conf_bsc_adc16_b bits on #conf_bsc_control bits.

bsc_adc16 can be fed only from GRIF-16 100 MHz ADC trigger discriminators.

bsc64_top and bsc64_bot buses

  • firmware 0x5bc8f90f: bsc_adc16 is remapped into 64 bits of top (bsc64_top) and bottom (bsc64_bot):
ag_bsc_remap bsc_remap_a(.adc(bsc_adc16[0]), .bsc_bot(bsc64_bot[7:0]), .bsc_top(bsc64_top[7:0]));
   ag_bsc_remap bsc_remap_b(.adc(bsc_adc16[1]), .bsc_bot(bsc64_bot[8+7:8+0]), .bsc_top(bsc64_top[8+7:8+0]));
   ag_bsc_remap bsc_remap_c(.adc(bsc_adc16[2]), .bsc_bot(bsc64_bot[2*8+7:2*8+0]), .bsc_top(bsc64_top[2*8+7:2*8+0]));
   ag_bsc_remap bsc_remap_d(.adc(bsc_adc16[3]), .bsc_bot(bsc64_bot[3*8+7:3*8+0]), .bsc_top(bsc64_top[3*8+7:3*8+0]));

   ag_bsc_remap bsc_remap_e(.adc(bsc_adc16[4]), .bsc_bot(bsc64_bot[4*8+7:4*8+0]), .bsc_top(bsc64_top[4*8+7:4*8+0]));
   ag_bsc_remap bsc_remap_f(.adc(bsc_adc16[5]), .bsc_bot(bsc64_bot[5*8+7:5*8+0]), .bsc_top(bsc64_top[5*8+7:5*8+0]));
   ag_bsc_remap bsc_remap_g(.adc(bsc_adc16[6]), .bsc_bot(bsc64_bot[6*8+7:6*8+0]), .bsc_top(bsc64_top[6*8+7:6*8+0]));
   ag_bsc_remap bsc_remap_h(.adc(bsc_adc16[7]), .bsc_bot(bsc64_bot[7*8+7:7*8+0]), .bsc_top(bsc64_top[7*8+7:7*8+0]));

module ag_bsc_remap
  (
   input wire [15:0]  adc,
   output wire [7:0]  bsc_bot,
   output wire [7:0]  bsc_top
   );

   assign bsc_top[3] = adc[0];
   assign bsc_top[2] = adc[1];
   assign bsc_top[1] = adc[2];
   assign bsc_top[0] = adc[3];

   assign bsc_top[7] = adc[4];
   assign bsc_top[6] = adc[5];
   assign bsc_top[5] = adc[6];
   assign bsc_top[4] = adc[7];

   assign bsc_bot[0] = adc[8];
   assign bsc_bot[1] = adc[9];
   assign bsc_bot[2] = adc[10];
   assign bsc_bot[3] = adc[11];

   assign bsc_bot[4] = adc[12];
   assign bsc_bot[5] = adc[13];
   assign bsc_bot[6] = adc[14];
   assign bsc_bot[7] = adc[15];

endmodule

bsc64 bus

the bsc64 bus is the 64 bars used by the trigger, formed from bsc64_top and bsc64_bot: 

      if (conf_bsc64_bot_only) begin
	 bsc64 <= bsc64_bot;
      end else if (conf_bsc64_top_only) begin
	 bsc64 <= bsc64_top;
      end else if (conf_bsc64_bot_top_or) begin
	 bsc64 <= bsc64_bot | bsc64_top;
      end else if (conf_bsc64_bot_top_and) begin
	 bsc64 <= bsc64_bot & bsc64_top;
      end else begin
	 bsc64 <= 64'b0;
      end

bsc_grand_or_trig

bsc_grand_or_trig is the grand-or of 64 bits of the bsc64 bus

to enable triggering on bsc_grand_or_trig, set corresponding bit in #conf_trig_enable bits

old bsc_mult_trig

(from fw 0x62c77f0b, old bsc_mult_trig was replaced by new bsc64 multiplicity trigger)

  • bsc64_mult is computed as multiplicity of the bsc64 bus (number of 64 bsc64 bits that fired)
  • bsc_mult_trig is computed:
      if (bsc64_mult >= conf_bsc64_mult) begin
	 bsc_mult_trig <= 1;
      end else begin
	 bsc_mult_trig <= 0;
      end

to enable the bsc multiplicity trigger, set the multiplicity value conf_bsc64_mult in #conf_bsc_control bits and enable the corresponding bit in #conf_trig_enable bits.

bsc64 multiplicity trigger

bsc64 BSC bar multiplicity trigger uses a time window. this time window is started by bsc64_grand_or and runs for conf_bsc64_mult_window clocks (8 nc clock). During this time, hits in bsc64_bus are accumulated (latched) and their multiplicity is computed. If multiplicity condition is satisfied (bigger or equal to conf_bsc64_mult_min), bsc64_mult_trig is fired and the bsc64 bit pattern is saved to the UDP packet. Then trigger waits for the bsc64_bus to be empty. Then trigger waits for conf_bsc64_empty_window clocks, if there is any bsc64 hits, we wait for empty again. So after bsc64 has been empty for conf_bsc64_empty_window clocks, multiplicity trigger is ready for the next event. This scheme cannot implement max multiplicity.

recommended values:

  • conf_bsc64_mult_window (8 bits): slightly longer than 3 cycles of SAS link: 3*18 = 54 clocks, good value is 80 (640 ns).
  • conf_bsc64_mult_min (8 bits): 2
  • conf_bsc64_empty_window (8 bits): 80 (640 ns)

Coincidence trigger

Coincidence trigger provides a combination of TPC, BSC and external scintillator (esata_nim_grand_or) signals: 

   assign coinc_input[0] = aw16_grand_or; // was aw16_mult_1ormore;
   assign coinc_input[1] = aw16_mlu_trig;
   assign coinc_input[2] = bsc_grand_or_trig;
   assign coinc_input[3] = bsc_mult_trig;
   assign coinc_input[4] = esata_nim_grand_or;
   assign coinc_input[5] = 0;
   assign coinc_input[6] = 0;
   assign coinc_input[7] = 0;

Coincidence trigger "start" mask selects which of the inputs can start the coincidence window.

Coincidence trigger "require" mask selects which inputs must have a hits for the coincidence to be satisfied.

Input hits are collected for the duration of the coincidence window, if all required inputs have hits, coinc_trig is fired.

Example settings:

  • coincidence of external scintillator, BSC and TPC AW "grand or" signals: start 0x10, required 0x15
  • coincidence of BSC grand-or and TPC AW grand-or signals: start 0x5, required 0x5
  • coincidence of BSC multiplicity and TPC AW grand-or triggers: start 0x9, required 0x9

Control registers

Register addresses

Note: all registers are 32 bits unless otherwise noted.

Note: RW means read-write register, RO means read-only, ROL means read-only, contents is latched by the "latch_out" bit

Address Quartus Name Access FwRev Description
0x08 num_sample RW GRIF-C magic 16-bit register to control UDP packet size
0x08 scratch_reg RW 0x618b790b 32-bit scratch register
0x1F compilation_time RO Firmware revision
0x20 conf_trig_width RW Trigger signal width, 16 ns clock
0x21 conf_busy_width RW Busy signal width, 16 ns clock (not used)
0x22 conf_pulser_width RW Pulser signal width, 16 ns clock
0x23 conf_pulser_period RW Pulser signal period, 16 ns clock
0x24 conf_pulser_burst_ctrl RW 0x62d1c47e Generate bursts of pulses: 0xNNTTTTTT, NN=number of pulses, TTTTTT=period between pulses, 16 ns clocks
0x25 conf_trig_enable RW see #conf_trig_enable bits
0x26 not used
0x27 not used
0x28 not used
0x29 conf_nim_mask RW enable bits for ADC NIM inputs, 2 bits per ADC sas link, 16 links
0x2A conf_esata_mask RW enable bits for ADC eSATA inputs, 2 bits per ADC sas link, 16 links
0x2B reset_out, latch_out, trigger_out W see #reg 0x2B bits
0x2C conf_aw16_coinc_a RW 0x5bc8f90f configure AW coincidence trigger, see #aw16_coinc
0x2C conf_aw16_coinc_a RW 0x62c77f0b removed
0x2D conf_aw16_coinc_b RW 0x5bc8f90f
0x2E conf_aw16_coinc_c RW 0x5bc8f90f
0x2F conf_aw16_coinc_d RW 0x5bc8f90f
0x30 sas_sd[15:0] ROL 0x5b120c9f (01Jun18_20:18) sas signal detect for each link
0x31 pll_625_status ROL 0x5b2057f5 (12Jun18_16:32) 62.5MHz PLL status, bits: 31=locked, 30=active clock, 29=esata_clk_bad, 28=clk625_bad, 27:0 not used, to be lock counter
0x32 clk_counter ROL 0x5b2057f5 (12Jun18_16:32) frequency counter of the system 125 MHz clock
0x33 clk_625_counter ROL 0x5b2057f5 (12Jun18_16:32) frequency counter of the currently selected 62.5 MHz clock (my_clk_625)
0x34 conf_control RW 0x5b398983 (01Jul18_19:10) see #conf_control bits below
0x35 conf_drift_width RW 0x5b398983 (01Jul18_19:10) width of drift time blank-out in 16 ns clocks
0x36 conf_scaledown RW 0x5b398983 (01Jul18_19:10) trigger scaledown, 0=no scaledown, 1=divide-by-2, 2=divide-by-3, etc
0x37 conf_mlu RW 0x5b398983 (01Jul18_19:10) AW MLU control bits, see #conf_mlu bits
0x38 conf_trig_delay RW 0x5baedfca (28Sep18_19:13) delay the trigger pulse, 16 ns clock
0x39 esata_clk_counter ROL 0x5baedfca (28Sep18_19:13) frequency counter of the TRG 125 MHz clock
0x3A esata_clk_esata_counter ROL 0x5baedfca (28Sep18_19:13) frequency counter of the external clock (eSATA 62.5 MHz clock)
0x3B conf_counter_adc_select RW 0x5bb7f6ae (05Oct18_16:41) select which 16 ADCs are connected to the selected adc counters, 0..15 - connect the adc16 signals, 16..47 connect the adc32 signals
0x3C sysreset_ts RO 0x5bb7f6ae (05Oct18_16:41) 125MHz counter of VME-SYSRESET
0x3C 0x618b790b not used
0x3D GRIF-C csr RW GRIF-C <= csr & ~par_value; // Selective clear
0x3E GRIF-C csr RW GRIF-C par_value; // Selective set
0x3F GRIF-C csr RW GRIF-C <= par_value; // write
0x3D 0x618b790b not used
0x3E 0x618b790b not used
0x3F 0x618b790b not used
0x40 conf_bsc_control RW 0x5bc13541 (12Oct18_16:58) Barrel Scintillator trigger control, see #conf_bsc_control bits
0x41 conf_coinc_control RW 0x5bc13541 (12Oct18_16:58) Coincidence trigger control, see #conf_coinc_control bits
0x42 reconfig_out WO 0x5bc13541 (12Oct18_16:58) reserved for rebooting the FPGA (does not work)
0x43 conf_trigger_timeout RW 0x5bc8f90f (18Oct18_14:20) Generate timeout trigger if there is no other trigger after given timeout, in 8 ns clocks, must be enabled by bit conf_enable_timeout_trig in #conf_trig_enable bits
0x44 eth_clk_counter ROL 0x618b790b
0x45 eth_clk_eth_counter ROL 0x618b790b
0x100 ts_625 ROL latched timestamp
0x101 counter_trig_out ROL counter of issued triggers
0x102 counter_trig_in ROL counter of triggers
0x103 counter_pulser ROL counter of pulser
0x104 counter_adc16_grand_or ROL
0x105 counter_adc32_grand_or ROL
0x106 counter_adc_grand_or ROL
0x107 counter_esata_nim_grand_or ROL
0x108 counter_adc16_mult_1ormore ROL
0x109 counter_adc16_mult_2ormore ROL
0x10A counter_adc16_mult_3ormore ROL
0x10B counter_adc16_mult_4ormore ROL
0x10C counter_aw16_coinc_a ROL 0x5bc8f90f counter of AW coincidence triggers
0x10C counter_aw16_coinc_a ROL 0x62c77f0b removed
0x10D counter_aw16_coinc_b ROL 0x5bc8f90f
0x10E counter_aw16_coinc_c ROL 0x5bc8f90f
0x10F counter_aw16_coinc_d ROL 0x5bc8f90f
0x110 counter_drift ROL 0x5b398983 (01Jul18_19:10) counter of triggers that passed the drift time blank-out
0x111 counter_scaledown ROL 0x5b398983 (01Jul18_19:10) counter of triggers that passed the scaledown
0x112 counter_aw16_coinc ROL 0x5b398983 (01Jul18_19:10) counter of AW coincidence triggers
0x113 counter_aw16_mlu ROL 0x5b398983 (01Jul18_19:10) counter of AW MLU triggers
0x114 counter_aw16_grand_or ROL 0x62c77f0b counter of AW grand-or triggers
0x114 counter_aw16_mult_1ormore ROL 0x5bb7f6ae (05Oct18_16:41) counter of AW 1ormore triggers
0x115 counter_aw16_mult_2ormore ROL 0x5bb7f6ae (05Oct18_16:41) counter of AW 2ormore triggers
0x115 counter_aw16_mult_2ormore ROL 0x62c77f0b removed
0x116 counter_aw16_mult_3ormore ROL 0x5bb7f6ae (05Oct18_16:41) counter of AW 3ormore triggers
0x117 counter_aw16_mult_4ormore ROL 0x5bb7f6ae (05Oct18_16:41) counter of AW 4ormore triggers
0x118 counter_bsc_grand_or ROL 0x5bc13541 (12Oct18_16:58) counter of BSC grand-or triggers
0x119 counter_bsc_mult ROL 0x5bc13541 (12Oct18_16:58) counter of old BSC multiplicity triggers
0x11A counter_coinc ROL 0x5bc13541 (12Oct18_16:58) counter of coincidence triggers
0x11B counter_timeout ROL 0x618b790b counter of timeout triggers
0x11C counter_bsc_mult_start ROL 0x62c77f0b counter of BSC multiplicity windows
0x11D counter_bsc_mult_trig ROL 0x62c77f0b counter of BSC multiplicity triggers
0x11E counter_coinc_start ROL 0x62d1b152 counter of coincidence windows
0x11F counter_aw16_mlu_start ROL 0x62d1b152 counter of TPC AW MLU windows
0x200..0x207 conf_adc16_masks RW all adc16 enable bits
0x300..0x30F conf_adc32_masks RW all adc32 enable bits
0x400..0x41F sas_bits[15:0][63:0] ROL all sas data bits for each link
0x420..0x42F sas_sd_counters[15:0] ROL 0x5b120c9f (01Jun18_20:18) sas signal detect counter for each link
0x430..0x43F counters_adc16_or16[15:0] ROL 0x5b120c9f (01Jun18_20:18) 16 counters of adc16 ORes
0x440..0x45F counters_adc32_or16[31:0] ROL 0x5b120c9f (01Jun18_20:18) 32 counters of adc32 ORes
0x460..0x46F counters_adc_selected[15:0] ROL 0x5bb7f6ae (05Oct18_16:41) 16 counters for selected group of adcs, see conf_counter_adc_select
0x470..0x4AF counters_bsc64[63:0] ROL 0x5bc13541 (12Oct18_16:58) 64 counters for the BSC bars

additional registers

reg  | rw/ro/rol | quartus name  | firmware   | description
-----------------------------------------------------------------
0x60 | rw | cb_control_out       | 0x618b790b | chronobox control
0x61 | rw | cb_status            | 0x618b790b |  chronobox status
0x62 | rw | cb_invert_a_out      | 0x618b790b | chronobox input invert
0x63 | rw | cb_invert_b_out      | 0x618b790b |
0x64 | rw | cb_enable_le_a_out   | 0x618b790b | timestamp enable leading edge
0x65 | rw | cb_enable_le_b_out   | 0x618b790b |
0x66 | rw | cb_enable_te_a_out   | 0x618b790b | timestamp enable traiing edge 
0x67 | rw | cb_enable_te_b_out   | 0x618b790b | 
0x6A | ro | cb_input_num         | 0x618b790b | chronobox number of inputs
0x6B | rw | cb_sync_mask_a_out   | 0x618b790b | chronobox sync signal source
0x6C | rw | cb_sync_mask_b_out   | 0x618b790b | 
0x6D | rw | cb_sync_reg_out      | 0x618b790b | chronobox sync register
0x6E | ro | cb_sync_status       | 0x618b790b | chronobox sync status
0x6F | rw | cb_latch_period_out  | 0x618b790b | chronobox scalers latch period
0x70 | ro | cb_fifo_status       | 0x618b790b | chronobox data fifo status
0x71 | ro | cb_fifo_data         | 0x618b790b | read chronobox data fifo (cb_fifo_rdack_out <= 1)
0x72 | rw | cb_udp_period_out    | 0x618b790b | period for flushing fifo to UDP
0x73 | rw | cb_udp_threshold_out | 0x618b790b | byte threshold for flushing fifo to UDP

conf_control bits

Bit Quartus Name FwRev Description
0 conf_clock_select 0x5b3aa19f (02Jul18_15:05) select 0=internal 62.5 MHz clock or 1=esata 62.5 MHz clock
1 conf_enable_aw_adc16 0x5baedfca (28Sep18_19:13) select source of TPC AW aw16 bus, see #aw16 bus
2 conf_enable_aw_adc32a 0x5baedfca (28Sep18_19:13)
3 conf_enable_aw_adc32b 0x5baedfca (28Sep18_19:13)
15..4
23..16 conf_mlu_prompt 0x5b3aa19f (02Jul18_15:05) MLU trigger prompt window, see #aw16_mlu
31..24 conf_mlu_wait 0x5b3aa19f (02Jul18_15:05) MLU trigger wait window, see #aw16_mlu

conf_mlu bits

Bit Quartus Name FwRev Description
31 mlu_reset 0x5b3aa19f (02Jul18_15:05) not used
30 mlu_write 0x5b3aa19f (02Jul18_15:05) 1=write data bit into given address
16 mlu_data 0x5b3aa19f (02Jul18_15:05) data bit for writing to MLU RAM
15..0 mlu_write_addr 0x5b3aa19f (02Jul18_15:05) MLU RAM write address for writing the data bit

conf_bsc_control bits

Bit Quartus Name FwRev Description
0 conf_bsc_adc_a 0x5bc13541 (12Oct18_16:58) enable mapping of BSC ADCs to ADC links 0..7
1 conf_bsc_adc_b 0x5bc13541 (12Oct18_16:58) enable mapping of BSC ADCs to ADC links 8..15
2 conf_bsc64_bot_only 0x5bc13541 (12Oct18_16:58) bsc64 uses bottom channels only
3 conf_bsc64_top_only 0x5bc13541 (12Oct18_16:58) bsc64 uses top channels only
4 conf_bsc64_bot_top_or 0x5bc13541 (12Oct18_16:58) bsc64 uses "or" of top and bottom
5 conf_bsc64_bot_top_and 0x5bc13541 (12Oct18_16:58) bsc64 uses "and" of top and bottom
6
7
15..8 conf_bsc64_mult_min 0x5bc13541 (12Oct18_16:58) minimum bsc64 multiplicity
23..16 conf_bsc64_empty_wondow 0x62d1c47e bsc64 empty window length, 8 ns clocks
31..24 conf_bsc64_mult_window 0x62c77f0b bsc64 multiplicity window length, 8 ns clocks

conf_coinc_control bits

Bit Quartus Name FwRev Description
0 conf_coinc_required[0] 0x5bc13541 (12Oct18_16:58) enable aw16_mult_1ormore
0 conf_coinc_required[0] 0x62c77f0b enable aw16_grand_or
1 conf_coinc_required[1] 0x5bc13541 (12Oct18_16:58) enable aw16_mlu_trig
2 conf_coinc_required[2] 0x5bc13541 (12Oct18_16:58) enable bsc_grand_or_trig
3 conf_coinc_required[3] 0x5bc13541 (12Oct18_16:58) enable bsc_mult_trig
3 conf_coinc_required[3] 0x62c77f0b enable bsc64_mult_trig
4 conf_coinc_required[4] 0x5bc13541 (12Oct18_16:58) enable esata_nim_grand_or
5 conf_coinc_required[5]
6 conf_coinc_required[6]
7 conf_coinc_required[7]
15..8 conf_coinc_window[7:0] 0x5bc13541 (12Oct18_16:58) coincidence window length in units of 125MHz clock (8 ns)
23..16 conf_coinc_start[7:0] 0x5bc13541 (12Oct18_16:58) start the coincidence window, same bits as "required"
31..24

conf_trig_enable bits

Bit Quartus Name FwRev Description
0 conf_enable_sw_trigger trigger on software trigger (how generated???)
1 conf_enable_pulser trigger on pulser
2 - 0x5b120c9f (01Jun18_20:18) not used
3 conf_pulser_run allow the pulser to run (frequency has to be set beforehand)
4 conf_output_pulser 0x5bc8f90f does nothing (top level ag_pulser_out is disconnected)
4 0x618b790b not used
5 conf_enable_esata_nim trigger on ESATA and NIM grand-or (esata and nim masks should be set beforehand)
6 conf_enable_adc16 trigger on adc16_grand_or
7 conf_enable_adc32 trigger on adc32_grand_or
8 conf_enable_adc16_1ormore trigger on adc16_mult_1ormore "1 or more"
9 conf_enable_adc16_2ormore same, "2 or more"
10 conf_enable_adc16_3ormore same, "3 or more"
11 conf_enable_adc16_4ormore same, "4 or more"
12 - 0x5b08938c (25May18_15:51) not used
13 conf_enable_udp 0x5a7a3fbd (06Feb18_15:52) enable sending UDP packets
14 - 0x5bc8f90f not used
15 conf_enable_adc 0x5b120c9f (01Jun18_20:18) trigger on adc_grand_or
16 conf_enable_aw16_coinc_a 0x5bc8f90f enable AW coincidence trigger, see #aw16_coinc
16 - 0x62c77f0b aw16_coinc_x removed
17 conf_enable_aw16_coinc_b 0x5bc8f90f
18 conf_enable_aw16_coinc_c 0x5bc8f90f
19 conf_enable_aw16_coinc_d 0x5bc8f90f
20 - 0x5b3aa19f (02Jul18_15:05) not used
20 conf_enable_aw16_grand_or 0x618b790b enable trigger on aw16_grand_or
21 conf_enable_aw16_coinc 0x5b3aa19f (02Jul18_15:05) enable trigger on aw16_coinc_trig
22 conf_enable_aw16_mlu 0x5b3aa19f (02Jul18_15:05) enable AW MLU trigger
23 conf_enable_timeout_trig 0x5bc8f90f (18Oct18_14:20) enable trigger timeout trigger
24 conf_enable_aw16_1ormore 0x5b3aa19f (02Jul18_15:05) trigger on aw16_mult_1ormore "1 or more"
24 - 0x62c77f0b aw16_mult_xxx removed
25 conf_enable_aw16_2ormore 0x5b3aa19f (02Jul18_15:05) same, "2 or more"
26 conf_enable_aw16_3ormore 0x5b3aa19f (02Jul18_15:05) same, "3 or more"
27 conf_enable_aw16_4ormore 0x5b3aa19f (02Jul18_15:05) same, "4 or more"
28 conf_enable_bsc_grand_or 0x5bc13541 (12Oct18_16:58) trigger on BSC grand-or
29 conf_enable_bsc_mult 0x5bc13541 (12Oct18_16:58) trigger on BSC multiplicity
30 conf_enable_coinc 0x5bc13541 (12Oct18_16:58) trigger on TPC/BSC/ext coincidence trigger
31 - not used

reg 0x2B bits

Write to this register will pulse corresponding fpga signals:

Bit Quartus Name FwRev Description
0 reset_out 0x5b120c9f (01Jun18_20:18) reset counters, etc
1 latch_out 0x5b120c9f (01Jun18_20:18) latch counters, sas bits, etc
2 trigger_out 0x5b120c9f (01Jun18_20:18) generate a software trigger

UDP data format

general format

trigger packet:

[0] udp packet counter
[1] 0x8ccccccc
...
[N] 0xEccccccc

different versions of trigger packets should be decoded according to packet length:
40 bytes: initial firmware
76 bytes: firmware 0x618b790b (Nov 2021)
80 bytes: firmware 0x62d1c47e (Jul 2022)

chronobox fifo packet, firmware 0x618b790b (Nov 2021)

[0] udp packet counter
[1] 0xCccccccc
[2] fifo status
[3] fifo data
...
[N] 0xEccccccc

0x0ccccccc is the 28 bit fifo packet counter

chronobox fifo packet, firmware 0x618b790b (Nov 2021)

[0] udp packet counter
[1] 0xDccccccc
[2] 0xDEADBEEF
[3] fifo status
[4] fifo data
...
[N] 0xEccccccc

0x0ccccccc is the 28 bit fifo packet counter

firmware 0x5bc8f90f

Offset Name Quartus name FwRev Description
0 packet counter none all 31-bit UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
1 0x8 packet header all 28 bits of counter_trig_out
2 trigger timestamp trig_ts all 62.5MHz trigger timestamp
3 accepted triggers counter_trig_out all counter of accepted triggers
4 input triggers counter_trig_in all counter of trigger input
5 pulser triggers counter_pulser all counter of pulser triggers
6 trigger bitmap udp_trig_bits 0x5a48448d (30Dec17_17:59) bitmap of trigger information, see below
7 nim bits udp_nim_bits_masked ??? 32 bits of ADC NIM inputs (2 bits per ADC)
8 esata bits udp_esata_bits_masked ??? 32 bits of ADC ESATA inputs (2 bits per ADC)
9 mlu bits aw16_prompt 0x5b398983 (01Jul18_19:10) 16 bits of MLU input, 1 bit per preamp
10 drift-blank-off counter udp_drift_counter 0x5b3aa19f (02Jul18_15:05) counter of triggers that passed the drift blank-off
11 scaledown counter udp_scaledown_counter 0x5b3aa19f (02Jul18_15:05) counter of triggers that passed the scaledown
X
12 0xE packet footer all 28 bits of counter_trig_out

firmware 0x618b790b (Nov 2021)

packet size 76 bytes 

0 udp packet counter
1	   udp_data_out  <= {4'h8,udp_counter_trig_out[27:0]};
2	   udp_data_out <= udp_trig_ts_625;
3	   udp_data_out  <= udp_counter_trig_out;
4	   udp_data_out  <= udp_counter_trig_in;
5	   udp_data_out  <= udp_counter_pulser;
6	   udp_data_out  <= udp_trig_bits;
7	   udp_data_out  <= udp_nim_bits;
8	   udp_data_out  <= udp_esata_bits;
9	   udp_data_out  <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
10	   udp_data_out  <= udp_counter_drift;
11	   udp_data_out  <= udp_counter_scaledown;
12	   udp_data_out  <= { 8'h00, udp_adc16_mult[7:0], 16'h0000 };
13	   udp_data_out  <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
14	   udp_data_out  <= { udp_bsc64_bus[31:0]};
15	   udp_data_out  <= { udp_bsc64_bus[63:32]};
16	   udp_data_out  <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
17	   udp_data_out  <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
18	   udp_data_out  <= {4'hE,udp_counter_trig_out[27:0]};

firmware 0x62d1c47e (Jul 2022)

packet size 80 bytes 

0 udp packet counter
1	   udp_data_out  <= {4'h8,udp_counter_trig_out[27:0]};
2	   udp_data_out <= udp_trig_ts_625;
3	   udp_data_out  <= udp_counter_trig_out;
4	   udp_data_out  <= udp_counter_trig_in;
5	   udp_data_out  <= udp_counter_pulser;
6	   udp_data_out  <= udp_trig_bits;
7	   udp_data_out  <= udp_nim_bits;
8	   udp_data_out  <= udp_esata_bits;
9	   udp_data_out  <= { udp_aw16_mlu_out, 7'h00, 8'h00, udp_aw16_prompt[15:0]};
10	   udp_data_out  <= udp_counter_drift;
11	   udp_data_out  <= udp_counter_scaledown;
12	   udp_data_out  <= { 8'h00, 8'h00, 16'h0000 };
13	   udp_data_out  <= { 8'h00, udp_aw16_mult[7:0], udp_aw16_bus[15:0]};
14	   udp_data_out  <= { udp_bsc64_bus[31:0]};
15	   udp_data_out  <= { udp_bsc64_bus[63:32]};
16	   udp_data_out  <= { 8'h00, 8'h00, 8'h00, udp_bsc64_mult[7:0] };
17	   udp_data_out  <= { 8'h00, 8'h00, 8'h00, udp_coinc_latch[7:0] };
18         udp_data_out  <= conf_fw_rev;
19	   udp_data_out  <= {4'hE,udp_counter_trig_out[27:0]};

Values of udp_coinc_latch[7:0]:

  • aaa

Values of udp_aw16_mult[7:0] and udp_aw16_bus[15:0]:

  • aaa

Values of udp_bsc64_mult[7:0] and udp_bsc64_bus[63:0]

  • aaa

trigger bitmap

Firmware ??? (one of the very early revisions) 

              udp_trig_bits[0] <= adc16_grand_or;
              udp_trig_bits[1] <= adc32_grand_or;
              udp_trig_bits[2] <= adc_grand_or;
              udp_trig_bits[3] <= esata_nim_grand_or;
              udp_trig_bits[4] <= adc16_coinc_top;
              udp_trig_bits[5] <= adc16_coinc_bot;
              udp_trig_bits[6] <= adc16_coinc;
              udp_trig_bits[7] <= 0;
              udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
              udp_trig_bits[31:24] <= mult16[7:0];

Firmware 0x5b08938c (25May18_15:51) 

              udp_trig_bits[0] <= adc16_grand_or;
              udp_trig_bits[1] <= adc32_grand_or;
              udp_trig_bits[2] <= adc_grand_or;
              udp_trig_bits[3] <= esata_nim_grand_or;
              udp_trig_bits[4] <= 0; // not used
              udp_trig_bits[5] <= 0; // not used
              udp_trig_bits[6] <= 0; // not used
              udp_trig_bits[7] <= 0;
              udp_trig_bits[23:8] <= 0; // not used
              udp_trig_bits[31:24] <= mult16[7:0];

Firmware 0x5b217dc4 (13Jun18_13:25) 

              udp_trig_bits[0] <= adc16_grand_or;
              udp_trig_bits[1] <= adc32_grand_or;
              udp_trig_bits[2] <= adc_grand_or;
              udp_trig_bits[3] <= esata_nim_grand_or;
              udp_trig_bits[4] <= 0; // not used
              udp_trig_bits[5] <= 0; // not used
              udp_trig_bits[6] <= 0; // not used
              udp_trig_bits[7] <= 0;
              udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
              udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)

Firmware 0x5b3aa19f (02Jul18_15:05) 

              udp_trig_bits[0] <= adc16_grand_or;
              udp_trig_bits[1] <= adc32_grand_or;
              udp_trig_bits[2] <= adc_grand_or;
              udp_trig_bits[3] <= esata_nim_grand_or;
              udp_trig_bits[4] <= 0; // not used
              udp_trig_bits[5] <= 0; // not used
              udp_trig_bits[6] <= 0; // not used
              udp_trig_bits[7] <= udp_mlu_out;
              udp_trig_bits[23:8] <= xadc16_or16[15:0]; // 16x AW preamps hits
              udp_trig_bits[31:24] <= xadc16_or16_mult[7:0]; // 16x AW preamp multiplicity (sum of xadc16_or16 bits)

Firmware 0x5bc8f90f (18Oct18_14:20) 

   udp_trig_bits  <= trig32_in;
   assign trig32_in[0]  = trigger; // software trigger
   assign trig32_in[1]  = 0; // not used pulser trigger
   assign trig32_in[2]  = 0; // not used conf_enable_sas_or
   assign trig32_in[3]  = 0; // not used conf_run_pulser
   assign trig32_in[4]  = 0; // not used conf_output_pulser
   assign trig32_in[5]  = esata_nim_grand_or;
   assign trig32_in[6]  = adc16_grand_or;
   assign trig32_in[7]  = adc32_grand_or;
   assign trig32_in[8]  = adc16_mult_1ormore;
   assign trig32_in[9]  = adc16_mult_2ormore;
   assign trig32_in[10] = adc16_mult_3ormore;
   assign trig32_in[11] = adc16_mult_4ormore;
   assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
   assign trig32_in[13] = 0; // not used conf_enable_udp
   assign trig32_in[14] = 0; // not used conf_enable_busy
   assign trig32_in[15] = adc_grand_or;
   assign trig32_in[16] = aw16_coinc_a;
   assign trig32_in[17] = aw16_coinc_b;
   assign trig32_in[18] = aw16_coinc_c;
   assign trig32_in[19] = aw16_coinc_d;
   assign trig32_in[20] = 0; // not used conf_clock_select
   assign trig32_in[21] = aw16_coinc_trig;
   assign trig32_in[22] = aw16_mlu_trig;
   assign trig32_in[23] = timeout_trig;
   assign trig32_in[24] = aw16_mult_1ormore;
   assign trig32_in[25] = aw16_mult_2ormore;
   assign trig32_in[26] = aw16_mult_3ormore;
   assign trig32_in[27] = aw16_mult_4ormore;
   assign trig32_in[28] = bsc_grand_or_trig;
   assign trig32_in[29] = bsc_mult_trig;
   assign trig32_in[30] = coinc_trig;
   assign trig32_in[31] = 0; // not used

Firmware 0x618b790b 

   udp_trig_bits  <= trig32_in;
   assign trig32_in[0]  = sw_trigger; // software trigger
   assign trig32_in[1]  = 0; // not used pulser trigger
   assign trig32_in[2]  = 0; // not used conf_enable_sas_or
   assign trig32_in[3]  = 0; // not used conf_pulser_run
   assign trig32_in[4]  = 0; // not used conf_output_pulser
   assign trig32_in[5]  = esata_nim_grand_or;
   assign trig32_in[6]  = adc16_grand_or;
   assign trig32_in[7]  = adc32_grand_or;
   assign trig32_in[8]  = adc16_mult_1ormore;
   assign trig32_in[9]  = adc16_mult_2ormore;
   assign trig32_in[10] = adc16_mult_3ormore;
   assign trig32_in[11] = adc16_mult_4ormore;
   assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
   assign trig32_in[13] = 0; // not used conf_enable_udp
   assign trig32_in[14] = 0; // not used conf_enable_busy
   assign trig32_in[15] = adc_grand_or;
   assign trig32_in[16] = aw16_coinc_a;
   assign trig32_in[17] = aw16_coinc_b;
   assign trig32_in[18] = aw16_coinc_c;
   assign trig32_in[19] = aw16_coinc_d;
   assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
   assign trig32_in[21] = aw16_coinc_trig;
   assign trig32_in[22] = aw16_mlu_trig;
   assign trig32_in[23] = timeout_trig;
   assign trig32_in[24] = aw16_mult_1ormore;
   assign trig32_in[25] = aw16_mult_2ormore;
   assign trig32_in[26] = aw16_mult_3ormore;
   assign trig32_in[27] = aw16_mult_4ormore;
   assign trig32_in[28] = bsc_grand_or_trig;
   assign trig32_in[29] = bsc_mult_trig;
   assign trig32_in[30] = coinc_trig;
   assign trig32_in[31] = 0; // not used

Firmware 0x62c77f0b 

   udp_trig_bits  <= trig32_in;
   assign trig32_in[0]  = sw_trigger; // software trigger
   assign trig32_in[1]  = 0; // not used pulser trigger
   assign trig32_in[2]  = 0; // not used conf_enable_sas_or
   assign trig32_in[3]  = 0; // not used conf_pulser_run
   assign trig32_in[4]  = 0; // not used conf_output_pulser
   assign trig32_in[5]  = esata_nim_grand_or;
   assign trig32_in[6]  = adc16_grand_or;
   assign trig32_in[7]  = adc32_grand_or;
   assign trig32_in[8]  = adc16_mult_1ormore;
   assign trig32_in[9]  = adc16_mult_2ormore;
   assign trig32_in[10] = adc16_mult_3ormore;
   assign trig32_in[11] = adc16_mult_4ormore;
   assign trig32_in[12] = 0; // not used conf_enable_adc16_coinc
   assign trig32_in[13] = 0; // not used conf_enable_udp
   assign trig32_in[14] = 0; // not used conf_enable_busy
   assign trig32_in[15] = adc_grand_or;
   assign trig32_in[16] = 0; // aw16_coinc_a;
   assign trig32_in[17] = 0; // aw16_coinc_b;
   assign trig32_in[18] = 0; // aw16_coinc_c;
   assign trig32_in[19] = 0; // aw16_coinc_d;
   assign trig32_in[20] = aw16_grand_or; // was not used conf_clock_select
   assign trig32_in[21] = aw16_coinc_trig;
   assign trig32_in[22] = aw16_mlu_trig;
   assign trig32_in[23] = timeout_trig;
   assign trig32_in[24] = 0; // aw16_mult_1ormore;
   assign trig32_in[25] = 0; // aw16_mult_2ormore;
   assign trig32_in[26] = 0; // aw16_mult_3ormore;
   assign trig32_in[27] = 0; // aw16_mult_4ormore;
   assign trig32_in[28] = bsc_grand_or_trig;
   assign trig32_in[29] = bsc64_mult_trig;
   assign trig32_in[30] = coinc_trig;
   assign trig32_in[31] = 0; // not used

TRG chronobox inputs

from trg_firmware/toplevel/grifc.v 

   localparam CB_N = 23;
   localparam CB_N1 = CB_N-1;

   wire [CB_N1:0]    cb_xinputs_async;

   assign cb_xinputs_async[0] = ag_trig_out;
   assign cb_xinputs_async[1] = ag_trig_scaledown_out;
   assign cb_xinputs_async[2] = ag_trig_drift_out;
   assign cb_xinputs_async[3] = ag_trig_received_out;
   
   assign cb_xinputs_async[4] = ag_cb_sw_trig;
   assign cb_xinputs_async[5] = ag_cb_pulser_trig;
   assign cb_xinputs_async[6] = ag_cb_esata_nim_trig;
   assign cb_xinputs_async[7] = ag_cb_adc16_grand_or_trig;
   assign cb_xinputs_async[8] = ag_cb_adc32_grand_or_trig;
   
   assign cb_xinputs_async[9] = ag_cb_aw16_grand_or_trig;
   assign cb_xinputs_async[10] = ag_cb_aw16_mult_1ormore;
   assign cb_xinputs_async[11] = ag_cb_aw16_mult_2ormore;
   assign cb_xinputs_async[12] = ag_cb_aw16_mult_3ormore;
   assign cb_xinputs_async[13] = ag_cb_aw16_mult_4ormore;
   assign cb_xinputs_async[14] = ag_cb_aw16_mlu_trig;
   
   assign cb_xinputs_async[15] = ag_cb_bsc64_grand_or_trig;
   assign cb_xinputs_async[16] = ag_cb_bsc64_mult_1ormore;
   assign cb_xinputs_async[17] = ag_cb_bsc64_mult_2ormore;
   assign cb_xinputs_async[18] = ag_cb_bsc64_mult_3ormore;
   assign cb_xinputs_async[19] = ag_cb_bsc64_mult_4ormore;
   assign cb_xinputs_async[20] = ag_cb_bsc64_mult_trig;
   
   assign cb_xinputs_async[21] = ag_cb_coinc_trig;

   assign cb_xinputs_async[22] = ag_cb_timeout_trig;

Example UDP packets

  • trigger data, marker words 0x8
ReadDataThread read 76
  0: 0x003666ed -- UDP packet counter from UDP transmitter
  1: 0x80000bf8 -- 0x8 is trigger data packet, 0xbf8 is the trigger counter from alphag.v
  2: 0x2edf8b41 -- trigger data
  3: 0x00000bf8
  4: 0x00000bf8
  5: 0x00000bee
  6: 0x00000001
  7: 0x00000000
  8: 0x00000000
  9: 0x00000003
 10: 0x00000bf8
 11: 0x00000bf8
 12: 0x00000000
 13: 0x00000000
 14: 0x00000000
 15: 0x00000000
 16: 0x00000000
 17: 0x00000000
 18: 0xe0000bf8 -- 0xE is end of trigger data, counter 0xbf8 must match the counter in the 0x8 word.
ReadDataThread read 76 -- next packet
  0: 0x003666ee -- UDP packet counter from UDP transmitter
...

ReadDataThread read 404
  0: 0x003658ed -- UDP packet counter from UDP transmitter
  1: 0xc000eacc -- 0xC is FIFO data, fifo packet counter 0xeacc from fifo_to_udp.v
  2: 0x00000061 -- FIFO status, low bits the the word counter, so up to 0x61 fifo words are to follow
  3: 0x87fb3d72 -- tsc hits
  4: 0x8ffb3d74
  5: 0x90fb3d74
  6: 0x91fb3d74
  7: 0x92fb3d74
  8: 0x93fb3d74
  9: 0x93fb3d75
 10: 0x94fb3d74
 11: 0x94fb3d77
 12: 0x87fb3d77
 13: 0x8ffb3d77
 14: 0x90fb3d77
 15: 0x91fb3d77
 16: 0x92fb3d77
 17: 0xfe000018 -- 0xFE scaler data starts, 0x18 words to follow
 18: 0x00000000
 19: 0x00000000
 20: 0x00000000
 21: 0x00000000
 22: 0x00000000
 23: 0x00000000
 24: 0x00000000
 25: 0x00000108
 26: 0x00000000
 27: 0x00000000
 28: 0x00000000
 29: 0x00000000
 30: 0x00000000
 31: 0x00000000
 32: 0x00000000
 33: 0x00000108
 34: 0x00000108
 35: 0x00000108
 36: 0x00000108
 37: 0x00000108
 38: 0x00000108
 39: 0x00000000
 40: 0x00000000
 41: 0xce56fa93 -- last word of scaler data is the sysclock counter (125 MHz)
 42: 0xff800048 -- timestamp wraparound
 43: 0x8f1f36e4 -- tsc hits
 44: 0x901f36e4
 45: 0x911f36e4
 46: 0x921f36e4
 47: 0x931f36e4
 48: 0x941f36e4
 49: 0x871f36e4
 50: 0x871f36e7
 51: 0x8f1f36e7
 52: 0x901f36e9
 53: 0x911f36e7
 54: 0x921f36e9
 55: 0x931f36e7
 56: 0x941f36e9
 57: 0x904330ac
 58: 0x914330ac
 59: 0x924330ac
 60: 0x934330ac
 61: 0x934330ad
 62: 0x944330ac
 63: 0x944330ad
 64: 0x874330ac
 65: 0x874330ad
 66: 0x8f4330ac
 67: 0x8f4330ad
 68: 0x904330ad
 69: 0x914330ad
 70: 0x924330ad
 71: 0x8f672a62
 72: 0x90672a62
 73: 0x91672a62
 74: 0x92672a62
 75: 0x93672a62
 76: 0x94672a62
 77: 0x87672a62
 78: 0x87672a65
 79: 0x8f672a65
 80: 0x90672a65
 81: 0x91672a65
 82: 0x92672a65
 83: 0x93672a65
 84: 0x94672a65
 85: 0xff000049
 86: 0x878b2422
 87: 0x8f8b2424
 88: 0x908b2424
 89: 0x918b2424
 90: 0x928b2424
 91: 0x938b2424
 92: 0x938b2425
 93: 0x948b2424
 94: 0x948b2427
 95: 0x878b2427
 96: 0x8f8b2427
 97: 0x908b2427
 98: 0x918b2427
 99: 0x928b2427
100: 0xe000eacc -- 0xE is end of fifo data, counter 0xeacc must match the counter in the 0xC word.
ReadDataThread read 344 -- next packet
...

TODO

  • DONE July 2022. add FwRev to the UDP data output
  • RJ45 SFP: PROBLEM, D.A. CABLE: GOOD, Fiber SFP: ???. fix "write did not happen" (send udp write command, there is no reply, read returns old data as if write never happened). suspect udp "write" packet is lost?
  • PROBLEM GONE Aug 2021. fix reply to wrong socket - udp packets should reply to same socket as they came from, udp data packets should be sent to same socket as requested them, not same socket as last command.
  • DONE 2021jul30. add fixes from Chris P. for the auto-negotiation and dhcp (see email from him).
  • DONE flash chip connected to FPGA. Aug 2021. implement ethernet flash programmer
  • DONE Aug 2021. updated maxv firmware. implement FPGA reboot
  • speed up programming the MLU by writing more than 1 bit at a time
  • DONE Nov 2021. add 64-bit bitmap of BSC trigger bits
  • DONE. add chronobox code
  • DONE. add avalon mux for alphag and chronobox packets
  • DONE. add chronobox fifo to udp packet sequencer
  • check that TxReadyOut is correct and it is safe to send an avalon packet while previous packet is still transmitting.
  • DONE. test fiber SFP is working
  • complete the UDP flash programmer (parallel flash erase and write)

End

//KO

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