TRG: Difference between revisions

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|-
|-
| 0 || conf_enable_sw_trigger || init || ???
| 0 || conf_enable_sw_trigger || init || ???
|-
| 1 || conf_enable_pulser = conf_trig_enable[1];
|-
| 2 || conf_enable_sas_or = conf_trig_enable[2];
|-
| 3 || conf_run_pulser = conf_trig_enable[3];
|-
| 4 || conf_output_pulser = conf_trig_enable[4];
|-
| 5 || conf_enable_esata_nim = conf_trig_enable[5];
|-
| 6 ||  wire conf_enable_adc16 = conf_trig_enable[6];
|-
| 7 ||  wire conf_enable_adc32 = conf_trig_enable[7];
|-
| 8 ||  wire conf_enable_1ormore = conf_trig_enable[8];
|-
| 9 ||  wire conf_enable_2ormore = conf_trig_enable[9];
|-
| 10 ||  wire conf_enable_3ormore = conf_trig_enable[10];
|-
| 11 ||  wire conf_enable_4ormore = conf_trig_enable[11];
|-
| 12 ||  wire conf_enable_adc16_coinc = conf_trig_enable[12];
|-
|-
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
| 13 || conf_enable_udp || 0x5a7a3fbd (06Feb18_15:52) || enable sending UDP packets
|-
|-
| 14 || conf_enable_busy || 0x5a7a3fbd (06Feb18_15:52) || enable activation of busy counter
| 14 || conf_enable_busy || 0x5a7a3fbd (06Feb18_15:52) || enable activation of busy counter
|-
| 15 || - || - || not used
|-
| 16 || conf_enable_coinc_a = conf_trig_enable[16];
|-
| 17 || conf_enable_coinc_b = conf_trig_enable[17];
|-
| 18 || conf_enable_coinc_c = conf_trig_enable[18];
|-
| 19 || conf_enable_coinc_d = conf_trig_enable[19];
|-
|-
|}
|}
<pre>
  wire conf_enable_sw_trigger = conf_trig_enable[0];
  wire conf_enable_pulser = conf_trig_enable[1];
  wire conf_enable_sas_or = conf_trig_enable[2];
  wire conf_run_pulser = conf_trig_enable[3];
  wire conf_output_pulser = conf_trig_enable[4];
  wire conf_enable_esata_nim = conf_trig_enable[5];
  wire conf_enable_adc16 = conf_trig_enable[6];
  wire conf_enable_adc32 = conf_trig_enable[7];
  wire conf_enable_1ormore = conf_trig_enable[8];
  wire conf_enable_2ormore = conf_trig_enable[9];
  wire conf_enable_3ormore = conf_trig_enable[10];
  wire conf_enable_4ormore = conf_trig_enable[11];
  wire conf_enable_adc16_coinc = conf_trig_enable[12];
  wire conf_enable_udp    = conf_trig_enable[13];
  wire conf_enable_busy    = conf_trig_enable[14];
  wire conf_enable_coinc_a = conf_trig_enable[16];
  wire conf_enable_coinc_b = conf_trig_enable[17];
  wire conf_enable_coinc_c = conf_trig_enable[18];
  wire conf_enable_coinc_d = conf_trig_enable[19];
</pre>


== UDP data format ==
== UDP data format ==

Revision as of 10:22, 10 February 2018

ALPHAT, the trigger control board for the ALPHA-g detector

References

  • xxx

General characteristics

Photos

Board schematics

Available hardware

Firmware update procedure

Firmware revisions

ALPHA-g trigger functions

Control registers

Register addresses

Note: all registers are 32 bits unless otherwise noted.

Address Quartus Name Access FwRev Description
0x1F compilation_time RO Firmware revision
0x20 conf_trig_width <= par_value;
0x21 conf_busy_width <= par_value;
0x22 conf_pulser_width <= par_value;
0x23 conf_pulser_period <= par_value;
0x24 sw_trigger_counter <= 10;
0x25 conf_trig_enable <= par_value;
0x26 conf_sas_trig_mask <= par_value; obsolete
0x27 conf_sas_trig_mask_a <= par_value; obsolete
0x28 conf_sas_trig_mask_b <= par_value; obsolete
0x29 conf_nim_mask <= par_value;
0x2A conf_esata_mask <= par_value;
0x2B conf_latch <= 1;
0x2C conf_coinc_a <= par_value;
0x2D conf_coinc_b <= par_value;
0x2E conf_coinc_c <= par_value;
0x2F conf_coinc_d <= par_value;
0x100..0x11F scaler_data[1023..0]
0x200..0x207 conf_adc16_masks
0x300..0x30F conf_adc32_masks
0x400..0x41F ag_sas_bits[1023..0] 
remaining GRIF-C registers

            14'h001:  param_out <= {2'h3, par_id, chan, 16'h0,  threshold    };
            14'h002:  param_out <= {2'h3, par_id, chan,         pulser_ctrl  };
            14'h003:  param_out <= {2'h3, par_id, chan, 31'h0,  polarity     };
            14'h004:  param_out <= {2'h3, par_id, chan, 16'h0,  diff_const   };
            14'h005:  param_out <= {2'h3, par_id, chan, 16'h0,  integ_const  };
	    14'h006:  param_out <= {2'h3, par_id, chan, 22'h0,  decimation   };
            14'h007:  param_out <= {2'h3, par_id, chan, 16'h0,  num_pretrig  };
            14'h008:  param_out <= {2'h3, par_id, chan, 16'h0,  num_sample   };
            14'h009:  param_out <= {2'h3, par_id, chan, 16'h0,  pole_corn    };
            14'h00A:  param_out <= {2'h3, par_id, chan, 16'h0,  hitdet_integ };
            14'h00B:  param_out <= {2'h3, par_id, chan, 16'h0,  hitdet_diff  };
            14'h00C:  param_out <= {2'h3, par_id, chan, 16'h0,  integ_delay  };
            14'h00D:  param_out <= {2'h3, par_id, chan, 30'h0,  wavebuf_mode };
            14'h00E:  param_out <= {2'h3, par_id, chan,         trig_deadtime};
            14'h00F:  param_out <= {2'h3, par_id, chan, 31'h0,  enable_adc   };
            14'h010:  param_out <= {2'h3, par_id, chan, 28'h0,  detectortype };
            14'h011:  param_out <= {2'h3, par_id, chan,         sync_livetime};
            14'h012:  param_out <= {2'h3, par_id, chan,         sync_deadtime};

GRIF-C CSR register
              14'h3D: csr                  <= csr & ~par_value; // Selective clear
	      14'h3E: csr                  <= csr |  par_value; // Selective set
	      14'h3F: csr                  <= par_value;

map of scaler_data

map of scaler_data:

         if (i==0)
	   assign scaler_data_wire[i*32+31:i*32] = ts_625;
	 else if (i==1)
	   assign scaler_data_wire[i*32+31:i*32] = counter_trig_out;
	 else if (i==2)
	   assign scaler_data_wire[i*32+31:i*32] = counter_trig_in;
	 else if (i==3)
	   assign scaler_data_wire[i*32+31:i*32] = counter_pulser;
	 else if (i==4)
	   assign scaler_data_wire[i*32+31:i*32] = counter_adc16_grand_or;
	 else if (i==5)
	   assign scaler_data_wire[i*32+31:i*32] = counter_adc32_grand_or;
	 else if (i==6)
	   assign scaler_data_wire[i*32+31:i*32] = counter_adc_grand_or;
	 else if (i==7)
	   assign scaler_data_wire[i*32+31:i*32] = counter_esata_nim_grand_or;
	 else if (i==8)
	   assign scaler_data_wire[i*32+31:i*32] = counter_mult16_1ormore;
	 else if (i==9)
	   assign scaler_data_wire[i*32+31:i*32] = counter_mult16_2ormore;
	 else if (i==10)
	   assign scaler_data_wire[i*32+31:i*32] = counter_mult16_3ormore;
	 else if (i==11)
	   assign scaler_data_wire[i*32+31:i*32] = counter_mult16_4ormore;
	 else if (i==12)
	   assign scaler_data_wire[i*32+31:i*32] = counter_cc01;
	 else if (i==13)
	   assign scaler_data_wire[i*32+31:i*32] = counter_cc23;
	 else if (i==14)
	   assign scaler_data_wire[i*32+31:i*32] = counter_cc45;
	 else if (i==15)
	   assign scaler_data_wire[i*32+31:i*32] = counter_cc67;
	 else if (i==16)
	   assign scaler_data_wire[i*32+31:i*32] = { counter_adc16_or16[1][15:0], counter_adc16_or16[0][15:0] };
	 else if (i==17)
	   assign scaler_data_wire[i*32+31:i*32] = { counter_adc16_or16[3][15:0], counter_adc16_or16[2][15:0] };
	 else if (i==18)
	   assign scaler_data_wire[i*32+31:i*32] = { counter_adc16_or16[5][15:0], counter_adc16_or16[4][15:0] };
	 else if (i==19)
	   assign scaler_data_wire[i*32+31:i*32] = { counter_adc16_or16[7][15:0], counter_adc16_or16[6][15:0] };
	 else if (i==20)
	   assign scaler_data_wire[i*32+31:i*32] = { counter_adc16_or16[9][15:0], counter_adc16_or16[8][15:0] };
	 else if (i==21)
	   assign scaler_data_wire[i*32+31:i*32] = { counter_adc16_or16[11][15:0], counter_adc16_or16[10][15:0] };
	 else if (i==22)
	   assign scaler_data_wire[i*32+31:i*32] = { counter_adc16_or16[13][15:0], counter_adc16_or16[12][15:0] };
	 else if (i==23)
	   assign scaler_data_wire[i*32+31:i*32] = { counter_adc16_or16[15][15:0], counter_adc16_or16[14][15:0] };
	 else
	   assign scaler_data_wire[1023:i*32] = 0;

conf_trig_enable bits

Bit Quartus Name FwRev Description
0 conf_enable_sw_trigger init ???
1 conf_enable_pulser = conf_trig_enable[1];
2 conf_enable_sas_or = conf_trig_enable[2];
3 conf_run_pulser = conf_trig_enable[3];
4 conf_output_pulser = conf_trig_enable[4];
5 conf_enable_esata_nim = conf_trig_enable[5];
6 wire conf_enable_adc16 = conf_trig_enable[6];
7 wire conf_enable_adc32 = conf_trig_enable[7];
8 wire conf_enable_1ormore = conf_trig_enable[8];
9 wire conf_enable_2ormore = conf_trig_enable[9];
10 wire conf_enable_3ormore = conf_trig_enable[10];
11 wire conf_enable_4ormore = conf_trig_enable[11];
12 wire conf_enable_adc16_coinc = conf_trig_enable[12];
13 conf_enable_udp 0x5a7a3fbd (06Feb18_15:52) enable sending UDP packets
14 conf_enable_busy 0x5a7a3fbd (06Feb18_15:52) enable activation of busy counter
15 - - not used
16 conf_enable_coinc_a = conf_trig_enable[16];
17 conf_enable_coinc_b = conf_trig_enable[17];
18 conf_enable_coinc_c = conf_trig_enable[18];
19 conf_enable_coinc_d = conf_trig_enable[19];

UDP data format

Offset Name Quartus name FwRev Description
0 packet counter none all UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
1 0x8 packet header all 28 bits of counter_trig_out
2 trigger timestamp trig_ts all 62.5MHz trigger timestamp
3 accepted triggers counter_trig_out all counter of accepted triggers
4 input triggers counter_trig_in all counter of trigger input
5 pulser triggers counter_pulser all counter of pulser triggers
6 trigger bitmap udp_trig_bits 0x5a48448d (30Dec17_17:59) bitmap of trigger information, see below
7 nim bits udp_nim_bits_masked ??? 32 bits of ADC NIM inputs (2 bits per ADC)
8 esata bits udp_esata_bits_masked ??? 32 bits of ADC ESATA inputs (2 bits per ADC)
X
9 0x9 packet footer all 28 bits of counter_trig_out

trigger bitmap

              udp_trig_bits[0] <= adc16_grand_or;
              udp_trig_bits[1] <= adc32_grand_or;
              udp_trig_bits[2] <= adc_grand_or;
              udp_trig_bits[3] <= esata_nim_grand_or;
              udp_trig_bits[4] <= adc16_coinc_top;
              udp_trig_bits[5] <= adc16_coinc_bot;
              udp_trig_bits[6] <= adc16_coinc;
              udp_trig_bits[7] <= 0;
              udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
              udp_trig_bits[31:24] <= mult16[7:0];

TODO

  • add FwRev to the UDP data output

End

//KO

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