TRG

ALPHAT, the trigger control board for the ALPHA-g detector

References

• xxx

Control registers

Number	Name	Access	FwRev	Description
0	FwRev	RO		Firmware revision (0x01YYMMDD)

            14'h001:  param_out <= {2'h3, par_id, chan, 16'h0,  threshold    };
            14'h002:  param_out <= {2'h3, par_id, chan,         pulser_ctrl  };
            14'h003:  param_out <= {2'h3, par_id, chan, 31'h0,  polarity     };
            14'h004:  param_out <= {2'h3, par_id, chan, 16'h0,  diff_const   };
            14'h005:  param_out <= {2'h3, par_id, chan, 16'h0,  integ_const  };
	    14'h006:  param_out <= {2'h3, par_id, chan, 22'h0,  decimation   };
            14'h007:  param_out <= {2'h3, par_id, chan, 16'h0,  num_pretrig  };
            14'h008:  param_out <= {2'h3, par_id, chan, 16'h0,  num_sample   };
            14'h009:  param_out <= {2'h3, par_id, chan, 16'h0,  pole_corn    };
            14'h00A:  param_out <= {2'h3, par_id, chan, 16'h0,  hitdet_integ };
            14'h00B:  param_out <= {2'h3, par_id, chan, 16'h0,  hitdet_diff  };
            14'h00C:  param_out <= {2'h3, par_id, chan, 16'h0,  integ_delay  };
            14'h00D:  param_out <= {2'h3, par_id, chan, 30'h0,  wavebuf_mode };
            14'h00E:  param_out <= {2'h3, par_id, chan,         trig_deadtime};
            14'h00F:  param_out <= {2'h3, par_id, chan, 31'h0,  enable_adc   };
            14'h010:  param_out <= {2'h3, par_id, chan, 28'h0,  detectortype };
            14'h011:  param_out <= {2'h3, par_id, chan,         sync_livetime};
            14'h012:  param_out <= {2'h3, par_id, chan,         sync_deadtime};
	    14'h01F:  param_out <= {2'h3, par_id, chan,     compilation_time };

              14'h20: conf_trig_width     <= par_value;
              14'h21: conf_busy_width     <= par_value;
              14'h22: conf_pulser_width   <= par_value;
              14'h23: conf_pulser_period   <= par_value;
              14'h24: sw_trigger_counter <= 10;
              14'h25: conf_trig_enable   <= par_value;
	      14'h26: conf_sas_trig_mask <= par_value;
	      14'h27: conf_sas_trig_mask_a <= par_value;
	      14'h28: conf_sas_trig_mask_b <= par_value;
	      14'h29: conf_nim_mask <= par_value;
	      14'h2A: conf_esata_mask <= par_value;
	      14'h2B: conf_latch <= 1;

              14'h3D: csr                  <= csr & ~par_value; // Selective clear
	      14'h3E: csr                  <= csr |  par_value; // Selective set
	      14'h3F: csr                  <= par_value;

0x100..0x11F: scaler_data[1023..0]
0x200..0x207: conf_adc16_masks
0x300..0x30F: conf_adc32_masks
0x400..0x41F: ag_sas_bits[1023..0]

UDP data format

Offset	Name	Quartus name	FwRev	Description
0	packet counter	none	all	UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
1	0x8 packet header		all	28 bits of counter_trig_out
2	trigger timestamp	trig_ts	all	62.5MHz trigger timestamp
3	accepted triggers	counter_trig_out	all	counter of accepted triggers
4	input triggers	counter_trig_in	all	counter of trigger input
5	pulser triggers	counter_pulser	all	counter of pulser triggers
6	trigger bitmap	udp_trig_bits	0x5a48448d (30Dec17_17:59)	bitmap of trigger information, see below
7	nim bits	udp_nim_bits_masked	???	32 bits of ADC NIM inputs (2 bits per ADC)
8	esata bits	udp_esata_bits_masked	???	32 bits of ADC ESATA inputs (2 bits per ADC)
X
9	0x9 packet footer		all	28 bits of counter_trig_out

trigger bitmap

              udp_trig_bits[0] <= adc16_grand_or;
              udp_trig_bits[1] <= adc32_grand_or;
              udp_trig_bits[2] <= adc_grand_or;
              udp_trig_bits[3] <= esata_nim_grand_or;
              udp_trig_bits[4] <= adc16_coinc_top;
              udp_trig_bits[5] <= adc16_coinc_bot;
              udp_trig_bits[6] <= adc16_coinc;
              udp_trig_bits[7] <= 0;
              udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
              udp_trig_bits[31:24] <= mult16[7:0];

TODO

• add FwRev to the UDP data output

End

//KO