TRG

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ALPHAT, the trigger control board for the ALPHA-g detector

References

  • xxx

General characteristics

Photos

Board schematics

Available hardware

Firmware update procedure

Firmware revisions

ALPHA-g trigger functions

Control registers

Number Name Access FwRev Description
0 FwRev RO Firmware revision (0x01YYMMDD)

UDP data format

Offset Name Quartus name FwRev Description
0 packet counter none all UDP packet counter, counting from 0, reset by reboot. Automatically added by UDP transmitter code in the GRIFC base firmware
1 0x8 packet header all 28 bits of counter_trig_out
2 trigger timestamp trig_ts all 62.5MHz trigger timestamp
3 accepted triggers counter_trig_out all counter of accepted triggers
4 input triggers counter_trig_in all counter of trigger input
5 pulser triggers counter_pulser all counter of pulser triggers
6 trigger bitmap udp_trig_bits 0x5a48448d (30Dec17_17:59) bitmap of trigger information, see below
7 nim bits udp_nim_bits_masked ??? 32 bits of ADC NIM inputs (2 bits per ADC)
8 esata bits udp_esata_bits_masked ??? 32 bits of ADC ESATA inputs (2 bits per ADC)
X
9 0x9 packet footer all 28 bits of counter_trig_out

trigger bitmap

              udp_trig_bits[0] <= adc16_grand_or;
              udp_trig_bits[1] <= adc32_grand_or;
              udp_trig_bits[2] <= adc_grand_or;
              udp_trig_bits[3] <= esata_nim_grand_or;
              udp_trig_bits[4] <= adc16_coinc_top;
              udp_trig_bits[5] <= adc16_coinc_bot;
              udp_trig_bits[6] <= adc16_coinc;
              udp_trig_bits[7] <= 0;
              udp_trig_bits[23:8] <= adc16_coinc_dff[15:0];
              udp_trig_bits[31:24] <= mult16[7:0];

TODO

  • add FwRev to the UDP data output

End

//KO