Daq

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Network configuration

The experiment private network number is: 192.168.1.x, gateway 192.168.1.1, netmask 255.255.255.0

network map: 

---- TRIUMF/CERN network --1gige-- alphagdaq --10gige-- juniper switch --1gige-- centrecom switch

alphagdaq network connections on the back of the machine: 

-----------------------------------------
|   | rj45 | rj45 |         | sfp | sfp |
-----------------------------------------

- left rj45 - copper 1gige - eno1 - spare (inactive)
- right rj45 - copper 1gige - eno2 - dhcp - cern/triumf network
- left sfp - 10gige - enp1s0f0 - static 192.168.1.1
- right sfp - 10gige - enp1s0f1 - spare (inactive)

connections between switches:

  • alphagdaq to juniper switch: direct attach (DAC) 10gige cable into any port of juniper switch
  • juniper switch to centrecom switch: rj45 sfp in any port of juniper switch - cat5e/cat6 cable - to any port of centrecom switch
  • cat5e/cat6 cable from any port of centrecom switch to the XXX port on the back of the juniper switch

connected to the juniper switch:

  • everything that sends event data to alphagdaq, specifically:
    • TRG (rj45 sfp)
    • 16x ADC (fiber sfp)
    • 64x PWB (fiber sfp)
  • 10gige uplink to alphagdaq (10gige DAC cable)
  • 1gige link to centrecom switch (rj45 sfp)
  • 40gige ports are not used

connected to the centrecom switch:

  • everything with copper rj45 connections, specifically:
    • CDM boards
    • HV, LV and VME power supplies
    • RaspberryPi3 boards

Clock configuration

AAA

MIDAS frontends

UDP

feudp receives udp packets from the ADC and PWB boards. For each udp packet 1 midas event is created, with 1 data bank containing the udp data. Events are sent into the MIDAS event buffer BUFUDP. The names of the data banks are assigned in ODB /eq/feudp/settings.

{ADC,PWB} --> 1gige --> switch --> 10gige --> alphagdaq --> feudp -> BUFUDP

CTRL

fectrl controls all the ADC, PWB and trigger boards. It provides run start and stop sequencing, runs the event synchronization sequence at the begin of the run, and records slow controls data (temperatures, voltages, etc).

fectrl receives UDP data packets from the trigger board and sends them to the MIDAS event buffer BUFUDP.

fectrl receives commands from the control web pages (for ADC, PWB and trigger) to reboot, initialize, etc the boards.

fectrl configures the event builder via odb /eq/fectrl/evbconfig.

ADC <-> http esper <-> fectrl -> slow control data into midas history

PWB <-> http esper <-> fectrl -> slow control data into midas history

TRG <-> udp comm <-> fectrl -> BUFUDP, slow control and counters into midas history

fectrl <-> midas rpc <-> mhttpd <-> json rpc <-> control web pages for ADC, PWB and trigger

EVB

feevb receives udp packet data from the MIDAS event buffer BUFUDP, inspects the packet timestamps and collects the data with matching timestamps into physics events. feevb has provisions to do data suppression, reduction and compression in addition to the data reduction done in the ADC and PWB firmware.

feevb event synchronization relies on the event synchronization sequence done by fectrl when a run is started.

{ADC, PWB, TRG} -> BUFUDP -> feevb -> SYSTEM -> mlogger -> compression -> disk storage

ODB entries

  • /Equipment/
    • CTRL/Settings
      • TBW
    • CTRL/Settings/Trig - trigger settings
      • Enable - if set to "n", fectrl will not do anything with the trigger board. Normal value "y"
      • Modules - hostnames of the trigger board. Normal value "alphat01"
      • NimMask - 32-bit mask for the 32x NIM inputs (see TRG manual). Normal value 0, unless external trigger is in use.
      • EsataMask - 32-bit mask for the 32x eSATA signals (see TRG manual). Normal value 0.
      • adc16_mask[16] - 16x 16-bit mask for the 100MHz GRIF-16 onboard ADCs (see TRG manual). Normal value 0xFFFF for all 16 data links.
      • adc32_mask[16] - 16x 32-bit mask for the 62.5MHz FMC-ADC32 ADCs (see TRG manual). Normal value 0xFFFFFFFF for all 16 data links.
      • PassThrough - if set to "y", trigger is passed through the trigger module without generating any events and without causing deadtime.
      • CoincA, B, C and D - 32-bit masks for the adc16 coincidence trigger (see TRG manual)
    • CTRL/Settings/PWB - PWB settings
      • Enable - if set to "n", fectrl will not do anything with PWBs. Normal value "y".
      • enable_boot_user_page - if set to "n", fectrl will not try to reboot PWBs into the user page firmware. Normal value "y".
      • enable_trigger - if set to "n", all PWBs will be set to ignore the trigger. Normal value "y".
      • modules[64] - hostnames of PWB boards
      • boot_user_page[64] - if set to "y" and enable_boot_user_page is "y", fectrl will reboot the corresponding PWB to the user page firmware.
      • trigger[64] - if set to "y" and enable_trigget is "y", fectrl will set the PWB to accept the trigger.
      • ch_enable - if set to "n" disables all PWB channels. Normal value is "y".
      • ch_force - is set to "y" disables channel suppression (all PWB channels are read)
      • suppress_reset - if set to "y" enables channel suppression for reset channels (threshold has to be set correctly)
      • suppress_fpn - if set to "y" enables channel suppression for fpn channels (threshold has to be set correctly)
      • suppress_pads - set to "y" enables channel suppression for TPC pad channels (threshold has to be set correctly)
      • baseline_{reset,fpn,pads}[64] - waveform baseline for each PWB position
      • threshold_{reset,fpn,pads} - waveform suppression threshold, see below:
      • ch_threshold - PWB sca_N_ch_threshold, if set to 0, threshold is computed as "baseline_pads[seqpwb]-threshold_pads". Normal value is 0.

ZZZ

ZZZ

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