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VT4 info

2018-07-08T03:16:15Z

Cpearson:

== VME-VT4 - 4-channel timestamp module using the VME-IO32 board ==

UPDATE: July 2018 - some changes were made to operation ...
Time starts at first cycle pulse after reset, and then runs continuously
Gates are counted and written in place of cycle counter on gate-rise/fall
Gate-count resets to zero at start of each new cycle

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x0003C || CSR || RW || Control/Status Register
|-
| 1 || 0x00040 || Test || RW || Test Register
|-
| 2 || 0x00044 || Tstamp || R || Firmware Timestamp
|-
| 3 || 0x00048 || Nwords || R || Data Words available
|-
| 4 || 0x0004C || Data_Low || R || Data lower half [bits 31:0]
|-
| 5 || 0x00050 || Data_Hi || R || Data upper half [bits 63:32] *and select nextword*
|}

===== CSR Register (0x00000) =====

The first 8 bits auto-clear after a few clocks, bits 8, 9 indicate databuffer empty/full
the other bits are currently unused and retain whatever is written to them

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Reset || W || autocleared to zero
|-
|1-7|| unused || W || autocleared to zero
|-
|8|| Empty|| R || Data Buffer Empty
|-
|9|| Full || R || Data Buffer Full
|-
|10-31|| unused || R/W || unused
|}

reset bit: Writing 1 here resets the module to powerup state.

=== Operation ===

inputs 1 to 6 are used

inputs 1-4 are tdc inputs
input 6 is tdc-gate
input 5 is "new-cycle"

at start of run, the module should be reset

cycles are counted, timestamps reset on first tdc-gate of each cycle
tdc inputs are only counted during tdc-gates
(tdc-gates are not counted)

data words are written to buffer on each: cycle, tdc-gate-rise, tdc-gate-fall, tdc-input[if gate high]

data words are all 64bits with same format (from msb to lsb) ...
[6bit id, 10bit cycle-count, 48bit timestamp]

6 id bits are cycle,gaterise,ch1-4 [tdc-gate-fall words will have no id bits set]

as the module is set up currently, if inputs/cycle/tdc-gate occur simultaneously, only one data word will be produced, but it will have all relevant id bits set.

Read data low half first, then upper half, as reading upper half moves to next word in buffer.

VT4 info

2018-05-31T01:05:57Z

Cpearson:

== VME-VT4 - 4-channel timestamp module using the VME-IO32 board ==

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x0003C || CSR || RW || Control/Status Register
|-
| 1 || 0x00040 || Test || RW || Test Register
|-
| 2 || 0x00044 || Tstamp || R || Firmware Timestamp
|-
| 3 || 0x00048 || Nwords || R || Data Words available
|-
| 4 || 0x0004C || Data_Low || R || Data lower half [bits 31:0]
|-
| 5 || 0x00050 || Data_Hi || R || Data upper half [bits 63:32] *and select nextword*
|}

===== CSR Register (0x00000) =====

The first 8 bits auto-clear after a few clocks, bits 8, 9 indicate databuffer empty/full
the other bits are currently unused and retain whatever is written to them

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Reset || W || autocleared to zero
|-
|1-7|| unused || W || autocleared to zero
|-
|8|| Empty|| R || Data Buffer Empty
|-
|9|| Full || R || Data Buffer Full
|-
|10-31|| unused || R/W || unused
|}

reset bit: Writing 1 here resets the module to powerup state.

=== Operation ===

inputs 1 to 6 are used

inputs 1-4 are tdc inputs
input 6 is tdc-gate
input 5 is "new-cycle"

at start of run, the module should be reset

cycles are counted, timestamps reset on first tdc-gate of each cycle
tdc inputs are only counted during tdc-gates
(tdc-gates are not counted)

data words are written to buffer on each: cycle, tdc-gate-rise, tdc-gate-fall, tdc-input[if gate high]

data words are all 64bits with same format (from msb to lsb) ...
[6bit id, 10bit cycle-count, 48bit timestamp]

6 id bits are cycle,gaterise,ch1-4 [tdc-gate-fall words will have no id bits set]

as the module is set up currently, if inputs/cycle/tdc-gate occur simultaneously, only one data word will be produced, but it will have all relevant id bits set.

Read data low half first, then upper half, as reading upper half moves to next word in buffer.

VT4 info

2018-05-31T01:03:53Z

Cpearson: New page: == VME-VT4 - 4-channel timestamp module using the VME-IO32 board == === VME interface === VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address. ...

== VME-VT4 - 4-channel timestamp module using the VME-IO32 board ==

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x0003C || CSR || RW || Control/Status Register
|-
| 1 || 0x00040 || Test || RW || Test Register
|-
| 2 || 0x00044 || Tstamp || R || Firmware Timestamp
|-
| 3 || 0x00048 || Nwords || R || Data Words available
|-
| 4 || 0x0004C || Data_Loq || R || Data lower half [bits 31:0]
|-
| 5 || 0x00050 || Data_Hi || R || Data upper half [bits 63:32]
|}

===== CSR Register (0x00000) =====

The first 8 bits auto-clear after a few clocks, bits 8, 9 indicate databuffer empty/full
the other bits are currently unused and retain whatever is written to them

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Reset || W || autocleared to zero
|-
|1-7|| unused || W || autocleared to zero
|-
|8|| Empty|| R || Data Buffer Empty
|-
|9|| Full || R || Data Buffer Full
|-
|10-31|| unused || R/W || unused
|}

reset bit: Writing 1 here resets the module to powerup state.

=== Operation ===

inputs 1 to 6 are used

inputs 1-4 are tdc inputs
input 6 is tdc-gate
input 5 is "new-cycle"

at start of run, the module should be reset

cycles are counted, timestamps reset on first tdc-gate of each cycle
tdc inputs are only counted during tdc-gates
(tdc-gates are not counted)

data words are written to buffer on each: cycle, tdc-gate-rise, tdc-gate-fall, tdc-input[if gate high]

data words are all 64bits with same format (from msb to lsb) ...
[6bit id, 10bit cycle-count, 48bit timestamp]

6 id bits are cycle,gaterise,ch1-4 [tdc-gate-fall words will have no id bits set]

as the module is set up currently, if inputs/cycle/tdc-gate occur simultaneously, only one data word will be produced, but it will have all relevant id bits set.

VME-PPG32

2013-02-22T19:21:11Z

Cpearson: /* Clock Control (0x00030) */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [https://edev.triumf.ca/projects/edevel00022] VME-PPG32 Rev0 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/projects/edevel00067] VME-PPG32 Rev1 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/projects/edevel00125] VME-PPG32 Rev2 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/documents/27] Rev0 board schematics on edev site
* [https://edev.triumf.ca/documents/111] Rev1 board schematics on edev site
* [https://edev.triumf.ca/documents/158] Rev2 board schematics on edev site
* [[Image:VME-PPG32 Rev1.pdf]] Rev1 board schematics, local copy
* [[Image:VME-PPG32 Rev2.pdf]] Rev2 board schematics, local copy

VME-PPG32-IO32 firmware: (IO32 functions, no PPG functions)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32-Rev0] Svn repository for VME-PPG32-Rev0 initial test firmware (IO32 function only, no PPG function)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1] Svn repository for VME-PPG32-Rev1 firmware (IO32 function only, no PPG function)

VME-PPG32 VME CPLD firmware: (VME address decoder)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode] Svn repository for VME-PPG32 Rev0 and Rev1 VME address decoder CPLD (Altera EPM3032)

VME-PPG32 firmware: (PPG function)
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ
* Rev1 and Rev2 boards: inputs are switchable between NIM and TTL (JMP3)
* Rev2 boards: outputs are switchable between NIM and TTL (SW1 micro switches)

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input - see note 1)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

FPGA resource Usage : 1044 LE, 500 kbits Memory

Note 1 :
Some modules allow an external clock frequency of 20-100MHz . Divide-downs must be programmed where external clock frequency is not 20MHz.
Examples of divide-down programming is shown at end of this document.

=== Onboard jumper settings ===

* JMP1 - set to "INP" for input with 50 Ohm termination, set to "DAC" for DAC output
* JMP2 - set to "INP" same as JMP1
* JMP3 - set to "NIM" (pins 1-2) for NIM inputs or "TTL" (pins 2-3) for TTL inputs
* JMP4 - "MSEL1" jumper set to "ACT" for use with the active-serial flash
* IrqSel - leave open
* JTAG - leave open (not a jumper block!)
* SW1..3 - VME base address selectors (see below)

=== Firmware update procedure ===

(note1: right now the PPG firmware update procedure is unnecessary complicated because there is no ppg.pof file in the PPG firmware distribution version "1mar12" and the PPG firmware does not include the Altera active-serial programmer block.)

(note2: VME-PPG32-IO32 firmware (sof file) is required to update the PPG firmware)

* obtain the PPG firmware zip file (from http://daq-plone.triumf.ca/HR/VME/ppg32)
* extract the ppg.jic file
* obtain the VME-PPG32-IO32 sof file (VME-PPG32.sof) from https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.sof?view=log

==== Update using USB-Blaster and jic file ====

* use Quartus programmer to burn the jic file through the EP3 active-serial flash loader:
* start Quartus programmer (tools->programmer)
* say "auto detect" - EP3, EPM1270 and EPM3032A should be detected
* attach VME-PPG32.sof to the EP3 part (context menu "change file")
* select "program"
* say "start"
* observe that 2 "red" LEDs have turned on on the PPG board (40MHz clock on outputs 4 and 20).
* say "auto detect"
* an "EPCS16" part should show up attached to the EP3.
* attach ppg.jic to the EPCS16 part
* select "program"
* say "start"
* observe progress bar go from 0 to 100% in about 2 minutes.
* PPG firmware is now loaded into the board
* cycle the power on the board to reboot into the PPG firmware
* when running the PPG firmware, all LEDs are off after reboot.

==== Update using VME flash programmer ====

(note: VME flash programmer interface does not work in ppg firmware version "1mar12").

* obtain the latest copy of srunner_vme (follow instructions here [[VME-NIMIO32#Firmware_update_procedure]]) (srunner_vme.cxx svn rev 214 or newer for jic support)
* ./srunner_vme_gef.exe -program -16 ppg.jic 0x100024
* reboot the PPG

(note: the above does not work: b) srunner_vme treats 0x10xxxx is an A24 address, but PPG firmware does not respond to A24 addresses; c) the active serial interface does not seem to work anyway)

(note: the reboot function is not available in the PPG firmware)

==== Update using VME flash programmer when running VME-PPG32-IO32 firmware ====

* ./test_VMENIMIO32_gef.exe --addr 0x100000 --read 0 ### to confirm VME-PPG32-IO32 firmware revision
* ./srunner_vme_gef.exe -program -16 ppg.jic 0x100020
* ./test_VMENIMIO32_gef.exe --addr 0x100000 --reboot ### PPG will stop responding
* ./test_a32.exe 0x100000 ### should read 0x00000000 (NOT 0xFFFFFFFF)

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || CSR || RW || Control/Status Register
|-
| 1 || 0x00004 || Test || RW || Test Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Inv_Mask || RW || Output Inversion Mask
|-
| 8 || 0x00020 || Version || R || Firmware Version Register
|-
| 9 || 0x00024 || Flash || RW || Serial Flash Control Register
|-
| 10 || 0x00028 || Serial || R || Serial Number Register
|-
| 11 || 0x0002C || Hardware || R || hardware Identification Register
|-
| 12 || 0x00030 || clock Control || RW || Clock Control Register
|}

===== CSR Register (0x00000) =====

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk-Toggle || W || Toggles between PPG external and internal Clk
|-
|2|| Ext-Start|| R/W || 1=Ext-PPG Start 0=Int-PPG Start
|-
|3|| PPG-Reset || R/W || 1=Reset 0=Normal operation
|-
|4|| Test-Mode || R/W || 1=Test Mode 0=Normal operation
|-
|16|| Ext-Clk-Sel || R || 1= External clock is selected 0 = Internal clock selected
|-
|17|| Ext-Clk good || R || 1= External clock is connected and is "good" 0= external clock not connected or is "bad"
|-
|?-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing an edge here toggles the ppg logic between the internal and external CLK (connected to Nim_Input[3]). The VME interface always uses the internal clock.
Note that the correct divide-down must be programmed unless external clock is the same frequency (i.e. 10MHz) as internal clock.

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start. (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[4])

Reset bit: Set bit to Reset PPG. Stops PPG pgm even if executing a long delay. Does NOT do a full reset to power-up condition. Bit must be cleared after Reset or module will not operate.

Test-Mode bit: Set bit to enable Test Mode. When Test Mode is enabled, inputs 1 and 2 become output the internal PPG clock and actual clock PPG is using, respectively. If internal clock is set, inputs 1 and 2 output identical clocks. If external clock is set, and the external clock is "good", input 1 will not change, but input 2 will show the external clock frequency.
If Test-Mode bit is cleared, Normal Mode is enabled, where inputs 1 and 2 act as regular inputs.

Ext-Clk-Sel: If bit is set, external clock is selected and LED 4 will be lit. If clear, internal clock is selected

Ext-Clk Good: If bit is set, external clock is connected to Nim_Input[3] and is "good". LED 2 will be lit. If clear, external clock is either not connected or is "bad".

===== Test Register (0x00004) =====

Simple Test Register - Value Written is preserved and can be read back.

===== Address Register (0x00008) =====

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address. Also in test-Mode, the NIM/LED outputs follow the state of this register.

===== Instruction Registers (0x0000C - 0x00018) =====

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

===== Output Inversion Mask (0x0001C) =====
32 individual inversion bits (1 per output) a 1 inverts the state of that output.

===== Firmware Version (0x00020) =====
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

===== Serial Flash Control (0x00024) =====
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

===== Serial Number (0x00028) =====
Returns the module serial number, and Board revision (if set) or 0xdead

===== hardware Type (0x0002C) =====
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

===== Clock Control (0x00030) =====
Set PLL parameters applied to external clock input. Default parameters are for 20Mhz External Clock, and multiply this by 5 to get 100Mhz ppg clock.

Register Contents as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 30-28 || Bits 26-24 || Bits 23-20 || Bits 16-8 || Bit 5 || Bit 4 || Bit 3 || Bit 2 || Bit 1 || Bit 0
|-
| Phase Counter Select || Counter Parameter || Counter Type || 9 bit Data || PLL Reset || Up/Down || PhaseStep || Write Parameter || reconfigure || Control Trigger
|-
|}

The Control Trigger Bit [bit 0] enables the four control signals in bits 1,2,3,5, and needs to be toggled from off to on, to apply these 4 signals.

On rising edge of control trigger ...
Phasestep=1 => clock phase is adjusted by 1 unit, in the direction selected by "Up/Down" [bit 4: 1=up,0=Down]
Write Parameter=1 => 9bit-Data, Counter-Type and Counter-Param are written into the PLL reconfiguration registers
Reconfigure=1 => PLL is reconfigured with the parameters currently in its reconfiguration registers
PLL-Reset=1 => PLL is reset

PhaseCounterSelect ...
0 => All Clocks
1 => M ?
2-6 => Clock 0-4

phasestep is applied immediately (to clocks selected by PhaseCounterSelect), and does not require a reconfiguration or reset.

The parameters below need to be written (with writeparameter=1), and then require a reconfiguration to be applied.

Counter-Type ...
0: N
1: M
2: Cp/LF
3: VCO
4-8: Clock 0-4
9-D: Clock 5-9 (Stratix Only)
E-F: Invalid

Counter-Parameter ...
0: HighCount [For VCO this parameter is: PostScale K=2 Yes/No]
1: LowCount
4: Bypass
5: Mode Odd/Even

Clock frequencies are defined by ...
VCO Frequency = Fin * M/N
The individual clock outputs [clock0-4] are given by ... VCO / C0-C4

Each of M,N,C0-C4 are the sum of a high and low count.
Note - can get 50% duty cycle with odd count by setting mode=odd with high=low+1
Each counter can be bypassed by setting bypass=1 (=> Scale=1)

Limits etc ...
Fin = 5 - 472 Mhz
Fvco = 600 - 1300 Mhz
Lock Time < 1ms

Examples ...
For Fin = 20Mhz [defaults settings on pwerup]
Fvco=1200,K=2 => 600Mhz .. M=30, N=1(Bypassed), C0=6(3+3) Fin=20Mhz => C0=100Mhz

For Fin=100Mhz [and M=30,N=1,C0=6] Need to Change N to 5 ...
Write: 0x00000305 0 0x01000205 0 0x05000105 0 0x04000005 0 0x3 0
type=0,hi=3 type=0,lo=2 type=0,mode=odd type=0,bypass=no Reconfigure

Change back from 100 to 20 - need to change N to bypassed ...
write: 0x04000105 0 0x3 0
type=0,bypass=no Reconfigure

For Deap 62.5 Mhz (20*25/8) Fvco=1000,k=2=>500 M=8 N=1 C0=5 gives 100Mhz
Fvco=1000,k=2=>500 M=8 N=1 C0=8 gives 62.5Mhz

**Note - to help debug clock setting problems the internal clock can be viewed on ppg output #1 (and the 20 Mhz internal clock on output #0), if the test-mode bit is set in the CSR [bit 4]. It is then possible to check the ppg clock is locked and at the correct frequency (100Mhz), and see the relation between the external and internal clocks.

=== Front Panel ===

==== NIM Inputs ====

The Input assignments are (as labelled on front panel) ...
4 - External Start (Not fully tested yet) Needs to stay high (low => stop!)
3 - External Clock (20Mhz, internally scaled - 100Mhz)
2 - Unassigned
1 - Unassigned

==== Input LEDs ====

The Input LED assignments are (as labelled on front panel) ...
4 - Clock setting (Lit => External Clk)
3 - NimIn[2] status
2 - External Clock Good indicator (Lit => Clock is good)
1 - Program Running

=== Test Software ===

==== c-shell script to run 2 nested loops ====

set dec_hex=( 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 \
0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf \
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 \
0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f \
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 )

# dly4,loop4,dly3,loop6,dly2,end,end
set inst=( \
0xff 0x00 0x4 0x100000 0x0 0x0 0x0 0x200004 \
0x1 0x1 0x3 0x100000 0x0 0x0 0x0 0x200006 \
0x2 0x2 0x2 0x100000 0x0 0x0 0x0 0x300000 \
0x0 0x0 0x0 0x300000 0x0 0x0 0x0 0x000000 )

set i=0
set j=0
while( $i < $#inst )
@ j++; vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 $dec_hex[$j]
@ i++; vme_poke -a VME_A32UD -A 0x0010000c -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100010 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100014 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100018 -d VME_D32 $inst[$i]
end

# start program (from addr 0)...
vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100000 -d VME_D32 0x1

==== c-shell script to set divide-downs for 100MHz frequency ====

This would be used with an external frequency input of 100MHz

vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x00000305 # set hi counter to 3
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x01000205 # set lo counter to 2
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x05000105 # set mode counter to odd
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000005 # set counter bypass to 0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0

==== c-shell script to set divide-downs for 10MHz frequency ====

This would be used when returning to the internal frequency of 10MHz :

vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000105 # set counter bypass to 1
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3 # reconfig clock
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd

=== Procedure for newly assembled board startup and test ===

(note1: VME-PPG32-IO32 firmware is used to test the board)

(note2: TTL inputs and outputs are not tested)

(note3: DAC outputs are not tested)

(note4: shorts between NIM outputs are not tested)

* set VME address jumper A20-23 to "1", jumpers A24-27 and A28-31 to "0"
* set inputs and outputs to "NIM" mode
* connect JTAG USB blaster
* power up the board (standalone or in a VME crate)
* start Quartus programmer
* select correct USB blaster
* run "auto detect", 3 devices should be detected: EP3C20Q240 (Cyclone3 FPGA), EPM1270 (parallel flash loader CPLD), EPM3032AT44 (VME address decoder CPLD)
* flash the VME address decoder pof file into the EPM3032 part (get pof file from here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode/VME_Addr_decode.pof?view=log)
* (do not do this) flash the CFI parallel flash loader into the EPM1270 part (get pof file where?!?)
* load the VME-PPG32-IO32 firmware sof file into the EP3 part (get sof file here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.sof?view=log)
* run "vmescan_gef.exe", it should detect the IO32 board at A24 VME address 0x00100000, data should correspond to the sof file revision date code
* confirm VME access LED is working (flashes during vme scan).
* confirm VME Data bus is okey: "./test_VMENIMIO32_gef.exe --addr 0x100000 --testbits 4"
* (do not do this) follow the firmware update instructions to flash the firmware pof file using the VME flash programmer at [[VME-NIMIO32#Firmware_update_procedure]] (get VME-PPG32-IO32 pof file from here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.pof?view=log)
* (do not do this) confirm FPGA reboot is working - "./test_VMENIMIO32_gef.exe --addr 0x100000 --reboot" prints 0xFFFFFFFF on the second read of firmware revision
* test NIM inputs and LEDs: use NIM pulse generator or any NIM module inverted output, connect to each NIM input, observe that corresponding "green" LEDs is lighting up
* test NIM outputs and LEDs: "./test_VMENIMIO32_gef.exe --addr 0x100000 --nimout 3 1 --pulsenim", observe all "red" LEDs are flashing, connect NIM outputs to NIM scaler, observe scaler counts at each LED flash
* load PPG firmware into the active serial flash (follow instructions here: [[#Update_using_VME_flash_programmer_when_running_VME-PPG32-IO32_firmware]]
* unplug the board from VME, wait 10 sec, plug it back in, confirm that it is detected by vmescan if running VME-PPG32-IO32 firmware or test_a32 or PPG test tools if running the PPG firmware (confirms the flash memory contents is good)

=== VME-PPG32-IO32 firmware ===

The VME-PPG32 board can run a special version of VME-NIMIO32 firmware (subproject "PPG32-Rev1" of the VME-NIMIO32 firmware). For instructions, please refer to the [[VME-NIMIO32]] documentation.

VME-PPG32

2013-02-21T00:01:26Z

Cpearson: /* Clock Control (0x00030) */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [https://edev.triumf.ca/projects/edevel00022] VME-PPG32 Rev0 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/projects/edevel00067] VME-PPG32 Rev1 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/projects/edevel00125] VME-PPG32 Rev2 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/documents/27] Rev0 board schematics on edev site
* [https://edev.triumf.ca/documents/111] Rev1 board schematics on edev site
* [https://edev.triumf.ca/documents/158] Rev2 board schematics on edev site
* [[Image:VME-PPG32 Rev1.pdf]] Rev1 board schematics, local copy
* [[Image:VME-PPG32 Rev2.pdf]] Rev2 board schematics, local copy

VME-PPG32-IO32 firmware: (IO32 functions, no PPG functions)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32-Rev0] Svn repository for VME-PPG32-Rev0 initial test firmware (IO32 function only, no PPG function)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1] Svn repository for VME-PPG32-Rev1 firmware (IO32 function only, no PPG function)

VME-PPG32 VME CPLD firmware: (VME address decoder)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode] Svn repository for VME-PPG32 Rev0 and Rev1 VME address decoder CPLD (Altera EPM3032)

VME-PPG32 firmware: (PPG function)
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ
* Rev1 and Rev2 boards: inputs are switchable between NIM and TTL (JMP3)
* Rev2 boards: outputs are switchable between NIM and TTL (SW1 micro switches)

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input - see note 1)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

FPGA resource Usage : 1044 LE, 500 kbits Memory

Note 1 :
Some modules allow an external clock frequency of 20-100MHz . Divide-downs must be programmed where external clock frequency is not 20MHz.
Examples of divide-down programming is shown at end of this document.

=== Onboard jumper settings ===

* JMP1 - set to "INP" for input with 50 Ohm termination, set to "DAC" for DAC output
* JMP2 - set to "INP" same as JMP1
* JMP3 - set to "NIM" (pins 1-2) for NIM inputs or "TTL" (pins 2-3) for TTL inputs
* JMP4 - "MSEL1" jumper set to "ACT" for use with the active-serial flash
* IrqSel - leave open
* JTAG - leave open (not a jumper block!)
* SW1..3 - VME base address selectors (see below)

=== Firmware update procedure ===

(note1: right now the PPG firmware update procedure is unnecessary complicated because there is no ppg.pof file in the PPG firmware distribution version "1mar12" and the PPG firmware does not include the Altera active-serial programmer block.)

(note2: VME-PPG32-IO32 firmware (sof file) is required to update the PPG firmware)

* obtain the PPG firmware zip file (from http://daq-plone.triumf.ca/HR/VME/ppg32)
* extract the ppg.jic file
* obtain the VME-PPG32-IO32 sof file (VME-PPG32.sof) from https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.sof?view=log

==== Update using USB-Blaster and jic file ====

* use Quartus programmer to burn the jic file through the EP3 active-serial flash loader:
* start Quartus programmer (tools->programmer)
* say "auto detect" - EP3, EPM1270 and EPM3032A should be detected
* attach VME-PPG32.sof to the EP3 part (context menu "change file")
* select "program"
* say "start"
* observe that 2 "red" LEDs have turned on on the PPG board (40MHz clock on outputs 4 and 20).
* say "auto detect"
* an "EPCS16" part should show up attached to the EP3.
* attach ppg.jic to the EPCS16 part
* select "program"
* say "start"
* observe progress bar go from 0 to 100% in about 2 minutes.
* PPG firmware is now loaded into the board
* cycle the power on the board to reboot into the PPG firmware
* when running the PPG firmware, all LEDs are off after reboot.

==== Update using VME flash programmer ====

(note: VME flash programmer interface does not work in ppg firmware version "1mar12").

* obtain the latest copy of srunner_vme (follow instructions here [[VME-NIMIO32#Firmware_update_procedure]]) (srunner_vme.cxx svn rev 214 or newer for jic support)
* ./srunner_vme_gef.exe -program -16 ppg.jic 0x100024
* reboot the PPG

(note: the above does not work: b) srunner_vme treats 0x10xxxx is an A24 address, but PPG firmware does not respond to A24 addresses; c) the active serial interface does not seem to work anyway)

(note: the reboot function is not available in the PPG firmware)

==== Update using VME flash programmer when running VME-PPG32-IO32 firmware ====

* ./test_VMENIMIO32_gef.exe --addr 0x100000 --read 0 ### to confirm VME-PPG32-IO32 firmware revision
* ./srunner_vme_gef.exe -program -16 ppg.jic 0x100020
* ./test_VMENIMIO32_gef.exe --addr 0x100000 --reboot ### PPG will stop responding
* ./test_a32.exe 0x100000 ### should read 0x00000000 (NOT 0xFFFFFFFF)

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || CSR || RW || Control/Status Register
|-
| 1 || 0x00004 || Test || RW || Test Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Inv_Mask || RW || Output Inversion Mask
|-
| 8 || 0x00020 || Version || R || Firmware Version Register
|-
| 9 || 0x00024 || Flash || RW || Serial Flash Control Register
|-
| 10 || 0x00028 || Serial || R || Serial Number Register
|-
| 11 || 0x0002C || Hardware || R || hardware Identification Register
|-
| 12 || 0x00030 || clock Control || RW || Clock Control Register
|}

===== CSR Register (0x00000) =====

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk-Toggle || W || Toggles between PPG external and internal Clk
|-
|2|| Ext-Start|| R/W || 1=Ext-PPG Start 0=Int-PPG Start
|-
|3|| PPG-Reset || R/W || 1=Reset 0=Normal operation
|-
|4|| Test-Mode || R/W || 1=Test Mode 0=Normal operation
|-
|16|| Ext-Clk-Sel || R || 1= External clock is selected 0 = Internal clock selected
|-
|17|| Ext-Clk good || R || 1= External clock is connected and is "good" 0= external clock not connected or is "bad"
|-
|?-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing an edge here toggles the ppg logic between the internal and external CLK (connected to Nim_Input[3]). The VME interface always uses the internal clock.
Note that the correct divide-down must be programmed unless external clock is the same frequency (i.e. 10MHz) as internal clock.

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start. (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[4])

Reset bit: Set bit to Reset PPG. Stops PPG pgm even if executing a long delay. Does NOT do a full reset to power-up condition. Bit must be cleared after Reset or module will not operate.

Test-Mode bit: Set bit to enable Test Mode. When Test Mode is enabled, inputs 1 and 2 become output the internal PPG clock and actual clock PPG is using, respectively. If internal clock is set, inputs 1 and 2 output identical clocks. If external clock is set, and the external clock is "good", input 1 will not change, but input 2 will show the external clock frequency.
If Test-Mode bit is cleared, Normal Mode is enabled, where inputs 1 and 2 act as regular inputs.

Ext-Clk-Sel: If bit is set, external clock is selected and LED 4 will be lit. If clear, internal clock is selected

Ext-Clk Good: If bit is set, external clock is connected to Nim_Input[3] and is "good". LED 2 will be lit. If clear, external clock is either not connected or is "bad".

===== Test Register (0x00004) =====

Simple Test Register - Value Written is preserved and can be read back.

===== Address Register (0x00008) =====

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address. Also in test-Mode, the NIM/LED outputs follow the state of this register.

===== Instruction Registers (0x0000C - 0x00018) =====

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

===== Output Inversion Mask (0x0001C) =====
32 individual inversion bits (1 per output) a 1 inverts the state of that output.

===== Firmware Version (0x00020) =====
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

===== Serial Flash Control (0x00024) =====
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

===== Serial Number (0x00028) =====
Returns the module serial number, and Board revision (if set) or 0xdead

===== hardware Type (0x0002C) =====
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

===== Clock Control (0x00030) =====
Set PLL parameters applied to external clock input. Default parameters are for 20Mhz External Clock, and multiply this by 5 to get 100Mhz ppg clock.

Register Contents as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 30-28 || Bits 26-24 || Bits 23-20 || Bits 16-8 || Bit 5 || Bit 4 || Bit 3 || Bit 2 || Bit 1 || Bit 0
|-
| Phase Counter Select || Counter Parameter || Counter Type || 9 bit Data || PLL Reset || Up/Down || PhaseStep || Write Parameter || reconfigure || Control Trigger
|-
|}

The Control Trigger Bit [bit 0] enables the four control signals in bits 1,2,3,5, and needs to be toggled from off to on, to apply these 4 signals.

On rising edge of control trigger ...
Phasestep=1 => clock phase is adjusted by 1 unit, in the direction selected by "Up/Down" [bit 4: 1=up,0=Down]
Write Parameter=1 => 9bit-Data, Counter-Type and Counter-Param are written into the PLL reconfiguration registers
Reconfigure=1 => PLL is reconfigured with the parameters currently in its reconfiguration registers
PLL-Reset=1 => PLL is reset

PhaseCounterSelect ...
0 => All Clocks
1 => M ?
2-6 => Clock 0-4

phasestep is applied immediately (to clocks selected by PhaseCounterSelect), and does not require a reconfiguration or reset.

The parameters below need to be written (with writeparameter=1), and then require a reconfiguration to be applied.

Counter-Type ...
0: N
1: M
2: Cp/LF
3: VCO
4-8: Clock 0-4
9-D: Clock 5-9 (Stratix Only)
E-F: Invalid

Counter-Parameter ...
0: HighCount [For VCO this parameter is: PostScale K=2 Yes/No]
1: LowCount
4: Bypass
5: Mode Odd/Even

Clock frequencies are defined by ...
VCO Frequency = Fin * M/N
The individual clock outputs [clock0-4] are given by ... VCO / C0-C4

Each of M,N,C0-C4 are the sum of a high and low count.
Note - can get 50% duty cycle with odd count by setting mode=odd with high=low+1
Each counter can be bypassed by setting bypass=1 (=> Scale=1)

Limits etc ...
Fin = 5 - 472 Mhz
Fvco = 600 - 1300 Mhz
Lock Time < 1ms

Examples ...
For Fin = 20Mhz [defaults settings on pwerup]
Fvco=1200,K=2 => 600Mhz .. M=30, N=1(Bypassed), C0=6(3+3) Fin=20Mhz => C0=100Mhz

For Fin=100Mhz [and M=30,N=1,C0=6] Need to Change N to 5 ...
Write: 0x00000305 0 0x01000205 0 0x05000105 0 0x04000005 0 0x3 0
type=0,hi=3 type=0,lo=2 type=0,mode=odd type=0,bypass=no Reconfigure

Change back from 100 to 20 - need to change N to bypassed ...
write: 0x04000105 0 0x3 0
type=0,bypass=no Reconfigure

For Deap 62.5 Mhz (20*25/8) Fvco=1000,k=2=>500 M=8 N=1 C0=5

**Note - to help debug clock setting problems the internal clock can be viewed on ppg output #1 (and the 20 Mhz internal clock on output #0), if the test-mode bit is set in the CSR [bit 4]. It is then possible to check the ppg clock is locked and at the correct frequency (100Mhz), and see the relation between the external and internal clocks.

=== Front Panel ===

==== NIM Inputs ====

The Input assignments are (as labelled on front panel) ...
4 - External Start (Not fully tested yet) Needs to stay high (low => stop!)
3 - External Clock (20Mhz, internally scaled - 100Mhz)
2 - Unassigned
1 - Unassigned

==== Input LEDs ====

The Input LED assignments are (as labelled on front panel) ...
4 - Clock setting (Lit => External Clk)
3 - NimIn[2] status
2 - External Clock Good indicator (Lit => Clock is good)
1 - Program Running

=== Test Software ===

==== c-shell script to run 2 nested loops ====

set dec_hex=( 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 \
0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf \
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 \
0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f \
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 )

# dly4,loop4,dly3,loop6,dly2,end,end
set inst=( \
0xff 0x00 0x4 0x100000 0x0 0x0 0x0 0x200004 \
0x1 0x1 0x3 0x100000 0x0 0x0 0x0 0x200006 \
0x2 0x2 0x2 0x100000 0x0 0x0 0x0 0x300000 \
0x0 0x0 0x0 0x300000 0x0 0x0 0x0 0x000000 )

set i=0
set j=0
while( $i < $#inst )
@ j++; vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 $dec_hex[$j]
@ i++; vme_poke -a VME_A32UD -A 0x0010000c -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100010 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100014 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100018 -d VME_D32 $inst[$i]
end

# start program (from addr 0)...
vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100000 -d VME_D32 0x1

==== c-shell script to set divide-downs for 100MHz frequency ====

This would be used with an external frequency input of 100MHz

vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x00000305 # set hi counter to 3
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x01000205 # set lo counter to 2
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x05000105 # set mode counter to odd
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000005 # set counter bypass to 0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0

==== c-shell script to set divide-downs for 10MHz frequency ====

This would be used when returning to the internal frequency of 10MHz :

vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000105 # set counter bypass to 1
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3 # reconfig clock
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd

=== Procedure for newly assembled board startup and test ===

(note1: VME-PPG32-IO32 firmware is used to test the board)

(note2: TTL inputs and outputs are not tested)

(note3: DAC outputs are not tested)

(note4: shorts between NIM outputs are not tested)

* set VME address jumper A20-23 to "1", jumpers A24-27 and A28-31 to "0"
* set inputs and outputs to "NIM" mode
* connect JTAG USB blaster
* power up the board (standalone or in a VME crate)
* start Quartus programmer
* select correct USB blaster
* run "auto detect", 3 devices should be detected: EP3C20Q240 (Cyclone3 FPGA), EPM1270 (parallel flash loader CPLD), EPM3032AT44 (VME address decoder CPLD)
* flash the VME address decoder pof file into the EPM3032 part (get pof file from here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode/VME_Addr_decode.pof?view=log)
* (do not do this) flash the CFI parallel flash loader into the EPM1270 part (get pof file where?!?)
* load the VME-PPG32-IO32 firmware sof file into the EP3 part (get sof file here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.sof?view=log)
* run "vmescan_gef.exe", it should detect the IO32 board at A24 VME address 0x00100000, data should correspond to the sof file revision date code
* confirm VME access LED is working (flashes during vme scan).
* confirm VME Data bus is okey: "./test_VMENIMIO32_gef.exe --addr 0x100000 --testbits 4"
* (do not do this) follow the firmware update instructions to flash the firmware pof file using the VME flash programmer at [[VME-NIMIO32#Firmware_update_procedure]] (get VME-PPG32-IO32 pof file from here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.pof?view=log)
* (do not do this) confirm FPGA reboot is working - "./test_VMENIMIO32_gef.exe --addr 0x100000 --reboot" prints 0xFFFFFFFF on the second read of firmware revision
* test NIM inputs and LEDs: use NIM pulse generator or any NIM module inverted output, connect to each NIM input, observe that corresponding "green" LEDs is lighting up
* test NIM outputs and LEDs: "./test_VMENIMIO32_gef.exe --addr 0x100000 --nimout 3 1 --pulsenim", observe all "red" LEDs are flashing, connect NIM outputs to NIM scaler, observe scaler counts at each LED flash
* load PPG firmware into the active serial flash (follow instructions here: [[#Update_using_VME_flash_programmer_when_running_VME-PPG32-IO32_firmware]]
* unplug the board from VME, wait 10 sec, plug it back in, confirm that it is detected by vmescan if running VME-PPG32-IO32 firmware or test_a32 or PPG test tools if running the PPG firmware (confirms the flash memory contents is good)

=== VME-PPG32-IO32 firmware ===

The VME-PPG32 board can run a special version of VME-NIMIO32 firmware (subproject "PPG32-Rev1" of the VME-NIMIO32 firmware). For instructions, please refer to the [[VME-NIMIO32]] documentation.

VME-PPG32

2013-02-20T23:59:32Z

Cpearson: /* Clock Control (0x00030) */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [https://edev.triumf.ca/projects/edevel00022] VME-PPG32 Rev0 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/projects/edevel00067] VME-PPG32 Rev1 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/projects/edevel00125] VME-PPG32 Rev2 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/documents/27] Rev0 board schematics on edev site
* [https://edev.triumf.ca/documents/111] Rev1 board schematics on edev site
* [https://edev.triumf.ca/documents/158] Rev2 board schematics on edev site
* [[Image:VME-PPG32 Rev1.pdf]] Rev1 board schematics, local copy
* [[Image:VME-PPG32 Rev2.pdf]] Rev2 board schematics, local copy

VME-PPG32-IO32 firmware: (IO32 functions, no PPG functions)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32-Rev0] Svn repository for VME-PPG32-Rev0 initial test firmware (IO32 function only, no PPG function)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1] Svn repository for VME-PPG32-Rev1 firmware (IO32 function only, no PPG function)

VME-PPG32 VME CPLD firmware: (VME address decoder)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode] Svn repository for VME-PPG32 Rev0 and Rev1 VME address decoder CPLD (Altera EPM3032)

VME-PPG32 firmware: (PPG function)
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ
* Rev1 and Rev2 boards: inputs are switchable between NIM and TTL (JMP3)
* Rev2 boards: outputs are switchable between NIM and TTL (SW1 micro switches)

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input - see note 1)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

FPGA resource Usage : 1044 LE, 500 kbits Memory

Note 1 :
Some modules allow an external clock frequency of 20-100MHz . Divide-downs must be programmed where external clock frequency is not 20MHz.
Examples of divide-down programming is shown at end of this document.

=== Onboard jumper settings ===

* JMP1 - set to "INP" for input with 50 Ohm termination, set to "DAC" for DAC output
* JMP2 - set to "INP" same as JMP1
* JMP3 - set to "NIM" (pins 1-2) for NIM inputs or "TTL" (pins 2-3) for TTL inputs
* JMP4 - "MSEL1" jumper set to "ACT" for use with the active-serial flash
* IrqSel - leave open
* JTAG - leave open (not a jumper block!)
* SW1..3 - VME base address selectors (see below)

=== Firmware update procedure ===

(note1: right now the PPG firmware update procedure is unnecessary complicated because there is no ppg.pof file in the PPG firmware distribution version "1mar12" and the PPG firmware does not include the Altera active-serial programmer block.)

(note2: VME-PPG32-IO32 firmware (sof file) is required to update the PPG firmware)

* obtain the PPG firmware zip file (from http://daq-plone.triumf.ca/HR/VME/ppg32)
* extract the ppg.jic file
* obtain the VME-PPG32-IO32 sof file (VME-PPG32.sof) from https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.sof?view=log

==== Update using USB-Blaster and jic file ====

* use Quartus programmer to burn the jic file through the EP3 active-serial flash loader:
* start Quartus programmer (tools->programmer)
* say "auto detect" - EP3, EPM1270 and EPM3032A should be detected
* attach VME-PPG32.sof to the EP3 part (context menu "change file")
* select "program"
* say "start"
* observe that 2 "red" LEDs have turned on on the PPG board (40MHz clock on outputs 4 and 20).
* say "auto detect"
* an "EPCS16" part should show up attached to the EP3.
* attach ppg.jic to the EPCS16 part
* select "program"
* say "start"
* observe progress bar go from 0 to 100% in about 2 minutes.
* PPG firmware is now loaded into the board
* cycle the power on the board to reboot into the PPG firmware
* when running the PPG firmware, all LEDs are off after reboot.

==== Update using VME flash programmer ====

(note: VME flash programmer interface does not work in ppg firmware version "1mar12").

* obtain the latest copy of srunner_vme (follow instructions here [[VME-NIMIO32#Firmware_update_procedure]]) (srunner_vme.cxx svn rev 214 or newer for jic support)
* ./srunner_vme_gef.exe -program -16 ppg.jic 0x100024
* reboot the PPG

(note: the above does not work: b) srunner_vme treats 0x10xxxx is an A24 address, but PPG firmware does not respond to A24 addresses; c) the active serial interface does not seem to work anyway)

(note: the reboot function is not available in the PPG firmware)

==== Update using VME flash programmer when running VME-PPG32-IO32 firmware ====

* ./test_VMENIMIO32_gef.exe --addr 0x100000 --read 0 ### to confirm VME-PPG32-IO32 firmware revision
* ./srunner_vme_gef.exe -program -16 ppg.jic 0x100020
* ./test_VMENIMIO32_gef.exe --addr 0x100000 --reboot ### PPG will stop responding
* ./test_a32.exe 0x100000 ### should read 0x00000000 (NOT 0xFFFFFFFF)

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || CSR || RW || Control/Status Register
|-
| 1 || 0x00004 || Test || RW || Test Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Inv_Mask || RW || Output Inversion Mask
|-
| 8 || 0x00020 || Version || R || Firmware Version Register
|-
| 9 || 0x00024 || Flash || RW || Serial Flash Control Register
|-
| 10 || 0x00028 || Serial || R || Serial Number Register
|-
| 11 || 0x0002C || Hardware || R || hardware Identification Register
|-
| 12 || 0x00030 || clock Control || RW || Clock Control Register
|}

===== CSR Register (0x00000) =====

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk-Toggle || W || Toggles between PPG external and internal Clk
|-
|2|| Ext-Start|| R/W || 1=Ext-PPG Start 0=Int-PPG Start
|-
|3|| PPG-Reset || R/W || 1=Reset 0=Normal operation
|-
|4|| Test-Mode || R/W || 1=Test Mode 0=Normal operation
|-
|16|| Ext-Clk-Sel || R || 1= External clock is selected 0 = Internal clock selected
|-
|17|| Ext-Clk good || R || 1= External clock is connected and is "good" 0= external clock not connected or is "bad"
|-
|?-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing an edge here toggles the ppg logic between the internal and external CLK (connected to Nim_Input[3]). The VME interface always uses the internal clock.
Note that the correct divide-down must be programmed unless external clock is the same frequency (i.e. 10MHz) as internal clock.

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start. (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[4])

Reset bit: Set bit to Reset PPG. Stops PPG pgm even if executing a long delay. Does NOT do a full reset to power-up condition. Bit must be cleared after Reset or module will not operate.

Test-Mode bit: Set bit to enable Test Mode. When Test Mode is enabled, inputs 1 and 2 become output the internal PPG clock and actual clock PPG is using, respectively. If internal clock is set, inputs 1 and 2 output identical clocks. If external clock is set, and the external clock is "good", input 1 will not change, but input 2 will show the external clock frequency.
If Test-Mode bit is cleared, Normal Mode is enabled, where inputs 1 and 2 act as regular inputs.

Ext-Clk-Sel: If bit is set, external clock is selected and LED 4 will be lit. If clear, internal clock is selected

Ext-Clk Good: If bit is set, external clock is connected to Nim_Input[3] and is "good". LED 2 will be lit. If clear, external clock is either not connected or is "bad".

===== Test Register (0x00004) =====

Simple Test Register - Value Written is preserved and can be read back.

===== Address Register (0x00008) =====

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address. Also in test-Mode, the NIM/LED outputs follow the state of this register.

===== Instruction Registers (0x0000C - 0x00018) =====

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

===== Output Inversion Mask (0x0001C) =====
32 individual inversion bits (1 per output) a 1 inverts the state of that output.

===== Firmware Version (0x00020) =====
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

===== Serial Flash Control (0x00024) =====
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

===== Serial Number (0x00028) =====
Returns the module serial number, and Board revision (if set) or 0xdead

===== hardware Type (0x0002C) =====
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

===== Clock Control (0x00030) =====
Set PLL parameters applied to external clock input. Default parameters are for 20Mhz External Clock, and multiply this by 5 to get 100Mhz ppg clock.

Register Contents as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 30-28 || Bits 26-24 || Bits 23-20 || Bits 16-8 || Bit 5 || Bit 4 || Bit 3 || Bit 2 || Bit 1 || Bit 0
|-
| Phase Counter Select || Counter Parameter || Counter Type || 9 bit Data || PLL Reset || Up/Down || PhaseStep || Write Parameter || reconfigure || Control Trigger
|-
|}

The Control Trigger Bit [bit 0] enables the four control signals in bits 1,2,3,5, and needs to be toggled from off to on, to apply these 4 signals.

On rising edge of control trigger ...
Phasestep=1 => clock phase is adjusted by 1 unit, in the direction selected by "Up/Down" [bit 4: 1=up,0=Down]
Write Parameter=1 => 9bit-Data, Counter-Type and Counter-Param are written into the PLL reconfiguration registers
Reconfigure=1 => PLL is reconfigured with the parameters currently in its reconfiguration registers
PLL-Reset=1 => PLL is reset

PhaseCounterSelect ...
0 => All Clocks
1 => M ?
2-6 => Clock 0-4

phasestep is applied immediately (to clocks selected by PhaseCounterSelect), and does not require a reconfiguration or reset.

The parameters below need to be written (with writeparameter=1), and then require a reconfiguration to be applied.

Counter-Type ...
0: N
1: M
2: Cp/LF
3: VCO
4-8: Clock 0-4
9-D: Clock 5-9 (Stratix Only)
E-F: Invalid

Counter-Parameter ...
0: HighCount [For VCO this parameter is: PostScale K=2 Yes/No]
1: LowCount
4: Bypass
5: Mode Odd/Even

Clock frequencies are defined by ...
VCO Frequency = Fin * M/N
The individual clock outputs [clock0-4] are given by ... VCO / C0-C4

Each of M,N,C0-C4 are the sum of a high and low count.
Note - can get 50% duty cycle with odd count by setting mode=odd with high=low+1
Each counter can be bypassed by setting bypass=1 (=> Scale=1)

Limits etc ...
Fin = 5 - 472 Mhz
Fvco = 600 - 1300 Mhz
Lock Time < 1ms

Examples ...
For Fin = 20Mhz [defaults settings on pwerup]
Fvco=1200,K=2 => 600Mhz .. M=30, N=1(Bypassed), C0=6(3+3) Fin=20Mhz => C0=100Mhz

For Fin=100Mhz [and M=30,N=1,C0=6] Need to Change N to 5 ...
Write: 0x00000305 0 0x01000205 0 0x05000105 0 0x04000005 0 0x3 0
type=0,hi=3 type=0,lo=2 type=0,mode=odd type=0,bypass=no Reconfigure

Change back from 100 to 20 - need to change N to bypassed ...
write: 0x04000105 0 0x3 0
type=0,bypass=no Reconfigure

For Deap 62.5 Mhz (20*25/8) Fvco=1000,k=2=>500 M=8 N=1 C0=5

**Note - to help debug clock setting problems the internal clock can be viewed on ppg output #1 (and the 20 Mhz internal clock on output #0), if Led-Control bit is set in the CSR [bit 4]

=== Front Panel ===

==== NIM Inputs ====

The Input assignments are (as labelled on front panel) ...
4 - External Start (Not fully tested yet) Needs to stay high (low => stop!)
3 - External Clock (20Mhz, internally scaled - 100Mhz)
2 - Unassigned
1 - Unassigned

==== Input LEDs ====

The Input LED assignments are (as labelled on front panel) ...
4 - Clock setting (Lit => External Clk)
3 - NimIn[2] status
2 - External Clock Good indicator (Lit => Clock is good)
1 - Program Running

=== Test Software ===

==== c-shell script to run 2 nested loops ====

set dec_hex=( 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 \
0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf \
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 \
0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f \
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 )

# dly4,loop4,dly3,loop6,dly2,end,end
set inst=( \
0xff 0x00 0x4 0x100000 0x0 0x0 0x0 0x200004 \
0x1 0x1 0x3 0x100000 0x0 0x0 0x0 0x200006 \
0x2 0x2 0x2 0x100000 0x0 0x0 0x0 0x300000 \
0x0 0x0 0x0 0x300000 0x0 0x0 0x0 0x000000 )

set i=0
set j=0
while( $i < $#inst )
@ j++; vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 $dec_hex[$j]
@ i++; vme_poke -a VME_A32UD -A 0x0010000c -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100010 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100014 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100018 -d VME_D32 $inst[$i]
end

# start program (from addr 0)...
vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100000 -d VME_D32 0x1

==== c-shell script to set divide-downs for 100MHz frequency ====

This would be used with an external frequency input of 100MHz

vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x00000305 # set hi counter to 3
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x01000205 # set lo counter to 2
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x05000105 # set mode counter to odd
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000005 # set counter bypass to 0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0

==== c-shell script to set divide-downs for 10MHz frequency ====

This would be used when returning to the internal frequency of 10MHz :

vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000105 # set counter bypass to 1
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3 # reconfig clock
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd

=== Procedure for newly assembled board startup and test ===

(note1: VME-PPG32-IO32 firmware is used to test the board)

(note2: TTL inputs and outputs are not tested)

(note3: DAC outputs are not tested)

(note4: shorts between NIM outputs are not tested)

* set VME address jumper A20-23 to "1", jumpers A24-27 and A28-31 to "0"
* set inputs and outputs to "NIM" mode
* connect JTAG USB blaster
* power up the board (standalone or in a VME crate)
* start Quartus programmer
* select correct USB blaster
* run "auto detect", 3 devices should be detected: EP3C20Q240 (Cyclone3 FPGA), EPM1270 (parallel flash loader CPLD), EPM3032AT44 (VME address decoder CPLD)
* flash the VME address decoder pof file into the EPM3032 part (get pof file from here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode/VME_Addr_decode.pof?view=log)
* (do not do this) flash the CFI parallel flash loader into the EPM1270 part (get pof file where?!?)
* load the VME-PPG32-IO32 firmware sof file into the EP3 part (get sof file here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.sof?view=log)
* run "vmescan_gef.exe", it should detect the IO32 board at A24 VME address 0x00100000, data should correspond to the sof file revision date code
* confirm VME access LED is working (flashes during vme scan).
* confirm VME Data bus is okey: "./test_VMENIMIO32_gef.exe --addr 0x100000 --testbits 4"
* (do not do this) follow the firmware update instructions to flash the firmware pof file using the VME flash programmer at [[VME-NIMIO32#Firmware_update_procedure]] (get VME-PPG32-IO32 pof file from here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.pof?view=log)
* (do not do this) confirm FPGA reboot is working - "./test_VMENIMIO32_gef.exe --addr 0x100000 --reboot" prints 0xFFFFFFFF on the second read of firmware revision
* test NIM inputs and LEDs: use NIM pulse generator or any NIM module inverted output, connect to each NIM input, observe that corresponding "green" LEDs is lighting up
* test NIM outputs and LEDs: "./test_VMENIMIO32_gef.exe --addr 0x100000 --nimout 3 1 --pulsenim", observe all "red" LEDs are flashing, connect NIM outputs to NIM scaler, observe scaler counts at each LED flash
* load PPG firmware into the active serial flash (follow instructions here: [[#Update_using_VME_flash_programmer_when_running_VME-PPG32-IO32_firmware]]
* unplug the board from VME, wait 10 sec, plug it back in, confirm that it is detected by vmescan if running VME-PPG32-IO32 firmware or test_a32 or PPG test tools if running the PPG firmware (confirms the flash memory contents is good)

=== VME-PPG32-IO32 firmware ===

The VME-PPG32 board can run a special version of VME-NIMIO32 firmware (subproject "PPG32-Rev1" of the VME-NIMIO32 firmware). For instructions, please refer to the [[VME-NIMIO32]] documentation.

VME-PPG32

2013-02-20T23:56:53Z

Cpearson: /* Clock Control (0x00030) */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [https://edev.triumf.ca/projects/edevel00022] VME-PPG32 Rev0 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/projects/edevel00067] VME-PPG32 Rev1 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/projects/edevel00125] VME-PPG32 Rev2 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/documents/27] Rev0 board schematics on edev site
* [https://edev.triumf.ca/documents/111] Rev1 board schematics on edev site
* [https://edev.triumf.ca/documents/158] Rev2 board schematics on edev site
* [[Image:VME-PPG32 Rev1.pdf]] Rev1 board schematics, local copy
* [[Image:VME-PPG32 Rev2.pdf]] Rev2 board schematics, local copy

VME-PPG32-IO32 firmware: (IO32 functions, no PPG functions)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32-Rev0] Svn repository for VME-PPG32-Rev0 initial test firmware (IO32 function only, no PPG function)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1] Svn repository for VME-PPG32-Rev1 firmware (IO32 function only, no PPG function)

VME-PPG32 VME CPLD firmware: (VME address decoder)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode] Svn repository for VME-PPG32 Rev0 and Rev1 VME address decoder CPLD (Altera EPM3032)

VME-PPG32 firmware: (PPG function)
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ
* Rev1 and Rev2 boards: inputs are switchable between NIM and TTL (JMP3)
* Rev2 boards: outputs are switchable between NIM and TTL (SW1 micro switches)

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input - see note 1)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

FPGA resource Usage : 1044 LE, 500 kbits Memory

Note 1 :
Some modules allow an external clock frequency of 20-100MHz . Divide-downs must be programmed where external clock frequency is not 20MHz.
Examples of divide-down programming is shown at end of this document.

=== Onboard jumper settings ===

* JMP1 - set to "INP" for input with 50 Ohm termination, set to "DAC" for DAC output
* JMP2 - set to "INP" same as JMP1
* JMP3 - set to "NIM" (pins 1-2) for NIM inputs or "TTL" (pins 2-3) for TTL inputs
* JMP4 - "MSEL1" jumper set to "ACT" for use with the active-serial flash
* IrqSel - leave open
* JTAG - leave open (not a jumper block!)
* SW1..3 - VME base address selectors (see below)

=== Firmware update procedure ===

(note1: right now the PPG firmware update procedure is unnecessary complicated because there is no ppg.pof file in the PPG firmware distribution version "1mar12" and the PPG firmware does not include the Altera active-serial programmer block.)

(note2: VME-PPG32-IO32 firmware (sof file) is required to update the PPG firmware)

* obtain the PPG firmware zip file (from http://daq-plone.triumf.ca/HR/VME/ppg32)
* extract the ppg.jic file
* obtain the VME-PPG32-IO32 sof file (VME-PPG32.sof) from https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.sof?view=log

==== Update using USB-Blaster and jic file ====

* use Quartus programmer to burn the jic file through the EP3 active-serial flash loader:
* start Quartus programmer (tools->programmer)
* say "auto detect" - EP3, EPM1270 and EPM3032A should be detected
* attach VME-PPG32.sof to the EP3 part (context menu "change file")
* select "program"
* say "start"
* observe that 2 "red" LEDs have turned on on the PPG board (40MHz clock on outputs 4 and 20).
* say "auto detect"
* an "EPCS16" part should show up attached to the EP3.
* attach ppg.jic to the EPCS16 part
* select "program"
* say "start"
* observe progress bar go from 0 to 100% in about 2 minutes.
* PPG firmware is now loaded into the board
* cycle the power on the board to reboot into the PPG firmware
* when running the PPG firmware, all LEDs are off after reboot.

==== Update using VME flash programmer ====

(note: VME flash programmer interface does not work in ppg firmware version "1mar12").

* obtain the latest copy of srunner_vme (follow instructions here [[VME-NIMIO32#Firmware_update_procedure]]) (srunner_vme.cxx svn rev 214 or newer for jic support)
* ./srunner_vme_gef.exe -program -16 ppg.jic 0x100024
* reboot the PPG

(note: the above does not work: b) srunner_vme treats 0x10xxxx is an A24 address, but PPG firmware does not respond to A24 addresses; c) the active serial interface does not seem to work anyway)

(note: the reboot function is not available in the PPG firmware)

==== Update using VME flash programmer when running VME-PPG32-IO32 firmware ====

* ./test_VMENIMIO32_gef.exe --addr 0x100000 --read 0 ### to confirm VME-PPG32-IO32 firmware revision
* ./srunner_vme_gef.exe -program -16 ppg.jic 0x100020
* ./test_VMENIMIO32_gef.exe --addr 0x100000 --reboot ### PPG will stop responding
* ./test_a32.exe 0x100000 ### should read 0x00000000 (NOT 0xFFFFFFFF)

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || CSR || RW || Control/Status Register
|-
| 1 || 0x00004 || Test || RW || Test Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Inv_Mask || RW || Output Inversion Mask
|-
| 8 || 0x00020 || Version || R || Firmware Version Register
|-
| 9 || 0x00024 || Flash || RW || Serial Flash Control Register
|-
| 10 || 0x00028 || Serial || R || Serial Number Register
|-
| 11 || 0x0002C || Hardware || R || hardware Identification Register
|-
| 12 || 0x00030 || clock Control || RW || Clock Control Register
|}

===== CSR Register (0x00000) =====

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk-Toggle || W || Toggles between PPG external and internal Clk
|-
|2|| Ext-Start|| R/W || 1=Ext-PPG Start 0=Int-PPG Start
|-
|3|| PPG-Reset || R/W || 1=Reset 0=Normal operation
|-
|4|| Test-Mode || R/W || 1=Test Mode 0=Normal operation
|-
|16|| Ext-Clk-Sel || R || 1= External clock is selected 0 = Internal clock selected
|-
|17|| Ext-Clk good || R || 1= External clock is connected and is "good" 0= external clock not connected or is "bad"
|-
|?-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing an edge here toggles the ppg logic between the internal and external CLK (connected to Nim_Input[3]). The VME interface always uses the internal clock.
Note that the correct divide-down must be programmed unless external clock is the same frequency (i.e. 10MHz) as internal clock.

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start. (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[4])

Reset bit: Set bit to Reset PPG. Stops PPG pgm even if executing a long delay. Does NOT do a full reset to power-up condition. Bit must be cleared after Reset or module will not operate.

Test-Mode bit: Set bit to enable Test Mode. When Test Mode is enabled, inputs 1 and 2 become output the internal PPG clock and actual clock PPG is using, respectively. If internal clock is set, inputs 1 and 2 output identical clocks. If external clock is set, and the external clock is "good", input 1 will not change, but input 2 will show the external clock frequency.
If Test-Mode bit is cleared, Normal Mode is enabled, where inputs 1 and 2 act as regular inputs.

Ext-Clk-Sel: If bit is set, external clock is selected and LED 4 will be lit. If clear, internal clock is selected

Ext-Clk Good: If bit is set, external clock is connected to Nim_Input[3] and is "good". LED 2 will be lit. If clear, external clock is either not connected or is "bad".

===== Test Register (0x00004) =====

Simple Test Register - Value Written is preserved and can be read back.

===== Address Register (0x00008) =====

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address. Also in test-Mode, the NIM/LED outputs follow the state of this register.

===== Instruction Registers (0x0000C - 0x00018) =====

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

===== Output Inversion Mask (0x0001C) =====
32 individual inversion bits (1 per output) a 1 inverts the state of that output.

===== Firmware Version (0x00020) =====
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

===== Serial Flash Control (0x00024) =====
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

===== Serial Number (0x00028) =====
Returns the module serial number, and Board revision (if set) or 0xdead

===== hardware Type (0x0002C) =====
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

===== Clock Control (0x00030) =====
Set PLL parameters applied to external clock input. Default parameters are for 20Mhz External Clock, and multiply this by 5 to get 100Mhz ppg clock.

Register Contents as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 30-28 || Bits 26-24 || Bits 23-20 || Bits 16-8 || Bit 5 || Bit 4 || Bit 3 || Bit 2 || Bit 1 || Bit 0
|-
| Phase Counter Select || Counter Parameter || Counter Type || 9 bit Data || PLL Reset || Up/Down || PhaseStep || Write Parameter || reconfigure || Control Trigger
|-
|}

The Control Trigger Bit [bit 0] enables the four control signals in bits 1,2,3,5, and needs to be toggled from off to on, to apply these 4 signals.

On rising edge of control trigger ...
Phasestep=1 => clock phase is adjusted by 1 unit, in the direction selected by "Up/Down" [bit 4: 1=up,0=Down]
Write Parameter=1 => 9bit-Data, Counter-Type and Counter-Param are written into the PLL reconfiguration registers
Reconfigure=1 => PLL is reconfigured with the parameters currently in its reconfiguration registers
PLL-Reset=1 => PLL is reset

PhaseCounterSelect ...
0 => All Clocks
1 => M ?
2-6 => Clock 0-4

phasestep is applied immediately (to clocks selected by PhaseCounterSelect), and does not require a reconfiguration or reset.

The parameters below need to be written (with writeparameter=1), and then require a reconfiguration to be applied.

Counter-Type ...
0: N
1: M
2: Cp/LF
3: VCO
4-8: Clock 0-4
9-D: Clock 5-9 (Stratix Only)
E-F: Invalid

Counter-Parameter ...
0: HighCount [For VCO this parameter is: PostScale K=2 Yes/No]
1: LowCount
4: Bypass
5: Mode Odd/Even

Clock frequencies are defined by ...
VCO Frequency = Fin * M/N
The individual clock outputs [clock0-4] are given by ... VCO / C0-C4

Each of M,N,C0-C4 are the sum of a high and low count.
Note - can get 50% duty cycle with odd count by setting mode=odd with high=low+1
Each counter can be bypassed by setting bypass=1 (=> Scale=1)

Limits etc ...
Fin = 5 - 472 Mhz
Fvco = 600 - 1300 Mhz
Lock Time < 1ms

Examples ...
For Fin = 20Mhz [defaults settings on pwerup]
Fvco=1200,K=2 => 600Mhz .. M=30, N=1(Bypassed), C0=6(3+3) Fin=20Mhz => C0=100Mhz

For Fin=100Mhz [and M=30,N=1,C0=6] Need to Change N to 5 ...
Write: 0x00000305 0 0x01000205 0 0x05000105 0 0x04000005 0 0x3 0
type=0,hi=3 type=0,lo=2 type=0,mode=odd type=0,bypass=no Reconfigure

Change back from 100 to 20 - need to change N to bypassed ...
write: 0x04000105 0 0x3 0
type=0,bypass=no Reconfigure

For Deap 62.5 Mhz (20*25/8) Fvco=1000,k=2=>500 M=8 N=1 C0=5

=== Front Panel ===

==== NIM Inputs ====

The Input assignments are (as labelled on front panel) ...
4 - External Start (Not fully tested yet) Needs to stay high (low => stop!)
3 - External Clock (20Mhz, internally scaled - 100Mhz)
2 - Unassigned
1 - Unassigned

==== Input LEDs ====

The Input LED assignments are (as labelled on front panel) ...
4 - Clock setting (Lit => External Clk)
3 - NimIn[2] status
2 - External Clock Good indicator (Lit => Clock is good)
1 - Program Running

=== Test Software ===

==== c-shell script to run 2 nested loops ====

set dec_hex=( 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 \
0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf \
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 \
0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f \
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 )

# dly4,loop4,dly3,loop6,dly2,end,end
set inst=( \
0xff 0x00 0x4 0x100000 0x0 0x0 0x0 0x200004 \
0x1 0x1 0x3 0x100000 0x0 0x0 0x0 0x200006 \
0x2 0x2 0x2 0x100000 0x0 0x0 0x0 0x300000 \
0x0 0x0 0x0 0x300000 0x0 0x0 0x0 0x000000 )

set i=0
set j=0
while( $i < $#inst )
@ j++; vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 $dec_hex[$j]
@ i++; vme_poke -a VME_A32UD -A 0x0010000c -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100010 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100014 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100018 -d VME_D32 $inst[$i]
end

# start program (from addr 0)...
vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100000 -d VME_D32 0x1

==== c-shell script to set divide-downs for 100MHz frequency ====

This would be used with an external frequency input of 100MHz

vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x00000305 # set hi counter to 3
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x01000205 # set lo counter to 2
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x05000105 # set mode counter to odd
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000005 # set counter bypass to 0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0

==== c-shell script to set divide-downs for 10MHz frequency ====

This would be used when returning to the internal frequency of 10MHz :

vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000105 # set counter bypass to 1
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3 # reconfig clock
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd

=== Procedure for newly assembled board startup and test ===

(note1: VME-PPG32-IO32 firmware is used to test the board)

(note2: TTL inputs and outputs are not tested)

(note3: DAC outputs are not tested)

(note4: shorts between NIM outputs are not tested)

* set VME address jumper A20-23 to "1", jumpers A24-27 and A28-31 to "0"
* set inputs and outputs to "NIM" mode
* connect JTAG USB blaster
* power up the board (standalone or in a VME crate)
* start Quartus programmer
* select correct USB blaster
* run "auto detect", 3 devices should be detected: EP3C20Q240 (Cyclone3 FPGA), EPM1270 (parallel flash loader CPLD), EPM3032AT44 (VME address decoder CPLD)
* flash the VME address decoder pof file into the EPM3032 part (get pof file from here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode/VME_Addr_decode.pof?view=log)
* (do not do this) flash the CFI parallel flash loader into the EPM1270 part (get pof file where?!?)
* load the VME-PPG32-IO32 firmware sof file into the EP3 part (get sof file here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.sof?view=log)
* run "vmescan_gef.exe", it should detect the IO32 board at A24 VME address 0x00100000, data should correspond to the sof file revision date code
* confirm VME access LED is working (flashes during vme scan).
* confirm VME Data bus is okey: "./test_VMENIMIO32_gef.exe --addr 0x100000 --testbits 4"
* (do not do this) follow the firmware update instructions to flash the firmware pof file using the VME flash programmer at [[VME-NIMIO32#Firmware_update_procedure]] (get VME-PPG32-IO32 pof file from here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.pof?view=log)
* (do not do this) confirm FPGA reboot is working - "./test_VMENIMIO32_gef.exe --addr 0x100000 --reboot" prints 0xFFFFFFFF on the second read of firmware revision
* test NIM inputs and LEDs: use NIM pulse generator or any NIM module inverted output, connect to each NIM input, observe that corresponding "green" LEDs is lighting up
* test NIM outputs and LEDs: "./test_VMENIMIO32_gef.exe --addr 0x100000 --nimout 3 1 --pulsenim", observe all "red" LEDs are flashing, connect NIM outputs to NIM scaler, observe scaler counts at each LED flash
* load PPG firmware into the active serial flash (follow instructions here: [[#Update_using_VME_flash_programmer_when_running_VME-PPG32-IO32_firmware]]
* unplug the board from VME, wait 10 sec, plug it back in, confirm that it is detected by vmescan if running VME-PPG32-IO32 firmware or test_a32 or PPG test tools if running the PPG firmware (confirms the flash memory contents is good)

=== VME-PPG32-IO32 firmware ===

The VME-PPG32 board can run a special version of VME-NIMIO32 firmware (subproject "PPG32-Rev1" of the VME-NIMIO32 firmware). For instructions, please refer to the [[VME-NIMIO32]] documentation.

VME-PPG32

2013-02-20T23:47:55Z

Cpearson: /* Clock Control (0x00030) */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [https://edev.triumf.ca/projects/edevel00022] VME-PPG32 Rev0 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/projects/edevel00067] VME-PPG32 Rev1 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/projects/edevel00125] VME-PPG32 Rev2 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/documents/27] Rev0 board schematics on edev site
* [https://edev.triumf.ca/documents/111] Rev1 board schematics on edev site
* [https://edev.triumf.ca/documents/158] Rev2 board schematics on edev site
* [[Image:VME-PPG32 Rev1.pdf]] Rev1 board schematics, local copy
* [[Image:VME-PPG32 Rev2.pdf]] Rev2 board schematics, local copy

VME-PPG32-IO32 firmware: (IO32 functions, no PPG functions)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32-Rev0] Svn repository for VME-PPG32-Rev0 initial test firmware (IO32 function only, no PPG function)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1] Svn repository for VME-PPG32-Rev1 firmware (IO32 function only, no PPG function)

VME-PPG32 VME CPLD firmware: (VME address decoder)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode] Svn repository for VME-PPG32 Rev0 and Rev1 VME address decoder CPLD (Altera EPM3032)

VME-PPG32 firmware: (PPG function)
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ
* Rev1 and Rev2 boards: inputs are switchable between NIM and TTL (JMP3)
* Rev2 boards: outputs are switchable between NIM and TTL (SW1 micro switches)

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input - see note 1)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

FPGA resource Usage : 1044 LE, 500 kbits Memory

Note 1 :
Some modules allow an external clock frequency of 20-100MHz . Divide-downs must be programmed where external clock frequency is not 20MHz.
Examples of divide-down programming is shown at end of this document.

=== Onboard jumper settings ===

* JMP1 - set to "INP" for input with 50 Ohm termination, set to "DAC" for DAC output
* JMP2 - set to "INP" same as JMP1
* JMP3 - set to "NIM" (pins 1-2) for NIM inputs or "TTL" (pins 2-3) for TTL inputs
* JMP4 - "MSEL1" jumper set to "ACT" for use with the active-serial flash
* IrqSel - leave open
* JTAG - leave open (not a jumper block!)
* SW1..3 - VME base address selectors (see below)

=== Firmware update procedure ===

(note1: right now the PPG firmware update procedure is unnecessary complicated because there is no ppg.pof file in the PPG firmware distribution version "1mar12" and the PPG firmware does not include the Altera active-serial programmer block.)

(note2: VME-PPG32-IO32 firmware (sof file) is required to update the PPG firmware)

* obtain the PPG firmware zip file (from http://daq-plone.triumf.ca/HR/VME/ppg32)
* extract the ppg.jic file
* obtain the VME-PPG32-IO32 sof file (VME-PPG32.sof) from https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.sof?view=log

==== Update using USB-Blaster and jic file ====

* use Quartus programmer to burn the jic file through the EP3 active-serial flash loader:
* start Quartus programmer (tools->programmer)
* say "auto detect" - EP3, EPM1270 and EPM3032A should be detected
* attach VME-PPG32.sof to the EP3 part (context menu "change file")
* select "program"
* say "start"
* observe that 2 "red" LEDs have turned on on the PPG board (40MHz clock on outputs 4 and 20).
* say "auto detect"
* an "EPCS16" part should show up attached to the EP3.
* attach ppg.jic to the EPCS16 part
* select "program"
* say "start"
* observe progress bar go from 0 to 100% in about 2 minutes.
* PPG firmware is now loaded into the board
* cycle the power on the board to reboot into the PPG firmware
* when running the PPG firmware, all LEDs are off after reboot.

==== Update using VME flash programmer ====

(note: VME flash programmer interface does not work in ppg firmware version "1mar12").

* obtain the latest copy of srunner_vme (follow instructions here [[VME-NIMIO32#Firmware_update_procedure]]) (srunner_vme.cxx svn rev 214 or newer for jic support)
* ./srunner_vme_gef.exe -program -16 ppg.jic 0x100024
* reboot the PPG

(note: the above does not work: b) srunner_vme treats 0x10xxxx is an A24 address, but PPG firmware does not respond to A24 addresses; c) the active serial interface does not seem to work anyway)

(note: the reboot function is not available in the PPG firmware)

==== Update using VME flash programmer when running VME-PPG32-IO32 firmware ====

* ./test_VMENIMIO32_gef.exe --addr 0x100000 --read 0 ### to confirm VME-PPG32-IO32 firmware revision
* ./srunner_vme_gef.exe -program -16 ppg.jic 0x100020
* ./test_VMENIMIO32_gef.exe --addr 0x100000 --reboot ### PPG will stop responding
* ./test_a32.exe 0x100000 ### should read 0x00000000 (NOT 0xFFFFFFFF)

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || CSR || RW || Control/Status Register
|-
| 1 || 0x00004 || Test || RW || Test Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Inv_Mask || RW || Output Inversion Mask
|-
| 8 || 0x00020 || Version || R || Firmware Version Register
|-
| 9 || 0x00024 || Flash || RW || Serial Flash Control Register
|-
| 10 || 0x00028 || Serial || R || Serial Number Register
|-
| 11 || 0x0002C || Hardware || R || hardware Identification Register
|-
| 12 || 0x00030 || clock Control || RW || Clock Control Register
|}

===== CSR Register (0x00000) =====

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk-Toggle || W || Toggles between PPG external and internal Clk
|-
|2|| Ext-Start|| R/W || 1=Ext-PPG Start 0=Int-PPG Start
|-
|3|| PPG-Reset || R/W || 1=Reset 0=Normal operation
|-
|4|| Test-Mode || R/W || 1=Test Mode 0=Normal operation
|-
|16|| Ext-Clk-Sel || R || 1= External clock is selected 0 = Internal clock selected
|-
|17|| Ext-Clk good || R || 1= External clock is connected and is "good" 0= external clock not connected or is "bad"
|-
|?-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing an edge here toggles the ppg logic between the internal and external CLK (connected to Nim_Input[3]). The VME interface always uses the internal clock.
Note that the correct divide-down must be programmed unless external clock is the same frequency (i.e. 10MHz) as internal clock.

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start. (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[4])

Reset bit: Set bit to Reset PPG. Stops PPG pgm even if executing a long delay. Does NOT do a full reset to power-up condition. Bit must be cleared after Reset or module will not operate.

Test-Mode bit: Set bit to enable Test Mode. When Test Mode is enabled, inputs 1 and 2 become output the internal PPG clock and actual clock PPG is using, respectively. If internal clock is set, inputs 1 and 2 output identical clocks. If external clock is set, and the external clock is "good", input 1 will not change, but input 2 will show the external clock frequency.
If Test-Mode bit is cleared, Normal Mode is enabled, where inputs 1 and 2 act as regular inputs.

Ext-Clk-Sel: If bit is set, external clock is selected and LED 4 will be lit. If clear, internal clock is selected

Ext-Clk Good: If bit is set, external clock is connected to Nim_Input[3] and is "good". LED 2 will be lit. If clear, external clock is either not connected or is "bad".

===== Test Register (0x00004) =====

Simple Test Register - Value Written is preserved and can be read back.

===== Address Register (0x00008) =====

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address. Also in test-Mode, the NIM/LED outputs follow the state of this register.

===== Instruction Registers (0x0000C - 0x00018) =====

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

===== Output Inversion Mask (0x0001C) =====
32 individual inversion bits (1 per output) a 1 inverts the state of that output.

===== Firmware Version (0x00020) =====
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

===== Serial Flash Control (0x00024) =====
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

===== Serial Number (0x00028) =====
Returns the module serial number, and Board revision (if set) or 0xdead

===== hardware Type (0x0002C) =====
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

===== Clock Control (0x00030) =====
Set PLL parameters applied to external clock input. Default parameters are for 20Mhz External Clock, and multiply this by 5 to get 100Mhz ppg clock.

Register Contents as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 30-28 || Bits 26-24 || Bits 23-20 || Bits 16-8 || Bit 5 || Bit 4 || Bit 3 || Bit 2 || Bit 1 || Bit 0
|-
| Phase Counter Select || Counter Parameter || Counter Type || 9 bit Data || PLL Reset || Up/Down || PhaseStep || Write Parameter || reconfigure || Control Trigger
|-
|}

The Control Trigger Bit [bit 0] enables the four control signals in bits 1,2,3,5, and needs to be toggled from off to on, to apply these 4 signals.

On rising edge of control trigger ...
Phasestep=1 => clock phase is adjusted by 1 unit, in the direction selected by "Up/Down" [bit 4: 1=up,0=Down]
Write Parameter=1 => 9bit-Data, Counter-Type and Counter-Param are written into the PLL reconfiguration registers
Reconfigure=1 => PLL is reconfigured with the parameters currently in its reconfiguration registers
PLL-Reset=1 => PLL is reset

PhaseCounterSelect ...
0 => All Clocks
1 => M ?
2-6 => Clock 0-4

phasestep is applied immediately (to clocks selected by PhaseCounterSelect), and does not require a reconfiguration or reset.

The parameters below need to be written (with writeparameter=1), and then require a reconfiguration to be applied.

Counter-Type ...
0: N
1: M
2: Cp/LF
3: VCO
4-8: Clock 0-4
9-D: Clock 5-9 (Stratix Only)
E-F: Invalid

Counter-Parameter ...
0: HighCount [For VCO this parameter is: PostScale K=2 Yes/No]
1: LowCount
4: Bypass
5: Mode Odd/Even

Clock frequencies are defined by ...
VCO Frequency = Fin * M/N
The individual clock outputs [clock0-4] are given by ... VCO / C0-C4

Each of M,N,C0-C4 are the sum of a high and low count.
Note - can get 50% duty cycle with odd count by setting mode=odd with high=low+1
Each counter can be bypassed by setting bypass=1 (=> Scale=1)

Limits etc ...
Fin = 5 - 472 Mhz
Fvco = 600 - 1300 Mhz
Lock Time < 1ms

Examples ...
For Fin = 20Mhz [defaults settings on pwerup]
Fvco=1200,K=2 => 600Mhz .. M=30, N=1(Bypassed), C0=6(3+3) Fin=20Mhz => C0=100Mhz

For Fin=100Mhz [and M=30,N=1,C0=6] Need to Change N to 5 ...
Write: 0x00000305 0 0x01000205 0 0x05000105 0 0x04000005 0 0x3 0
type=0,hi=3 type=0,lo=2 type=0,mode=odd type=0,bypass=no reconfigure

Change back from 100 to 20 - need to change N to bypassed ...
write:

=== Front Panel ===

==== NIM Inputs ====

The Input assignments are (as labelled on front panel) ...
4 - External Start (Not fully tested yet) Needs to stay high (low => stop!)
3 - External Clock (20Mhz, internally scaled - 100Mhz)
2 - Unassigned
1 - Unassigned

==== Input LEDs ====

The Input LED assignments are (as labelled on front panel) ...
4 - Clock setting (Lit => External Clk)
3 - NimIn[2] status
2 - External Clock Good indicator (Lit => Clock is good)
1 - Program Running

=== Test Software ===

==== c-shell script to run 2 nested loops ====

set dec_hex=( 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 \
0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf \
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 \
0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f \
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 )

# dly4,loop4,dly3,loop6,dly2,end,end
set inst=( \
0xff 0x00 0x4 0x100000 0x0 0x0 0x0 0x200004 \
0x1 0x1 0x3 0x100000 0x0 0x0 0x0 0x200006 \
0x2 0x2 0x2 0x100000 0x0 0x0 0x0 0x300000 \
0x0 0x0 0x0 0x300000 0x0 0x0 0x0 0x000000 )

set i=0
set j=0
while( $i < $#inst )
@ j++; vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 $dec_hex[$j]
@ i++; vme_poke -a VME_A32UD -A 0x0010000c -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100010 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100014 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100018 -d VME_D32 $inst[$i]
end

# start program (from addr 0)...
vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100000 -d VME_D32 0x1

==== c-shell script to set divide-downs for 100MHz frequency ====

This would be used with an external frequency input of 100MHz

vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x00000305 # set hi counter to 3
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x01000205 # set lo counter to 2
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x05000105 # set mode counter to odd
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000005 # set counter bypass to 0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0

==== c-shell script to set divide-downs for 10MHz frequency ====

This would be used when returning to the internal frequency of 10MHz :

vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000105 # set counter bypass to 1
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3 # reconfig clock
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd

=== Procedure for newly assembled board startup and test ===

(note1: VME-PPG32-IO32 firmware is used to test the board)

(note2: TTL inputs and outputs are not tested)

(note3: DAC outputs are not tested)

(note4: shorts between NIM outputs are not tested)

* set VME address jumper A20-23 to "1", jumpers A24-27 and A28-31 to "0"
* set inputs and outputs to "NIM" mode
* connect JTAG USB blaster
* power up the board (standalone or in a VME crate)
* start Quartus programmer
* select correct USB blaster
* run "auto detect", 3 devices should be detected: EP3C20Q240 (Cyclone3 FPGA), EPM1270 (parallel flash loader CPLD), EPM3032AT44 (VME address decoder CPLD)
* flash the VME address decoder pof file into the EPM3032 part (get pof file from here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode/VME_Addr_decode.pof?view=log)
* (do not do this) flash the CFI parallel flash loader into the EPM1270 part (get pof file where?!?)
* load the VME-PPG32-IO32 firmware sof file into the EP3 part (get sof file here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.sof?view=log)
* run "vmescan_gef.exe", it should detect the IO32 board at A24 VME address 0x00100000, data should correspond to the sof file revision date code
* confirm VME access LED is working (flashes during vme scan).
* confirm VME Data bus is okey: "./test_VMENIMIO32_gef.exe --addr 0x100000 --testbits 4"
* (do not do this) follow the firmware update instructions to flash the firmware pof file using the VME flash programmer at [[VME-NIMIO32#Firmware_update_procedure]] (get VME-PPG32-IO32 pof file from here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.pof?view=log)
* (do not do this) confirm FPGA reboot is working - "./test_VMENIMIO32_gef.exe --addr 0x100000 --reboot" prints 0xFFFFFFFF on the second read of firmware revision
* test NIM inputs and LEDs: use NIM pulse generator or any NIM module inverted output, connect to each NIM input, observe that corresponding "green" LEDs is lighting up
* test NIM outputs and LEDs: "./test_VMENIMIO32_gef.exe --addr 0x100000 --nimout 3 1 --pulsenim", observe all "red" LEDs are flashing, connect NIM outputs to NIM scaler, observe scaler counts at each LED flash
* load PPG firmware into the active serial flash (follow instructions here: [[#Update_using_VME_flash_programmer_when_running_VME-PPG32-IO32_firmware]]
* unplug the board from VME, wait 10 sec, plug it back in, confirm that it is detected by vmescan if running VME-PPG32-IO32 firmware or test_a32 or PPG test tools if running the PPG firmware (confirms the flash memory contents is good)

=== VME-PPG32-IO32 firmware ===

The VME-PPG32 board can run a special version of VME-NIMIO32 firmware (subproject "PPG32-Rev1" of the VME-NIMIO32 firmware). For instructions, please refer to the [[VME-NIMIO32]] documentation.

VME-PPG32

2013-02-20T23:46:50Z

Cpearson: /* Clock Control (0x00030) */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [https://edev.triumf.ca/projects/edevel00022] VME-PPG32 Rev0 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/projects/edevel00067] VME-PPG32 Rev1 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/projects/edevel00125] VME-PPG32 Rev2 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/documents/27] Rev0 board schematics on edev site
* [https://edev.triumf.ca/documents/111] Rev1 board schematics on edev site
* [https://edev.triumf.ca/documents/158] Rev2 board schematics on edev site
* [[Image:VME-PPG32 Rev1.pdf]] Rev1 board schematics, local copy
* [[Image:VME-PPG32 Rev2.pdf]] Rev2 board schematics, local copy

VME-PPG32-IO32 firmware: (IO32 functions, no PPG functions)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32-Rev0] Svn repository for VME-PPG32-Rev0 initial test firmware (IO32 function only, no PPG function)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1] Svn repository for VME-PPG32-Rev1 firmware (IO32 function only, no PPG function)

VME-PPG32 VME CPLD firmware: (VME address decoder)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode] Svn repository for VME-PPG32 Rev0 and Rev1 VME address decoder CPLD (Altera EPM3032)

VME-PPG32 firmware: (PPG function)
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ
* Rev1 and Rev2 boards: inputs are switchable between NIM and TTL (JMP3)
* Rev2 boards: outputs are switchable between NIM and TTL (SW1 micro switches)

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input - see note 1)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

FPGA resource Usage : 1044 LE, 500 kbits Memory

Note 1 :
Some modules allow an external clock frequency of 20-100MHz . Divide-downs must be programmed where external clock frequency is not 20MHz.
Examples of divide-down programming is shown at end of this document.

=== Onboard jumper settings ===

* JMP1 - set to "INP" for input with 50 Ohm termination, set to "DAC" for DAC output
* JMP2 - set to "INP" same as JMP1
* JMP3 - set to "NIM" (pins 1-2) for NIM inputs or "TTL" (pins 2-3) for TTL inputs
* JMP4 - "MSEL1" jumper set to "ACT" for use with the active-serial flash
* IrqSel - leave open
* JTAG - leave open (not a jumper block!)
* SW1..3 - VME base address selectors (see below)

=== Firmware update procedure ===

(note1: right now the PPG firmware update procedure is unnecessary complicated because there is no ppg.pof file in the PPG firmware distribution version "1mar12" and the PPG firmware does not include the Altera active-serial programmer block.)

(note2: VME-PPG32-IO32 firmware (sof file) is required to update the PPG firmware)

* obtain the PPG firmware zip file (from http://daq-plone.triumf.ca/HR/VME/ppg32)
* extract the ppg.jic file
* obtain the VME-PPG32-IO32 sof file (VME-PPG32.sof) from https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.sof?view=log

==== Update using USB-Blaster and jic file ====

* use Quartus programmer to burn the jic file through the EP3 active-serial flash loader:
* start Quartus programmer (tools->programmer)
* say "auto detect" - EP3, EPM1270 and EPM3032A should be detected
* attach VME-PPG32.sof to the EP3 part (context menu "change file")
* select "program"
* say "start"
* observe that 2 "red" LEDs have turned on on the PPG board (40MHz clock on outputs 4 and 20).
* say "auto detect"
* an "EPCS16" part should show up attached to the EP3.
* attach ppg.jic to the EPCS16 part
* select "program"
* say "start"
* observe progress bar go from 0 to 100% in about 2 minutes.
* PPG firmware is now loaded into the board
* cycle the power on the board to reboot into the PPG firmware
* when running the PPG firmware, all LEDs are off after reboot.

==== Update using VME flash programmer ====

(note: VME flash programmer interface does not work in ppg firmware version "1mar12").

* obtain the latest copy of srunner_vme (follow instructions here [[VME-NIMIO32#Firmware_update_procedure]]) (srunner_vme.cxx svn rev 214 or newer for jic support)
* ./srunner_vme_gef.exe -program -16 ppg.jic 0x100024
* reboot the PPG

(note: the above does not work: b) srunner_vme treats 0x10xxxx is an A24 address, but PPG firmware does not respond to A24 addresses; c) the active serial interface does not seem to work anyway)

(note: the reboot function is not available in the PPG firmware)

==== Update using VME flash programmer when running VME-PPG32-IO32 firmware ====

* ./test_VMENIMIO32_gef.exe --addr 0x100000 --read 0 ### to confirm VME-PPG32-IO32 firmware revision
* ./srunner_vme_gef.exe -program -16 ppg.jic 0x100020
* ./test_VMENIMIO32_gef.exe --addr 0x100000 --reboot ### PPG will stop responding
* ./test_a32.exe 0x100000 ### should read 0x00000000 (NOT 0xFFFFFFFF)

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || CSR || RW || Control/Status Register
|-
| 1 || 0x00004 || Test || RW || Test Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Inv_Mask || RW || Output Inversion Mask
|-
| 8 || 0x00020 || Version || R || Firmware Version Register
|-
| 9 || 0x00024 || Flash || RW || Serial Flash Control Register
|-
| 10 || 0x00028 || Serial || R || Serial Number Register
|-
| 11 || 0x0002C || Hardware || R || hardware Identification Register
|-
| 12 || 0x00030 || clock Control || RW || Clock Control Register
|}

===== CSR Register (0x00000) =====

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk-Toggle || W || Toggles between PPG external and internal Clk
|-
|2|| Ext-Start|| R/W || 1=Ext-PPG Start 0=Int-PPG Start
|-
|3|| PPG-Reset || R/W || 1=Reset 0=Normal operation
|-
|4|| Test-Mode || R/W || 1=Test Mode 0=Normal operation
|-
|16|| Ext-Clk-Sel || R || 1= External clock is selected 0 = Internal clock selected
|-
|17|| Ext-Clk good || R || 1= External clock is connected and is "good" 0= external clock not connected or is "bad"
|-
|?-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing an edge here toggles the ppg logic between the internal and external CLK (connected to Nim_Input[3]). The VME interface always uses the internal clock.
Note that the correct divide-down must be programmed unless external clock is the same frequency (i.e. 10MHz) as internal clock.

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start. (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[4])

Reset bit: Set bit to Reset PPG. Stops PPG pgm even if executing a long delay. Does NOT do a full reset to power-up condition. Bit must be cleared after Reset or module will not operate.

Test-Mode bit: Set bit to enable Test Mode. When Test Mode is enabled, inputs 1 and 2 become output the internal PPG clock and actual clock PPG is using, respectively. If internal clock is set, inputs 1 and 2 output identical clocks. If external clock is set, and the external clock is "good", input 1 will not change, but input 2 will show the external clock frequency.
If Test-Mode bit is cleared, Normal Mode is enabled, where inputs 1 and 2 act as regular inputs.

Ext-Clk-Sel: If bit is set, external clock is selected and LED 4 will be lit. If clear, internal clock is selected

Ext-Clk Good: If bit is set, external clock is connected to Nim_Input[3] and is "good". LED 2 will be lit. If clear, external clock is either not connected or is "bad".

===== Test Register (0x00004) =====

Simple Test Register - Value Written is preserved and can be read back.

===== Address Register (0x00008) =====

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address. Also in test-Mode, the NIM/LED outputs follow the state of this register.

===== Instruction Registers (0x0000C - 0x00018) =====

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

===== Output Inversion Mask (0x0001C) =====
32 individual inversion bits (1 per output) a 1 inverts the state of that output.

===== Firmware Version (0x00020) =====
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

===== Serial Flash Control (0x00024) =====
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

===== Serial Number (0x00028) =====
Returns the module serial number, and Board revision (if set) or 0xdead

===== hardware Type (0x0002C) =====
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

===== Clock Control (0x00030) =====
Set PLL parameters applied to external clock input. Default parameters are for 20Mhz External Clock, and multiply this by 5 to get 100Mhz ppg clock.

Register Contents as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 30-28 || Bits 26-24 || Bits 23-20 || Bits 16-8 || Bit 5 || Bit 4 || Bit 3 || Bit 2 || Bit 1 || Bit 0
|-
| Phase Counter Select || Counter Parameter || Counter Type || 9 bit Data || PLL Reset || Up/Down || PhaseStep || Write Parameter || reconfigure || Control Trigger
|-
|}

The Control Trigger Bit [bit 0] enables the four control signals in bits 1,2,3,5, and needs to be toggled from off to on, to apply these 4 signals.

On rising edge of control trigger ...
Phasestep=1 => clock phase is adjusted by 1 unit, in the direction selected by "Up/Down" [bit 4: 1=up,0=Down]
Write Parameter=1 => 9bit-Data, Counter-Type and Counter-Param are written into the PLL reconfiguration registers
Reconfigure=1 => PLL is reconfigured with the parameters currently in its reconfiguration registers
PLL-Reset=1 => PLL is reset

PhaseCounterSelect ...
0 => All Clocks
1 => M ?
2-6 => Clock 0-4

phasestep is applied immediately (to clocks selected by PhaseCounterSelect), and does not require a reconfiguration or reset.

The parameters below need to be written (with writeparameter=1), and then require a reconfiguration to be applied.

Counter-Type ...
0: N
1: M
2: Cp/LF
3: VCO
4-8: Clock 0-4
9-D: Clock 5-9 (Stratix Only)
E-F: Invalid

Counter-Parameter ...
0: HighCount [For VCO this parameter is: PostScale K=2 Yes/No]
1: LowCount
4: Bypass
5: Mode Odd/Even

Clock frequencies are defined by ...
VCO Frequency = Fin * M/N
The individual clock outputs [clock0-4] are given by ... VCO / C0-C4

Each of M,N,C0-C4 are the sum of a high and low count.
Note - can get 50% duty cycle with odd count by setting mode=odd with high=low+1
Each counter can be bypassed by setting bypass=1 (=> Scale=1)

Limits etc ...
Fin = 5 - 472 Mhz
Fvco = 600 - 1300 Mhz
Lock Time < 1ms

Examples ...
For Fin = 20Mhz [defaults settings on pwerup]
Fvco=1200,K=2 => 600Mhz .. M=30, N=1(Bypassed), C0=6(3+3) Fin=20Mhz => C0=100Mhz

For Fin=100Mhz [and M=30,N=1,C0=6] Need to Change N to 5 ...
Write: 0x00000305 0 0x01000205 0 0x05000105 0 0x04000005
type=0,hi=3 type=0,lo=2 type=0,mode=odd type=0,bypass=no

Change back from 100 to 20 - need to change N to bypassed ...
write:

=== Front Panel ===

==== NIM Inputs ====

The Input assignments are (as labelled on front panel) ...
4 - External Start (Not fully tested yet) Needs to stay high (low => stop!)
3 - External Clock (20Mhz, internally scaled - 100Mhz)
2 - Unassigned
1 - Unassigned

==== Input LEDs ====

The Input LED assignments are (as labelled on front panel) ...
4 - Clock setting (Lit => External Clk)
3 - NimIn[2] status
2 - External Clock Good indicator (Lit => Clock is good)
1 - Program Running

=== Test Software ===

==== c-shell script to run 2 nested loops ====

set dec_hex=( 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 \
0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf \
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 \
0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f \
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 )

# dly4,loop4,dly3,loop6,dly2,end,end
set inst=( \
0xff 0x00 0x4 0x100000 0x0 0x0 0x0 0x200004 \
0x1 0x1 0x3 0x100000 0x0 0x0 0x0 0x200006 \
0x2 0x2 0x2 0x100000 0x0 0x0 0x0 0x300000 \
0x0 0x0 0x0 0x300000 0x0 0x0 0x0 0x000000 )

set i=0
set j=0
while( $i < $#inst )
@ j++; vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 $dec_hex[$j]
@ i++; vme_poke -a VME_A32UD -A 0x0010000c -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100010 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100014 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100018 -d VME_D32 $inst[$i]
end

# start program (from addr 0)...
vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100000 -d VME_D32 0x1

==== c-shell script to set divide-downs for 100MHz frequency ====

This would be used with an external frequency input of 100MHz

vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x00000305 # set hi counter to 3
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x01000205 # set lo counter to 2
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x05000105 # set mode counter to odd
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000005 # set counter bypass to 0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0

==== c-shell script to set divide-downs for 10MHz frequency ====

This would be used when returning to the internal frequency of 10MHz :

vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000105 # set counter bypass to 1
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3 # reconfig clock
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd

=== Procedure for newly assembled board startup and test ===

(note1: VME-PPG32-IO32 firmware is used to test the board)

(note2: TTL inputs and outputs are not tested)

(note3: DAC outputs are not tested)

(note4: shorts between NIM outputs are not tested)

* set VME address jumper A20-23 to "1", jumpers A24-27 and A28-31 to "0"
* set inputs and outputs to "NIM" mode
* connect JTAG USB blaster
* power up the board (standalone or in a VME crate)
* start Quartus programmer
* select correct USB blaster
* run "auto detect", 3 devices should be detected: EP3C20Q240 (Cyclone3 FPGA), EPM1270 (parallel flash loader CPLD), EPM3032AT44 (VME address decoder CPLD)
* flash the VME address decoder pof file into the EPM3032 part (get pof file from here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode/VME_Addr_decode.pof?view=log)
* (do not do this) flash the CFI parallel flash loader into the EPM1270 part (get pof file where?!?)
* load the VME-PPG32-IO32 firmware sof file into the EP3 part (get sof file here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.sof?view=log)
* run "vmescan_gef.exe", it should detect the IO32 board at A24 VME address 0x00100000, data should correspond to the sof file revision date code
* confirm VME access LED is working (flashes during vme scan).
* confirm VME Data bus is okey: "./test_VMENIMIO32_gef.exe --addr 0x100000 --testbits 4"
* (do not do this) follow the firmware update instructions to flash the firmware pof file using the VME flash programmer at [[VME-NIMIO32#Firmware_update_procedure]] (get VME-PPG32-IO32 pof file from here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.pof?view=log)
* (do not do this) confirm FPGA reboot is working - "./test_VMENIMIO32_gef.exe --addr 0x100000 --reboot" prints 0xFFFFFFFF on the second read of firmware revision
* test NIM inputs and LEDs: use NIM pulse generator or any NIM module inverted output, connect to each NIM input, observe that corresponding "green" LEDs is lighting up
* test NIM outputs and LEDs: "./test_VMENIMIO32_gef.exe --addr 0x100000 --nimout 3 1 --pulsenim", observe all "red" LEDs are flashing, connect NIM outputs to NIM scaler, observe scaler counts at each LED flash
* load PPG firmware into the active serial flash (follow instructions here: [[#Update_using_VME_flash_programmer_when_running_VME-PPG32-IO32_firmware]]
* unplug the board from VME, wait 10 sec, plug it back in, confirm that it is detected by vmescan if running VME-PPG32-IO32 firmware or test_a32 or PPG test tools if running the PPG firmware (confirms the flash memory contents is good)

=== VME-PPG32-IO32 firmware ===

The VME-PPG32 board can run a special version of VME-NIMIO32 firmware (subproject "PPG32-Rev1" of the VME-NIMIO32 firmware). For instructions, please refer to the [[VME-NIMIO32]] documentation.

VME-PPG32

2013-02-20T23:34:18Z

Cpearson: /* Clock Control (0x00030) */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [https://edev.triumf.ca/projects/edevel00022] VME-PPG32 Rev0 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/projects/edevel00067] VME-PPG32 Rev1 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/projects/edevel00125] VME-PPG32 Rev2 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/documents/27] Rev0 board schematics on edev site
* [https://edev.triumf.ca/documents/111] Rev1 board schematics on edev site
* [https://edev.triumf.ca/documents/158] Rev2 board schematics on edev site
* [[Image:VME-PPG32 Rev1.pdf]] Rev1 board schematics, local copy
* [[Image:VME-PPG32 Rev2.pdf]] Rev2 board schematics, local copy

VME-PPG32-IO32 firmware: (IO32 functions, no PPG functions)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32-Rev0] Svn repository for VME-PPG32-Rev0 initial test firmware (IO32 function only, no PPG function)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1] Svn repository for VME-PPG32-Rev1 firmware (IO32 function only, no PPG function)

VME-PPG32 VME CPLD firmware: (VME address decoder)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode] Svn repository for VME-PPG32 Rev0 and Rev1 VME address decoder CPLD (Altera EPM3032)

VME-PPG32 firmware: (PPG function)
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ
* Rev1 and Rev2 boards: inputs are switchable between NIM and TTL (JMP3)
* Rev2 boards: outputs are switchable between NIM and TTL (SW1 micro switches)

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input - see note 1)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

FPGA resource Usage : 1044 LE, 500 kbits Memory

Note 1 :
Some modules allow an external clock frequency of 20-100MHz . Divide-downs must be programmed where external clock frequency is not 20MHz.
Examples of divide-down programming is shown at end of this document.

=== Onboard jumper settings ===

* JMP1 - set to "INP" for input with 50 Ohm termination, set to "DAC" for DAC output
* JMP2 - set to "INP" same as JMP1
* JMP3 - set to "NIM" (pins 1-2) for NIM inputs or "TTL" (pins 2-3) for TTL inputs
* JMP4 - "MSEL1" jumper set to "ACT" for use with the active-serial flash
* IrqSel - leave open
* JTAG - leave open (not a jumper block!)
* SW1..3 - VME base address selectors (see below)

=== Firmware update procedure ===

(note1: right now the PPG firmware update procedure is unnecessary complicated because there is no ppg.pof file in the PPG firmware distribution version "1mar12" and the PPG firmware does not include the Altera active-serial programmer block.)

(note2: VME-PPG32-IO32 firmware (sof file) is required to update the PPG firmware)

* obtain the PPG firmware zip file (from http://daq-plone.triumf.ca/HR/VME/ppg32)
* extract the ppg.jic file
* obtain the VME-PPG32-IO32 sof file (VME-PPG32.sof) from https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.sof?view=log

==== Update using USB-Blaster and jic file ====

* use Quartus programmer to burn the jic file through the EP3 active-serial flash loader:
* start Quartus programmer (tools->programmer)
* say "auto detect" - EP3, EPM1270 and EPM3032A should be detected
* attach VME-PPG32.sof to the EP3 part (context menu "change file")
* select "program"
* say "start"
* observe that 2 "red" LEDs have turned on on the PPG board (40MHz clock on outputs 4 and 20).
* say "auto detect"
* an "EPCS16" part should show up attached to the EP3.
* attach ppg.jic to the EPCS16 part
* select "program"
* say "start"
* observe progress bar go from 0 to 100% in about 2 minutes.
* PPG firmware is now loaded into the board
* cycle the power on the board to reboot into the PPG firmware
* when running the PPG firmware, all LEDs are off after reboot.

==== Update using VME flash programmer ====

(note: VME flash programmer interface does not work in ppg firmware version "1mar12").

* obtain the latest copy of srunner_vme (follow instructions here [[VME-NIMIO32#Firmware_update_procedure]]) (srunner_vme.cxx svn rev 214 or newer for jic support)
* ./srunner_vme_gef.exe -program -16 ppg.jic 0x100024
* reboot the PPG

(note: the above does not work: b) srunner_vme treats 0x10xxxx is an A24 address, but PPG firmware does not respond to A24 addresses; c) the active serial interface does not seem to work anyway)

(note: the reboot function is not available in the PPG firmware)

==== Update using VME flash programmer when running VME-PPG32-IO32 firmware ====

* ./test_VMENIMIO32_gef.exe --addr 0x100000 --read 0 ### to confirm VME-PPG32-IO32 firmware revision
* ./srunner_vme_gef.exe -program -16 ppg.jic 0x100020
* ./test_VMENIMIO32_gef.exe --addr 0x100000 --reboot ### PPG will stop responding
* ./test_a32.exe 0x100000 ### should read 0x00000000 (NOT 0xFFFFFFFF)

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || CSR || RW || Control/Status Register
|-
| 1 || 0x00004 || Test || RW || Test Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Inv_Mask || RW || Output Inversion Mask
|-
| 8 || 0x00020 || Version || R || Firmware Version Register
|-
| 9 || 0x00024 || Flash || RW || Serial Flash Control Register
|-
| 10 || 0x00028 || Serial || R || Serial Number Register
|-
| 11 || 0x0002C || Hardware || R || hardware Identification Register
|-
| 12 || 0x00030 || clock Control || RW || Clock Control Register
|}

===== CSR Register (0x00000) =====

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk-Toggle || W || Toggles between PPG external and internal Clk
|-
|2|| Ext-Start|| R/W || 1=Ext-PPG Start 0=Int-PPG Start
|-
|3|| PPG-Reset || R/W || 1=Reset 0=Normal operation
|-
|4|| Test-Mode || R/W || 1=Test Mode 0=Normal operation
|-
|16|| Ext-Clk-Sel || R || 1= External clock is selected 0 = Internal clock selected
|-
|17|| Ext-Clk good || R || 1= External clock is connected and is "good" 0= external clock not connected or is "bad"
|-
|?-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing an edge here toggles the ppg logic between the internal and external CLK (connected to Nim_Input[3]). The VME interface always uses the internal clock.
Note that the correct divide-down must be programmed unless external clock is the same frequency (i.e. 10MHz) as internal clock.

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start. (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[4])

Reset bit: Set bit to Reset PPG. Stops PPG pgm even if executing a long delay. Does NOT do a full reset to power-up condition. Bit must be cleared after Reset or module will not operate.

Test-Mode bit: Set bit to enable Test Mode. When Test Mode is enabled, inputs 1 and 2 become output the internal PPG clock and actual clock PPG is using, respectively. If internal clock is set, inputs 1 and 2 output identical clocks. If external clock is set, and the external clock is "good", input 1 will not change, but input 2 will show the external clock frequency.
If Test-Mode bit is cleared, Normal Mode is enabled, where inputs 1 and 2 act as regular inputs.

Ext-Clk-Sel: If bit is set, external clock is selected and LED 4 will be lit. If clear, internal clock is selected

Ext-Clk Good: If bit is set, external clock is connected to Nim_Input[3] and is "good". LED 2 will be lit. If clear, external clock is either not connected or is "bad".

===== Test Register (0x00004) =====

Simple Test Register - Value Written is preserved and can be read back.

===== Address Register (0x00008) =====

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address. Also in test-Mode, the NIM/LED outputs follow the state of this register.

===== Instruction Registers (0x0000C - 0x00018) =====

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

===== Output Inversion Mask (0x0001C) =====
32 individual inversion bits (1 per output) a 1 inverts the state of that output.

===== Firmware Version (0x00020) =====
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

===== Serial Flash Control (0x00024) =====
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

===== Serial Number (0x00028) =====
Returns the module serial number, and Board revision (if set) or 0xdead

===== hardware Type (0x0002C) =====
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

===== Clock Control (0x00030) =====
Set PLL parameters applied to external clock input. Default parameters are for 20Mhz External Clock, and multiply this by 5 to get 100Mhz ppg clock.

Register Contents as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 30-28 || Bits 26-24 || Bits 23-20 || Bits 16-8 || Bit 5 || Bit 4 || Bit 3 || Bit 2 || Bit 1 || Bit 0
|-
| Phase Counter Select || Counter Parameter || Counter Type || 9 bit Data || PLL Reset || Up/Down || PhaseStep || Write Parameter || reconfigure || Control Trigger
|-
|}

The Control Trigger Bit [bit 0] enables the four control signals in bits 1,2,3,5, and needs to be toggled from off to on, to apply these 4 signals.

On rising edge of control trigger ...
Phasestep=1 => clock phase is adjusted by 1 unit, in the direction selected by "Up/Down" [bit 4: 1=up,0=Down]
Write Parameter=1 => 9bit-Data, Counter-Type and Counter-Param are written into the PLL reconfiguration registers
Reconfigure=1 => PLL is reconfigured with the parameters currently in its reconfiguration registers
PLL-Reset=1 => PLL is reset

PhaseCounterSelect ...
0 => All Clocks
1 => M ?
2-6 => Clock 0-4

phasestep is applied immediately (to clocks selected by PhaseCounterSelect), and does not require a reconfiguration or reset.

The parameters below need to be written (with writeparameter=1), and then require a reconfiguration to be applied.

Counter-Type ...
0: N
1: M
2: Cp/LF
3: VCO
4-8: Clock 0-4
9-D: Clock 5-9 (Stratix Only)
E-F: Invalid

Counter-Parameter ...
0: HighCount
1: LowCount
4: Bypass
5: Mode Odd/Even

Clock frequencies are defined by ...
VCO Frequency = Fin * M/N
The individual clock outputs [clock0-4] are given by ... VCO / C0-C4

Each of M,N,C0-C4 are the sum of a high and low count.
Note - can get 50% duty cycle with odd count by setting mode=odd with high=low+1
Each counter can be bypassed by setting bypass=1 (=> Scale=1)

Limits etc ...
Fin = 5 - 472 Mhz
Fvco = 600 - 1300 Mhz
Lock Time < 1ms

Examples ...
For Fin = 20Mhz [defaults settings on pwerup]
if parameters have been changed - need to set

=== Front Panel ===

==== NIM Inputs ====

The Input assignments are (as labelled on front panel) ...
4 - External Start (Not fully tested yet) Needs to stay high (low => stop!)
3 - External Clock (20Mhz, internally scaled - 100Mhz)
2 - Unassigned
1 - Unassigned

==== Input LEDs ====

The Input LED assignments are (as labelled on front panel) ...
4 - Clock setting (Lit => External Clk)
3 - NimIn[2] status
2 - External Clock Good indicator (Lit => Clock is good)
1 - Program Running

=== Test Software ===

==== c-shell script to run 2 nested loops ====

set dec_hex=( 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 \
0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf \
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 \
0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f \
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 )

# dly4,loop4,dly3,loop6,dly2,end,end
set inst=( \
0xff 0x00 0x4 0x100000 0x0 0x0 0x0 0x200004 \
0x1 0x1 0x3 0x100000 0x0 0x0 0x0 0x200006 \
0x2 0x2 0x2 0x100000 0x0 0x0 0x0 0x300000 \
0x0 0x0 0x0 0x300000 0x0 0x0 0x0 0x000000 )

set i=0
set j=0
while( $i < $#inst )
@ j++; vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 $dec_hex[$j]
@ i++; vme_poke -a VME_A32UD -A 0x0010000c -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100010 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100014 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100018 -d VME_D32 $inst[$i]
end

# start program (from addr 0)...
vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100000 -d VME_D32 0x1

==== c-shell script to set divide-downs for 100MHz frequency ====

This would be used with an external frequency input of 100MHz

vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x00000305 # set hi counter to 3
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x01000205 # set lo counter to 2
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x05000105 # set mode counter to odd
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000005 # set counter bypass to 0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0

==== c-shell script to set divide-downs for 10MHz frequency ====

This would be used when returning to the internal frequency of 10MHz :

vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000105 # set counter bypass to 1
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3 # reconfig clock
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd

=== Procedure for newly assembled board startup and test ===

(note1: VME-PPG32-IO32 firmware is used to test the board)

(note2: TTL inputs and outputs are not tested)

(note3: DAC outputs are not tested)

(note4: shorts between NIM outputs are not tested)

* set VME address jumper A20-23 to "1", jumpers A24-27 and A28-31 to "0"
* set inputs and outputs to "NIM" mode
* connect JTAG USB blaster
* power up the board (standalone or in a VME crate)
* start Quartus programmer
* select correct USB blaster
* run "auto detect", 3 devices should be detected: EP3C20Q240 (Cyclone3 FPGA), EPM1270 (parallel flash loader CPLD), EPM3032AT44 (VME address decoder CPLD)
* flash the VME address decoder pof file into the EPM3032 part (get pof file from here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode/VME_Addr_decode.pof?view=log)
* (do not do this) flash the CFI parallel flash loader into the EPM1270 part (get pof file where?!?)
* load the VME-PPG32-IO32 firmware sof file into the EP3 part (get sof file here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.sof?view=log)
* run "vmescan_gef.exe", it should detect the IO32 board at A24 VME address 0x00100000, data should correspond to the sof file revision date code
* confirm VME access LED is working (flashes during vme scan).
* confirm VME Data bus is okey: "./test_VMENIMIO32_gef.exe --addr 0x100000 --testbits 4"
* (do not do this) follow the firmware update instructions to flash the firmware pof file using the VME flash programmer at [[VME-NIMIO32#Firmware_update_procedure]] (get VME-PPG32-IO32 pof file from here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.pof?view=log)
* (do not do this) confirm FPGA reboot is working - "./test_VMENIMIO32_gef.exe --addr 0x100000 --reboot" prints 0xFFFFFFFF on the second read of firmware revision
* test NIM inputs and LEDs: use NIM pulse generator or any NIM module inverted output, connect to each NIM input, observe that corresponding "green" LEDs is lighting up
* test NIM outputs and LEDs: "./test_VMENIMIO32_gef.exe --addr 0x100000 --nimout 3 1 --pulsenim", observe all "red" LEDs are flashing, connect NIM outputs to NIM scaler, observe scaler counts at each LED flash
* load PPG firmware into the active serial flash (follow instructions here: [[#Update_using_VME_flash_programmer_when_running_VME-PPG32-IO32_firmware]]
* unplug the board from VME, wait 10 sec, plug it back in, confirm that it is detected by vmescan if running VME-PPG32-IO32 firmware or test_a32 or PPG test tools if running the PPG firmware (confirms the flash memory contents is good)

=== VME-PPG32-IO32 firmware ===

The VME-PPG32 board can run a special version of VME-NIMIO32 firmware (subproject "PPG32-Rev1" of the VME-NIMIO32 firmware). For instructions, please refer to the [[VME-NIMIO32]] documentation.

VME-PPG32

2013-02-20T23:32:32Z

Cpearson: /* Clock Control (0x00030) */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [https://edev.triumf.ca/projects/edevel00022] VME-PPG32 Rev0 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/projects/edevel00067] VME-PPG32 Rev1 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/projects/edevel00125] VME-PPG32 Rev2 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/documents/27] Rev0 board schematics on edev site
* [https://edev.triumf.ca/documents/111] Rev1 board schematics on edev site
* [https://edev.triumf.ca/documents/158] Rev2 board schematics on edev site
* [[Image:VME-PPG32 Rev1.pdf]] Rev1 board schematics, local copy
* [[Image:VME-PPG32 Rev2.pdf]] Rev2 board schematics, local copy

VME-PPG32-IO32 firmware: (IO32 functions, no PPG functions)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32-Rev0] Svn repository for VME-PPG32-Rev0 initial test firmware (IO32 function only, no PPG function)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1] Svn repository for VME-PPG32-Rev1 firmware (IO32 function only, no PPG function)

VME-PPG32 VME CPLD firmware: (VME address decoder)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode] Svn repository for VME-PPG32 Rev0 and Rev1 VME address decoder CPLD (Altera EPM3032)

VME-PPG32 firmware: (PPG function)
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ
* Rev1 and Rev2 boards: inputs are switchable between NIM and TTL (JMP3)
* Rev2 boards: outputs are switchable between NIM and TTL (SW1 micro switches)

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input - see note 1)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

FPGA resource Usage : 1044 LE, 500 kbits Memory

Note 1 :
Some modules allow an external clock frequency of 20-100MHz . Divide-downs must be programmed where external clock frequency is not 20MHz.
Examples of divide-down programming is shown at end of this document.

=== Onboard jumper settings ===

* JMP1 - set to "INP" for input with 50 Ohm termination, set to "DAC" for DAC output
* JMP2 - set to "INP" same as JMP1
* JMP3 - set to "NIM" (pins 1-2) for NIM inputs or "TTL" (pins 2-3) for TTL inputs
* JMP4 - "MSEL1" jumper set to "ACT" for use with the active-serial flash
* IrqSel - leave open
* JTAG - leave open (not a jumper block!)
* SW1..3 - VME base address selectors (see below)

=== Firmware update procedure ===

(note1: right now the PPG firmware update procedure is unnecessary complicated because there is no ppg.pof file in the PPG firmware distribution version "1mar12" and the PPG firmware does not include the Altera active-serial programmer block.)

(note2: VME-PPG32-IO32 firmware (sof file) is required to update the PPG firmware)

* obtain the PPG firmware zip file (from http://daq-plone.triumf.ca/HR/VME/ppg32)
* extract the ppg.jic file
* obtain the VME-PPG32-IO32 sof file (VME-PPG32.sof) from https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.sof?view=log

==== Update using USB-Blaster and jic file ====

* use Quartus programmer to burn the jic file through the EP3 active-serial flash loader:
* start Quartus programmer (tools->programmer)
* say "auto detect" - EP3, EPM1270 and EPM3032A should be detected
* attach VME-PPG32.sof to the EP3 part (context menu "change file")
* select "program"
* say "start"
* observe that 2 "red" LEDs have turned on on the PPG board (40MHz clock on outputs 4 and 20).
* say "auto detect"
* an "EPCS16" part should show up attached to the EP3.
* attach ppg.jic to the EPCS16 part
* select "program"
* say "start"
* observe progress bar go from 0 to 100% in about 2 minutes.
* PPG firmware is now loaded into the board
* cycle the power on the board to reboot into the PPG firmware
* when running the PPG firmware, all LEDs are off after reboot.

==== Update using VME flash programmer ====

(note: VME flash programmer interface does not work in ppg firmware version "1mar12").

* obtain the latest copy of srunner_vme (follow instructions here [[VME-NIMIO32#Firmware_update_procedure]]) (srunner_vme.cxx svn rev 214 or newer for jic support)
* ./srunner_vme_gef.exe -program -16 ppg.jic 0x100024
* reboot the PPG

(note: the above does not work: b) srunner_vme treats 0x10xxxx is an A24 address, but PPG firmware does not respond to A24 addresses; c) the active serial interface does not seem to work anyway)

(note: the reboot function is not available in the PPG firmware)

==== Update using VME flash programmer when running VME-PPG32-IO32 firmware ====

* ./test_VMENIMIO32_gef.exe --addr 0x100000 --read 0 ### to confirm VME-PPG32-IO32 firmware revision
* ./srunner_vme_gef.exe -program -16 ppg.jic 0x100020
* ./test_VMENIMIO32_gef.exe --addr 0x100000 --reboot ### PPG will stop responding
* ./test_a32.exe 0x100000 ### should read 0x00000000 (NOT 0xFFFFFFFF)

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || CSR || RW || Control/Status Register
|-
| 1 || 0x00004 || Test || RW || Test Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Inv_Mask || RW || Output Inversion Mask
|-
| 8 || 0x00020 || Version || R || Firmware Version Register
|-
| 9 || 0x00024 || Flash || RW || Serial Flash Control Register
|-
| 10 || 0x00028 || Serial || R || Serial Number Register
|-
| 11 || 0x0002C || Hardware || R || hardware Identification Register
|-
| 12 || 0x00030 || clock Control || RW || Clock Control Register
|}

===== CSR Register (0x00000) =====

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk-Toggle || W || Toggles between PPG external and internal Clk
|-
|2|| Ext-Start|| R/W || 1=Ext-PPG Start 0=Int-PPG Start
|-
|3|| PPG-Reset || R/W || 1=Reset 0=Normal operation
|-
|4|| Test-Mode || R/W || 1=Test Mode 0=Normal operation
|-
|16|| Ext-Clk-Sel || R || 1= External clock is selected 0 = Internal clock selected
|-
|17|| Ext-Clk good || R || 1= External clock is connected and is "good" 0= external clock not connected or is "bad"
|-
|?-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing an edge here toggles the ppg logic between the internal and external CLK (connected to Nim_Input[3]). The VME interface always uses the internal clock.
Note that the correct divide-down must be programmed unless external clock is the same frequency (i.e. 10MHz) as internal clock.

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start. (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[4])

Reset bit: Set bit to Reset PPG. Stops PPG pgm even if executing a long delay. Does NOT do a full reset to power-up condition. Bit must be cleared after Reset or module will not operate.

Test-Mode bit: Set bit to enable Test Mode. When Test Mode is enabled, inputs 1 and 2 become output the internal PPG clock and actual clock PPG is using, respectively. If internal clock is set, inputs 1 and 2 output identical clocks. If external clock is set, and the external clock is "good", input 1 will not change, but input 2 will show the external clock frequency.
If Test-Mode bit is cleared, Normal Mode is enabled, where inputs 1 and 2 act as regular inputs.

Ext-Clk-Sel: If bit is set, external clock is selected and LED 4 will be lit. If clear, internal clock is selected

Ext-Clk Good: If bit is set, external clock is connected to Nim_Input[3] and is "good". LED 2 will be lit. If clear, external clock is either not connected or is "bad".

===== Test Register (0x00004) =====

Simple Test Register - Value Written is preserved and can be read back.

===== Address Register (0x00008) =====

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address. Also in test-Mode, the NIM/LED outputs follow the state of this register.

===== Instruction Registers (0x0000C - 0x00018) =====

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

===== Output Inversion Mask (0x0001C) =====
32 individual inversion bits (1 per output) a 1 inverts the state of that output.

===== Firmware Version (0x00020) =====
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

===== Serial Flash Control (0x00024) =====
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

===== Serial Number (0x00028) =====
Returns the module serial number, and Board revision (if set) or 0xdead

===== hardware Type (0x0002C) =====
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

===== Clock Control (0x00030) =====
Set PLL parameters applied to external clock input. Default parameters are for 20Mhz External Clock, and multiply this by 5 to get 100Mhz ppg clock.

Register Contents as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 30-28 || Bits 26-24 || Bits 23-20 || Bits 16-8 || Bit 5 || Bit 4 || Bit 3 || Bit 2 || Bit 1 || Bit 0
|-
| Phase Counter Select || Counter Parameter || Counter Type || 9 bit Data || PLL Reset || Up/Down || PhaseStep || Write Parameter || reconfigure || Control Trigger
|-
|}

The Control Trigger Bit [bit 0] enables the four control signals in bits 1,2,3,5, and needs to be toggled from off to on, to apply these 4 signals.

On rising edge of control trigger ...
Phasestep=1 => clock phase is adjusted by 1 unit, in the direction selected by "Up/Down" [bit 4: 1=up,0=Down]
Write Parameter=1 => 9bit-Data, Counter-Type and Counter-Param are written into the PLL reconfiguration registers
Reconfigure=1 => PLL is reconfigured with the parameters currently in its reconfiguration registers
PLL-Reset=1 => PLL is reset

PhaseCounterSelect ...
0 => All Clocks
1 => M ?
2-6 => Clock 0-4

phasestep is applied immediately (to clocks selected by PhaseCounterSelect), and does not require a reconfiguration or reset.

The parameters below need to be written (with writeparameter=1), and then require a reconfiguration to be applied.

Counter-Type ...
0: N
1: M
2: Cp/LF
3: VCO
4-8: Clock 0-4
9-D: Clock 5-9 (Stratix Only)
E-F: Invalid

Counter-Parameter ...
0: HighCount
1: LowCount
4: Bypass
5: Mode Odd/Even

Clock frequencies are defined by ...
VCO Frequency = Fin * M/N
The individual clock outputs [clock0-4] are given by ... VCO / C0-C4

Each of M,N,C0-C4 are the sum of a high and low count.
Note - can get 50% duty cycle with odd count by setting mode=odd with high=low+1
Each counter can be bypassed by setting bypass=1 (=> Scale=1)

Limits etc ...
Fin = 5 - 472 Mhz
Fvco = 600 - 1300 Mhz
Lock Time < 1ms

=== Front Panel ===

==== NIM Inputs ====

The Input assignments are (as labelled on front panel) ...
4 - External Start (Not fully tested yet) Needs to stay high (low => stop!)
3 - External Clock (20Mhz, internally scaled - 100Mhz)
2 - Unassigned
1 - Unassigned

==== Input LEDs ====

The Input LED assignments are (as labelled on front panel) ...
4 - Clock setting (Lit => External Clk)
3 - NimIn[2] status
2 - External Clock Good indicator (Lit => Clock is good)
1 - Program Running

=== Test Software ===

==== c-shell script to run 2 nested loops ====

set dec_hex=( 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 \
0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf \
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 \
0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f \
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 )

# dly4,loop4,dly3,loop6,dly2,end,end
set inst=( \
0xff 0x00 0x4 0x100000 0x0 0x0 0x0 0x200004 \
0x1 0x1 0x3 0x100000 0x0 0x0 0x0 0x200006 \
0x2 0x2 0x2 0x100000 0x0 0x0 0x0 0x300000 \
0x0 0x0 0x0 0x300000 0x0 0x0 0x0 0x000000 )

set i=0
set j=0
while( $i < $#inst )
@ j++; vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 $dec_hex[$j]
@ i++; vme_poke -a VME_A32UD -A 0x0010000c -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100010 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100014 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100018 -d VME_D32 $inst[$i]
end

# start program (from addr 0)...
vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100000 -d VME_D32 0x1

==== c-shell script to set divide-downs for 100MHz frequency ====

This would be used with an external frequency input of 100MHz

vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x00000305 # set hi counter to 3
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x01000205 # set lo counter to 2
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x05000105 # set mode counter to odd
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000005 # set counter bypass to 0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0

==== c-shell script to set divide-downs for 10MHz frequency ====

This would be used when returning to the internal frequency of 10MHz :

vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000105 # set counter bypass to 1
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3 # reconfig clock
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd

=== Procedure for newly assembled board startup and test ===

(note1: VME-PPG32-IO32 firmware is used to test the board)

(note2: TTL inputs and outputs are not tested)

(note3: DAC outputs are not tested)

(note4: shorts between NIM outputs are not tested)

* set VME address jumper A20-23 to "1", jumpers A24-27 and A28-31 to "0"
* set inputs and outputs to "NIM" mode
* connect JTAG USB blaster
* power up the board (standalone or in a VME crate)
* start Quartus programmer
* select correct USB blaster
* run "auto detect", 3 devices should be detected: EP3C20Q240 (Cyclone3 FPGA), EPM1270 (parallel flash loader CPLD), EPM3032AT44 (VME address decoder CPLD)
* flash the VME address decoder pof file into the EPM3032 part (get pof file from here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode/VME_Addr_decode.pof?view=log)
* (do not do this) flash the CFI parallel flash loader into the EPM1270 part (get pof file where?!?)
* load the VME-PPG32-IO32 firmware sof file into the EP3 part (get sof file here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.sof?view=log)
* run "vmescan_gef.exe", it should detect the IO32 board at A24 VME address 0x00100000, data should correspond to the sof file revision date code
* confirm VME access LED is working (flashes during vme scan).
* confirm VME Data bus is okey: "./test_VMENIMIO32_gef.exe --addr 0x100000 --testbits 4"
* (do not do this) follow the firmware update instructions to flash the firmware pof file using the VME flash programmer at [[VME-NIMIO32#Firmware_update_procedure]] (get VME-PPG32-IO32 pof file from here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.pof?view=log)
* (do not do this) confirm FPGA reboot is working - "./test_VMENIMIO32_gef.exe --addr 0x100000 --reboot" prints 0xFFFFFFFF on the second read of firmware revision
* test NIM inputs and LEDs: use NIM pulse generator or any NIM module inverted output, connect to each NIM input, observe that corresponding "green" LEDs is lighting up
* test NIM outputs and LEDs: "./test_VMENIMIO32_gef.exe --addr 0x100000 --nimout 3 1 --pulsenim", observe all "red" LEDs are flashing, connect NIM outputs to NIM scaler, observe scaler counts at each LED flash
* load PPG firmware into the active serial flash (follow instructions here: [[#Update_using_VME_flash_programmer_when_running_VME-PPG32-IO32_firmware]]
* unplug the board from VME, wait 10 sec, plug it back in, confirm that it is detected by vmescan if running VME-PPG32-IO32 firmware or test_a32 or PPG test tools if running the PPG firmware (confirms the flash memory contents is good)

=== VME-PPG32-IO32 firmware ===

The VME-PPG32 board can run a special version of VME-NIMIO32 firmware (subproject "PPG32-Rev1" of the VME-NIMIO32 firmware). For instructions, please refer to the [[VME-NIMIO32]] documentation.

VME-PPG32

2013-02-20T23:22:30Z

Cpearson: /* Clock Control (0x00030) */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [https://edev.triumf.ca/projects/edevel00022] VME-PPG32 Rev0 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/projects/edevel00067] VME-PPG32 Rev1 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/projects/edevel00125] VME-PPG32 Rev2 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/documents/27] Rev0 board schematics on edev site
* [https://edev.triumf.ca/documents/111] Rev1 board schematics on edev site
* [https://edev.triumf.ca/documents/158] Rev2 board schematics on edev site
* [[Image:VME-PPG32 Rev1.pdf]] Rev1 board schematics, local copy
* [[Image:VME-PPG32 Rev2.pdf]] Rev2 board schematics, local copy

VME-PPG32-IO32 firmware: (IO32 functions, no PPG functions)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32-Rev0] Svn repository for VME-PPG32-Rev0 initial test firmware (IO32 function only, no PPG function)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1] Svn repository for VME-PPG32-Rev1 firmware (IO32 function only, no PPG function)

VME-PPG32 VME CPLD firmware: (VME address decoder)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode] Svn repository for VME-PPG32 Rev0 and Rev1 VME address decoder CPLD (Altera EPM3032)

VME-PPG32 firmware: (PPG function)
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ
* Rev1 and Rev2 boards: inputs are switchable between NIM and TTL (JMP3)
* Rev2 boards: outputs are switchable between NIM and TTL (SW1 micro switches)

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input - see note 1)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

FPGA resource Usage : 1044 LE, 500 kbits Memory

Note 1 :
Some modules allow an external clock frequency of 20-100MHz . Divide-downs must be programmed where external clock frequency is not 20MHz.
Examples of divide-down programming is shown at end of this document.

=== Onboard jumper settings ===

* JMP1 - set to "INP" for input with 50 Ohm termination, set to "DAC" for DAC output
* JMP2 - set to "INP" same as JMP1
* JMP3 - set to "NIM" (pins 1-2) for NIM inputs or "TTL" (pins 2-3) for TTL inputs
* JMP4 - "MSEL1" jumper set to "ACT" for use with the active-serial flash
* IrqSel - leave open
* JTAG - leave open (not a jumper block!)
* SW1..3 - VME base address selectors (see below)

=== Firmware update procedure ===

(note1: right now the PPG firmware update procedure is unnecessary complicated because there is no ppg.pof file in the PPG firmware distribution version "1mar12" and the PPG firmware does not include the Altera active-serial programmer block.)

(note2: VME-PPG32-IO32 firmware (sof file) is required to update the PPG firmware)

* obtain the PPG firmware zip file (from http://daq-plone.triumf.ca/HR/VME/ppg32)
* extract the ppg.jic file
* obtain the VME-PPG32-IO32 sof file (VME-PPG32.sof) from https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.sof?view=log

==== Update using USB-Blaster and jic file ====

* use Quartus programmer to burn the jic file through the EP3 active-serial flash loader:
* start Quartus programmer (tools->programmer)
* say "auto detect" - EP3, EPM1270 and EPM3032A should be detected
* attach VME-PPG32.sof to the EP3 part (context menu "change file")
* select "program"
* say "start"
* observe that 2 "red" LEDs have turned on on the PPG board (40MHz clock on outputs 4 and 20).
* say "auto detect"
* an "EPCS16" part should show up attached to the EP3.
* attach ppg.jic to the EPCS16 part
* select "program"
* say "start"
* observe progress bar go from 0 to 100% in about 2 minutes.
* PPG firmware is now loaded into the board
* cycle the power on the board to reboot into the PPG firmware
* when running the PPG firmware, all LEDs are off after reboot.

==== Update using VME flash programmer ====

(note: VME flash programmer interface does not work in ppg firmware version "1mar12").

* obtain the latest copy of srunner_vme (follow instructions here [[VME-NIMIO32#Firmware_update_procedure]]) (srunner_vme.cxx svn rev 214 or newer for jic support)
* ./srunner_vme_gef.exe -program -16 ppg.jic 0x100024
* reboot the PPG

(note: the above does not work: b) srunner_vme treats 0x10xxxx is an A24 address, but PPG firmware does not respond to A24 addresses; c) the active serial interface does not seem to work anyway)

(note: the reboot function is not available in the PPG firmware)

==== Update using VME flash programmer when running VME-PPG32-IO32 firmware ====

* ./test_VMENIMIO32_gef.exe --addr 0x100000 --read 0 ### to confirm VME-PPG32-IO32 firmware revision
* ./srunner_vme_gef.exe -program -16 ppg.jic 0x100020
* ./test_VMENIMIO32_gef.exe --addr 0x100000 --reboot ### PPG will stop responding
* ./test_a32.exe 0x100000 ### should read 0x00000000 (NOT 0xFFFFFFFF)

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || CSR || RW || Control/Status Register
|-
| 1 || 0x00004 || Test || RW || Test Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Inv_Mask || RW || Output Inversion Mask
|-
| 8 || 0x00020 || Version || R || Firmware Version Register
|-
| 9 || 0x00024 || Flash || RW || Serial Flash Control Register
|-
| 10 || 0x00028 || Serial || R || Serial Number Register
|-
| 11 || 0x0002C || Hardware || R || hardware Identification Register
|-
| 12 || 0x00030 || clock Control || RW || Clock Control Register
|}

===== CSR Register (0x00000) =====

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk-Toggle || W || Toggles between PPG external and internal Clk
|-
|2|| Ext-Start|| R/W || 1=Ext-PPG Start 0=Int-PPG Start
|-
|3|| PPG-Reset || R/W || 1=Reset 0=Normal operation
|-
|4|| Test-Mode || R/W || 1=Test Mode 0=Normal operation
|-
|16|| Ext-Clk-Sel || R || 1= External clock is selected 0 = Internal clock selected
|-
|17|| Ext-Clk good || R || 1= External clock is connected and is "good" 0= external clock not connected or is "bad"
|-
|?-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing an edge here toggles the ppg logic between the internal and external CLK (connected to Nim_Input[3]). The VME interface always uses the internal clock.
Note that the correct divide-down must be programmed unless external clock is the same frequency (i.e. 10MHz) as internal clock.

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start. (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[4])

Reset bit: Set bit to Reset PPG. Stops PPG pgm even if executing a long delay. Does NOT do a full reset to power-up condition. Bit must be cleared after Reset or module will not operate.

Test-Mode bit: Set bit to enable Test Mode. When Test Mode is enabled, inputs 1 and 2 become output the internal PPG clock and actual clock PPG is using, respectively. If internal clock is set, inputs 1 and 2 output identical clocks. If external clock is set, and the external clock is "good", input 1 will not change, but input 2 will show the external clock frequency.
If Test-Mode bit is cleared, Normal Mode is enabled, where inputs 1 and 2 act as regular inputs.

Ext-Clk-Sel: If bit is set, external clock is selected and LED 4 will be lit. If clear, internal clock is selected

Ext-Clk Good: If bit is set, external clock is connected to Nim_Input[3] and is "good". LED 2 will be lit. If clear, external clock is either not connected or is "bad".

===== Test Register (0x00004) =====

Simple Test Register - Value Written is preserved and can be read back.

===== Address Register (0x00008) =====

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address. Also in test-Mode, the NIM/LED outputs follow the state of this register.

===== Instruction Registers (0x0000C - 0x00018) =====

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

===== Output Inversion Mask (0x0001C) =====
32 individual inversion bits (1 per output) a 1 inverts the state of that output.

===== Firmware Version (0x00020) =====
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

===== Serial Flash Control (0x00024) =====
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

===== Serial Number (0x00028) =====
Returns the module serial number, and Board revision (if set) or 0xdead

===== hardware Type (0x0002C) =====
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

===== Clock Control (0x00030) =====
Set PLL parameters applied to external clock input. Default parameters are for 20Mhz External Clock, and multiply this by 5 to get 100Mhz ppg clock.

Register Contents as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 30-28 || Bits 26-24 || Bits 23-20 || Bits 16-8 || Bit 5 || Bit 4 || Bit 3 || Bit 2 || Bit 1 || Bit 0
|-
| Phase Counter Select || Counter Parameter || Counter Type || 9 bit Data || PLL Reset || Up/Down || PhaseStep || Write Parameter || reconfigure || Control Trigger
|-
|}

The Control Trigger Bit [bit 0] enables the four control signals in bits 1,2,3,5, and needs to be toggled from off to on, to apply these 4 signals.

On rising edge of control trigger ...
Phasestep=1 => clock phase is adjusted by 1 unit, in the direction selected by "Up/Down" [bit 4: 1=up,0=Down]
Write Parameter=1 => 9bit-Data, Counter-Type and Counter-Param are written into the PLL reconfiguration registers
Reconfigure=1 => PLL is reconfigured with the parameters currently in its reconfiguration registers
PLL-Reset=1 => PLL is reset

PhaseCounterSelect ...
0 => All Clocks
1 => M ?
2-6 => Clock 0-4

Counter-Type ...
0: N
1: M
2: Cp/LF
3: VCO
4-8: Clock 0-4
9-D: Clock 5-9 (Stratix Only)
E-F: Invalid

Counter-Parameter ...
0: HighCount
1: LowCount
4: Bypass
5: Mode Odd/Even

=== Front Panel ===

==== NIM Inputs ====

The Input assignments are (as labelled on front panel) ...
4 - External Start (Not fully tested yet) Needs to stay high (low => stop!)
3 - External Clock (20Mhz, internally scaled - 100Mhz)
2 - Unassigned
1 - Unassigned

==== Input LEDs ====

The Input LED assignments are (as labelled on front panel) ...
4 - Clock setting (Lit => External Clk)
3 - NimIn[2] status
2 - External Clock Good indicator (Lit => Clock is good)
1 - Program Running

=== Test Software ===

==== c-shell script to run 2 nested loops ====

set dec_hex=( 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 \
0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf \
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 \
0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f \
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 )

# dly4,loop4,dly3,loop6,dly2,end,end
set inst=( \
0xff 0x00 0x4 0x100000 0x0 0x0 0x0 0x200004 \
0x1 0x1 0x3 0x100000 0x0 0x0 0x0 0x200006 \
0x2 0x2 0x2 0x100000 0x0 0x0 0x0 0x300000 \
0x0 0x0 0x0 0x300000 0x0 0x0 0x0 0x000000 )

set i=0
set j=0
while( $i < $#inst )
@ j++; vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 $dec_hex[$j]
@ i++; vme_poke -a VME_A32UD -A 0x0010000c -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100010 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100014 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100018 -d VME_D32 $inst[$i]
end

# start program (from addr 0)...
vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100000 -d VME_D32 0x1

==== c-shell script to set divide-downs for 100MHz frequency ====

This would be used with an external frequency input of 100MHz

vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x00000305 # set hi counter to 3
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x01000205 # set lo counter to 2
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x05000105 # set mode counter to odd
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000005 # set counter bypass to 0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0

==== c-shell script to set divide-downs for 10MHz frequency ====

This would be used when returning to the internal frequency of 10MHz :

vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000105 # set counter bypass to 1
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3 # reconfig clock
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd

=== Procedure for newly assembled board startup and test ===

(note1: VME-PPG32-IO32 firmware is used to test the board)

(note2: TTL inputs and outputs are not tested)

(note3: DAC outputs are not tested)

(note4: shorts between NIM outputs are not tested)

* set VME address jumper A20-23 to "1", jumpers A24-27 and A28-31 to "0"
* set inputs and outputs to "NIM" mode
* connect JTAG USB blaster
* power up the board (standalone or in a VME crate)
* start Quartus programmer
* select correct USB blaster
* run "auto detect", 3 devices should be detected: EP3C20Q240 (Cyclone3 FPGA), EPM1270 (parallel flash loader CPLD), EPM3032AT44 (VME address decoder CPLD)
* flash the VME address decoder pof file into the EPM3032 part (get pof file from here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode/VME_Addr_decode.pof?view=log)
* (do not do this) flash the CFI parallel flash loader into the EPM1270 part (get pof file where?!?)
* load the VME-PPG32-IO32 firmware sof file into the EP3 part (get sof file here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.sof?view=log)
* run "vmescan_gef.exe", it should detect the IO32 board at A24 VME address 0x00100000, data should correspond to the sof file revision date code
* confirm VME access LED is working (flashes during vme scan).
* confirm VME Data bus is okey: "./test_VMENIMIO32_gef.exe --addr 0x100000 --testbits 4"
* (do not do this) follow the firmware update instructions to flash the firmware pof file using the VME flash programmer at [[VME-NIMIO32#Firmware_update_procedure]] (get VME-PPG32-IO32 pof file from here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.pof?view=log)
* (do not do this) confirm FPGA reboot is working - "./test_VMENIMIO32_gef.exe --addr 0x100000 --reboot" prints 0xFFFFFFFF on the second read of firmware revision
* test NIM inputs and LEDs: use NIM pulse generator or any NIM module inverted output, connect to each NIM input, observe that corresponding "green" LEDs is lighting up
* test NIM outputs and LEDs: "./test_VMENIMIO32_gef.exe --addr 0x100000 --nimout 3 1 --pulsenim", observe all "red" LEDs are flashing, connect NIM outputs to NIM scaler, observe scaler counts at each LED flash
* load PPG firmware into the active serial flash (follow instructions here: [[#Update_using_VME_flash_programmer_when_running_VME-PPG32-IO32_firmware]]
* unplug the board from VME, wait 10 sec, plug it back in, confirm that it is detected by vmescan if running VME-PPG32-IO32 firmware or test_a32 or PPG test tools if running the PPG firmware (confirms the flash memory contents is good)

=== VME-PPG32-IO32 firmware ===

The VME-PPG32 board can run a special version of VME-NIMIO32 firmware (subproject "PPG32-Rev1" of the VME-NIMIO32 firmware). For instructions, please refer to the [[VME-NIMIO32]] documentation.

VME-PPG32

2013-02-20T23:06:53Z

Cpearson: /* Clock Control (0x00030) */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [https://edev.triumf.ca/projects/edevel00022] VME-PPG32 Rev0 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/projects/edevel00067] VME-PPG32 Rev1 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/projects/edevel00125] VME-PPG32 Rev2 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/documents/27] Rev0 board schematics on edev site
* [https://edev.triumf.ca/documents/111] Rev1 board schematics on edev site
* [https://edev.triumf.ca/documents/158] Rev2 board schematics on edev site
* [[Image:VME-PPG32 Rev1.pdf]] Rev1 board schematics, local copy
* [[Image:VME-PPG32 Rev2.pdf]] Rev2 board schematics, local copy

VME-PPG32-IO32 firmware: (IO32 functions, no PPG functions)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32-Rev0] Svn repository for VME-PPG32-Rev0 initial test firmware (IO32 function only, no PPG function)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1] Svn repository for VME-PPG32-Rev1 firmware (IO32 function only, no PPG function)

VME-PPG32 VME CPLD firmware: (VME address decoder)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode] Svn repository for VME-PPG32 Rev0 and Rev1 VME address decoder CPLD (Altera EPM3032)

VME-PPG32 firmware: (PPG function)
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ
* Rev1 and Rev2 boards: inputs are switchable between NIM and TTL (JMP3)
* Rev2 boards: outputs are switchable between NIM and TTL (SW1 micro switches)

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input - see note 1)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

FPGA resource Usage : 1044 LE, 500 kbits Memory

Note 1 :
Some modules allow an external clock frequency of 20-100MHz . Divide-downs must be programmed where external clock frequency is not 20MHz.
Examples of divide-down programming is shown at end of this document.

=== Onboard jumper settings ===

* JMP1 - set to "INP" for input with 50 Ohm termination, set to "DAC" for DAC output
* JMP2 - set to "INP" same as JMP1
* JMP3 - set to "NIM" (pins 1-2) for NIM inputs or "TTL" (pins 2-3) for TTL inputs
* JMP4 - "MSEL1" jumper set to "ACT" for use with the active-serial flash
* IrqSel - leave open
* JTAG - leave open (not a jumper block!)
* SW1..3 - VME base address selectors (see below)

=== Firmware update procedure ===

(note1: right now the PPG firmware update procedure is unnecessary complicated because there is no ppg.pof file in the PPG firmware distribution version "1mar12" and the PPG firmware does not include the Altera active-serial programmer block.)

(note2: VME-PPG32-IO32 firmware (sof file) is required to update the PPG firmware)

* obtain the PPG firmware zip file (from http://daq-plone.triumf.ca/HR/VME/ppg32)
* extract the ppg.jic file
* obtain the VME-PPG32-IO32 sof file (VME-PPG32.sof) from https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.sof?view=log

==== Update using USB-Blaster and jic file ====

* use Quartus programmer to burn the jic file through the EP3 active-serial flash loader:
* start Quartus programmer (tools->programmer)
* say "auto detect" - EP3, EPM1270 and EPM3032A should be detected
* attach VME-PPG32.sof to the EP3 part (context menu "change file")
* select "program"
* say "start"
* observe that 2 "red" LEDs have turned on on the PPG board (40MHz clock on outputs 4 and 20).
* say "auto detect"
* an "EPCS16" part should show up attached to the EP3.
* attach ppg.jic to the EPCS16 part
* select "program"
* say "start"
* observe progress bar go from 0 to 100% in about 2 minutes.
* PPG firmware is now loaded into the board
* cycle the power on the board to reboot into the PPG firmware
* when running the PPG firmware, all LEDs are off after reboot.

==== Update using VME flash programmer ====

(note: VME flash programmer interface does not work in ppg firmware version "1mar12").

* obtain the latest copy of srunner_vme (follow instructions here [[VME-NIMIO32#Firmware_update_procedure]]) (srunner_vme.cxx svn rev 214 or newer for jic support)
* ./srunner_vme_gef.exe -program -16 ppg.jic 0x100024
* reboot the PPG

(note: the above does not work: b) srunner_vme treats 0x10xxxx is an A24 address, but PPG firmware does not respond to A24 addresses; c) the active serial interface does not seem to work anyway)

(note: the reboot function is not available in the PPG firmware)

==== Update using VME flash programmer when running VME-PPG32-IO32 firmware ====

* ./test_VMENIMIO32_gef.exe --addr 0x100000 --read 0 ### to confirm VME-PPG32-IO32 firmware revision
* ./srunner_vme_gef.exe -program -16 ppg.jic 0x100020
* ./test_VMENIMIO32_gef.exe --addr 0x100000 --reboot ### PPG will stop responding
* ./test_a32.exe 0x100000 ### should read 0x00000000 (NOT 0xFFFFFFFF)

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || CSR || RW || Control/Status Register
|-
| 1 || 0x00004 || Test || RW || Test Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Inv_Mask || RW || Output Inversion Mask
|-
| 8 || 0x00020 || Version || R || Firmware Version Register
|-
| 9 || 0x00024 || Flash || RW || Serial Flash Control Register
|-
| 10 || 0x00028 || Serial || R || Serial Number Register
|-
| 11 || 0x0002C || Hardware || R || hardware Identification Register
|-
| 12 || 0x00030 || clock Control || RW || Clock Control Register
|}

===== CSR Register (0x00000) =====

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk-Toggle || W || Toggles between PPG external and internal Clk
|-
|2|| Ext-Start|| R/W || 1=Ext-PPG Start 0=Int-PPG Start
|-
|3|| PPG-Reset || R/W || 1=Reset 0=Normal operation
|-
|4|| Test-Mode || R/W || 1=Test Mode 0=Normal operation
|-
|16|| Ext-Clk-Sel || R || 1= External clock is selected 0 = Internal clock selected
|-
|17|| Ext-Clk good || R || 1= External clock is connected and is "good" 0= external clock not connected or is "bad"
|-
|?-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing an edge here toggles the ppg logic between the internal and external CLK (connected to Nim_Input[3]). The VME interface always uses the internal clock.
Note that the correct divide-down must be programmed unless external clock is the same frequency (i.e. 10MHz) as internal clock.

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start. (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[4])

Reset bit: Set bit to Reset PPG. Stops PPG pgm even if executing a long delay. Does NOT do a full reset to power-up condition. Bit must be cleared after Reset or module will not operate.

Test-Mode bit: Set bit to enable Test Mode. When Test Mode is enabled, inputs 1 and 2 become output the internal PPG clock and actual clock PPG is using, respectively. If internal clock is set, inputs 1 and 2 output identical clocks. If external clock is set, and the external clock is "good", input 1 will not change, but input 2 will show the external clock frequency.
If Test-Mode bit is cleared, Normal Mode is enabled, where inputs 1 and 2 act as regular inputs.

Ext-Clk-Sel: If bit is set, external clock is selected and LED 4 will be lit. If clear, internal clock is selected

Ext-Clk Good: If bit is set, external clock is connected to Nim_Input[3] and is "good". LED 2 will be lit. If clear, external clock is either not connected or is "bad".

===== Test Register (0x00004) =====

Simple Test Register - Value Written is preserved and can be read back.

===== Address Register (0x00008) =====

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address. Also in test-Mode, the NIM/LED outputs follow the state of this register.

===== Instruction Registers (0x0000C - 0x00018) =====

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

===== Output Inversion Mask (0x0001C) =====
32 individual inversion bits (1 per output) a 1 inverts the state of that output.

===== Firmware Version (0x00020) =====
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

===== Serial Flash Control (0x00024) =====
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

===== Serial Number (0x00028) =====
Returns the module serial number, and Board revision (if set) or 0xdead

===== hardware Type (0x0002C) =====
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

===== Clock Control (0x00030) =====
Set PLL parameters applied to external clock input. Default parameters are for 20Mhz External Clock, and multiply this by 5 to get 100Mhz ppg clock.

Register Contents as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 30-28 || Bits 26-24 || Bits 23-20 || Bits 16-8 || Bit 5 || Bit 4 || Bit 3 || Bit 2 || Bit 1 || Bit 0
|-
| Phase Counter Select || Counter Parameter || Counter Type || 9 bit Data || PLL Reset || Up/Down || PhaseStep || Write Parameter || reconfigure || Control Trigger
|-
|}

The Control Trigger Bit [bit 0] enables the four control signals in bits 1,2,3,5, and needs to be toggled from off to on, to apply these 4 signals.

On rising edge of control trigger ...
Phasestep=1 => clock phase is adjusted by 1 unit, in the direction selected by "Up/Down" [bit 4]
Write Parameter=1 => 9bit-Data, Counter-Type and Counter-Param are written into the PLL reconfiguration registers
Reconfigure=1 => PLL is reconfigured with the parameters currently in its reconfiguration registers
PLL-Reset=1 => PLL is reset

=== Front Panel ===

==== NIM Inputs ====

The Input assignments are (as labelled on front panel) ...
4 - External Start (Not fully tested yet) Needs to stay high (low => stop!)
3 - External Clock (20Mhz, internally scaled - 100Mhz)
2 - Unassigned
1 - Unassigned

==== Input LEDs ====

The Input LED assignments are (as labelled on front panel) ...
4 - Clock setting (Lit => External Clk)
3 - NimIn[2] status
2 - External Clock Good indicator (Lit => Clock is good)
1 - Program Running

=== Test Software ===

==== c-shell script to run 2 nested loops ====

set dec_hex=( 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 \
0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf \
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 \
0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f \
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 )

# dly4,loop4,dly3,loop6,dly2,end,end
set inst=( \
0xff 0x00 0x4 0x100000 0x0 0x0 0x0 0x200004 \
0x1 0x1 0x3 0x100000 0x0 0x0 0x0 0x200006 \
0x2 0x2 0x2 0x100000 0x0 0x0 0x0 0x300000 \
0x0 0x0 0x0 0x300000 0x0 0x0 0x0 0x000000 )

set i=0
set j=0
while( $i < $#inst )
@ j++; vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 $dec_hex[$j]
@ i++; vme_poke -a VME_A32UD -A 0x0010000c -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100010 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100014 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100018 -d VME_D32 $inst[$i]
end

# start program (from addr 0)...
vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100000 -d VME_D32 0x1

==== c-shell script to set divide-downs for 100MHz frequency ====

This would be used with an external frequency input of 100MHz

vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x00000305 # set hi counter to 3
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x01000205 # set lo counter to 2
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x05000105 # set mode counter to odd
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000005 # set counter bypass to 0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0

==== c-shell script to set divide-downs for 10MHz frequency ====

This would be used when returning to the internal frequency of 10MHz :

vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000105 # set counter bypass to 1
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3 # reconfig clock
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd

=== Procedure for newly assembled board startup and test ===

(note1: VME-PPG32-IO32 firmware is used to test the board)

(note2: TTL inputs and outputs are not tested)

(note3: DAC outputs are not tested)

(note4: shorts between NIM outputs are not tested)

* set VME address jumper A20-23 to "1", jumpers A24-27 and A28-31 to "0"
* set inputs and outputs to "NIM" mode
* connect JTAG USB blaster
* power up the board (standalone or in a VME crate)
* start Quartus programmer
* select correct USB blaster
* run "auto detect", 3 devices should be detected: EP3C20Q240 (Cyclone3 FPGA), EPM1270 (parallel flash loader CPLD), EPM3032AT44 (VME address decoder CPLD)
* flash the VME address decoder pof file into the EPM3032 part (get pof file from here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode/VME_Addr_decode.pof?view=log)
* (do not do this) flash the CFI parallel flash loader into the EPM1270 part (get pof file where?!?)
* load the VME-PPG32-IO32 firmware sof file into the EP3 part (get sof file here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.sof?view=log)
* run "vmescan_gef.exe", it should detect the IO32 board at A24 VME address 0x00100000, data should correspond to the sof file revision date code
* confirm VME access LED is working (flashes during vme scan).
* confirm VME Data bus is okey: "./test_VMENIMIO32_gef.exe --addr 0x100000 --testbits 4"
* (do not do this) follow the firmware update instructions to flash the firmware pof file using the VME flash programmer at [[VME-NIMIO32#Firmware_update_procedure]] (get VME-PPG32-IO32 pof file from here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.pof?view=log)
* (do not do this) confirm FPGA reboot is working - "./test_VMENIMIO32_gef.exe --addr 0x100000 --reboot" prints 0xFFFFFFFF on the second read of firmware revision
* test NIM inputs and LEDs: use NIM pulse generator or any NIM module inverted output, connect to each NIM input, observe that corresponding "green" LEDs is lighting up
* test NIM outputs and LEDs: "./test_VMENIMIO32_gef.exe --addr 0x100000 --nimout 3 1 --pulsenim", observe all "red" LEDs are flashing, connect NIM outputs to NIM scaler, observe scaler counts at each LED flash
* load PPG firmware into the active serial flash (follow instructions here: [[#Update_using_VME_flash_programmer_when_running_VME-PPG32-IO32_firmware]]
* unplug the board from VME, wait 10 sec, plug it back in, confirm that it is detected by vmescan if running VME-PPG32-IO32 firmware or test_a32 or PPG test tools if running the PPG firmware (confirms the flash memory contents is good)

=== VME-PPG32-IO32 firmware ===

The VME-PPG32 board can run a special version of VME-NIMIO32 firmware (subproject "PPG32-Rev1" of the VME-NIMIO32 firmware). For instructions, please refer to the [[VME-NIMIO32]] documentation.

VME-PPG32

2013-02-20T22:48:33Z

Cpearson: /* Registers */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [https://edev.triumf.ca/projects/edevel00022] VME-PPG32 Rev0 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/projects/edevel00067] VME-PPG32 Rev1 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/projects/edevel00125] VME-PPG32 Rev2 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/documents/27] Rev0 board schematics on edev site
* [https://edev.triumf.ca/documents/111] Rev1 board schematics on edev site
* [https://edev.triumf.ca/documents/158] Rev2 board schematics on edev site
* [[Image:VME-PPG32 Rev1.pdf]] Rev1 board schematics, local copy
* [[Image:VME-PPG32 Rev2.pdf]] Rev2 board schematics, local copy

VME-PPG32-IO32 firmware: (IO32 functions, no PPG functions)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32-Rev0] Svn repository for VME-PPG32-Rev0 initial test firmware (IO32 function only, no PPG function)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1] Svn repository for VME-PPG32-Rev1 firmware (IO32 function only, no PPG function)

VME-PPG32 VME CPLD firmware: (VME address decoder)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode] Svn repository for VME-PPG32 Rev0 and Rev1 VME address decoder CPLD (Altera EPM3032)

VME-PPG32 firmware: (PPG function)
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ
* Rev1 and Rev2 boards: inputs are switchable between NIM and TTL (JMP3)
* Rev2 boards: outputs are switchable between NIM and TTL (SW1 micro switches)

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input - see note 1)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

FPGA resource Usage : 1044 LE, 500 kbits Memory

Note 1 :
Some modules allow an external clock frequency of 20-100MHz . Divide-downs must be programmed where external clock frequency is not 20MHz.
Examples of divide-down programming is shown at end of this document.

=== Onboard jumper settings ===

* JMP1 - set to "INP" for input with 50 Ohm termination, set to "DAC" for DAC output
* JMP2 - set to "INP" same as JMP1
* JMP3 - set to "NIM" (pins 1-2) for NIM inputs or "TTL" (pins 2-3) for TTL inputs
* JMP4 - "MSEL1" jumper set to "ACT" for use with the active-serial flash
* IrqSel - leave open
* JTAG - leave open (not a jumper block!)
* SW1..3 - VME base address selectors (see below)

=== Firmware update procedure ===

(note1: right now the PPG firmware update procedure is unnecessary complicated because there is no ppg.pof file in the PPG firmware distribution version "1mar12" and the PPG firmware does not include the Altera active-serial programmer block.)

(note2: VME-PPG32-IO32 firmware (sof file) is required to update the PPG firmware)

* obtain the PPG firmware zip file (from http://daq-plone.triumf.ca/HR/VME/ppg32)
* extract the ppg.jic file
* obtain the VME-PPG32-IO32 sof file (VME-PPG32.sof) from https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.sof?view=log

==== Update using USB-Blaster and jic file ====

* use Quartus programmer to burn the jic file through the EP3 active-serial flash loader:
* start Quartus programmer (tools->programmer)
* say "auto detect" - EP3, EPM1270 and EPM3032A should be detected
* attach VME-PPG32.sof to the EP3 part (context menu "change file")
* select "program"
* say "start"
* observe that 2 "red" LEDs have turned on on the PPG board (40MHz clock on outputs 4 and 20).
* say "auto detect"
* an "EPCS16" part should show up attached to the EP3.
* attach ppg.jic to the EPCS16 part
* select "program"
* say "start"
* observe progress bar go from 0 to 100% in about 2 minutes.
* PPG firmware is now loaded into the board
* cycle the power on the board to reboot into the PPG firmware
* when running the PPG firmware, all LEDs are off after reboot.

==== Update using VME flash programmer ====

(note: VME flash programmer interface does not work in ppg firmware version "1mar12").

* obtain the latest copy of srunner_vme (follow instructions here [[VME-NIMIO32#Firmware_update_procedure]]) (srunner_vme.cxx svn rev 214 or newer for jic support)
* ./srunner_vme_gef.exe -program -16 ppg.jic 0x100024
* reboot the PPG

(note: the above does not work: b) srunner_vme treats 0x10xxxx is an A24 address, but PPG firmware does not respond to A24 addresses; c) the active serial interface does not seem to work anyway)

(note: the reboot function is not available in the PPG firmware)

==== Update using VME flash programmer when running VME-PPG32-IO32 firmware ====

* ./test_VMENIMIO32_gef.exe --addr 0x100000 --read 0 ### to confirm VME-PPG32-IO32 firmware revision
* ./srunner_vme_gef.exe -program -16 ppg.jic 0x100020
* ./test_VMENIMIO32_gef.exe --addr 0x100000 --reboot ### PPG will stop responding
* ./test_a32.exe 0x100000 ### should read 0x00000000 (NOT 0xFFFFFFFF)

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || CSR || RW || Control/Status Register
|-
| 1 || 0x00004 || Test || RW || Test Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Inv_Mask || RW || Output Inversion Mask
|-
| 8 || 0x00020 || Version || R || Firmware Version Register
|-
| 9 || 0x00024 || Flash || RW || Serial Flash Control Register
|-
| 10 || 0x00028 || Serial || R || Serial Number Register
|-
| 11 || 0x0002C || Hardware || R || hardware Identification Register
|-
| 12 || 0x00030 || clock Control || RW || Clock Control Register
|}

===== CSR Register (0x00000) =====

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk-Toggle || W || Toggles between PPG external and internal Clk
|-
|2|| Ext-Start|| R/W || 1=Ext-PPG Start 0=Int-PPG Start
|-
|3|| PPG-Reset || R/W || 1=Reset 0=Normal operation
|-
|4|| Test-Mode || R/W || 1=Test Mode 0=Normal operation
|-
|16|| Ext-Clk-Sel || R || 1= External clock is selected 0 = Internal clock selected
|-
|17|| Ext-Clk good || R || 1= External clock is connected and is "good" 0= external clock not connected or is "bad"
|-
|?-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing an edge here toggles the ppg logic between the internal and external CLK (connected to Nim_Input[3]). The VME interface always uses the internal clock.
Note that the correct divide-down must be programmed unless external clock is the same frequency (i.e. 10MHz) as internal clock.

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start. (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[4])

Reset bit: Set bit to Reset PPG. Stops PPG pgm even if executing a long delay. Does NOT do a full reset to power-up condition. Bit must be cleared after Reset or module will not operate.

Test-Mode bit: Set bit to enable Test Mode. When Test Mode is enabled, inputs 1 and 2 become output the internal PPG clock and actual clock PPG is using, respectively. If internal clock is set, inputs 1 and 2 output identical clocks. If external clock is set, and the external clock is "good", input 1 will not change, but input 2 will show the external clock frequency.
If Test-Mode bit is cleared, Normal Mode is enabled, where inputs 1 and 2 act as regular inputs.

Ext-Clk-Sel: If bit is set, external clock is selected and LED 4 will be lit. If clear, internal clock is selected

Ext-Clk Good: If bit is set, external clock is connected to Nim_Input[3] and is "good". LED 2 will be lit. If clear, external clock is either not connected or is "bad".

===== Test Register (0x00004) =====

Simple Test Register - Value Written is preserved and can be read back.

===== Address Register (0x00008) =====

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address. Also in test-Mode, the NIM/LED outputs follow the state of this register.

===== Instruction Registers (0x0000C - 0x00018) =====

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

===== Output Inversion Mask (0x0001C) =====
32 individual inversion bits (1 per output) a 1 inverts the state of that output.

===== Firmware Version (0x00020) =====
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

===== Serial Flash Control (0x00024) =====
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

===== Serial Number (0x00028) =====
Returns the module serial number, and Board revision (if set) or 0xdead

===== hardware Type (0x0002C) =====
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

===== Clock Control (0x00030) =====
Set PLL parameters applied to external clock input. Default parameters are for 20Mhz External Clock, and multiply this by 5 to get 100Mhz ppg clock.

Register Contents as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 30-28 || Bits 26-24 || Bits 23-20 || Bits 16-8 || Bit 5 || Bit 4 || Bit 3 || Bit 2 || Bit 1 || Bit 0
|-
| Phase Counter Select || Counter Parameter || Counter Type || 9 bit Data || PLL Reset || Up/Down || PhaseStep || Write Parameter || reconfigure || Unused?
|-
|}

=== Front Panel ===

==== NIM Inputs ====

The Input assignments are (as labelled on front panel) ...
4 - External Start (Not fully tested yet) Needs to stay high (low => stop!)
3 - External Clock (20Mhz, internally scaled - 100Mhz)
2 - Unassigned
1 - Unassigned

==== Input LEDs ====

The Input LED assignments are (as labelled on front panel) ...
4 - Clock setting (Lit => External Clk)
3 - NimIn[2] status
2 - External Clock Good indicator (Lit => Clock is good)
1 - Program Running

=== Test Software ===

==== c-shell script to run 2 nested loops ====

set dec_hex=( 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 \
0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf \
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 \
0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f \
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 )

# dly4,loop4,dly3,loop6,dly2,end,end
set inst=( \
0xff 0x00 0x4 0x100000 0x0 0x0 0x0 0x200004 \
0x1 0x1 0x3 0x100000 0x0 0x0 0x0 0x200006 \
0x2 0x2 0x2 0x100000 0x0 0x0 0x0 0x300000 \
0x0 0x0 0x0 0x300000 0x0 0x0 0x0 0x000000 )

set i=0
set j=0
while( $i < $#inst )
@ j++; vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 $dec_hex[$j]
@ i++; vme_poke -a VME_A32UD -A 0x0010000c -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100010 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100014 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100018 -d VME_D32 $inst[$i]
end

# start program (from addr 0)...
vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100000 -d VME_D32 0x1

==== c-shell script to set divide-downs for 100MHz frequency ====

This would be used with an external frequency input of 100MHz

vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x00000305 # set hi counter to 3
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x01000205 # set lo counter to 2
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x05000105 # set mode counter to odd
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000005 # set counter bypass to 0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0

==== c-shell script to set divide-downs for 10MHz frequency ====

This would be used when returning to the internal frequency of 10MHz :

vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000105 # set counter bypass to 1
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3 # reconfig clock
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd

=== Procedure for newly assembled board startup and test ===

(note1: VME-PPG32-IO32 firmware is used to test the board)

(note2: TTL inputs and outputs are not tested)

(note3: DAC outputs are not tested)

(note4: shorts between NIM outputs are not tested)

* set VME address jumper A20-23 to "1", jumpers A24-27 and A28-31 to "0"
* set inputs and outputs to "NIM" mode
* connect JTAG USB blaster
* power up the board (standalone or in a VME crate)
* start Quartus programmer
* select correct USB blaster
* run "auto detect", 3 devices should be detected: EP3C20Q240 (Cyclone3 FPGA), EPM1270 (parallel flash loader CPLD), EPM3032AT44 (VME address decoder CPLD)
* flash the VME address decoder pof file into the EPM3032 part (get pof file from here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode/VME_Addr_decode.pof?view=log)
* (do not do this) flash the CFI parallel flash loader into the EPM1270 part (get pof file where?!?)
* load the VME-PPG32-IO32 firmware sof file into the EP3 part (get sof file here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.sof?view=log)
* run "vmescan_gef.exe", it should detect the IO32 board at A24 VME address 0x00100000, data should correspond to the sof file revision date code
* confirm VME access LED is working (flashes during vme scan).
* confirm VME Data bus is okey: "./test_VMENIMIO32_gef.exe --addr 0x100000 --testbits 4"
* (do not do this) follow the firmware update instructions to flash the firmware pof file using the VME flash programmer at [[VME-NIMIO32#Firmware_update_procedure]] (get VME-PPG32-IO32 pof file from here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.pof?view=log)
* (do not do this) confirm FPGA reboot is working - "./test_VMENIMIO32_gef.exe --addr 0x100000 --reboot" prints 0xFFFFFFFF on the second read of firmware revision
* test NIM inputs and LEDs: use NIM pulse generator or any NIM module inverted output, connect to each NIM input, observe that corresponding "green" LEDs is lighting up
* test NIM outputs and LEDs: "./test_VMENIMIO32_gef.exe --addr 0x100000 --nimout 3 1 --pulsenim", observe all "red" LEDs are flashing, connect NIM outputs to NIM scaler, observe scaler counts at each LED flash
* load PPG firmware into the active serial flash (follow instructions here: [[#Update_using_VME_flash_programmer_when_running_VME-PPG32-IO32_firmware]]
* unplug the board from VME, wait 10 sec, plug it back in, confirm that it is detected by vmescan if running VME-PPG32-IO32 firmware or test_a32 or PPG test tools if running the PPG firmware (confirms the flash memory contents is good)

=== VME-PPG32-IO32 firmware ===

The VME-PPG32 board can run a special version of VME-NIMIO32 firmware (subproject "PPG32-Rev1" of the VME-NIMIO32 firmware). For instructions, please refer to the [[VME-NIMIO32]] documentation.

VME-PPG32

2013-02-20T22:17:29Z

Cpearson: /* Registers */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [https://edev.triumf.ca/projects/edevel00022] VME-PPG32 Rev0 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/projects/edevel00067] VME-PPG32 Rev1 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/projects/edevel00125] VME-PPG32 Rev2 (REA 198) project page on edev.triumf.ca
* [https://edev.triumf.ca/documents/27] Rev0 board schematics on edev site
* [https://edev.triumf.ca/documents/111] Rev1 board schematics on edev site
* [https://edev.triumf.ca/documents/158] Rev2 board schematics on edev site
* [[Image:VME-PPG32 Rev1.pdf]] Rev1 board schematics, local copy
* [[Image:VME-PPG32 Rev2.pdf]] Rev2 board schematics, local copy

VME-PPG32-IO32 firmware: (IO32 functions, no PPG functions)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32-Rev0] Svn repository for VME-PPG32-Rev0 initial test firmware (IO32 function only, no PPG function)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1] Svn repository for VME-PPG32-Rev1 firmware (IO32 function only, no PPG function)

VME-PPG32 VME CPLD firmware: (VME address decoder)
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode] Svn repository for VME-PPG32 Rev0 and Rev1 VME address decoder CPLD (Altera EPM3032)

VME-PPG32 firmware: (PPG function)
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ
* Rev1 and Rev2 boards: inputs are switchable between NIM and TTL (JMP3)
* Rev2 boards: outputs are switchable between NIM and TTL (SW1 micro switches)

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input - see note 1)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

FPGA resource Usage : 1044 LE, 500 kbits Memory

Note 1 :
Some modules allow an external clock frequency of 20-100MHz . Divide-downs must be programmed where external clock frequency is not 20MHz.
Examples of divide-down programming is shown at end of this document.

=== Onboard jumper settings ===

* JMP1 - set to "INP" for input with 50 Ohm termination, set to "DAC" for DAC output
* JMP2 - set to "INP" same as JMP1
* JMP3 - set to "NIM" (pins 1-2) for NIM inputs or "TTL" (pins 2-3) for TTL inputs
* JMP4 - "MSEL1" jumper set to "ACT" for use with the active-serial flash
* IrqSel - leave open
* JTAG - leave open (not a jumper block!)
* SW1..3 - VME base address selectors (see below)

=== Firmware update procedure ===

(note1: right now the PPG firmware update procedure is unnecessary complicated because there is no ppg.pof file in the PPG firmware distribution version "1mar12" and the PPG firmware does not include the Altera active-serial programmer block.)

(note2: VME-PPG32-IO32 firmware (sof file) is required to update the PPG firmware)

* obtain the PPG firmware zip file (from http://daq-plone.triumf.ca/HR/VME/ppg32)
* extract the ppg.jic file
* obtain the VME-PPG32-IO32 sof file (VME-PPG32.sof) from https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.sof?view=log

==== Update using USB-Blaster and jic file ====

* use Quartus programmer to burn the jic file through the EP3 active-serial flash loader:
* start Quartus programmer (tools->programmer)
* say "auto detect" - EP3, EPM1270 and EPM3032A should be detected
* attach VME-PPG32.sof to the EP3 part (context menu "change file")
* select "program"
* say "start"
* observe that 2 "red" LEDs have turned on on the PPG board (40MHz clock on outputs 4 and 20).
* say "auto detect"
* an "EPCS16" part should show up attached to the EP3.
* attach ppg.jic to the EPCS16 part
* select "program"
* say "start"
* observe progress bar go from 0 to 100% in about 2 minutes.
* PPG firmware is now loaded into the board
* cycle the power on the board to reboot into the PPG firmware
* when running the PPG firmware, all LEDs are off after reboot.

==== Update using VME flash programmer ====

(note: VME flash programmer interface does not work in ppg firmware version "1mar12").

* obtain the latest copy of srunner_vme (follow instructions here [[VME-NIMIO32#Firmware_update_procedure]]) (srunner_vme.cxx svn rev 214 or newer for jic support)
* ./srunner_vme_gef.exe -program -16 ppg.jic 0x100024
* reboot the PPG

(note: the above does not work: b) srunner_vme treats 0x10xxxx is an A24 address, but PPG firmware does not respond to A24 addresses; c) the active serial interface does not seem to work anyway)

(note: the reboot function is not available in the PPG firmware)

==== Update using VME flash programmer when running VME-PPG32-IO32 firmware ====

* ./test_VMENIMIO32_gef.exe --addr 0x100000 --read 0 ### to confirm VME-PPG32-IO32 firmware revision
* ./srunner_vme_gef.exe -program -16 ppg.jic 0x100020
* ./test_VMENIMIO32_gef.exe --addr 0x100000 --reboot ### PPG will stop responding
* ./test_a32.exe 0x100000 ### should read 0x00000000 (NOT 0xFFFFFFFF)

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || CSR || RW || Control/Status Register
|-
| 1 || 0x00004 || Test || RW || Test Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Inv_Mask || RW || Output Inversion Mask
|-
| 8 || 0x00020 || Version || R || Firmware Version Register
|-
| 9 || 0x00024 || Flash || RW || Serial Flash Control Register
|-
| 10 || 0x00028 || Serial || R || Serial Number Register
|-
| 11 || 0x0002C || Hardware || R || hardware Identification Register
|-
| 12 || 0x00030 || clock Control || RW || Clock Control Register
|}

===== CSR Register (0x00000) =====

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk-Toggle || W || Toggles between PPG external and internal Clk
|-
|2|| Ext-Start|| R/W || 1=Ext-PPG Start 0=Int-PPG Start
|-
|3|| PPG-Reset || R/W || 1=Reset 0=Normal operation
|-
|4|| Test-Mode || R/W || 1=Test Mode 0=Normal operation
|-
|16|| Ext-Clk-Sel || R || 1= External clock is selected 0 = Internal clock selected
|-
|17|| Ext-Clk good || R || 1= External clock is connected and is "good" 0= external clock not connected or is "bad"
|-
|?-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing an edge here toggles the ppg logic between the internal and external CLK (connected to Nim_Input[3]). The VME interface always uses the internal clock.
Note that the correct divide-down must be programmed unless external clock is the same frequency (i.e. 10MHz) as internal clock.

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start. (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[4])

Reset bit: Set bit to Reset PPG. Stops PPG pgm even if executing a long delay. Does NOT do a full reset to power-up condition. Bit must be cleared after Reset or module will not operate.

Test-Mode bit: Set bit to enable Test Mode. When Test Mode is enabled, inputs 1 and 2 become output the internal PPG clock and actual clock PPG is using, respectively. If internal clock is set, inputs 1 and 2 output identical clocks. If external clock is set, and the external clock is "good", input 1 will not change, but input 2 will show the external clock frequency.
If Test-Mode bit is cleared, Normal Mode is enabled, where inputs 1 and 2 act as regular inputs.

Ext-Clk-Sel: If bit is set, external clock is selected and LED 4 will be lit. If clear, internal clock is selected

Ext-Clk Good: If bit is set, external clock is connected to Nim_Input[3] and is "good". LED 2 will be lit. If clear, external clock is either not connected or is "bad".

===== Test Register (0x00004) =====

Simple Test Register - Value Written is preserved and can be read back.

===== Address Register (0x00008) =====

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address. Also in test-Mode, the NIM/LED outputs follow the state of this register.

===== Instruction Registers (0x0000C - 0x00018) =====

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

===== Output Inversion Mask (0x0001C) =====
32 individual inversion bits (1 per output) a 1 inverts the state of that output.

===== Firmware Version (0x00020) =====
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

===== Serial Flash Control (0x00024) =====
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

===== Serial Number (0x00028) =====
Returns the module serial number, and Board revision (if set) or 0xdead

===== hardware Type (0x0002C) =====
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

===== Clock Control (0x00030) =====

=== Front Panel ===

==== NIM Inputs ====

The Input assignments are (as labelled on front panel) ...
4 - External Start (Not fully tested yet) Needs to stay high (low => stop!)
3 - External Clock (20Mhz, internally scaled - 100Mhz)
2 - Unassigned
1 - Unassigned

==== Input LEDs ====

The Input LED assignments are (as labelled on front panel) ...
4 - Clock setting (Lit => External Clk)
3 - NimIn[2] status
2 - External Clock Good indicator (Lit => Clock is good)
1 - Program Running

=== Test Software ===

==== c-shell script to run 2 nested loops ====

set dec_hex=( 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 \
0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf \
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 \
0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f \
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 )

# dly4,loop4,dly3,loop6,dly2,end,end
set inst=( \
0xff 0x00 0x4 0x100000 0x0 0x0 0x0 0x200004 \
0x1 0x1 0x3 0x100000 0x0 0x0 0x0 0x200006 \
0x2 0x2 0x2 0x100000 0x0 0x0 0x0 0x300000 \
0x0 0x0 0x0 0x300000 0x0 0x0 0x0 0x000000 )

set i=0
set j=0
while( $i < $#inst )
@ j++; vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 $dec_hex[$j]
@ i++; vme_poke -a VME_A32UD -A 0x0010000c -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100010 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100014 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100018 -d VME_D32 $inst[$i]
end

# start program (from addr 0)...
vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100000 -d VME_D32 0x1

==== c-shell script to set divide-downs for 100MHz frequency ====

This would be used with an external frequency input of 100MHz

vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x00000305 # set hi counter to 3
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x01000205 # set lo counter to 2
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x05000105 # set mode counter to odd
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000005 # set counter bypass to 0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0

==== c-shell script to set divide-downs for 10MHz frequency ====

This would be used when returning to the internal frequency of 10MHz :

vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000105 # set counter bypass to 1
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3 # reconfig clock
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd

=== Procedure for newly assembled board startup and test ===

(note1: VME-PPG32-IO32 firmware is used to test the board)

(note2: TTL inputs and outputs are not tested)

(note3: DAC outputs are not tested)

(note4: shorts between NIM outputs are not tested)

* set VME address jumper A20-23 to "1", jumpers A24-27 and A28-31 to "0"
* set inputs and outputs to "NIM" mode
* connect JTAG USB blaster
* power up the board (standalone or in a VME crate)
* start Quartus programmer
* select correct USB blaster
* run "auto detect", 3 devices should be detected: EP3C20Q240 (Cyclone3 FPGA), EPM1270 (parallel flash loader CPLD), EPM3032AT44 (VME address decoder CPLD)
* flash the VME address decoder pof file into the EPM3032 part (get pof file from here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode/VME_Addr_decode.pof?view=log)
* (do not do this) flash the CFI parallel flash loader into the EPM1270 part (get pof file where?!?)
* load the VME-PPG32-IO32 firmware sof file into the EP3 part (get sof file here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.sof?view=log)
* run "vmescan_gef.exe", it should detect the IO32 board at A24 VME address 0x00100000, data should correspond to the sof file revision date code
* confirm VME access LED is working (flashes during vme scan).
* confirm VME Data bus is okey: "./test_VMENIMIO32_gef.exe --addr 0x100000 --testbits 4"
* (do not do this) follow the firmware update instructions to flash the firmware pof file using the VME flash programmer at [[VME-NIMIO32#Firmware_update_procedure]] (get VME-PPG32-IO32 pof file from here: https://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/VME-NIMIO32/PPG32-Rev1/VME-PPG32.pof?view=log)
* (do not do this) confirm FPGA reboot is working - "./test_VMENIMIO32_gef.exe --addr 0x100000 --reboot" prints 0xFFFFFFFF on the second read of firmware revision
* test NIM inputs and LEDs: use NIM pulse generator or any NIM module inverted output, connect to each NIM input, observe that corresponding "green" LEDs is lighting up
* test NIM outputs and LEDs: "./test_VMENIMIO32_gef.exe --addr 0x100000 --nimout 3 1 --pulsenim", observe all "red" LEDs are flashing, connect NIM outputs to NIM scaler, observe scaler counts at each LED flash
* load PPG firmware into the active serial flash (follow instructions here: [[#Update_using_VME_flash_programmer_when_running_VME-PPG32-IO32_firmware]]
* unplug the board from VME, wait 10 sec, plug it back in, confirm that it is detected by vmescan if running VME-PPG32-IO32 firmware or test_a32 or PPG test tools if running the PPG firmware (confirms the flash memory contents is good)

=== VME-PPG32-IO32 firmware ===

The VME-PPG32 board can run a special version of VME-NIMIO32 firmware (subproject "PPG32-Rev1" of the VME-NIMIO32 firmware). For instructions, please refer to the [[VME-NIMIO32]] documentation.

VME-PPG32

2012-03-03T00:06:31Z

Cpearson: /* CSR Register (0x00004) */

VME-PPG32

2012-03-02T23:52:09Z

Cpearson: /* PPG characteristics */

VME-PPG32

2012-03-02T23:46:49Z

Cpearson: /* Test Software */

VME-PPG32

2012-03-02T23:39:41Z

Cpearson: /* CSR Register (0x00004) */

VME-PPG32

2012-03-02T22:49:11Z

Cpearson: /* Front Panel */

VME-PPG32

2011-10-06T05:29:47Z

Cpearson: /* Serial Number (0x00028) */

VME-PPG32

2011-01-25T23:50:11Z

Cpearson: /* NIM Inputs */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [http://edev.triumf.ca/projects/edevel00022] VME-PPG32 (REA 198) project page on edev.triumf.ca
* [http://edev.triumf.ca/documents/27] Rev0 board schematics
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32] Svn repository for initial test firmware
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

FPGA resource Usage : 1044 LE, 500 kbits Memory

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || CSR || RW || Control/Status Register
|-
| 1 || 0x00004 || Test || RW || Test Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Inv_Mask || RW || Output Inversion Mask
|-
| 8 || 0x00020 || Version || R || Firmware Version Register
|-
| 9 || 0x00024 || Flash || RW || Serial Flash Control Register
|-
| 10 || 0x00028 || Serial || R || Serial Number Register
|-
| 11 || 0x0002C || Hardware || R || hardware Identification Register
|}

===== Test Register (0x00000) =====

Simple Test Register - Value Written is preserved and can be read back.

===== CSR Register (0x00004) =====

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk || R/W || The PPG logic uses the external Clk
|-
|2|| Ext-Start|| R/W ||
|-
|3|| Slow-Clk || R/W ||
|-
|4|| Test-Mode || R/W ||
|-
|5-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing 1 here switches the ppg logic to use the external CLK (Nim_Input[0]) (The VME interface always uses the internal clock)

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[1])

Slow-Clk bit: Writing 1 here Switches the ppg clock to a much slower one (2kHz) for low speed/long delay operation.
NOTE - this is currently ignored.

Test-mode bit: Writing 1 here Changes the outputs (LED/NIM) to simple follow the state of the Address register.

===== Address Register (0x00008) =====

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address. Also in test-Mode, the NIM/LED outputs follow the state of this register.

===== Instruction Registers (0x0000C - 0x00018) =====

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

===== Output Inversion Mask (0x0001C) =====
32 individual inversion bits (1 per output) a 1 inverts the state of that output.

===== Firmware Version (0x00020) =====
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

===== Serial Flash Control (0x00024) =====
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

===== Serial Number (0x00028) =====
Returns the module serial number, and Board revision (if set) or -1

===== hardware Type (0x0002C) =====
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

=== Front Panel ===

==== NIM Inputs ====

The Input assignments are (Left-Right, Top-Bottom) ...
0 - External Clock (20Mhz, internally scaled - 100Mhz)
1 - External Start (Not fully tested yet) Needs to stay high (low => stop!)
2 - Unassigned
3 - Unassigned

==== Input LEDs ====

The Input LED assignments are (Left-Right, Top-Bottom) ...
0 - External Clock Good indicator (Lit => Clock is good)
1 - Program Running
2 - Clock setting (Lit => External Clk)
3 - NimIn[3] status

=== Test Software ===

==== c-shell script to run 2 nested loops ====

set dec_hex=( 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 \
0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf \
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 \
0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f \
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 )

# dly4,loop4,dly3,loop6,dly2,end,end
set inst=( \
0xff 0x00 0x4 0x100000 0x0 0x0 0x0 0x200004 \
0x1 0x1 0x3 0x100000 0x0 0x0 0x0 0x200006 \
0x2 0x2 0x2 0x100000 0x0 0x0 0x0 0x300000 \
0x0 0x0 0x0 0x300000 0x0 0x0 0x0 0x000000 )

set i=0
set j=0
while( $i < $#inst )
@ j++; vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 $dec_hex[$j]
@ i++; vme_poke -a VME_A32UD -A 0x0010000c -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100010 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100014 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100018 -d VME_D32 $inst[$i]
end

# start program (from addr 0)...
vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100000 -d VME_D32 0x1

VME-PPG32

2011-01-25T23:49:00Z

Cpearson: /* VME-PPG32 - pulse pattern generator VME FPGA board */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [http://edev.triumf.ca/projects/edevel00022] VME-PPG32 (REA 198) project page on edev.triumf.ca
* [http://edev.triumf.ca/documents/27] Rev0 board schematics
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32] Svn repository for initial test firmware
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

FPGA resource Usage : 1044 LE, 500 kbits Memory

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || CSR || RW || Control/Status Register
|-
| 1 || 0x00004 || Test || RW || Test Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Inv_Mask || RW || Output Inversion Mask
|-
| 8 || 0x00020 || Version || R || Firmware Version Register
|-
| 9 || 0x00024 || Flash || RW || Serial Flash Control Register
|-
| 10 || 0x00028 || Serial || R || Serial Number Register
|-
| 11 || 0x0002C || Hardware || R || hardware Identification Register
|}

===== Test Register (0x00000) =====

Simple Test Register - Value Written is preserved and can be read back.

===== CSR Register (0x00004) =====

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk || R/W || The PPG logic uses the external Clk
|-
|2|| Ext-Start|| R/W ||
|-
|3|| Slow-Clk || R/W ||
|-
|4|| Test-Mode || R/W ||
|-
|5-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing 1 here switches the ppg logic to use the external CLK (Nim_Input[0]) (The VME interface always uses the internal clock)

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[1])

Slow-Clk bit: Writing 1 here Switches the ppg clock to a much slower one (2kHz) for low speed/long delay operation.
NOTE - this is currently ignored.

Test-mode bit: Writing 1 here Changes the outputs (LED/NIM) to simple follow the state of the Address register.

===== Address Register (0x00008) =====

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address. Also in test-Mode, the NIM/LED outputs follow the state of this register.

===== Instruction Registers (0x0000C - 0x00018) =====

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

===== Output Inversion Mask (0x0001C) =====
32 individual inversion bits (1 per output) a 1 inverts the state of that output.

===== Firmware Version (0x00020) =====
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

===== Serial Flash Control (0x00024) =====
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

===== Serial Number (0x00028) =====
Returns the module serial number, and Board revision (if set) or -1

===== hardware Type (0x0002C) =====
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

=== Front Panel ===

==== NIM Inputs ====

The Input assignments are (Left-Right, Top-Bottom) ...
0 - External Clock (20Mhz, internally scaled - 100Mhz)
1 - External Start (Not fully tested yet)
2 - Unassigned
3 - Unassigned

==== Input LEDs ====

The Input LED assignments are (Left-Right, Top-Bottom) ...
0 - External Clock Good indicator (Lit => Clock is good)
1 - Program Running
2 - Clock setting (Lit => External Clk)
3 - NimIn[3] status

=== Test Software ===

==== c-shell script to run 2 nested loops ====

set dec_hex=( 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 \
0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf \
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 \
0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f \
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 )

# dly4,loop4,dly3,loop6,dly2,end,end
set inst=( \
0xff 0x00 0x4 0x100000 0x0 0x0 0x0 0x200004 \
0x1 0x1 0x3 0x100000 0x0 0x0 0x0 0x200006 \
0x2 0x2 0x2 0x100000 0x0 0x0 0x0 0x300000 \
0x0 0x0 0x0 0x300000 0x0 0x0 0x0 0x000000 )

set i=0
set j=0
while( $i < $#inst )
@ j++; vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 $dec_hex[$j]
@ i++; vme_poke -a VME_A32UD -A 0x0010000c -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100010 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100014 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100018 -d VME_D32 $inst[$i]
end

# start program (from addr 0)...
vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100000 -d VME_D32 0x1

VME-PPG32

2011-01-20T01:15:34Z

Cpearson: /* Registers */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [http://edev.triumf.ca/projects/edevel00022] VME-PPG32 (REA 198) project page on edev.triumf.ca
* [http://edev.triumf.ca/documents/27] Rev0 board schematics
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32] Svn repository for initial test firmware
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

FPGA resource Usage : 1044 LE, 500 kbits Memory

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || CSR || RW || Control/Status Register
|-
| 1 || 0x00004 || Test || RW || Test Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Inv_Mask || RW || Output Inversion Mask
|-
| 8 || 0x00020 || Version || R || Firmware Version Register
|-
| 9 || 0x00024 || Flash || RW || Serial Flash Control Register
|-
| 10 || 0x00028 || Serial || R || Serial Number Register
|-
| 11 || 0x0002C || Hardware || R || hardware Identification Register
|}

===== Test Register (0x00000) =====

Simple Test Register - Value Written is preserved and can be read back.

===== CSR Register (0x00004) =====

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk || R/W || The PPG logic uses the external Clk
|-
|2|| Ext-Start|| R/W ||
|-
|3|| Slow-Clk || R/W ||
|-
|4|| Test-Mode || R/W ||
|-
|5-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing 1 here switches the ppg logic to use the external CLK (Nim_Input[0]) (The VME interface always uses the internal clock)

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[1])

Slow-Clk bit: Writing 1 here Switches the ppg clock to a much slower one (2kHz) for low speed/long delay operation.
NOTE - this is currently ignored.

Test-mode bit: Writing 1 here Changes the outputs (LED/NIM) to simple follow the state of the Address register.

===== Address Register (0x00008) =====

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address. Also in test-Mode, the NIM/LED outputs follow the state of this register.

===== Instruction Registers (0x0000C - 0x00018) =====

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

===== Output Inversion Mask (0x0001C) =====
32 individual inversion bits (1 per output) a 1 inverts the state of that output.

===== Firmware Version (0x00020) =====
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

===== Serial Flash Control (0x00024) =====
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

===== Serial Number (0x00028) =====
Returns the module serial number, and Board revision (if set) or -1

===== hardware Type (0x0002C) =====
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

=== Test Software ===

==== c-shell script to run 2 nested loops ====

set dec_hex=( 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 \
0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf \
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 \
0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f \
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 )

# dly4,loop4,dly3,loop6,dly2,end,end
set inst=( \
0xff 0x00 0x4 0x100000 0x0 0x0 0x0 0x200004 \
0x1 0x1 0x3 0x100000 0x0 0x0 0x0 0x200006 \
0x2 0x2 0x2 0x100000 0x0 0x0 0x0 0x300000 \
0x0 0x0 0x0 0x300000 0x0 0x0 0x0 0x000000 )

set i=0
set j=0
while( $i < $#inst )
@ j++; vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 $dec_hex[$j]
@ i++; vme_poke -a VME_A32UD -A 0x0010000c -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100010 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100014 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100018 -d VME_D32 $inst[$i]
end

# start program (from addr 0)...
vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100000 -d VME_D32 0x1

VME-PPG32

2011-01-16T19:31:20Z

Cpearson: /* c-shell script to run 2 nested loops */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [http://edev.triumf.ca/projects/edevel00022] VME-PPG32 (REA 198) project page on edev.triumf.ca
* [http://edev.triumf.ca/documents/27] Rev0 board schematics
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32] Svn repository for initial test firmware
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

FPGA resource Usage : 1044 LE, 500 kbits Memory

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || Test || RW || Test Register
|-
| 1 || 0x00004 || CSR || RW || Control/Status Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Inv_Mask || RW || Output Inversion Mask
|-
| 8 || 0x00020 || Version || R || Firmware Version Register
|-
| 9 || 0x00024 || Flash || RW || Serial Flash Control Register
|-
| 10 || 0x00028 || Serial || R || Serial Number Register
|-
| 11 || 0x0002C || Hardware || R || hardware Identification Register
|}

===== Test Register (0x00000) =====

Simple Test Register - Value Written is preserved and can be read back.

===== CSR Register (0x00004) =====

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk || R/W || The PPG logic uses the external Clk
|-
|2|| Ext-Start|| R/W ||
|-
|3|| Slow-Clk || R/W ||
|-
|4|| Test-Mode || R/W ||
|-
|5-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing 1 here switches the ppg logic to use the external CLK (Nim_Input[0]) (The VME interface always uses the internal clock)

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[1])

Slow-Clk bit: Writing 1 here Switches the ppg clock to a much slower one (2kHz) for low speed/long delay operation.
NOTE - this is currently ignored.

Test-mode bit: Writing 1 here Changes the outputs (LED/NIM) to simple follow the state of the Address register.

===== Address Register (0x00008) =====

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address. Also in test-Mode, the NIM/LED outputs follow the state of this register.

===== Instruction Registers (0x0000C - 0x00018) =====

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

===== Output Inversion Mask (0x0001C) =====
32 individual inversion bits (1 per output) a 1 inverts the state of that output.

===== Firmware Version (0x00020) =====
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

===== Serial Flash Control (0x00024) =====
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

===== Serial Number (0x00028) =====
Returns the module serial number, and Board revision (if set) or -1

===== hardware Type (0x0002C) =====
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

=== Test Software ===

==== c-shell script to run 2 nested loops ====

set dec_hex=( 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 \
0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf \
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 \
0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f \
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 )

# dly4,loop4,dly3,loop6,dly2,end,end
set inst=( \
0xff 0x00 0x4 0x100000 0x0 0x0 0x0 0x200004 \
0x1 0x1 0x3 0x100000 0x0 0x0 0x0 0x200006 \
0x2 0x2 0x2 0x100000 0x0 0x0 0x0 0x300000 \
0x0 0x0 0x0 0x300000 0x0 0x0 0x0 0x000000 )

set i=0
set j=0
while( $i < $#inst )
@ j++; vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 $dec_hex[$j]
@ i++; vme_poke -a VME_A32UD -A 0x0010000c -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100010 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100014 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100018 -d VME_D32 $inst[$i]
end

# start program (from addr 0)...
vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100000 -d VME_D32 0x1

VME-PPG32

2011-01-16T19:31:02Z

Cpearson: /* c-shell script to run 2 nested loops */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [http://edev.triumf.ca/projects/edevel00022] VME-PPG32 (REA 198) project page on edev.triumf.ca
* [http://edev.triumf.ca/documents/27] Rev0 board schematics
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32] Svn repository for initial test firmware
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

FPGA resource Usage : 1044 LE, 500 kbits Memory

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || Test || RW || Test Register
|-
| 1 || 0x00004 || CSR || RW || Control/Status Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Inv_Mask || RW || Output Inversion Mask
|-
| 8 || 0x00020 || Version || R || Firmware Version Register
|-
| 9 || 0x00024 || Flash || RW || Serial Flash Control Register
|-
| 10 || 0x00028 || Serial || R || Serial Number Register
|-
| 11 || 0x0002C || Hardware || R || hardware Identification Register
|}

===== Test Register (0x00000) =====

Simple Test Register - Value Written is preserved and can be read back.

===== CSR Register (0x00004) =====

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk || R/W || The PPG logic uses the external Clk
|-
|2|| Ext-Start|| R/W ||
|-
|3|| Slow-Clk || R/W ||
|-
|4|| Test-Mode || R/W ||
|-
|5-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing 1 here switches the ppg logic to use the external CLK (Nim_Input[0]) (The VME interface always uses the internal clock)

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[1])

Slow-Clk bit: Writing 1 here Switches the ppg clock to a much slower one (2kHz) for low speed/long delay operation.
NOTE - this is currently ignored.

Test-mode bit: Writing 1 here Changes the outputs (LED/NIM) to simple follow the state of the Address register.

===== Address Register (0x00008) =====

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address. Also in test-Mode, the NIM/LED outputs follow the state of this register.

===== Instruction Registers (0x0000C - 0x00018) =====

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

===== Output Inversion Mask (0x0001C) =====
32 individual inversion bits (1 per output) a 1 inverts the state of that output.

===== Firmware Version (0x00020) =====
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

===== Serial Flash Control (0x00024) =====
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

===== Serial Number (0x00028) =====
Returns the module serial number, and Board revision (if set) or -1

===== hardware Type (0x0002C) =====
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

=== Test Software ===

==== c-shell script to run 2 nested loops ====

set dec_hex=( 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 \
0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf \
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 \
0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f \
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 )

# dly4,loop4,dly3,loop6,dly2,end,end
set inst=( \
0xff 0x00 0x4 0x100000 0x0 0x0 0x0 0x200004 \
0x1 0x1 0x3 0x100000 0x0 0x0 0x0 0x200006 \
0x2 0x2 0x2 0x100000 0x0 0x0 0x0 0x300000 \
0x0 0x0 0x0 0x300000 0x0 0x0 0x0 0x000000 )

set i=0
set j=0
while( $i < $#inst )
@ j++; vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 $dec_hex[$j]
@ i++; vme_poke -a VME_A32UD -A 0x0010000c -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100010 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100014 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100018 -d VME_D32 $inst[$i]
end

# start program (from addr 0)...
vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100000 -d VME_D32 0x1

VME-PPG32

2010-11-09T23:41:08Z

Cpearson: /* VME interface */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [http://edev.triumf.ca/projects/edevel00022] VME-PPG32 (REA 198) project page on edev.triumf.ca
* [http://edev.triumf.ca/documents/27] Rev0 board schematics
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32] Svn repository for initial test firmware
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

FPGA resource Usage : 1044 LE, 500 kbits Memory

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || Test || RW || Test Register
|-
| 1 || 0x00004 || CSR || RW || Control/Status Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Inv_Mask || RW || Output Inversion Mask
|-
| 8 || 0x00020 || Version || R || Firmware Version Register
|-
| 9 || 0x00024 || Flash || RW || Serial Flash Control Register
|-
| 10 || 0x00028 || Serial || R || Serial Number Register
|-
| 11 || 0x0002C || Hardware || R || hardware Identification Register
|}

===== Test Register (0x00000) =====

Simple Test Register - Value Written is preserved and can be read back.

===== CSR Register (0x00004) =====

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk || R/W || The PPG logic uses the external Clk
|-
|2|| Ext-Start|| R/W ||
|-
|3|| Slow-Clk || R/W ||
|-
|4|| Test-Mode || R/W ||
|-
|5-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing 1 here switches the ppg logic to use the external CLK (Nim_Input[0]) (The VME interface always uses the internal clock)

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[1])

Slow-Clk bit: Writing 1 here Switches the ppg clock to a much slower one (2kHz) for low speed/long delay operation.
NOTE - this is currently ignored.

Test-mode bit: Writing 1 here Changes the outputs (LED/NIM) to simple follow the state of the Address register.

===== Address Register (0x00008) =====

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address. Also in test-Mode, the NIM/LED outputs follow the state of this register.

===== Instruction Registers (0x0000C - 0x00018) =====

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

===== Output Inversion Mask (0x0001C) =====
32 individual inversion bits (1 per output) a 1 inverts the state of that output.

===== Firmware Version (0x00020) =====
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

===== Serial Flash Control (0x00024) =====
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

===== Serial Number (0x00028) =====
Returns the module serial number, and Board revision (if set) or -1

===== hardware Type (0x0002C) =====
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

=== Test Software ===

==== c-shell script to run 2 nested loops ====

set dec_hex=( 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 \
0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf \
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 \
0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f \
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 )

set inst=( # dly4,loop4,dly3,loop6,dly2,end,end \
0xff 0x00 0x4 0x100000 0x0 0x0 0x0 0x200004 \
0x1 0x1 0x3 0x100000 0x0 0x0 0x0 0x200006 \
0x2 0x2 0x2 0x100000 0x0 0x0 0x0 0x300000 \
0x0 0x0 0x0 0x300000 0x0 0x0 0x0 0x000000 )

set i=0
set j=0
while( $i < $#inst )
@ j++; vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 $dec_hex[$j]
@ i++; vme_poke -a VME_A32UD -A 0x0010000c -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100010 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100014 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100018 -d VME_D32 $inst[$i]
end

# start program (from addr 0)...
vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100000 -d VME_D32 0x1

VME-PPG32

2010-11-09T23:34:08Z

Cpearson: /* Registers */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [http://edev.triumf.ca/projects/edevel00022] VME-PPG32 (REA 198) project page on edev.triumf.ca
* [http://edev.triumf.ca/documents/27] Rev0 board schematics
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32] Svn repository for initial test firmware
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

FPGA resource Usage : 1044 LE, 500 kbits Memory

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || Test || RW || Test Register
|-
| 1 || 0x00004 || CSR || RW || Control/Status Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Inv_Mask || RW || Output Inversion Mask
|-
| 8 || 0x00020 || Version || R || Firmware Version Register
|-
| 9 || 0x00024 || Flash || RW || Serial Flash Control Register
|-
| 10 || 0x00028 || Serial || R || Serial Number Register
|-
| 11 || 0x0002C || Hardware || R || hardware Identification Register
|}

===== Test Register (0x00000) =====

Simple Test Register - Value Written is preserved and can be read back.

===== CSR Register (0x00004) =====

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk || R/W || The PPG logic uses the external Clk
|-
|2|| Ext-Start|| R/W ||
|-
|3|| Slow-Clk || R/W ||
|-
|4|| Test-Mode || R/W ||
|-
|5-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing 1 here switches the ppg logic to use the external CLK (Nim_Input[0]) (The VME interface always uses the internal clock)

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[1])

Slow-Clk bit: Writing 1 here Switches the ppg clock to a much slower one (2kHz) for low speed/long delay operation.
NOTE - this is currently ignored.

Test-mode bit: Writing 1 here Changes the outputs (LED/NIM) to simple follow the state of the Address register.

===== Address Register (0x00008) =====

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address. Also in test-Mode, the NIM/LED outputs follow the state of this register.

===== Instruction Registers (0x0000C - 0x00018) =====

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

===== Firmware Version (0x0001C) =====
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

===== Serial Flash Control (0x00020) =====
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

===== Serial Number (0x00024) =====
Returns the module serial number, and Board revision (if set) or -1

===== hardware Type (0x00028) =====
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

=== Test Software ===

==== c-shell script to run 2 nested loops ====

set dec_hex=( 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 \
0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf \
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 \
0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f \
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 )

set inst=( # dly4,loop4,dly3,loop6,dly2,end,end \
0xff 0x00 0x4 0x100000 0x0 0x0 0x0 0x200004 \
0x1 0x1 0x3 0x100000 0x0 0x0 0x0 0x200006 \
0x2 0x2 0x2 0x100000 0x0 0x0 0x0 0x300000 \
0x0 0x0 0x0 0x300000 0x0 0x0 0x0 0x000000 )

set i=0
set j=0
while( $i < $#inst )
@ j++; vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 $dec_hex[$j]
@ i++; vme_poke -a VME_A32UD -A 0x0010000c -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100010 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100014 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100018 -d VME_D32 $inst[$i]
end

# start program (from addr 0)...
vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100000 -d VME_D32 0x1

VME-PPG32

2010-11-09T23:33:05Z

Cpearson: /* PPG characteristics */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [http://edev.triumf.ca/projects/edevel00022] VME-PPG32 (REA 198) project page on edev.triumf.ca
* [http://edev.triumf.ca/documents/27] Rev0 board schematics
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32] Svn repository for initial test firmware
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

FPGA resource Usage : 1044 LE, 500 kbits Memory

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || Test || RW || Test Register
|-
| 1 || 0x00004 || CSR || RW || Control/Status Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Version || R || Firmware Version Register
|-
| 8 || 0x00020 || Flash || RW || Serial Flash Control Register
|-
| 9 || 0x00024 || Serial || R || Serial Number Register
|-
| 10 || 0x00028 || Hardware || R || hardware Identification Register
|}

===== Test Register (0x00000) =====

Simple Test Register - Value Written is preserved and can be read back.

===== CSR Register (0x00004) =====

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk || R/W || The PPG logic uses the external Clk
|-
|2|| Ext-Start|| R/W ||
|-
|3|| Slow-Clk || R/W ||
|-
|4|| Test-Mode || R/W ||
|-
|5-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing 1 here switches the ppg logic to use the external CLK (Nim_Input[0]) (The VME interface always uses the internal clock)

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[1])

Slow-Clk bit: Writing 1 here Switches the ppg clock to a much slower one (2kHz) for low speed/long delay operation.
NOTE - this is currently ignored.

Test-mode bit: Writing 1 here Changes the outputs (LED/NIM) to simple follow the state of the Address register.

===== Address Register (0x00008) =====

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address. Also in test-Mode, the NIM/LED outputs follow the state of this register.

===== Instruction Registers (0x0000C - 0x00018) =====

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

===== Firmware Version (0x0001C) =====
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

===== Serial Flash Control (0x00020) =====
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

===== Serial Number (0x00024) =====
Returns the module serial number, and Board revision (if set) or -1

===== hardware Type (0x00028) =====
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

=== Test Software ===

==== c-shell script to run 2 nested loops ====

set dec_hex=( 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 \
0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf \
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 \
0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f \
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 )

set inst=( # dly4,loop4,dly3,loop6,dly2,end,end \
0xff 0x00 0x4 0x100000 0x0 0x0 0x0 0x200004 \
0x1 0x1 0x3 0x100000 0x0 0x0 0x0 0x200006 \
0x2 0x2 0x2 0x100000 0x0 0x0 0x0 0x300000 \
0x0 0x0 0x0 0x300000 0x0 0x0 0x0 0x000000 )

set i=0
set j=0
while( $i < $#inst )
@ j++; vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 $dec_hex[$j]
@ i++; vme_poke -a VME_A32UD -A 0x0010000c -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100010 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100014 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100018 -d VME_D32 $inst[$i]
end

# start program (from addr 0)...
vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100000 -d VME_D32 0x1

VME-PPG32

2010-11-09T06:42:36Z

Cpearson: /* c-shell script to run 2 nested loops */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [http://edev.triumf.ca/projects/edevel00022] VME-PPG32 (REA 198) project page on edev.triumf.ca
* [http://edev.triumf.ca/documents/27] Rev0 board schematics
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32] Svn repository for initial test firmware
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || Test || RW || Test Register
|-
| 1 || 0x00004 || CSR || RW || Control/Status Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Version || R || Firmware Version Register
|-
| 8 || 0x00020 || Flash || RW || Serial Flash Control Register
|-
| 9 || 0x00024 || Serial || R || Serial Number Register
|-
| 10 || 0x00028 || Hardware || R || hardware Identification Register
|}

===== Test Register (0x00000) =====

Simple Test Register - Value Written is preserved and can be read back.

===== CSR Register (0x00004) =====

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk || R/W || The PPG logic uses the external Clk
|-
|2|| Ext-Start|| R/W ||
|-
|3|| Slow-Clk || R/W ||
|-
|4|| Test-Mode || R/W ||
|-
|5-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing 1 here switches the ppg logic to use the external CLK (Nim_Input[0]) (The VME interface always uses the internal clock)

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[1])

Slow-Clk bit: Writing 1 here Switches the ppg clock to a much slower one (2kHz) for low speed/long delay operation.
NOTE - this is currently ignored.

Test-mode bit: Writing 1 here Changes the outputs (LED/NIM) to simple follow the state of the Address register.

===== Address Register (0x00008) =====

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address. Also in test-Mode, the NIM/LED outputs follow the state of this register.

===== Instruction Registers (0x0000C - 0x00018) =====

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

===== Firmware Version (0x0001C) =====
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

===== Serial Flash Control (0x00020) =====
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

===== Serial Number (0x00024) =====
Returns the module serial number, and Board revision (if set) or -1

===== hardware Type (0x00028) =====
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

=== Test Software ===

==== c-shell script to run 2 nested loops ====

set dec_hex=( 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 \
0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf \
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 \
0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f \
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 )

set inst=( # dly4,loop4,dly3,loop6,dly2,end,end \
0xff 0x00 0x4 0x100000 0x0 0x0 0x0 0x200004 \
0x1 0x1 0x3 0x100000 0x0 0x0 0x0 0x200006 \
0x2 0x2 0x2 0x100000 0x0 0x0 0x0 0x300000 \
0x0 0x0 0x0 0x300000 0x0 0x0 0x0 0x000000 )

set i=0
set j=0
while( $i < $#inst )
@ j++; vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 $dec_hex[$j]
@ i++; vme_poke -a VME_A32UD -A 0x0010000c -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100010 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100014 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100018 -d VME_D32 $inst[$i]
end

# start program (from addr 0)...
vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100000 -d VME_D32 0x1

VME-PPG32

2010-11-09T06:42:13Z

Cpearson: /* VME-PPG32 - pulse pattern generator VME FPGA board */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [http://edev.triumf.ca/projects/edevel00022] VME-PPG32 (REA 198) project page on edev.triumf.ca
* [http://edev.triumf.ca/documents/27] Rev0 board schematics
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32] Svn repository for initial test firmware
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || Test || RW || Test Register
|-
| 1 || 0x00004 || CSR || RW || Control/Status Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Version || R || Firmware Version Register
|-
| 8 || 0x00020 || Flash || RW || Serial Flash Control Register
|-
| 9 || 0x00024 || Serial || R || Serial Number Register
|-
| 10 || 0x00028 || Hardware || R || hardware Identification Register
|}

===== Test Register (0x00000) =====

Simple Test Register - Value Written is preserved and can be read back.

===== CSR Register (0x00004) =====

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk || R/W || The PPG logic uses the external Clk
|-
|2|| Ext-Start|| R/W ||
|-
|3|| Slow-Clk || R/W ||
|-
|4|| Test-Mode || R/W ||
|-
|5-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing 1 here switches the ppg logic to use the external CLK (Nim_Input[0]) (The VME interface always uses the internal clock)

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[1])

Slow-Clk bit: Writing 1 here Switches the ppg clock to a much slower one (2kHz) for low speed/long delay operation.
NOTE - this is currently ignored.

Test-mode bit: Writing 1 here Changes the outputs (LED/NIM) to simple follow the state of the Address register.

===== Address Register (0x00008) =====

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address. Also in test-Mode, the NIM/LED outputs follow the state of this register.

===== Instruction Registers (0x0000C - 0x00018) =====

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

===== Firmware Version (0x0001C) =====
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

===== Serial Flash Control (0x00020) =====
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

===== Serial Number (0x00024) =====
Returns the module serial number, and Board revision (if set) or -1

===== hardware Type (0x00028) =====
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

=== Test Software ===

==== c-shell script to run 2 nested loops ====

set dec_hex=( 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 \
0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf \
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 \
0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f \
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 )

set inst=( # dly4,loop4,dly3,loop6,dly2,end,end \
0xff 0x00 0x4 0x100000 0x0 0x0 0x0 0x200004 \
0x1 0x1 0x3 0x100000 0x0 0x0 0x0 0x200006 \
0x2 0x2 0x2 0x100000 0x0 0x0 0x0 0x300000 \
0x0 0x0 0x0 0x300000 0x0 0x0 0x0 0x000000 )

set i=0
set j=0
while( $i < $#inst )
@ j++; vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 $dec_hex[$j]
@ i++; vme_poke -a VME_A32UD -A 0x0010000c -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100010 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100014 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100018 -d VME_D32 $inst[$i]
end

# start program (from addr 0)...
vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100000 -d VME_D32 0x1

VME-PPG32

2010-11-09T06:36:33Z

Cpearson: /* Address Register (0x00008) */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [http://edev.triumf.ca/projects/edevel00022] VME-PPG32 (REA 198) project page on edev.triumf.ca
* [http://edev.triumf.ca/documents/27] Rev0 board schematics
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32] Svn repository for initial test firmware
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || Test || RW || Test Register
|-
| 1 || 0x00004 || CSR || RW || Control/Status Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Version || R || Firmware Version Register
|-
| 8 || 0x00020 || Flash || RW || Serial Flash Control Register
|-
| 9 || 0x00024 || Serial || R || Serial Number Register
|-
| 10 || 0x00028 || Hardware || R || hardware Identification Register
|}

===== Test Register (0x00000) =====

Simple Test Register - Value Written is preserved and can be read back.

===== CSR Register (0x00004) =====

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk || R/W || The PPG logic uses the external Clk
|-
|2|| Ext-Start|| R/W ||
|-
|3|| Slow-Clk || R/W ||
|-
|4|| Test-Mode || R/W ||
|-
|5-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing 1 here switches the ppg logic to use the external CLK (Nim_Input[0]) (The VME interface always uses the internal clock)

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[1])

Slow-Clk bit: Writing 1 here Switches the ppg clock to a much slower one (2kHz) for low speed/long delay operation.
NOTE - this is currently ignored.

Test-mode bit: Writing 1 here Changes the outputs (LED/NIM) to simple follow the state of the Address register.

===== Address Register (0x00008) =====

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address. Also in test-Mode, the NIM/LED outputs follow the state of this register.

===== Instruction Registers (0x0000C - 0x00018) =====

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

===== Firmware Version (0x0001C) =====
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

===== Serial Flash Control (0x00020) =====
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

===== Serial Number (0x00024) =====
Returns the module serial number, and Board revision (if set) or -1

===== hardware Type (0x00028) =====
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

VME-PPG32

2010-11-09T06:34:40Z

Cpearson: /* VME-PPG32 - pulse pattern generator VME FPGA board */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [http://edev.triumf.ca/projects/edevel00022] VME-PPG32 (REA 198) project page on edev.triumf.ca
* [http://edev.triumf.ca/documents/27] Rev0 board schematics
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32] Svn repository for initial test firmware
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

=== VME interface ===

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || Test || RW || Test Register
|-
| 1 || 0x00004 || CSR || RW || Control/Status Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Version || R || Firmware Version Register
|-
| 8 || 0x00020 || Flash || RW || Serial Flash Control Register
|-
| 9 || 0x00024 || Serial || R || Serial Number Register
|-
| 10 || 0x00028 || Hardware || R || hardware Identification Register
|}

===== Test Register (0x00000) =====

Simple Test Register - Value Written is preserved and can be read back.

===== CSR Register (0x00004) =====

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk || R/W || The PPG logic uses the external Clk
|-
|2|| Ext-Start|| R/W ||
|-
|3|| Slow-Clk || R/W ||
|-
|4|| Test-Mode || R/W ||
|-
|5-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing 1 here switches the ppg logic to use the external CLK (Nim_Input[0]) (The VME interface always uses the internal clock)

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[1])

Slow-Clk bit: Writing 1 here Switches the ppg clock to a much slower one (2kHz) for low speed/long delay operation.
NOTE - this is currently ignored.

Test-mode bit: Writing 1 here Changes the outputs (LED/NIM) to simple follow the state of the Address register.

===== Address Register (0x00008) =====

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address

===== Instruction Registers (0x0000C - 0x00018) =====

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

===== Firmware Version (0x0001C) =====
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

===== Serial Flash Control (0x00020) =====
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

===== Serial Number (0x00024) =====
Returns the module serial number, and Board revision (if set) or -1

===== hardware Type (0x00028) =====
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

VME-PPG32

2010-11-09T06:33:04Z

Cpearson: /* General characteristics */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [http://edev.triumf.ca/projects/edevel00022] VME-PPG32 (REA 198) project page on edev.triumf.ca
* [http://edev.triumf.ca/documents/27] Rev0 board schematics
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32] Svn repository for initial test firmware
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ

==== PPG characteristics ====

4k words (128bit words) of program memory.
256 entry stack.
Halt/Continue/Loop/Subroutine/Branch instructions
100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input)
fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

==== VME interface ====

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || Test || RW || Test Register
|-
| 1 || 0x00004 || CSR || RW || Control/Status Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Version || R || Firmware Version Register
|-
| 8 || 0x00020 || Flash || RW || Serial Flash Control Register
|-
| 9 || 0x00024 || Serial || R || Serial Number Register
|-
| 10 || 0x00028 || Hardware || R || hardware Identification Register
|}

=== Test Register (0x00000) ===

Simple Test Register - Value Written is preserved and can be read back.

=== CSR Register (0x00004) ===

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk || R/W || The PPG logic uses the external Clk
|-
|2|| Ext-Start|| R/W ||
|-
|3|| Slow-Clk || R/W ||
|-
|4|| Test-Mode || R/W ||
|-
|5-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing 1 here switches the ppg logic to use the external CLK (Nim_Input[0]) (The VME interface always uses the internal clock)

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[1])

Slow-Clk bit: Writing 1 here Switches the ppg clock to a much slower one (2kHz) for low speed/long delay operation.
NOTE - this is currently ignored.

Test-mode bit: Writing 1 here Changes the outputs (LED/NIM) to simple follow the state of the Address register.

=== Address Register (0x00008) ===

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address

=== Instruction Registers (0x0000C - 0x00018) ===

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

=== Firmware Version (0x0001C) ===
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

=== Serial Flash Control (0x00020) ===
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

=== Serial Number (0x00024) ===
Returns the module serial number, and Board revision (if set) or -1

=== hardware Type (0x00028) ===
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

VME-PPG32

2010-11-09T06:28:15Z

Cpearson: /* Instruction Registers (0x0000C - 0x00018) */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [http://edev.triumf.ca/projects/edevel00022] VME-PPG32 (REA 198) project page on edev.triumf.ca
* [http://edev.triumf.ca/documents/27] Rev0 board schematics
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32] Svn repository for initial test firmware
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ

==== VME interface ====

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || Test || RW || Test Register
|-
| 1 || 0x00004 || CSR || RW || Control/Status Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Version || R || Firmware Version Register
|-
| 8 || 0x00020 || Flash || RW || Serial Flash Control Register
|-
| 9 || 0x00024 || Serial || R || Serial Number Register
|-
| 10 || 0x00028 || Hardware || R || hardware Identification Register
|}

=== Test Register (0x00000) ===

Simple Test Register - Value Written is preserved and can be read back.

=== CSR Register (0x00004) ===

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk || R/W || The PPG logic uses the external Clk
|-
|2|| Ext-Start|| R/W ||
|-
|3|| Slow-Clk || R/W ||
|-
|4|| Test-Mode || R/W ||
|-
|5-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing 1 here switches the ppg logic to use the external CLK (Nim_Input[0]) (The VME interface always uses the internal clock)

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[1])

Slow-Clk bit: Writing 1 here Switches the ppg clock to a much slower one (2kHz) for low speed/long delay operation.
NOTE - this is currently ignored.

Test-mode bit: Writing 1 here Changes the outputs (LED/NIM) to simple follow the state of the Address register.

=== Address Register (0x00008) ===

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address

=== Instruction Registers (0x0000C - 0x00018) ===

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

=== Firmware Version (0x0001C) ===
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

=== Serial Flash Control (0x00020) ===
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

=== Serial Number (0x00024) ===
Returns the module serial number, and Board revision (if set) or -1

=== hardware Type (0x00028) ===
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

VME-PPG32

2010-11-09T06:25:24Z

Cpearson: /* Registers */

== VME-PPG32 - pulse pattern generator VME FPGA board ==

=== References ===

* [http://edev.triumf.ca/projects/edevel00022] VME-PPG32 (REA 198) project page on edev.triumf.ca
* [http://edev.triumf.ca/documents/27] Rev0 board schematics
* [http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32] Svn repository for initial test firmware
* [http://daq-plone.triumf.ca/HR/VME/ppg32] Current PPG firmware Source/binary

=== General characteristics ===

==== Available hardware ====

* Altera cyclone 3 FPGA: EP3C40Q240C8
* Serial flash for FPGA configuration: Altera EPCS16
* VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 32 NIM outputs
* 4 NIM inputs
* 32 "NIM output" LEDs
* 4 "NIM input" LEDs
* 1 "VME access" LED
* 2 output serial DAC: AD5439YRUZ

==== VME interface ====

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
VME registers are listed in the table below.

==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
! Number || Address || Name || Access || Description
|-
| 0 || 0x00000 || Test || RW || Test Register
|-
| 1 || 0x00004 || CSR || RW || Control/Status Register
|-
| 2 || 0x00008 || Addr || RW || Program Address Register
|-
| 3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
| 4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
| 5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
| 7 || 0x0001C || Version || R || Firmware Version Register
|-
| 8 || 0x00020 || Flash || RW || Serial Flash Control Register
|-
| 9 || 0x00024 || Serial || R || Serial Number Register
|-
| 10 || 0x00028 || Hardware || R || hardware Identification Register
|}

=== Test Register (0x00000) ===

Simple Test Register - Value Written is preserved and can be read back.

=== CSR Register (0x00004) ===

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information.
(writes to the 26 bits of status information are ignored, and overwritten on the next status update)

{| cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit || Name || Access || description
|-
|0|| Run || R/W || Run Control/Status
|-
|1|| Ext-Clk || R/W || The PPG logic uses the external Clk
|-
|2|| Ext-Start|| R/W ||
|-
|3|| Slow-Clk || R/W ||
|-
|4|| Test-Mode || R/W ||
|-
|5-31|| Status || R || Readback of PC,SP,Current Delay Counter
|}

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing 1 here switches the ppg logic to use the external CLK (Nim_Input[0]) (The VME interface always uses the internal clock)

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[1])

Slow-Clk bit: Writing 1 here Switches the ppg clock to a much slower one (2kHz) for low speed/long delay operation.
NOTE - this is currently ignored.

Test-mode bit: Writing 1 here Changes the outputs (LED/NIM) to simple follow the state of the Address register.

=== Address Register (0x00008) ===

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address

=== Instruction Registers (0x0000C - 0x00018) ===

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...
{| cellpadding="10" cellspacing="0" border="1"
|+Instruction Format
|-
!Bits 0-31 || Bits 32-63 || Bits 64-95 || Bits 96-115 || Bits 116-117 || Bits 118-127
|-
| 32 Output Set Bits || 32 Output Clear Bits || 32bit Delay Count || 20bit Data || 4bit instruction type || Ignored
|-
|}

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

The instruction types are ...
0 - Halt
1 - Continue
2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million )
3 - End Loop
4 - Call Subroutine ( 20 bit data used for address )
5 - Return from subroutine
6 - Branch ( 20 bit data used for address )

=== Firmware Version (0x0001C) ===
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

=== Serial Flash Control (0x00020) ===
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

=== Serial Number (0x00024) ===
Returns the module serial number, and Board revision (if set) or -1

=== hardware Type (0x00028) ===
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32

VME-PPG32

2010-11-09T05:49:43Z

Cpearson: /* VME-PPG32 - pulse pattern generator VME FPGA board */

VME-PPG32

2010-11-09T05:35:16Z

Cpearson: /* References */

VF48

2010-10-15T23:20:58Z

Cpearson: /* VME Mapping */

= VF48 - 48 channels@60Msps, 10bits =

== General characteristics ==
The VF48 is a one-unit wide VME 6U housing 48 channels digitized by six fast 10-bit ADCs. For each channel, the input signal (50 Ω impedance) is amplified by a high speed differential amplifier (AD8132) and them converted by the ADCs at a maximum rate of 60 Msps.

The digitized signal goes to a FPGA (Cyclone EPC12) which will calculate the charge of the signal, evaluate the exact trigger time, build an event which will contain all this information and send the event constructed to a local collector. Each FPGA manages eight channels. There are six FPGA connected to the ADCs and one FPGA which collects the data.

The board can be accessed in A24/A32/A40 addressing mode, D16, D32 and MBLT64 data transfer mode.

It has also a board available to access the VF48 throw a LVDS link. This link can transfer the data at a speed up to 100 Mbits/s. This link can afford all the control necessary to run the VF48. It can accept a clock which permits the synchronization of many VF48 units.

The board contains a trigger structure which permits to trigger the data in three different manners. The trigger can come from an external NIM signal, from a software command or from an internal mechanism. The internal mechanism manages multiple channels hit, deadtime, threshold and multiplicity and is totally programmable by the user.

[[Image:blockdigvf48.jpg|Block Diagram of the VF48]]

= VME interface =
The VF48 board can access the VME bus in VME A24. See Table 2.1.1 to have more information about the Address Modifier accepted.

{|style="color:green; background-color:#ffffcc;" cellpadding="10" cellspacing="0" border="1"
|+ Summarizes all the supported address Modifer
|-
!AM||Description
|-
|3F
|A24 supervisory block transfer (BLT)
|-
|3D
|A24 supervisory data access
|-
|3C
|A24 supervisory 64-bit block transfer (MBLT)
|-
|3B
|A24 non privileged block transfer (BLT)
|-
|39
|A24 non privileged data access
|-
|38
|A24 non privileged 64-bit block transfer (MBLT)
|-
|}

=== Base Address ===

The base address of the board is 0xA00000 + n • 0x10000. The number n is defined by the alignment of the switch on the board. For example, if the alignment on the switch is : ID[3..0] = 1011, then the base address will be 0xAB0000.

Every board will manage a window going until 0x00FFFF above the base address. In the previous example, the VME window was from 0xAB0000 to 0xABFFFF.

=== Data Transfer Capabilities ===
The board can access the VME BUS in VME_D16, VME_D32, VME 32-bit and 64-bit block transfers (BLT32 and MBLT64). The VME_D8 is not compatible. D32 is recommended for accessing collector registers and 64-bit block transfer (MBLT64) is recommended for reading data from the VME data FIFO. See VME Mapping to have more details on this.

==VME Mapping==

The Table 2.2.1 describes the VME Mapping of the VF48 collector registers. In the Table 2.2.1, the W column indicates if the register is available for a Write. The R column indicates if the register is available for a Read. The last three columns indicate permitted access modes. [X=>Any Value, N=>Any non-zero Value]

– VME Mapping
{| style="color:green; background-color:#ffffcc;" cellpadding="10" cellspacing="0" border="1"
|-!Offset ||VME Mapping ||Access ||Mode
|-
|0x000X||CSR||R/W||D32
|-
|0x001X||SSCSR ||W||D32
|-
|0x002X||TestReg||R/W||D32
|-
|0x003X||Firmware ID ||R ||D32
|-
|0x0040,1||SoftReset||W||D32
|-
|0x0044,5||Nframes(Also A0)||R||D32
|-
|0x005X||Param DAT ||W ||D32
|-
|0x006X||Param ID ||W ||D32
|-
|0x007X||Software Trigger ||W ||D16/32
|-
|0x008X||LVDS Reset||W ||D16/32
|-
|0x009X||Group Enable ||R/W ||D16/32
|-
|0x00AX||NbrFrames ||R ||D16/32
|-
|0x00BX||General Reset || W ||D16/32
|-
|0x00CX||Trigger Config A||R/W||D32
|-
|0x00DX||Trigger Config B||R/W||D32
|-
|0x00EX||Serial Program||R/W||D16/32
|-
|0xNNXX||Event Data ||R ||D32/BLT32/MBLT64
|-
|}

===CSR Description ===
Only six bits of the CSR (Control & Status Registry) are used. They are indicated in the Table 2.2.2.

{| style="color:green; background-color:#ffffcc;" cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit ||CSR Description ||Access
|-
|0|| Run ||R/W
|-
|1|| Parameter ID Ready|| R
|-
|2|| Parameter DATA Ready||R
|-
|3|| Event Fifo Empty||R
|-
|4|| ||
|-
|5||CRC Error detected || R
|-
|6|| ||
|-
|7||External Trigger || R/W
|-
|}

The RUN bit allows the system to accept triggers and start the acquisition.

The Parameter ID Ready bit and Parameter DAT Ready bit indicate if parameter is ready to be read. The parameter section will describe more precisely how these bits work.

The Event Fifo Empty bit indicates if the event fifo is empty. When this signal is low, there’s data ready to be read.

The CRC Error Detected bit indicates if a CRC Error has been detected in the serial communication on the board. This bit should never go on.

The External trigger bit selects the external trigger. If this bit is set to 1, the trigger that will start the acquisition must come from the connector on the front panel. If this bit is zero, then a real signal must be detected on one of the 48 channels if you want to have event built.

=== Firmware ID (0x000030) ===
It returns the firmware ID

===Parameter DAT (0x000050)===
Register used to write the parameter. See the section Writing/Reading Parameter for more details.

=== Parameter ID (0x000060)===
Register used to write the parameter. See the section Writing/Reading Parameter for more details.

===Soft Trigger (0x000070)===
It generates a trigger on the front end to force the system to acquire data.

===Group Enable (0x000090)===
It allows enabling a group of channels. Bit 0 enables channel 1 to 8, bit 1 enables channel 9 to 16 until bit 5 which enable channels 41 to 48. By default, they are all enabled.
2.2.7. Nbr Frames (0x0000A0)
It gives the number of data present in the event fifo. See section 4. Triggers & Events for more details.

===Global Reset (0x0000B0)===
It resets all the system.

===Event Data (0x000100-0x00FFFF)===
It reads all the data in the fifo. See section 4. Triggers & Events for more details.

= Writing/Reading Parameter =
To write a parameter, you must write the parameter ID (See Table 3.1.1) followed by the parameter Data. You write the parameter ID by doing a VME Write at the address Param ID and you write the parameter Data by doing a VME Write at the address Param DAT.

During a parameter read, it is necessary to be aware that parameter is not immediately in the register ParamDAT. The bit 2 of the CSR rises up when the parameter is ready and falls down when you read it. So, the procedure to read a parameter is this. First, you send the request by writing the parameter ID (VME Write at the address ParamID) with bit 7 set to 1. You must also send a fake data, because if you don’t send a fake data, the request will never be sent. After, you read bit 2 of the CSR until it has been set. When the bit is set, you do a VME Read at the address ParamDAT .

===Parameter Frame Header===
The first 16 bits of a frame contain information describing the contents of the parameter.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Parameter Frame Header
|-
!15|| || || ||11|| || || ||7||6|| || || || || || 0
|-
|C ||C||C||C|| D||D||D||D||R||V||P||P||P||P||P||P
|}

* C : Destination Card or Port or Cyclone
* D : Destination Channel (0-5)
* R : ReadBit
* V : Version (0- No extension; 1- Param ID 32 bit)
* P : Parameter ID

Description of the fields Parameter Frame Header:
Destination Card
Bits 11 - 8 contain the number of the card where parameter must be sent. The following table describes the direction which has to take parameter according to the number of destination of card, the number of port or the number of cyclone on the board.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Destination Cyclone
|-
!11 ||10|| 9|| 8|| Destination Cyclone ||Port
|-
|0 ||0|| 0|| 0|| Channel 1 to 8 ||0
|-
|0 ||0|| 0|| 1|| Channel 9 to 16 ||1
|-
|0 ||0|| 1|| 0|| Channel 17 to 24|| 2
|-
|0 ||0|| 1|| 1|| Channel 25 to 32|| 3
|-
|0 ||1|| 0|| 0|| Channel 33 to 40|| 4
|-
|0 ||1|| 0|| 1|| Channel 41 to 48|| 5
|-
|0 ||1|| 1|| 0|| Not used ||Not used
|-
|1 ||1|| 1|| 1|| Not used ||Not used
|}
* Destination Channel
This field is not used for the current version. We don’t care of these bits.

* ReadBit
Bit 7 indicates if command is a demand of writing or reading of the parameter. If ReadBit is HIGH, then it is a read and parameter should be sent back to the collector. If ReadBit is LOW, then it is a write and parameter should be recorded.

During a parameter read, it is necessary to be aware that parameter is not immediately in the register ParamDAT. The bit 2 of the CSR rises up when the parameter is ready and falls down when you read it.
Version Bit

This bit must be zero in this version
Parameter ID
The last six bits contains the parameter ID. Each parameter available is displayed in the Table 3.1.3

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Parameter List
|-
!ID# ||Parameter List|| Default Value|| Access
|-
|0 || || ||
|-
|1|| PED ||0x0000 ||R/W
|-
|2|| Hit Det Threshold|| 0x000A ||R/W
|-
|3|| Clip Delay ||0x0028 ||R/W
|-
|4|| PreTrigger ||0x0020 ||R/W
|-
|5|| Segment Size ||0x0100 ||R/W
|-
|6|| K ||0x0190 ||R/W
|-
|7|| L ||0x0200 ||R/W
|-
|8|| M ||0x1000 ||R/W
|-
|9|| Channel Enable ||0x00FF ||R/W
|-
|10|| Mbits 1 - Feature Enable|| 0x0000 ||R/W
|-
|11|| Mbits 2 - Feature Enable|| 0x0000 ||R/W
|-
|12|| Latency ||0x0005 ||R/W
|-
|13|| Firmware ID ||0x0207 ||R/W
|-
|14|| Attenuator ||0x0190 ||R/W
|-
|15|| Trigger Threshold|| 0x000A ||R/W
|}

=== Parameter Description ===
This section is there to describe each parameter.
1 - PED
This parameter is not used yet.
2 – Hit Detection Threshold
This parameter defines the threshold to detect a hit. If the signal given by the ADC is above this threshold value, the system will start to calculate the charge, but if the signal doesn’t reach the trigger threshold, the charge won’t be used.
3 – Clip Delay
This parameter is not used yet.
4 – Pre-Trigger
This parameter defines the number of clock where the data must be recorded before the trigger.
5 – Segment Size
This parameter defines the number of raw data that must be recorded.
6 - K
This parameter defines the peaking time. See the signal processing section for more details.
7 - L
This parameter represents the duration of the peaking time and the flat top together. See the signal processing section for more details.
8 - M
This parameter defines a multiplication factor of the convoluted signal. See the signal processing section for more details.
9 – Channel Enable
This parameter indicates the channels that must be included in the event. Bit 0 enables channel 0, bit 1 enables channel 1, so in succession until channel 7. By default, all channels are enabled.

Note: In version previous to version 2.0.7, the parameter 11 was FeatureDelay_B. This parameter doesn’t exist anymore.
10 – M_Bits
This parameter is a parameter where each bit has a different purpose. The Table 3.2.1 gives information about these bits.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Description of the MBits parameter
|-
!Bit|| Version 2.0 and more|| Version before 2.0
|-
|0|| Data Simulation|| Data Simulation
|-
|1|| Suppress Raw Data|| Supress Raw Data
|-
|2|| Select Corrected Data|| Select Corrected Data
|-
|3|| PolPlus|| PolPlus
|-
|4|| BLR Speed (bit 0)|| Disable ADC
|-
|5|| BLR Speed (bit 1)|| Fake One Data
|-
|6|| Hold BLR ||-
|-
|7|| - ||-
|-
|8|| Disable ADC ||-
|-
|9|| Offset 1 ||-
|-
|10|| Offset 2 ||-
|-
|11|| Low Gain Selection ||-
|-
|12|| Card Revision Number (bit 0) ||-
|-
|13|| Card Revision Number (bit 1) ||-
|-
|14|| Card Revision Number (bit 2) ||-
|-
|15|| Card Revision Number (bit 3) ||-
|}

The bit 0, Data Simulation, enables the simulator. If this bit is set, the simulated data will be continually sent.

The bit 1, Suppress Raw Data, suppresses the raw data independently of the segment size parameter.

The bit 2, Select Corrected Data, is not used in the current version.

The bit 3, PolPlus, is used to invert numerically the input. If the input is 0b0100010001, and the bit PolPlus set then the input will be 0b1011101110.

The bit 8, Disable ADC, disable the ADC.

The bit 5, Fake One Data, has the same use as the bit 0, Data Simulation, but it will be activated for only one valid signal.

All the other bits are reserved for future use. The names indicated represent the function that is reserved for the bit to be compatible with other project.
11 – M_Bits 2
This parameter is a parameter where each bit has a different purpose. The Table 3.2.2 gives information about these bits.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Description of the MBits 2 parameter
|-
!Bit|| Version 2.0 and more|| Version before 2.0
|-
|0|| Enable Channel Suppression ||-
|-
|1|| Doesn't send time evaluation ||-
|-
|2|| Doesn't send charge calculated ||-
|-
|3|| -||-
|-
|4|| -||-
|-
|5|| -||-
|-
|6|| -||-
|-
|7|| -||-
|-
|15..8||Sampling Rate Divider||-
|}

* bit 0, Enable Channel Suppression, disable an entire channel within a group if none of the sample values of that channel is above the hit threshold.

* bit 1, Doesn’t send charge calculated, disables the calculation of the charge. If this bit is set, the charge won’t be calculated.

* bit 2, Doesn’t send time evaluation, disables the evaluation of the time when the signals passes above the threshold. If this bis set, the time won’t be evaluated.

Note: In version previous to version 2.0.7, the parameter 11 was FeatureDelay_B. This parameter doesn’t exist anymore.
12 – Latency
This parameter defines the number of clock to be added to the pre-trigger. This parameter should represent the time between the hit detection and the trigger accepted received by the front end.
13 – Firmware ID
This parameter is firmware ID. For example, if the version is 1.0.0, it will return 0x0100. If the version is 11.12.13, it will return 0x0BCD.
14 – Attenuator
This parameter defines the attenuation of the integration. See the signal processing section for more details.
15 – Trigger Threshold
This parameter defines the threshold to accept a trigger. If the signal given by the ADC is above the threshold value, a trigger request will be sent to the collector.

= Triggers & Events=

When a trigger is accepted, the front end starts to build an event which will be transferred to the collector. Each event has the same format. This section defines this format, but before, let us defines some terms usually used in this section.

A Packet is a word of 32 bits which contains information related with an event.

An Event is a series of packet beginning with a header and ending by a trailer.

== Trigger Detection==
Each channel goes through a comparator in order to trigger the feature evaluation. The hit threshold is a positive difference of 2 ADC values separated by 2 samples (ex: 2,3,4,5,6,7  hit Thr= 6-3).
In the case the input signal has the opposite polarity, you can either reverse the input signal (the VF48 input is bipolar) or reverse the polarity by software. The polarity switch is applied to the digitized ADC values. Currrently no dedicated reverse polarity function is available. Use the example found under midas/examples/Triumf/c/fevmemodules.c/BOR function.
The acceptance of the next trigger is garanteed when there is space for one event or more. A corresponding deadtime is generated for the duration of the capture of the raw data in the frontend buffer. The buffer size is fixed at 1000 samples. Therefore the pipeline advantage starts when the event size is less than 500 samples (this limits is set by the hardware type used on the board).
There is an output signal (busy out signal) available reflecting the non acceptance of trigger by the VF48. This correspond to the "deadtime" from the raw data capture ored with the condition of the frontend buffer having no more room for a complete event.

== Event Description==
An event is broken in many packets which follow a precise order. It always has to begin with a header and end with a trailer. The header and the trailer contain the trigger number and they must be identical. The header is always followed by a timestamp. Then, for each channel enabled, it could contain the raw data, the CFD time evaluated and the charge calculated. The Table 4.2.1 shows the content of an event.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Event’s content
|-
!Packet's Type ||MSB
|-
|Event Header ||0x8
|-
|Time Stamp 1 ||0xA
|-
|Time Stamp 2 ||0xA
|-
|Channel ID ||0xC
|-
|Raw Data (of current channel) ||0x0
|-
|CFD Time (of current channel) ||0x4
|-
|Charge (of current channel) ||0x5
|-
|Channel ID ||0xC
|-
|Raw Data (of current channel) ||0x0
|-
|CFD Time (of current channel) ||0x4
|-
|Charge (of current channel) ||0x5
|-
|… ||
|-
|Channel ID ||0xC
|-
|-
|Raw Data (of current channel) ||0x0
|-
|CFD Time (of current channel) ||0x4
|-
|Charge (of current channel) ||0x5
|-
|Event Trailer ||0xE
|}

The number of raw data is configurable by the parameter Segment Size (Chan Param ID:5). The next section will describe more in detail each of these packets.

== Event Packet Format==
This section describes in detail the contents of each of the packets. Firstly, inside a packet, the 4 MSB indicates the type of packet. The next table makes the association between the MSB and the packets.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Event Packet MSB Association
|-
!Packet's Type ||MSB
|-
|Header ||0x8
|-
|Time Stamp 1 ||0xA
|-
|Time Stamp 2 ||0xA
|-
|Channel ID ||0xC
|-
|Raw Data ||0x0
|-
|CFD Time ||0x4
|-
|Charge ||0x5
|-
|Trailer ||0xE
|-
|Header Error ||0x9
|-
|Error ||0xF
|-
|Header ||0x8xxxxxxx
|}

The packet Header is always the first packet of an event. It contains the trigger number in the bits 23 to 0.

Table 4.3.2 – Header 0x8xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||0||0||0||colspan="4" align="center"|0|| T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T
|}
Trigger Number

Header Error - 0x9xxxxxxx
The Header Error packet occurs when the first packet of a group was not a Header packet. This could be caused by an internal error. If this packet is detected, the current event must be rejected. However, this packet must not happen and if it does, you should contact your supplier.

Table 4.3.3 – Header Error 0x9xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||0||0||1||colspan="4" align="center"|0||colspan="24" align="center"|Trigger Number
|}

Time Stamp - 0xAxxxxxxx
The Time Stamp packet is the second packet and the third packet of en event. It contains a 48 bits time stamps. The time between two steps is of 25 ns . Then, with a 48 bits timestamp, the maximum time measured is 7 036 874,418 seconds. Then, system can count time without completing a buckle during more than 81 days.

Table 4.3.4 – Time Stamp – 0xAxxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||0||1||0||colspan="4" align="center"|0|| colspan="24" align="center"|Time Stamp
|}

The first time stamp packet contains bit 47 to 24 and the second time stamp packet contains bits 23 to 0.
Channel ID - 0xCxxxxxxx
The channel ID packet is the first packet of a sub-event. It contains all the information to be able to identify the channel. Bit 3 to 0 indicates the channel number. This number can go from 0 to 7. It corresponds to the channel of a particular group. Then, bits 6 to 3 identify the group. They can so take a value going from 0 to 5. Bit 7 is not used in this version.

Table 4.3.5 – Channel ID – 0xC0xxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || ||11|| || ||8||7||6|| || ||3|| || ||0
|-
| 1||1||0||0||colspan="4" align="center"|0||0||0||0||0||0||0||0||0||0||0||0||0|| 0||0||0||0||0|| colspan="3" align="center"|Group||colspan="4" align="center"|Channel
|}

Data - 0x0xxxxxxx
The Data packet comes after the channel ID packet. It simply contains two data of 10 bits each. The number of data packet within an event is related to the segment size parameter (Chan Param ID: 5). It could arise problems to have a null value or an odd value of the segment size.

Table 4.3.6 – Data – 0x0xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || ||13|| || || ||9|| || || || || || || || ||0
|-
| 0||0||0||0||colspan="4" align="center"|0|| colspan="10" align="center"|Sampe n+1|| 0||0||0||0|| colspan="10" align="center"|Sample n
|}

Be careful about the position of the second data. It doesn’t start exactly to bit 16. It starts to bit 14. This is done to keep the compatibility with an ADC that would a 14 bits data.
CFD Time - 0x4xxxxxxx
The CFD Time packet is the second packet before the last packet. It contains the CFD Time.

Table 4.3.7 – CFD Time – 0x40xxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 0||1||0||0||colspan="4" align="center"|0|| colspan="24" align="center"| CFD Time
|}

Time algorithm: CDF Equivalent. The input is first clipped with a delay of 3 clocks. If the clipped signal is above the hit threshold then the maximum value of the clipped waveform is evaluated. The CFD time is then evaluated by interpolating the time at 50% charge using the two samples on either side of the 50% fraction.

Charge - 0x5xxxxxxx
The Charge Packet is the first packet before the trailer packet. It contains the charge internally calculated.

Table 4.3.8 – Charge – 0x50xxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 0||1||0||1||colspan="4" align="center"|0|| colspan="24" align="center"|Charge
|}

Trailer - 0xExxxxxxx
The trailer is always the last packet of an event. It contains the trigger number in the bits 23 to 0. The bit 28 indicates an out of sequence flag, then, if this bit is 1, that means that an internal error took place and the packet should be rejected. In theory, system is stable and this type of error should not occur.

Table 4.3.9 – Trailer – 0xExxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||1||1||0||colspan="4" align="center"|0|| colspan="24" align="center"| Trigger Number
|}

Error - 0xFxxxxxxx
The Error packet occurs when a particular packet is not at his right position. This could occur if a timestamp is missing or if a timestamp is not followed by channel. This could be caused by an internal error. If this packet is detected, the entire event must be rejected. However, this packet must not happened and if it does, you should contact your supplier.

Table 4.3.10 – Error 0x9xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||1||1||1|| colspan="28" align="center"|Invalid
|}

== Event Acquisition==
Procedure to read events is very simple. It is a question of reading the number of packet presently available by making a reading on the bus VME at the address NbrFrames. Then, a reading in burst of the number of packet available can be made. The reading of events is done in fifo mode only. This means that the reading is done always at the same address, the Event Data address.

To start the acquisition, you must set the bit 0 of the CSR to 1. To stop the acquisition, you set the bit 0 of the CSR to 0.

The system integrates a signal processing logic which calculates the charge and the precise time where the hit has been detected. In the FE FPGA the continuous flow of digitized signal samples from the ADC is directed to the signal processing logic. The signal processor runs continuously. It performs tasks equivalent to a spectroscopy amplifier connected to an analog multi-channel analyzer.

== Aux Output==
The aux_out front panel output can be set to provide a trigger output, busy output or system clock output, this function is selected by triggerconfig[3..0] and CSR[16] ...

*triggerconfig[0] = 1 sets AuxTrigDisable prevents trigger from reaching aux-out (This was for tactic)
*triggerconfig[1] = 1 Enables the self-trigger Logic (when 0 the logic is just a a simple OR of the 6 Front End trigger requests)
*triggerconfig[2] = 1 selects tigc trigger (rather than the self trigger)
*triggerconfig[3] = 1 sets the system clock to aux_out (rather than trigger)
There is also a "select busy out" signal [CSR[16]] which overrides all the above and puts the busy signal to aux_out

The triggerconfig register is 64bits wide, the remaining 60 bits are used to set the self-trigger logic
*triggerconfig[39.. 4] = GroupThresholds 6 multiplicity thresholds, of 6 bits each (0-63)
*triggerconfig[57..40] = FeGroups 6 Logical-group-id's of 3 bits each (0-7)
*triggerconfig[63..58] = GroupCoincidence 6 bits, 1 bit enabling each of the 6 logical groups

There are 6 frontend FPGAs with 8 channels each. Each frontend sends its trigger multiplicity (0-8) to the collector. There are 6 possible logical groups to assign each of the frontends to (One simple scheme would be to put all 6 frontends in a single logical group - the multiplicity from this group would then be the total multiplicity on this VF48, in this case, all 6 groupids would be the same, only 1 bit would be enabled in GroupCoincidence, and only 1 multiplicity(GroupThreshold) would need to be set)

The above trigger logic settings are currently assigned using 4 ODB variables described below ...

GroupID - Sets the Logical GroupID for each frontend
{| style="color:black; cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || ||24||23|| || || || || || |16||15|| || || || || || ||8||7|| || || || || || ||0
|-
| colspan="14" align="center"|Unused
| colspan="3" align="center"|GroupIDFe5
| colspan="3" align="center"|GroupIDFe4
| colspan="3" align="center"|GroupIDFe3
| colspan="3" align="center"|GroupIDFe2
| colspan="3" align="center"|GroupIDFe1
| colspan="3" align="center"|GroupIDFe0
|}

GroupMulti02 - Sets the required multiplicity for logical groups 0 to 2
{| style="color:black; cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || ||24||23|| || || || || || |16||15|| || || || || || ||8||7|| || || || || || ||0
|-
| colspan="14" align="center"|Unused
| colspan="6" align="center"|MultiplicityGroup2
| colspan="6" align="center"|MultiplicityGroup1
| colspan="6" align="center"|MultiplicityGroup0
|}

GroupMulti35 - Sets the required multiplicity for logical groups 3 to 5
{| style="color:black; cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || ||24||23|| || || || || || |16||15|| || || || || || ||8||7|| || || || || || ||0
|-
| colspan="14" align="center"|Unused
| colspan="6" align="center"|MultiplicityGroup5
| colspan="6" align="center"|MultiplicityGroup4
| colspan="6" align="center"|MultiplicityGroup3
|}

GroupCoincidence - Sets which logical groups multiplicities are required to be satisfied (All The groups set active here, are required in coincidence in order to get a trigger)
{| style="color:black; cellpadding="10" cellspacing="0" border="1"
!31|| ... ||16||15|| || || || || || ||8||7||6||5||4||3||2||1||0
|-
| colspan="13" align="center"|Unused
| GroupID5
| GroupID4
| GroupID3
| GroupID2
| GroupID1
| GroupID0
|}

= Signal Processing =

The system integrates a signal processing logic which calculates the charge and the precise time where the hit has been detected. In the FE FPGA the continuous flow of digitized signal samples from the ADC is directed to the signal processing logic. The signal processor runs continuously. It performs tasks equivalent to a spectroscopy amplifier connected to an analog multi-channel analyzer.

[[Image:splogic.jpg]]

== Real-Time Digital Filter and Charge Evaluation==

The filtering involves many steps. The first step is the deconvolution of the exponential tail of the pulse shape within an arbitrary time window. The moving window deconvolution method is well documented in the litterature. It is implemented as a finite impulse response filter (FIR). If D0, D1, … Dn, represent the digitized signal samples, and L the span of the moving window, the nth point of the transformed sequence Fn is given by the relation:

(1) [[Image:f1vf48.jpg]]

where τ is the exponential time constant of the signal in units of data samples. The deconvolution is useful in the case of a germanium detector to compensate for the differences in ballistic deficit as a function of the rise time of the signal. Depending on the position of the photon interaction, the charge collection time may vary from event to event by as much as 150 nanoseconds. With a preamplifier decay time constant of 50 microseconds, this translates into a fluctuation of the raw signal peak amplitude corresponding to 3 Kev for a 1 Mev gamma. With an analog system, this fluctuation is reduced significantly by using a long filter peaking time, but it never vanishes. With the moving window deconvolution method, the tail pulse shape is transformed into a quasi-rectangular pulse shape, with a duration determined by the span of the moving window. The transformed signal has a leading edge reflecting the shape of the original signal (with a slight correction for the exponential decay), and then reaches a constant maximum value that is exactly the same for a given total charge deposited in the detector whatever the rise-time. The processed signal also returns to zero with no tail.

It can be seen from equation (1) that the first two terms will cancel the DC baseline. However, the sum term that cancels exactly the exponential decay will unfortunately respond to a baseline level with a gain of L/τ. The sum term also limits the effectiveness of the low frequency filtering effect of the first two terms. To alleviate this problem, one can resort to double sampling, or use a baseline restoring scheme. We have chosen this later approach. The baseline restoring process is active only when no signal is present.

At this stage, the filtering is not yet complete. Only the low frequency part of the noise spectrum has been attenuated. The high frequency filtering is performed by applying another FIR transformation to the corrected deconvoluted signal. The most efficient filter for the evaluation of the trend of a noisy straight line (the flat part of the rectangular pulse shape) is the simple floating average transformation, commonly called a boxcar filter:

(2) [[Image:f2vf48.jpg]]

K is chosen to be as close as possible to the size of the flat portion of the rectangular pulse Fn . For a theoretical signal having a zero rise time and an exponential decay with time constant equal to τ, the sequence of points Gn represents a trapeze with a rise time of K, a flat portion of L-K, and a fall time of K. Every point of the flat top part of the pulse is a proper evaluation of the charge. Selecting the maximum value is simple, but it generates a small average bias proportional to the noise. We rather select the measurement point at a pre-determined time after the beginning of the pulse, based on the timing information produced by the CFD discriminator. This amounts to selecting the point at random (as far as the amplitude is concerned) in the flat top region, thereby reducing the bias.

Due to constraint design (the division by τ would involve excessive FPGA resources), we multiply both sides of equation (1) by τ (parameter M), and we do not normalize by the number of points. The result appearing in the event list is given by

It can be scaled down by software when the histograms are constructed.

== Digital Constant Fraction Discriminator==
Analog constant fraction discriminators (CFD) are widely used to minimize the time walk associated with the detection of signals featuring widely varying amplitudes. The same principle can be applied to digital signal samples, with some differences in the physical implementation. In the VF48 firmware, the implementation reproduces exactly the definition of a CFD: The amplitude of the signal is evaluated, and a threshold is calculated with a predefined fraction. The same signal, delayed through a digital delay line (dual port RAM), is then compared with this calculated threshold until the point immediately below, and the point immediately above the threshold are found. Then, a linear interpolation is performed to evaluate the time corresponding to the threshold crossing. We use time units of 1/16 of the ADC sampling clock period for the interpolation. Often, the rise time is not constant from event to event, as it depends on the position where the electron-holes pairs were created in the crystal. So, it is important to clip the incoming signal to a width equal or shorter than the fastest signal rise time envisioned before the CFD logic. This is achieved by subtracting two samples separated by the proper number of sampling clocks. This has the same effect as the clipping delay line of an analog CFD. The digital CFD produces two outputs: a logic signal synchronized with the ADC clock, when the constant fraction threshold is crossed, and a higher precision time stamp word. The logic signal is used by the trigger logic, whilst the time stamp is part of the event data stream.

== Latency and Event Segment Buffers==

In order to accommodate for the latency of the trigger system, a circular latency buffer is used to keep the past values of the signal samples available for a time equal or longer than the trigger decision latency. The input of the buffer is either the raw data signal, or the output of the deconvolution logic. This can be selected by a run parameter. The maximum capacity of the latency buffer is presently 512 elements. When a trigger is accepted, this delay allows the recovery of the associated signal since its very beginning. We usually also include a few samples that have occurred before the signal. The latency buffer is implemented in a dual port random access memory running continuously. The read address is equal to the write address minus the number of clock cycles we want to have the data delayed. The signal data is continuously written in the memory, and the delayed data continuously available on the readout port. When a trigger is accepted, a transfer gate is generated for a duration corresponding to the size of the data segment requested, and the data read out is transferred to the next buffer stage: the segment event buffer.

The segment buffer is a simple 1024 word FIFO that stores the waveform data segments, plus two extra bits indicating the beginning and end of these segments. The FIFO is read out asynchronously by the list formatter. The function of the Segment Buffer is to store a few events in order to deramdomize the data flow. The segment buffer also generates an almost full flag that is transmitted to the master trigger system. This is the mechanism that throttles the trigger rate when the data acquisition becomes throughput limited. When the throughput is significantly lower than the system bandwidth, the data acquisition is dead-timeless.

== Digital Constant Fraction Discriminator==
Analog constant fraction discriminators (CFD) are widely used to minimize the time walk associated with the detection of signals featuring widely varying amplitudes. The same principle can be applied to digital signal samples, with some differences in the physical implementation. In the VF48 firmware, the implementation reproduces exactly the definition of a CFD: The amplitude of the signal is evaluated, and a threshold is calculated with a predefined fraction. The same signal, delayed through a digital delay line (dual port RAM), is then compared with this calculated threshold until the point immediately below, and the point immediately above the threshold are found. Then, a linear interpolation is performed to evaluate the time corresponding to the threshold crossing. We use time units of 1/16 of the ADC sampling clock period for the interpolation. Often, the rise time is not constant from event to event, as it depends on the position where the electron-holes pairs were created in the crystal. So, it is important to clip the incoming signal to a width equal or shorter than the fastest signal rise time envisioned before the CFD logic. This is achieved by subtracting two samples separated by the proper number of sampling clocks. This has the same effect as the clipping delay line of an analog CFD. The digital CFD produces two outputs: a logic signal synchronized with the ADC clock, when the constant fraction threshold is crossed, and a higher precision time stamp word. The logic signal is used by the trigger logic, whilst the time stamp is part of the event data stream.

== Latency and Event Segment Buffers==

In order to accommodate for the latency of the trigger system, a circular latency buffer is used to keep the past values of the signal samples available for a time equal or longer than the trigger decision latency. The input of the buffer is either the raw data signal, or the output of the deconvolution logic. This can be selected by a run parameter. The maximum capacity of the latency buffer is presently 512 elements. When a trigger is accepted, this delay allows the recovery of the associated signal since its very beginning. We usually also include a few samples that have occurred before the signal. The latency buffer is implemented in a dual port random access memory running continuously. The read address is equal to the write address minus the number of clock cycles we want to have the data delayed. The signal data is continuously written in the memory, and the delayed data continuously available on the readout port. When a trigger is accepted, a transfer gate is generated for a duration corresponding to the size of the data segment requested, and the data read out is transferred to the next buffer stage: the segment event buffer.

The segment buffer is a simple 1024 word FIFO that stores the waveform data segments, plus two extra bits indicating the beginning and end of these segments. The FIFO is read out asynchronously by the list formatter. The function of the Segment Buffer is to store a few events in order to deramdomize the data flow. The segment buffer also generates an almost full flag that is transmitted to the master trigger system. This is the mechanism that throttles the trigger rate when the data acquisition becomes throughput limited. When the throughput is significantly lower than the system bandwidth, the data acquisition is dead-timeless.

= Firmware Update=

To do an update, you will need the ByteBlaster II connector connected on the parallel port of your PC and to the connector J3 on the VF48 board. (Or an USB Blaster module)

Then, you must download the programmer on the Altera Website:
https://www.altera.com/support/software/download/programming/quartus2/dnl-quartus2_programmer.jsp

Then, you start the program. You change the mode from JTAG to Active Serial Programming. You push the Hardware Setup button and you select ByteBlaster II. Then, you push the Add File button and you select the pof file that we supplied you. After, you click in the Program/Configure case and finally you push the Start button.

When the firmware has been programmed, you must unplug the ByteBlaster II connector from the VF48 board, shut down the power and put it back.

If the green light is on, programming was completed successfully. If the green light is off, did you forget to unplug the ByteBlaster II connector? If no, restart all the procedure.

== Label Convention==

A label convention is done to name each version that is created. It starts by the firmware main revision. Then, we add respectively the sub revision, the sampling frequency, the system clock frequency and the special features if they exist.

For example, the name VF48_V207_X6_40_20_Alpha.pof is associated to the firmware version 2.0.7 with a sampling frequency of 40 MHz and a system frequency of 20 MHz. The special feature Alpha signifies that this version is done specifically for Alpha project.

== Firmware history ==

VF48

2010-10-15T23:20:58Z

Cpearson: /* VME Mapping */

VF48

2010-09-17T00:05:27Z

Cpearson: /* Aux Output */

= VF48 - 48 channels@60Msps, 10bits =

== General characteristics ==
The VF48 is a one-unit wide VME 6U housing 48 channels digitized by six fast 10-bit ADCs. For each channel, the input signal (50 Ω impedance) is amplified by a high speed differential amplifier (AD8132) and them converted by the ADCs at a maximum rate of 60 Msps.

The digitized signal goes to a FPGA (Cyclone EPC12) which will calculate the charge of the signal, evaluate the exact trigger time, build an event which will contain all this information and send the event constructed to a local collector. Each FPGA manages eight channels. There are six FPGA connected to the ADCs and one FPGA which collects the data.

The board can be accessed in A24/A32/A40 addressing mode, D16, D32 and MBLT64 data transfer mode.

It has also a board available to access the VF48 throw a LVDS link. This link can transfer the data at a speed up to 100 Mbits/s. This link can afford all the control necessary to run the VF48. It can accept a clock which permits the synchronization of many VF48 units.

The board contains a trigger structure which permits to trigger the data in three different manners. The trigger can come from an external NIM signal, from a software command or from an internal mechanism. The internal mechanism manages multiple channels hit, deadtime, threshold and multiplicity and is totally programmable by the user.

[[Image:blockdigvf48.jpg|Block Diagram of the VF48]]

= VME interface =
The VF48 board can access the VME bus in VME A24. See Table 2.1.1 to have more information about the Address Modifier accepted.

{|style="color:green; background-color:#ffffcc;" cellpadding="10" cellspacing="0" border="1"
|+ Summarizes all the supported address Modifer
|-
!AM||Description
|-
|3F
|A24 supervisory block transfer (BLT)
|-
|3D
|A24 supervisory data access
|-
|3C
|A24 supervisory 64-bit block transfer (MBLT)
|-
|3B
|A24 non privileged block transfer (BLT)
|-
|39
|A24 non privileged data access
|-
|38
|A24 non privileged 64-bit block transfer (MBLT)
|-
|}

=== Base Address ===

The base address of the board is 0xA00000 + n • 0x10000. The number n is defined by the alignment of the switch on the board. For example, if the alignment on the switch is : ID[3..0] = 1011, then the base address will be 0xAB0000.

Every board will manage a window going until 0x00FFFF above the base address. In the previous example, the VME window was from 0xAB0000 to 0xABFFFF.

=== Data Transfer Capabilities ===
The board can access the VME BUS in VME_D16, VME_D32, VME 32-bit and 64-bit block transfers (BLT32 and MBLT64). The VME_D8 is not compatible. D32 is recommended for accessing collector registers and 64-bit block transfer (MBLT64) is recommended for reading data from the VME data FIFO. See VME Mapping to have more details on this.

==VME Mapping==

The Table 2.2.1 describes the VME Mapping of the VF48 collector registers. In the Table 2.2.1, the W column indicates if the register is available for a Write. The R column indicates if the register is available for a Read. The last three columns indicate permitted access modes.

– VME Mapping
{| style="color:green; background-color:#ffffcc;" cellpadding="10" cellspacing="0" border="1"
|-!Offset ||VME Mapping ||Access ||Mode
|-
|0x0000||CSR||R/W||D16/32
|-
|0x0010|| || ||
|-
|0x0020|| || ||
|-
|0x0030||Firmware ID ||R || D16/32
|-
|0x0040|| || ||
|-
|0x0050||Param DAT ||W ||D16/32
|-
|0x0060||Param ID ||W ||D16/32
|-
|0x0070||Soft Trigger ||W ||D16/32
|-
|0x0080|| || ||
|-
|0x0090||Group Enable ||R/W ||D16/32
|-
|0x00A0||NbrFrames ||R ||D16/32
|-
|0x00B0||Global Reset || W ||
|-
|0x01XX||Event Data ||R ||D32/BLT32/MBLT64
|-
|}

===CSR Description ===
Only six bits of the CSR (Control & Status Registry) are used. They are indicated in the Table 2.2.2.

{| style="color:green; background-color:#ffffcc;" cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit ||CSR Description ||Access
|-
|0|| Run ||R/W
|-
|1|| Parameter ID Ready|| R
|-
|2|| Parameter DATA Ready||R
|-
|3|| Event Fifo Empty||R
|-
|4|| ||
|-
|5||CRC Error detected || R
|-
|6|| ||
|-
|7||External Trigger || R/W
|-
|}

The RUN bit allows the system to accept triggers and start the acquisition.

The Parameter ID Ready bit and Parameter DAT Ready bit indicate if parameter is ready to be read. The parameter section will describe more precisely how these bits work.

The Event Fifo Empty bit indicates if the event fifo is empty. When this signal is low, there’s data ready to be read.

The CRC Error Detected bit indicates if a CRC Error has been detected in the serial communication on the board. This bit should never go on.

The External trigger bit selects the external trigger. If this bit is set to 1, the trigger that will start the acquisition must come from the connector on the front panel. If this bit is zero, then a real signal must be detected on one of the 48 channels if you want to have event built.

=== Firmware ID (0x000030) ===
It returns the firmware ID

===Parameter DAT (0x000050)===
Register used to write the parameter. See the section Writing/Reading Parameter for more details.

=== Parameter ID (0x000060)===
Register used to write the parameter. See the section Writing/Reading Parameter for more details.

===Soft Trigger (0x000070)===
It generates a trigger on the front end to force the system to acquire data.

===Group Enable (0x000090)===
It allows enabling a group of channels. Bit 0 enables channel 1 to 8, bit 1 enables channel 9 to 16 until bit 5 which enable channels 41 to 48. By default, they are all enabled.
2.2.7. Nbr Frames (0x0000A0)
It gives the number of data present in the event fifo. See section 4. Triggers & Events for more details.

===Global Reset (0x0000B0)===
It resets all the system.

===Event Data (0x000100-0x00FFFF)===
It reads all the data in the fifo. See section 4. Triggers & Events for more details.

= Writing/Reading Parameter =
To write a parameter, you must write the parameter ID (See Table 3.1.1) followed by the parameter Data. You write the parameter ID by doing a VME Write at the address Param ID and you write the parameter Data by doing a VME Write at the address Param DAT.

During a parameter read, it is necessary to be aware that parameter is not immediately in the register ParamDAT. The bit 2 of the CSR rises up when the parameter is ready and falls down when you read it. So, the procedure to read a parameter is this. First, you send the request by writing the parameter ID (VME Write at the address ParamID) with bit 7 set to 1. You must also send a fake data, because if you don’t send a fake data, the request will never be sent. After, you read bit 2 of the CSR until it has been set. When the bit is set, you do a VME Read at the address ParamDAT .

===Parameter Frame Header===
The first 16 bits of a frame contain information describing the contents of the parameter.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Parameter Frame Header
|-
!15|| || || ||11|| || || ||7||6|| || || || || || 0
|-
|C ||C||C||C|| D||D||D||D||R||V||P||P||P||P||P||P
|}

* C : Destination Card or Port or Cyclone
* D : Destination Channel (0-5)
* R : ReadBit
* V : Version (0- No extension; 1- Param ID 32 bit)
* P : Parameter ID

Description of the fields Parameter Frame Header:
Destination Card
Bits 11 - 8 contain the number of the card where parameter must be sent. The following table describes the direction which has to take parameter according to the number of destination of card, the number of port or the number of cyclone on the board.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Destination Cyclone
|-
!11 ||10|| 9|| 8|| Destination Cyclone ||Port
|-
|0 ||0|| 0|| 0|| Channel 1 to 8 ||0
|-
|0 ||0|| 0|| 1|| Channel 9 to 16 ||1
|-
|0 ||0|| 1|| 0|| Channel 17 to 24|| 2
|-
|0 ||0|| 1|| 1|| Channel 25 to 32|| 3
|-
|0 ||1|| 0|| 0|| Channel 33 to 40|| 4
|-
|0 ||1|| 0|| 1|| Channel 41 to 48|| 5
|-
|0 ||1|| 1|| 0|| Not used ||Not used
|-
|1 ||1|| 1|| 1|| Not used ||Not used
|}
* Destination Channel
This field is not used for the current version. We don’t care of these bits.

* ReadBit
Bit 7 indicates if command is a demand of writing or reading of the parameter. If ReadBit is HIGH, then it is a read and parameter should be sent back to the collector. If ReadBit is LOW, then it is a write and parameter should be recorded.

During a parameter read, it is necessary to be aware that parameter is not immediately in the register ParamDAT. The bit 2 of the CSR rises up when the parameter is ready and falls down when you read it.
Version Bit

This bit must be zero in this version
Parameter ID
The last six bits contains the parameter ID. Each parameter available is displayed in the Table 3.1.3

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Parameter List
|-
!ID# ||Parameter List|| Default Value|| Access
|-
|0 || || ||
|-
|1|| PED ||0x0000 ||R/W
|-
|2|| Hit Det Threshold|| 0x000A ||R/W
|-
|3|| Clip Delay ||0x0028 ||R/W
|-
|4|| PreTrigger ||0x0020 ||R/W
|-
|5|| Segment Size ||0x0100 ||R/W
|-
|6|| K ||0x0190 ||R/W
|-
|7|| L ||0x0200 ||R/W
|-
|8|| M ||0x1000 ||R/W
|-
|9|| Channel Enable ||0x00FF ||R/W
|-
|10|| Mbits 1 - Feature Enable|| 0x0000 ||R/W
|-
|11|| Mbits 2 - Feature Enable|| 0x0000 ||R/W
|-
|12|| Latency ||0x0005 ||R/W
|-
|13|| Firmware ID ||0x0207 ||R/W
|-
|14|| Attenuator ||0x0190 ||R/W
|-
|15|| Trigger Threshold|| 0x000A ||R/W
|}

=== Parameter Description ===
This section is there to describe each parameter.
1 - PED
This parameter is not used yet.
2 – Hit Detection Threshold
This parameter defines the threshold to detect a hit. If the signal given by the ADC is above this threshold value, the system will start to calculate the charge, but if the signal doesn’t reach the trigger threshold, the charge won’t be used.
3 – Clip Delay
This parameter is not used yet.
4 – Pre-Trigger
This parameter defines the number of clock where the data must be recorded before the trigger.
5 – Segment Size
This parameter defines the number of raw data that must be recorded.
6 - K
This parameter defines the peaking time. See the signal processing section for more details.
7 - L
This parameter represents the duration of the peaking time and the flat top together. See the signal processing section for more details.
8 - M
This parameter defines a multiplication factor of the convoluted signal. See the signal processing section for more details.
9 – Channel Enable
This parameter indicates the channels that must be included in the event. Bit 0 enables channel 0, bit 1 enables channel 1, so in succession until channel 7. By default, all channels are enabled.

Note: In version previous to version 2.0.7, the parameter 11 was FeatureDelay_B. This parameter doesn’t exist anymore.
10 – M_Bits
This parameter is a parameter where each bit has a different purpose. The Table 3.2.1 gives information about these bits.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Description of the MBits parameter
|-
!Bit|| Version 2.0 and more|| Version before 2.0
|-
|0|| Data Simulation|| Data Simulation
|-
|1|| Suppress Raw Data|| Supress Raw Data
|-
|2|| Select Corrected Data|| Select Corrected Data
|-
|3|| PolPlus|| PolPlus
|-
|4|| BLR Speed (bit 0)|| Disable ADC
|-
|5|| BLR Speed (bit 1)|| Fake One Data
|-
|6|| Hold BLR ||-
|-
|7|| - ||-
|-
|8|| Disable ADC ||-
|-
|9|| Offset 1 ||-
|-
|10|| Offset 2 ||-
|-
|11|| Low Gain Selection ||-
|-
|12|| Card Revision Number (bit 0) ||-
|-
|13|| Card Revision Number (bit 1) ||-
|-
|14|| Card Revision Number (bit 2) ||-
|-
|15|| Card Revision Number (bit 3) ||-
|}

The bit 0, Data Simulation, enables the simulator. If this bit is set, the simulated data will be continually sent.

The bit 1, Suppress Raw Data, suppresses the raw data independently of the segment size parameter.

The bit 2, Select Corrected Data, is not used in the current version.

The bit 3, PolPlus, is used to invert numerically the input. If the input is 0b0100010001, and the bit PolPlus set then the input will be 0b1011101110.

The bit 8, Disable ADC, disable the ADC.

The bit 5, Fake One Data, has the same use as the bit 0, Data Simulation, but it will be activated for only one valid signal.

All the other bits are reserved for future use. The names indicated represent the function that is reserved for the bit to be compatible with other project.
11 – M_Bits 2
This parameter is a parameter where each bit has a different purpose. The Table 3.2.2 gives information about these bits.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Description of the MBits 2 parameter
|-
!Bit|| Version 2.0 and more|| Version before 2.0
|-
|0|| Enable Channel Suppression ||-
|-
|1|| Doesn't send time evaluation ||-
|-
|2|| Doesn't send charge calculated ||-
|-
|3|| -||-
|-
|4|| -||-
|-
|5|| -||-
|-
|6|| -||-
|-
|7|| -||-
|-
|15..8||Sampling Rate Divider||-
|}

* bit 0, Enable Channel Suppression, disable an entire channel within a group if none of the sample values of that channel is above the hit threshold.

* bit 1, Doesn’t send charge calculated, disables the calculation of the charge. If this bit is set, the charge won’t be calculated.

* bit 2, Doesn’t send time evaluation, disables the evaluation of the time when the signals passes above the threshold. If this bis set, the time won’t be evaluated.

Note: In version previous to version 2.0.7, the parameter 11 was FeatureDelay_B. This parameter doesn’t exist anymore.
12 – Latency
This parameter defines the number of clock to be added to the pre-trigger. This parameter should represent the time between the hit detection and the trigger accepted received by the front end.
13 – Firmware ID
This parameter is firmware ID. For example, if the version is 1.0.0, it will return 0x0100. If the version is 11.12.13, it will return 0x0BCD.
14 – Attenuator
This parameter defines the attenuation of the integration. See the signal processing section for more details.
15 – Trigger Threshold
This parameter defines the threshold to accept a trigger. If the signal given by the ADC is above the threshold value, a trigger request will be sent to the collector.

= Triggers & Events=

When a trigger is accepted, the front end starts to build an event which will be transferred to the collector. Each event has the same format. This section defines this format, but before, let us defines some terms usually used in this section.

A Packet is a word of 32 bits which contains information related with an event.

An Event is a series of packet beginning with a header and ending by a trailer.

== Trigger Detection==
Each channel goes through a comparator in order to trigger the feature evaluation. The hit threshold is a positive difference of 2 ADC values separated by 2 samples (ex: 2,3,4,5,6,7  hit Thr= 6-3).
In the case the input signal has the opposite polarity, you can either reverse the input signal (the VF48 input is bipolar) or reverse the polarity by software. The polarity switch is applied to the digitized ADC values. Currrently no dedicated reverse polarity function is available. Use the example found under midas/examples/Triumf/c/fevmemodules.c/BOR function.
The acceptance of the next trigger is garanteed when there is space for one event or more. A corresponding deadtime is generated for the duration of the capture of the raw data in the frontend buffer. The buffer size is fixed at 1000 samples. Therefore the pipeline advantage starts when the event size is less than 500 samples (this limits is set by the hardware type used on the board).
There is an output signal (busy out signal) available reflecting the non acceptance of trigger by the VF48. This correspond to the "deadtime" from the raw data capture ored with the condition of the frontend buffer having no more room for a complete event.

== Event Description==
An event is broken in many packets which follow a precise order. It always has to begin with a header and end with a trailer. The header and the trailer contain the trigger number and they must be identical. The header is always followed by a timestamp. Then, for each channel enabled, it could contain the raw data, the CFD time evaluated and the charge calculated. The Table 4.2.1 shows the content of an event.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Event’s content
|-
!Packet's Type ||MSB
|-
|Event Header ||0x8
|-
|Time Stamp 1 ||0xA
|-
|Time Stamp 2 ||0xA
|-
|Channel ID ||0xC
|-
|Raw Data (of current channel) ||0x0
|-
|CFD Time (of current channel) ||0x4
|-
|Charge (of current channel) ||0x5
|-
|Channel ID ||0xC
|-
|Raw Data (of current channel) ||0x0
|-
|CFD Time (of current channel) ||0x4
|-
|Charge (of current channel) ||0x5
|-
|… ||
|-
|Channel ID ||0xC
|-
|-
|Raw Data (of current channel) ||0x0
|-
|CFD Time (of current channel) ||0x4
|-
|Charge (of current channel) ||0x5
|-
|Event Trailer ||0xE
|}

The number of raw data is configurable by the parameter Segment Size (Chan Param ID:5). The next section will describe more in detail each of these packets.

== Event Packet Format==
This section describes in detail the contents of each of the packets. Firstly, inside a packet, the 4 MSB indicates the type of packet. The next table makes the association between the MSB and the packets.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Event Packet MSB Association
|-
!Packet's Type ||MSB
|-
|Header ||0x8
|-
|Time Stamp 1 ||0xA
|-
|Time Stamp 2 ||0xA
|-
|Channel ID ||0xC
|-
|Raw Data ||0x0
|-
|CFD Time ||0x4
|-
|Charge ||0x5
|-
|Trailer ||0xE
|-
|Header Error ||0x9
|-
|Error ||0xF
|-
|Header ||0x8xxxxxxx
|}

The packet Header is always the first packet of an event. It contains the trigger number in the bits 23 to 0.

Table 4.3.2 – Header 0x8xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||0||0||0||colspan="4" align="center"|0|| T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T
|}
Trigger Number

Header Error - 0x9xxxxxxx
The Header Error packet occurs when the first packet of a group was not a Header packet. This could be caused by an internal error. If this packet is detected, the current event must be rejected. However, this packet must not happen and if it does, you should contact your supplier.

Table 4.3.3 – Header Error 0x9xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||0||0||1||colspan="4" align="center"|0||colspan="24" align="center"|Trigger Number
|}

Time Stamp - 0xAxxxxxxx
The Time Stamp packet is the second packet and the third packet of en event. It contains a 48 bits time stamps. The time between two steps is of 25 ns . Then, with a 48 bits timestamp, the maximum time measured is 7 036 874,418 seconds. Then, system can count time without completing a buckle during more than 81 days.

Table 4.3.4 – Time Stamp – 0xAxxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||0||1||0||colspan="4" align="center"|0|| colspan="24" align="center"|Time Stamp
|}

The first time stamp packet contains bit 47 to 24 and the second time stamp packet contains bits 23 to 0.
Channel ID - 0xCxxxxxxx
The channel ID packet is the first packet of a sub-event. It contains all the information to be able to identify the channel. Bit 3 to 0 indicates the channel number. This number can go from 0 to 7. It corresponds to the channel of a particular group. Then, bits 6 to 3 identify the group. They can so take a value going from 0 to 5. Bit 7 is not used in this version.

Table 4.3.5 – Channel ID – 0xC0xxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || ||11|| || ||8||7||6|| || ||3|| || ||0
|-
| 1||1||0||0||colspan="4" align="center"|0||0||0||0||0||0||0||0||0||0||0||0||0|| 0||0||0||0||0|| colspan="3" align="center"|Group||colspan="4" align="center"|Channel
|}

Data - 0x0xxxxxxx
The Data packet comes after the channel ID packet. It simply contains two data of 10 bits each. The number of data packet within an event is related to the segment size parameter (Chan Param ID: 5). It could arise problems to have a null value or an odd value of the segment size.

Table 4.3.6 – Data – 0x0xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || ||13|| || || ||9|| || || || || || || || ||0
|-
| 0||0||0||0||colspan="4" align="center"|0|| colspan="10" align="center"|Sampe n+1|| 0||0||0||0|| colspan="10" align="center"|Sample n
|}

Be careful about the position of the second data. It doesn’t start exactly to bit 16. It starts to bit 14. This is done to keep the compatibility with an ADC that would a 14 bits data.
CFD Time - 0x4xxxxxxx
The CFD Time packet is the second packet before the last packet. It contains the CFD Time.

Table 4.3.7 – CFD Time – 0x40xxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 0||1||0||0||colspan="4" align="center"|0|| colspan="24" align="center"| CFD Time
|}

Time algorithm: CDF Equivalent. The input is first clipped with a delay of 3 clocks. If the clipped signal is above the hit threshold then the maximum value of the clipped waveform is evaluated. The CFD time is then evaluated by interpolating the time at 50% charge using the two samples on either side of the 50% fraction.

Charge - 0x5xxxxxxx
The Charge Packet is the first packet before the trailer packet. It contains the charge internally calculated.

Table 4.3.8 – Charge – 0x50xxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 0||1||0||1||colspan="4" align="center"|0|| colspan="24" align="center"|Charge
|}

Trailer - 0xExxxxxxx
The trailer is always the last packet of an event. It contains the trigger number in the bits 23 to 0. The bit 28 indicates an out of sequence flag, then, if this bit is 1, that means that an internal error took place and the packet should be rejected. In theory, system is stable and this type of error should not occur.

Table 4.3.9 – Trailer – 0xExxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||1||1||0||colspan="4" align="center"|0|| colspan="24" align="center"| Trigger Number
|}

Error - 0xFxxxxxxx
The Error packet occurs when a particular packet is not at his right position. This could occur if a timestamp is missing or if a timestamp is not followed by channel. This could be caused by an internal error. If this packet is detected, the entire event must be rejected. However, this packet must not happened and if it does, you should contact your supplier.

Table 4.3.10 – Error 0x9xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||1||1||1|| colspan="28" align="center"|Invalid
|}

== Event Acquisition==
Procedure to read events is very simple. It is a question of reading the number of packet presently available by making a reading on the bus VME at the address NbrFrames. Then, a reading in burst of the number of packet available can be made. The reading of events is done in fifo mode only. This means that the reading is done always at the same address, the Event Data address.

To start the acquisition, you must set the bit 0 of the CSR to 1. To stop the acquisition, you set the bit 0 of the CSR to 0.

The system integrates a signal processing logic which calculates the charge and the precise time where the hit has been detected. In the FE FPGA the continuous flow of digitized signal samples from the ADC is directed to the signal processing logic. The signal processor runs continuously. It performs tasks equivalent to a spectroscopy amplifier connected to an analog multi-channel analyzer.

== Aux Output==
The aux_out front panel output can be set to provide a trigger output, busy output or system clock output, this function is selected by triggerconfig[3..0] and CSR[16] ...

*triggerconfig[0] = 1 sets AuxTrigDisable prevents trigger from reaching aux-out (This was for tactic)
*triggerconfig[1] = 1 Enables the self-trigger Logic (when 0 the logic is just a a simple OR of the 6 Front End trigger requests)
*triggerconfig[2] = 1 selects tigc trigger (rather than the self trigger)
*triggerconfig[3] = 1 sets the system clock to aux_out (rather than trigger)
There is also a "select busy out" signal [CSR[16]] which overrides all the above and puts the busy signal to aux_out

The triggerconfig register is 64bits wide, the remaining 60 bits are used to set the self-trigger logic
*triggerconfig[39.. 4] = GroupThresholds 6 multiplicity thresholds, of 6 bits each (0-63)
*triggerconfig[57..40] = FeGroups 6 Logical-group-id's of 3 bits each (0-7)
*triggerconfig[63..58] = GroupCoincidence 6 bits, 1 bit enabling each of the 6 logical groups

There are 6 frontend FPGAs with 8 channels each. Each frontend sends its trigger multiplicity (0-8) to the collector. There are 6 possible logical groups to assign each of the frontends to (One simple scheme would be to put all 6 frontends in a single logical group - the multiplicity from this group would then be the total multiplicity on this VF48, in this case, all 6 groupids would be the same, only 1 bit would be enabled in GroupCoincidence, and only 1 multiplicity(GroupThreshold) would need to be set)

The above trigger logic settings are currently assigned using 4 ODB variables described below ...

GroupID - Sets the Logical GroupID for each frontend
{| style="color:black; cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || ||24||23|| || || || || || |16||15|| || || || || || ||8||7|| || || || || || ||0
|-
| colspan="14" align="center"|Unused
| colspan="3" align="center"|GroupIDFe5
| colspan="3" align="center"|GroupIDFe4
| colspan="3" align="center"|GroupIDFe3
| colspan="3" align="center"|GroupIDFe2
| colspan="3" align="center"|GroupIDFe1
| colspan="3" align="center"|GroupIDFe0
|}

GroupMulti02 - Sets the required multiplicity for logical groups 0 to 2
{| style="color:black; cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || ||24||23|| || || || || || |16||15|| || || || || || ||8||7|| || || || || || ||0
|-
| colspan="14" align="center"|Unused
| colspan="6" align="center"|MultiplicityGroup2
| colspan="6" align="center"|MultiplicityGroup1
| colspan="6" align="center"|MultiplicityGroup0
|}

GroupMulti35 - Sets the required multiplicity for logical groups 3 to 5
{| style="color:black; cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || ||24||23|| || || || || || |16||15|| || || || || || ||8||7|| || || || || || ||0
|-
| colspan="14" align="center"|Unused
| colspan="6" align="center"|MultiplicityGroup5
| colspan="6" align="center"|MultiplicityGroup4
| colspan="6" align="center"|MultiplicityGroup3
|}

GroupCoincidence - Sets which logical groups multiplicities are required to be satisfied (All The groups set active here, are required in coincidence in order to get a trigger)
{| style="color:black; cellpadding="10" cellspacing="0" border="1"
!31|| ... ||16||15|| || || || || || ||8||7||6||5||4||3||2||1||0
|-
| colspan="13" align="center"|Unused
| GroupID5
| GroupID4
| GroupID3
| GroupID2
| GroupID1
| GroupID0
|}

= Signal Processing =

The system integrates a signal processing logic which calculates the charge and the precise time where the hit has been detected. In the FE FPGA the continuous flow of digitized signal samples from the ADC is directed to the signal processing logic. The signal processor runs continuously. It performs tasks equivalent to a spectroscopy amplifier connected to an analog multi-channel analyzer.

[[Image:splogic.jpg]]

== Real-Time Digital Filter and Charge Evaluation==

The filtering involves many steps. The first step is the deconvolution of the exponential tail of the pulse shape within an arbitrary time window. The moving window deconvolution method is well documented in the litterature. It is implemented as a finite impulse response filter (FIR). If D0, D1, … Dn, represent the digitized signal samples, and L the span of the moving window, the nth point of the transformed sequence Fn is given by the relation:

(1) [[Image:f1vf48.jpg]]

where τ is the exponential time constant of the signal in units of data samples. The deconvolution is useful in the case of a germanium detector to compensate for the differences in ballistic deficit as a function of the rise time of the signal. Depending on the position of the photon interaction, the charge collection time may vary from event to event by as much as 150 nanoseconds. With a preamplifier decay time constant of 50 microseconds, this translates into a fluctuation of the raw signal peak amplitude corresponding to 3 Kev for a 1 Mev gamma. With an analog system, this fluctuation is reduced significantly by using a long filter peaking time, but it never vanishes. With the moving window deconvolution method, the tail pulse shape is transformed into a quasi-rectangular pulse shape, with a duration determined by the span of the moving window. The transformed signal has a leading edge reflecting the shape of the original signal (with a slight correction for the exponential decay), and then reaches a constant maximum value that is exactly the same for a given total charge deposited in the detector whatever the rise-time. The processed signal also returns to zero with no tail.

It can be seen from equation (1) that the first two terms will cancel the DC baseline. However, the sum term that cancels exactly the exponential decay will unfortunately respond to a baseline level with a gain of L/τ. The sum term also limits the effectiveness of the low frequency filtering effect of the first two terms. To alleviate this problem, one can resort to double sampling, or use a baseline restoring scheme. We have chosen this later approach. The baseline restoring process is active only when no signal is present.

At this stage, the filtering is not yet complete. Only the low frequency part of the noise spectrum has been attenuated. The high frequency filtering is performed by applying another FIR transformation to the corrected deconvoluted signal. The most efficient filter for the evaluation of the trend of a noisy straight line (the flat part of the rectangular pulse shape) is the simple floating average transformation, commonly called a boxcar filter:

(2) [[Image:f2vf48.jpg]]

K is chosen to be as close as possible to the size of the flat portion of the rectangular pulse Fn . For a theoretical signal having a zero rise time and an exponential decay with time constant equal to τ, the sequence of points Gn represents a trapeze with a rise time of K, a flat portion of L-K, and a fall time of K. Every point of the flat top part of the pulse is a proper evaluation of the charge. Selecting the maximum value is simple, but it generates a small average bias proportional to the noise. We rather select the measurement point at a pre-determined time after the beginning of the pulse, based on the timing information produced by the CFD discriminator. This amounts to selecting the point at random (as far as the amplitude is concerned) in the flat top region, thereby reducing the bias.

Due to constraint design (the division by τ would involve excessive FPGA resources), we multiply both sides of equation (1) by τ (parameter M), and we do not normalize by the number of points. The result appearing in the event list is given by

It can be scaled down by software when the histograms are constructed.

== Digital Constant Fraction Discriminator==
Analog constant fraction discriminators (CFD) are widely used to minimize the time walk associated with the detection of signals featuring widely varying amplitudes. The same principle can be applied to digital signal samples, with some differences in the physical implementation. In the VF48 firmware, the implementation reproduces exactly the definition of a CFD: The amplitude of the signal is evaluated, and a threshold is calculated with a predefined fraction. The same signal, delayed through a digital delay line (dual port RAM), is then compared with this calculated threshold until the point immediately below, and the point immediately above the threshold are found. Then, a linear interpolation is performed to evaluate the time corresponding to the threshold crossing. We use time units of 1/16 of the ADC sampling clock period for the interpolation. Often, the rise time is not constant from event to event, as it depends on the position where the electron-holes pairs were created in the crystal. So, it is important to clip the incoming signal to a width equal or shorter than the fastest signal rise time envisioned before the CFD logic. This is achieved by subtracting two samples separated by the proper number of sampling clocks. This has the same effect as the clipping delay line of an analog CFD. The digital CFD produces two outputs: a logic signal synchronized with the ADC clock, when the constant fraction threshold is crossed, and a higher precision time stamp word. The logic signal is used by the trigger logic, whilst the time stamp is part of the event data stream.

== Latency and Event Segment Buffers==

In order to accommodate for the latency of the trigger system, a circular latency buffer is used to keep the past values of the signal samples available for a time equal or longer than the trigger decision latency. The input of the buffer is either the raw data signal, or the output of the deconvolution logic. This can be selected by a run parameter. The maximum capacity of the latency buffer is presently 512 elements. When a trigger is accepted, this delay allows the recovery of the associated signal since its very beginning. We usually also include a few samples that have occurred before the signal. The latency buffer is implemented in a dual port random access memory running continuously. The read address is equal to the write address minus the number of clock cycles we want to have the data delayed. The signal data is continuously written in the memory, and the delayed data continuously available on the readout port. When a trigger is accepted, a transfer gate is generated for a duration corresponding to the size of the data segment requested, and the data read out is transferred to the next buffer stage: the segment event buffer.

The segment buffer is a simple 1024 word FIFO that stores the waveform data segments, plus two extra bits indicating the beginning and end of these segments. The FIFO is read out asynchronously by the list formatter. The function of the Segment Buffer is to store a few events in order to deramdomize the data flow. The segment buffer also generates an almost full flag that is transmitted to the master trigger system. This is the mechanism that throttles the trigger rate when the data acquisition becomes throughput limited. When the throughput is significantly lower than the system bandwidth, the data acquisition is dead-timeless.

== Digital Constant Fraction Discriminator==
Analog constant fraction discriminators (CFD) are widely used to minimize the time walk associated with the detection of signals featuring widely varying amplitudes. The same principle can be applied to digital signal samples, with some differences in the physical implementation. In the VF48 firmware, the implementation reproduces exactly the definition of a CFD: The amplitude of the signal is evaluated, and a threshold is calculated with a predefined fraction. The same signal, delayed through a digital delay line (dual port RAM), is then compared with this calculated threshold until the point immediately below, and the point immediately above the threshold are found. Then, a linear interpolation is performed to evaluate the time corresponding to the threshold crossing. We use time units of 1/16 of the ADC sampling clock period for the interpolation. Often, the rise time is not constant from event to event, as it depends on the position where the electron-holes pairs were created in the crystal. So, it is important to clip the incoming signal to a width equal or shorter than the fastest signal rise time envisioned before the CFD logic. This is achieved by subtracting two samples separated by the proper number of sampling clocks. This has the same effect as the clipping delay line of an analog CFD. The digital CFD produces two outputs: a logic signal synchronized with the ADC clock, when the constant fraction threshold is crossed, and a higher precision time stamp word. The logic signal is used by the trigger logic, whilst the time stamp is part of the event data stream.

== Latency and Event Segment Buffers==

In order to accommodate for the latency of the trigger system, a circular latency buffer is used to keep the past values of the signal samples available for a time equal or longer than the trigger decision latency. The input of the buffer is either the raw data signal, or the output of the deconvolution logic. This can be selected by a run parameter. The maximum capacity of the latency buffer is presently 512 elements. When a trigger is accepted, this delay allows the recovery of the associated signal since its very beginning. We usually also include a few samples that have occurred before the signal. The latency buffer is implemented in a dual port random access memory running continuously. The read address is equal to the write address minus the number of clock cycles we want to have the data delayed. The signal data is continuously written in the memory, and the delayed data continuously available on the readout port. When a trigger is accepted, a transfer gate is generated for a duration corresponding to the size of the data segment requested, and the data read out is transferred to the next buffer stage: the segment event buffer.

The segment buffer is a simple 1024 word FIFO that stores the waveform data segments, plus two extra bits indicating the beginning and end of these segments. The FIFO is read out asynchronously by the list formatter. The function of the Segment Buffer is to store a few events in order to deramdomize the data flow. The segment buffer also generates an almost full flag that is transmitted to the master trigger system. This is the mechanism that throttles the trigger rate when the data acquisition becomes throughput limited. When the throughput is significantly lower than the system bandwidth, the data acquisition is dead-timeless.

= Firmware Update=

To do an update, you will need the ByteBlaster II connector connected on the parallel port of your PC and to the connector J3 on the VF48 board. (Or an USB Blaster module)

Then, you must download the programmer on the Altera Website:
https://www.altera.com/support/software/download/programming/quartus2/dnl-quartus2_programmer.jsp

Then, you start the program. You change the mode from JTAG to Active Serial Programming. You push the Hardware Setup button and you select ByteBlaster II. Then, you push the Add File button and you select the pof file that we supplied you. After, you click in the Program/Configure case and finally you push the Start button.

When the firmware has been programmed, you must unplug the ByteBlaster II connector from the VF48 board, shut down the power and put it back.

If the green light is on, programming was completed successfully. If the green light is off, did you forget to unplug the ByteBlaster II connector? If no, restart all the procedure.

== Label Convention==

A label convention is done to name each version that is created. It starts by the firmware main revision. Then, we add respectively the sub revision, the sampling frequency, the system clock frequency and the special features if they exist.

For example, the name VF48_V207_X6_40_20_Alpha.pof is associated to the firmware version 2.0.7 with a sampling frequency of 40 MHz and a system frequency of 20 MHz. The special feature Alpha signifies that this version is done specifically for Alpha project.

== Firmware history ==

VF48

2010-09-17T00:05:27Z

Cpearson: /* Aux Output */

= VF48 - 48 channels@60Msps, 10bits =

== General characteristics ==
The VF48 is a one-unit wide VME 6U housing 48 channels digitized by six fast 10-bit ADCs. For each channel, the input signal (50 Ω impedance) is amplified by a high speed differential amplifier (AD8132) and them converted by the ADCs at a maximum rate of 60 Msps.

The digitized signal goes to a FPGA (Cyclone EPC12) which will calculate the charge of the signal, evaluate the exact trigger time, build an event which will contain all this information and send the event constructed to a local collector. Each FPGA manages eight channels. There are six FPGA connected to the ADCs and one FPGA which collects the data.

The board can be accessed in A24/A32/A40 addressing mode, D16, D32 and MBLT64 data transfer mode.

It has also a board available to access the VF48 throw a LVDS link. This link can transfer the data at a speed up to 100 Mbits/s. This link can afford all the control necessary to run the VF48. It can accept a clock which permits the synchronization of many VF48 units.

The board contains a trigger structure which permits to trigger the data in three different manners. The trigger can come from an external NIM signal, from a software command or from an internal mechanism. The internal mechanism manages multiple channels hit, deadtime, threshold and multiplicity and is totally programmable by the user.

[[Image:blockdigvf48.jpg|Block Diagram of the VF48]]

= VME interface =
The VF48 board can access the VME bus in VME A24. See Table 2.1.1 to have more information about the Address Modifier accepted.

{|style="color:green; background-color:#ffffcc;" cellpadding="10" cellspacing="0" border="1"
|+ Summarizes all the supported address Modifer
|-
!AM||Description
|-
|3F
|A24 supervisory block transfer (BLT)
|-
|3D
|A24 supervisory data access
|-
|3C
|A24 supervisory 64-bit block transfer (MBLT)
|-
|3B
|A24 non privileged block transfer (BLT)
|-
|39
|A24 non privileged data access
|-
|38
|A24 non privileged 64-bit block transfer (MBLT)
|-
|}

=== Base Address ===

The base address of the board is 0xA00000 + n • 0x10000. The number n is defined by the alignment of the switch on the board. For example, if the alignment on the switch is : ID[3..0] = 1011, then the base address will be 0xAB0000.

Every board will manage a window going until 0x00FFFF above the base address. In the previous example, the VME window was from 0xAB0000 to 0xABFFFF.

=== Data Transfer Capabilities ===
The board can access the VME BUS in VME_D16, VME_D32, VME 32-bit and 64-bit block transfers (BLT32 and MBLT64). The VME_D8 is not compatible. D32 is recommended for accessing collector registers and 64-bit block transfer (MBLT64) is recommended for reading data from the VME data FIFO. See VME Mapping to have more details on this.

==VME Mapping==

The Table 2.2.1 describes the VME Mapping of the VF48 collector registers. In the Table 2.2.1, the W column indicates if the register is available for a Write. The R column indicates if the register is available for a Read. The last three columns indicate permitted access modes.

– VME Mapping
{| style="color:green; background-color:#ffffcc;" cellpadding="10" cellspacing="0" border="1"
|-!Offset ||VME Mapping ||Access ||Mode
|-
|0x0000||CSR||R/W||D16/32
|-
|0x0010|| || ||
|-
|0x0020|| || ||
|-
|0x0030||Firmware ID ||R || D16/32
|-
|0x0040|| || ||
|-
|0x0050||Param DAT ||W ||D16/32
|-
|0x0060||Param ID ||W ||D16/32
|-
|0x0070||Soft Trigger ||W ||D16/32
|-
|0x0080|| || ||
|-
|0x0090||Group Enable ||R/W ||D16/32
|-
|0x00A0||NbrFrames ||R ||D16/32
|-
|0x00B0||Global Reset || W ||
|-
|0x01XX||Event Data ||R ||D32/BLT32/MBLT64
|-
|}

===CSR Description ===
Only six bits of the CSR (Control & Status Registry) are used. They are indicated in the Table 2.2.2.

{| style="color:green; background-color:#ffffcc;" cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit ||CSR Description ||Access
|-
|0|| Run ||R/W
|-
|1|| Parameter ID Ready|| R
|-
|2|| Parameter DATA Ready||R
|-
|3|| Event Fifo Empty||R
|-
|4|| ||
|-
|5||CRC Error detected || R
|-
|6|| ||
|-
|7||External Trigger || R/W
|-
|}

The RUN bit allows the system to accept triggers and start the acquisition.

The Parameter ID Ready bit and Parameter DAT Ready bit indicate if parameter is ready to be read. The parameter section will describe more precisely how these bits work.

The Event Fifo Empty bit indicates if the event fifo is empty. When this signal is low, there’s data ready to be read.

The CRC Error Detected bit indicates if a CRC Error has been detected in the serial communication on the board. This bit should never go on.

The External trigger bit selects the external trigger. If this bit is set to 1, the trigger that will start the acquisition must come from the connector on the front panel. If this bit is zero, then a real signal must be detected on one of the 48 channels if you want to have event built.

=== Firmware ID (0x000030) ===
It returns the firmware ID

===Parameter DAT (0x000050)===
Register used to write the parameter. See the section Writing/Reading Parameter for more details.

=== Parameter ID (0x000060)===
Register used to write the parameter. See the section Writing/Reading Parameter for more details.

===Soft Trigger (0x000070)===
It generates a trigger on the front end to force the system to acquire data.

===Group Enable (0x000090)===
It allows enabling a group of channels. Bit 0 enables channel 1 to 8, bit 1 enables channel 9 to 16 until bit 5 which enable channels 41 to 48. By default, they are all enabled.
2.2.7. Nbr Frames (0x0000A0)
It gives the number of data present in the event fifo. See section 4. Triggers & Events for more details.

===Global Reset (0x0000B0)===
It resets all the system.

===Event Data (0x000100-0x00FFFF)===
It reads all the data in the fifo. See section 4. Triggers & Events for more details.

= Writing/Reading Parameter =
To write a parameter, you must write the parameter ID (See Table 3.1.1) followed by the parameter Data. You write the parameter ID by doing a VME Write at the address Param ID and you write the parameter Data by doing a VME Write at the address Param DAT.

During a parameter read, it is necessary to be aware that parameter is not immediately in the register ParamDAT. The bit 2 of the CSR rises up when the parameter is ready and falls down when you read it. So, the procedure to read a parameter is this. First, you send the request by writing the parameter ID (VME Write at the address ParamID) with bit 7 set to 1. You must also send a fake data, because if you don’t send a fake data, the request will never be sent. After, you read bit 2 of the CSR until it has been set. When the bit is set, you do a VME Read at the address ParamDAT .

===Parameter Frame Header===
The first 16 bits of a frame contain information describing the contents of the parameter.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Parameter Frame Header
|-
!15|| || || ||11|| || || ||7||6|| || || || || || 0
|-
|C ||C||C||C|| D||D||D||D||R||V||P||P||P||P||P||P
|}

* C : Destination Card or Port or Cyclone
* D : Destination Channel (0-5)
* R : ReadBit
* V : Version (0- No extension; 1- Param ID 32 bit)
* P : Parameter ID

Description of the fields Parameter Frame Header:
Destination Card
Bits 11 - 8 contain the number of the card where parameter must be sent. The following table describes the direction which has to take parameter according to the number of destination of card, the number of port or the number of cyclone on the board.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Destination Cyclone
|-
!11 ||10|| 9|| 8|| Destination Cyclone ||Port
|-
|0 ||0|| 0|| 0|| Channel 1 to 8 ||0
|-
|0 ||0|| 0|| 1|| Channel 9 to 16 ||1
|-
|0 ||0|| 1|| 0|| Channel 17 to 24|| 2
|-
|0 ||0|| 1|| 1|| Channel 25 to 32|| 3
|-
|0 ||1|| 0|| 0|| Channel 33 to 40|| 4
|-
|0 ||1|| 0|| 1|| Channel 41 to 48|| 5
|-
|0 ||1|| 1|| 0|| Not used ||Not used
|-
|1 ||1|| 1|| 1|| Not used ||Not used
|}
* Destination Channel
This field is not used for the current version. We don’t care of these bits.

* ReadBit
Bit 7 indicates if command is a demand of writing or reading of the parameter. If ReadBit is HIGH, then it is a read and parameter should be sent back to the collector. If ReadBit is LOW, then it is a write and parameter should be recorded.

During a parameter read, it is necessary to be aware that parameter is not immediately in the register ParamDAT. The bit 2 of the CSR rises up when the parameter is ready and falls down when you read it.
Version Bit

This bit must be zero in this version
Parameter ID
The last six bits contains the parameter ID. Each parameter available is displayed in the Table 3.1.3

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Parameter List
|-
!ID# ||Parameter List|| Default Value|| Access
|-
|0 || || ||
|-
|1|| PED ||0x0000 ||R/W
|-
|2|| Hit Det Threshold|| 0x000A ||R/W
|-
|3|| Clip Delay ||0x0028 ||R/W
|-
|4|| PreTrigger ||0x0020 ||R/W
|-
|5|| Segment Size ||0x0100 ||R/W
|-
|6|| K ||0x0190 ||R/W
|-
|7|| L ||0x0200 ||R/W
|-
|8|| M ||0x1000 ||R/W
|-
|9|| Channel Enable ||0x00FF ||R/W
|-
|10|| Mbits 1 - Feature Enable|| 0x0000 ||R/W
|-
|11|| Mbits 2 - Feature Enable|| 0x0000 ||R/W
|-
|12|| Latency ||0x0005 ||R/W
|-
|13|| Firmware ID ||0x0207 ||R/W
|-
|14|| Attenuator ||0x0190 ||R/W
|-
|15|| Trigger Threshold|| 0x000A ||R/W
|}

=== Parameter Description ===
This section is there to describe each parameter.
1 - PED
This parameter is not used yet.
2 – Hit Detection Threshold
This parameter defines the threshold to detect a hit. If the signal given by the ADC is above this threshold value, the system will start to calculate the charge, but if the signal doesn’t reach the trigger threshold, the charge won’t be used.
3 – Clip Delay
This parameter is not used yet.
4 – Pre-Trigger
This parameter defines the number of clock where the data must be recorded before the trigger.
5 – Segment Size
This parameter defines the number of raw data that must be recorded.
6 - K
This parameter defines the peaking time. See the signal processing section for more details.
7 - L
This parameter represents the duration of the peaking time and the flat top together. See the signal processing section for more details.
8 - M
This parameter defines a multiplication factor of the convoluted signal. See the signal processing section for more details.
9 – Channel Enable
This parameter indicates the channels that must be included in the event. Bit 0 enables channel 0, bit 1 enables channel 1, so in succession until channel 7. By default, all channels are enabled.

Note: In version previous to version 2.0.7, the parameter 11 was FeatureDelay_B. This parameter doesn’t exist anymore.
10 – M_Bits
This parameter is a parameter where each bit has a different purpose. The Table 3.2.1 gives information about these bits.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Description of the MBits parameter
|-
!Bit|| Version 2.0 and more|| Version before 2.0
|-
|0|| Data Simulation|| Data Simulation
|-
|1|| Suppress Raw Data|| Supress Raw Data
|-
|2|| Select Corrected Data|| Select Corrected Data
|-
|3|| PolPlus|| PolPlus
|-
|4|| BLR Speed (bit 0)|| Disable ADC
|-
|5|| BLR Speed (bit 1)|| Fake One Data
|-
|6|| Hold BLR ||-
|-
|7|| - ||-
|-
|8|| Disable ADC ||-
|-
|9|| Offset 1 ||-
|-
|10|| Offset 2 ||-
|-
|11|| Low Gain Selection ||-
|-
|12|| Card Revision Number (bit 0) ||-
|-
|13|| Card Revision Number (bit 1) ||-
|-
|14|| Card Revision Number (bit 2) ||-
|-
|15|| Card Revision Number (bit 3) ||-
|}

The bit 0, Data Simulation, enables the simulator. If this bit is set, the simulated data will be continually sent.

The bit 1, Suppress Raw Data, suppresses the raw data independently of the segment size parameter.

The bit 2, Select Corrected Data, is not used in the current version.

The bit 3, PolPlus, is used to invert numerically the input. If the input is 0b0100010001, and the bit PolPlus set then the input will be 0b1011101110.

The bit 8, Disable ADC, disable the ADC.

The bit 5, Fake One Data, has the same use as the bit 0, Data Simulation, but it will be activated for only one valid signal.

All the other bits are reserved for future use. The names indicated represent the function that is reserved for the bit to be compatible with other project.
11 – M_Bits 2
This parameter is a parameter where each bit has a different purpose. The Table 3.2.2 gives information about these bits.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Description of the MBits 2 parameter
|-
!Bit|| Version 2.0 and more|| Version before 2.0
|-
|0|| Enable Channel Suppression ||-
|-
|1|| Doesn't send time evaluation ||-
|-
|2|| Doesn't send charge calculated ||-
|-
|3|| -||-
|-
|4|| -||-
|-
|5|| -||-
|-
|6|| -||-
|-
|7|| -||-
|-
|15..8||Sampling Rate Divider||-
|}

* bit 0, Enable Channel Suppression, disable an entire channel within a group if none of the sample values of that channel is above the hit threshold.

* bit 1, Doesn’t send charge calculated, disables the calculation of the charge. If this bit is set, the charge won’t be calculated.

* bit 2, Doesn’t send time evaluation, disables the evaluation of the time when the signals passes above the threshold. If this bis set, the time won’t be evaluated.

Note: In version previous to version 2.0.7, the parameter 11 was FeatureDelay_B. This parameter doesn’t exist anymore.
12 – Latency
This parameter defines the number of clock to be added to the pre-trigger. This parameter should represent the time between the hit detection and the trigger accepted received by the front end.
13 – Firmware ID
This parameter is firmware ID. For example, if the version is 1.0.0, it will return 0x0100. If the version is 11.12.13, it will return 0x0BCD.
14 – Attenuator
This parameter defines the attenuation of the integration. See the signal processing section for more details.
15 – Trigger Threshold
This parameter defines the threshold to accept a trigger. If the signal given by the ADC is above the threshold value, a trigger request will be sent to the collector.

= Triggers & Events=

When a trigger is accepted, the front end starts to build an event which will be transferred to the collector. Each event has the same format. This section defines this format, but before, let us defines some terms usually used in this section.

A Packet is a word of 32 bits which contains information related with an event.

An Event is a series of packet beginning with a header and ending by a trailer.

== Trigger Detection==
Each channel goes through a comparator in order to trigger the feature evaluation. The hit threshold is a positive difference of 2 ADC values separated by 2 samples (ex: 2,3,4,5,6,7  hit Thr= 6-3).
In the case the input signal has the opposite polarity, you can either reverse the input signal (the VF48 input is bipolar) or reverse the polarity by software. The polarity switch is applied to the digitized ADC values. Currrently no dedicated reverse polarity function is available. Use the example found under midas/examples/Triumf/c/fevmemodules.c/BOR function.
The acceptance of the next trigger is garanteed when there is space for one event or more. A corresponding deadtime is generated for the duration of the capture of the raw data in the frontend buffer. The buffer size is fixed at 1000 samples. Therefore the pipeline advantage starts when the event size is less than 500 samples (this limits is set by the hardware type used on the board).
There is an output signal (busy out signal) available reflecting the non acceptance of trigger by the VF48. This correspond to the "deadtime" from the raw data capture ored with the condition of the frontend buffer having no more room for a complete event.

== Event Description==
An event is broken in many packets which follow a precise order. It always has to begin with a header and end with a trailer. The header and the trailer contain the trigger number and they must be identical. The header is always followed by a timestamp. Then, for each channel enabled, it could contain the raw data, the CFD time evaluated and the charge calculated. The Table 4.2.1 shows the content of an event.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Event’s content
|-
!Packet's Type ||MSB
|-
|Event Header ||0x8
|-
|Time Stamp 1 ||0xA
|-
|Time Stamp 2 ||0xA
|-
|Channel ID ||0xC
|-
|Raw Data (of current channel) ||0x0
|-
|CFD Time (of current channel) ||0x4
|-
|Charge (of current channel) ||0x5
|-
|Channel ID ||0xC
|-
|Raw Data (of current channel) ||0x0
|-
|CFD Time (of current channel) ||0x4
|-
|Charge (of current channel) ||0x5
|-
|… ||
|-
|Channel ID ||0xC
|-
|-
|Raw Data (of current channel) ||0x0
|-
|CFD Time (of current channel) ||0x4
|-
|Charge (of current channel) ||0x5
|-
|Event Trailer ||0xE
|}

The number of raw data is configurable by the parameter Segment Size (Chan Param ID:5). The next section will describe more in detail each of these packets.

== Event Packet Format==
This section describes in detail the contents of each of the packets. Firstly, inside a packet, the 4 MSB indicates the type of packet. The next table makes the association between the MSB and the packets.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Event Packet MSB Association
|-
!Packet's Type ||MSB
|-
|Header ||0x8
|-
|Time Stamp 1 ||0xA
|-
|Time Stamp 2 ||0xA
|-
|Channel ID ||0xC
|-
|Raw Data ||0x0
|-
|CFD Time ||0x4
|-
|Charge ||0x5
|-
|Trailer ||0xE
|-
|Header Error ||0x9
|-
|Error ||0xF
|-
|Header ||0x8xxxxxxx
|}

The packet Header is always the first packet of an event. It contains the trigger number in the bits 23 to 0.

Table 4.3.2 – Header 0x8xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||0||0||0||colspan="4" align="center"|0|| T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T
|}
Trigger Number

Header Error - 0x9xxxxxxx
The Header Error packet occurs when the first packet of a group was not a Header packet. This could be caused by an internal error. If this packet is detected, the current event must be rejected. However, this packet must not happen and if it does, you should contact your supplier.

Table 4.3.3 – Header Error 0x9xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||0||0||1||colspan="4" align="center"|0||colspan="24" align="center"|Trigger Number
|}

Time Stamp - 0xAxxxxxxx
The Time Stamp packet is the second packet and the third packet of en event. It contains a 48 bits time stamps. The time between two steps is of 25 ns . Then, with a 48 bits timestamp, the maximum time measured is 7 036 874,418 seconds. Then, system can count time without completing a buckle during more than 81 days.

Table 4.3.4 – Time Stamp – 0xAxxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||0||1||0||colspan="4" align="center"|0|| colspan="24" align="center"|Time Stamp
|}

The first time stamp packet contains bit 47 to 24 and the second time stamp packet contains bits 23 to 0.
Channel ID - 0xCxxxxxxx
The channel ID packet is the first packet of a sub-event. It contains all the information to be able to identify the channel. Bit 3 to 0 indicates the channel number. This number can go from 0 to 7. It corresponds to the channel of a particular group. Then, bits 6 to 3 identify the group. They can so take a value going from 0 to 5. Bit 7 is not used in this version.

Table 4.3.5 – Channel ID – 0xC0xxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || ||11|| || ||8||7||6|| || ||3|| || ||0
|-
| 1||1||0||0||colspan="4" align="center"|0||0||0||0||0||0||0||0||0||0||0||0||0|| 0||0||0||0||0|| colspan="3" align="center"|Group||colspan="4" align="center"|Channel
|}

Data - 0x0xxxxxxx
The Data packet comes after the channel ID packet. It simply contains two data of 10 bits each. The number of data packet within an event is related to the segment size parameter (Chan Param ID: 5). It could arise problems to have a null value or an odd value of the segment size.

Table 4.3.6 – Data – 0x0xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || ||13|| || || ||9|| || || || || || || || ||0
|-
| 0||0||0||0||colspan="4" align="center"|0|| colspan="10" align="center"|Sampe n+1|| 0||0||0||0|| colspan="10" align="center"|Sample n
|}

Be careful about the position of the second data. It doesn’t start exactly to bit 16. It starts to bit 14. This is done to keep the compatibility with an ADC that would a 14 bits data.
CFD Time - 0x4xxxxxxx
The CFD Time packet is the second packet before the last packet. It contains the CFD Time.

Table 4.3.7 – CFD Time – 0x40xxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 0||1||0||0||colspan="4" align="center"|0|| colspan="24" align="center"| CFD Time
|}

Time algorithm: CDF Equivalent. The input is first clipped with a delay of 3 clocks. If the clipped signal is above the hit threshold then the maximum value of the clipped waveform is evaluated. The CFD time is then evaluated by interpolating the time at 50% charge using the two samples on either side of the 50% fraction.

Charge - 0x5xxxxxxx
The Charge Packet is the first packet before the trailer packet. It contains the charge internally calculated.

Table 4.3.8 – Charge – 0x50xxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 0||1||0||1||colspan="4" align="center"|0|| colspan="24" align="center"|Charge
|}

Trailer - 0xExxxxxxx
The trailer is always the last packet of an event. It contains the trigger number in the bits 23 to 0. The bit 28 indicates an out of sequence flag, then, if this bit is 1, that means that an internal error took place and the packet should be rejected. In theory, system is stable and this type of error should not occur.

Table 4.3.9 – Trailer – 0xExxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||1||1||0||colspan="4" align="center"|0|| colspan="24" align="center"| Trigger Number
|}

Error - 0xFxxxxxxx
The Error packet occurs when a particular packet is not at his right position. This could occur if a timestamp is missing or if a timestamp is not followed by channel. This could be caused by an internal error. If this packet is detected, the entire event must be rejected. However, this packet must not happened and if it does, you should contact your supplier.

Table 4.3.10 – Error 0x9xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||1||1||1|| colspan="28" align="center"|Invalid
|}

== Event Acquisition==
Procedure to read events is very simple. It is a question of reading the number of packet presently available by making a reading on the bus VME at the address NbrFrames. Then, a reading in burst of the number of packet available can be made. The reading of events is done in fifo mode only. This means that the reading is done always at the same address, the Event Data address.

To start the acquisition, you must set the bit 0 of the CSR to 1. To stop the acquisition, you set the bit 0 of the CSR to 0.

The system integrates a signal processing logic which calculates the charge and the precise time where the hit has been detected. In the FE FPGA the continuous flow of digitized signal samples from the ADC is directed to the signal processing logic. The signal processor runs continuously. It performs tasks equivalent to a spectroscopy amplifier connected to an analog multi-channel analyzer.

== Aux Output==
The aux_out front panel output can be set to provide a trigger output, busy output or system clock output, this function is selected by triggerconfig[3..0] and CSR[16] ...

*triggerconfig[0] = 1 sets AuxTrigDisable prevents trigger from reaching aux-out (This was for tactic)
*triggerconfig[1] = 1 Enables the self-trigger Logic (when 0 the logic is just a a simple OR of the 6 Front End trigger requests)
*triggerconfig[2] = 1 selects tigc trigger (rather than the self trigger)
*triggerconfig[3] = 1 sets the system clock to aux_out (rather than trigger)
There is also a "select busy out" signal [CSR[16]] which overrides all the above and puts the busy signal to aux_out

The triggerconfig register is 64bits wide, the remaining 60 bits are used to set the self-trigger logic
*triggerconfig[39.. 4] = GroupThresholds 6 multiplicity thresholds, of 6 bits each (0-63)
*triggerconfig[57..40] = FeGroups 6 Logical-group-id's of 3 bits each (0-7)
*triggerconfig[63..58] = GroupCoincidence 6 bits, 1 bit enabling each of the 6 logical groups

There are 6 frontend FPGAs with 8 channels each. Each frontend sends its trigger multiplicity (0-8) to the collector. There are 6 possible logical groups to assign each of the frontends to (One simple scheme would be to put all 6 frontends in a single logical group - the multiplicity from this group would then be the total multiplicity on this VF48, in this case, all 6 groupids would be the same, only 1 bit would be enabled in GroupCoincidence, and only 1 multiplicity(GroupThreshold) would need to be set)

The above trigger logic settings are currently assigned using 4 ODB variables described below ...

GroupID - Sets the Logical GroupID for each frontend
{| style="color:black; cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || ||24||23|| || || || || || |16||15|| || || || || || ||8||7|| || || || || || ||0
|-
| colspan="14" align="center"|Unused
| colspan="3" align="center"|GroupIDFe5
| colspan="3" align="center"|GroupIDFe4
| colspan="3" align="center"|GroupIDFe3
| colspan="3" align="center"|GroupIDFe2
| colspan="3" align="center"|GroupIDFe1
| colspan="3" align="center"|GroupIDFe0
|}

GroupMulti02 - Sets the required multiplicity for logical groups 0 to 2
{| style="color:black; cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || ||24||23|| || || || || || |16||15|| || || || || || ||8||7|| || || || || || ||0
|-
| colspan="14" align="center"|Unused
| colspan="6" align="center"|MultiplicityGroup2
| colspan="6" align="center"|MultiplicityGroup1
| colspan="6" align="center"|MultiplicityGroup0
|}

GroupMulti35 - Sets the required multiplicity for logical groups 3 to 5
{| style="color:black; cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || ||24||23|| || || || || || |16||15|| || || || || || ||8||7|| || || || || || ||0
|-
| colspan="14" align="center"|Unused
| colspan="6" align="center"|MultiplicityGroup5
| colspan="6" align="center"|MultiplicityGroup4
| colspan="6" align="center"|MultiplicityGroup3
|}

GroupCoincidence - Sets which logical groups multiplicities are required to be satisfied (All The groups set active here, are required in coincidence in order to get a trigger)
{| style="color:black; cellpadding="10" cellspacing="0" border="1"
!31|| ... ||16||15|| || || || || || ||8||7||6||5||4||3||2||1||0
|-
| colspan="13" align="center"|Unused
| GroupID5
| GroupID4
| GroupID3
| GroupID2
| GroupID1
| GroupID0
|}

= Signal Processing =

The system integrates a signal processing logic which calculates the charge and the precise time where the hit has been detected. In the FE FPGA the continuous flow of digitized signal samples from the ADC is directed to the signal processing logic. The signal processor runs continuously. It performs tasks equivalent to a spectroscopy amplifier connected to an analog multi-channel analyzer.

[[Image:splogic.jpg]]

== Real-Time Digital Filter and Charge Evaluation==

The filtering involves many steps. The first step is the deconvolution of the exponential tail of the pulse shape within an arbitrary time window. The moving window deconvolution method is well documented in the litterature. It is implemented as a finite impulse response filter (FIR). If D0, D1, … Dn, represent the digitized signal samples, and L the span of the moving window, the nth point of the transformed sequence Fn is given by the relation:

(1) [[Image:f1vf48.jpg]]

where τ is the exponential time constant of the signal in units of data samples. The deconvolution is useful in the case of a germanium detector to compensate for the differences in ballistic deficit as a function of the rise time of the signal. Depending on the position of the photon interaction, the charge collection time may vary from event to event by as much as 150 nanoseconds. With a preamplifier decay time constant of 50 microseconds, this translates into a fluctuation of the raw signal peak amplitude corresponding to 3 Kev for a 1 Mev gamma. With an analog system, this fluctuation is reduced significantly by using a long filter peaking time, but it never vanishes. With the moving window deconvolution method, the tail pulse shape is transformed into a quasi-rectangular pulse shape, with a duration determined by the span of the moving window. The transformed signal has a leading edge reflecting the shape of the original signal (with a slight correction for the exponential decay), and then reaches a constant maximum value that is exactly the same for a given total charge deposited in the detector whatever the rise-time. The processed signal also returns to zero with no tail.

It can be seen from equation (1) that the first two terms will cancel the DC baseline. However, the sum term that cancels exactly the exponential decay will unfortunately respond to a baseline level with a gain of L/τ. The sum term also limits the effectiveness of the low frequency filtering effect of the first two terms. To alleviate this problem, one can resort to double sampling, or use a baseline restoring scheme. We have chosen this later approach. The baseline restoring process is active only when no signal is present.

At this stage, the filtering is not yet complete. Only the low frequency part of the noise spectrum has been attenuated. The high frequency filtering is performed by applying another FIR transformation to the corrected deconvoluted signal. The most efficient filter for the evaluation of the trend of a noisy straight line (the flat part of the rectangular pulse shape) is the simple floating average transformation, commonly called a boxcar filter:

(2) [[Image:f2vf48.jpg]]

K is chosen to be as close as possible to the size of the flat portion of the rectangular pulse Fn . For a theoretical signal having a zero rise time and an exponential decay with time constant equal to τ, the sequence of points Gn represents a trapeze with a rise time of K, a flat portion of L-K, and a fall time of K. Every point of the flat top part of the pulse is a proper evaluation of the charge. Selecting the maximum value is simple, but it generates a small average bias proportional to the noise. We rather select the measurement point at a pre-determined time after the beginning of the pulse, based on the timing information produced by the CFD discriminator. This amounts to selecting the point at random (as far as the amplitude is concerned) in the flat top region, thereby reducing the bias.

Due to constraint design (the division by τ would involve excessive FPGA resources), we multiply both sides of equation (1) by τ (parameter M), and we do not normalize by the number of points. The result appearing in the event list is given by

It can be scaled down by software when the histograms are constructed.

== Digital Constant Fraction Discriminator==
Analog constant fraction discriminators (CFD) are widely used to minimize the time walk associated with the detection of signals featuring widely varying amplitudes. The same principle can be applied to digital signal samples, with some differences in the physical implementation. In the VF48 firmware, the implementation reproduces exactly the definition of a CFD: The amplitude of the signal is evaluated, and a threshold is calculated with a predefined fraction. The same signal, delayed through a digital delay line (dual port RAM), is then compared with this calculated threshold until the point immediately below, and the point immediately above the threshold are found. Then, a linear interpolation is performed to evaluate the time corresponding to the threshold crossing. We use time units of 1/16 of the ADC sampling clock period for the interpolation. Often, the rise time is not constant from event to event, as it depends on the position where the electron-holes pairs were created in the crystal. So, it is important to clip the incoming signal to a width equal or shorter than the fastest signal rise time envisioned before the CFD logic. This is achieved by subtracting two samples separated by the proper number of sampling clocks. This has the same effect as the clipping delay line of an analog CFD. The digital CFD produces two outputs: a logic signal synchronized with the ADC clock, when the constant fraction threshold is crossed, and a higher precision time stamp word. The logic signal is used by the trigger logic, whilst the time stamp is part of the event data stream.

== Latency and Event Segment Buffers==

In order to accommodate for the latency of the trigger system, a circular latency buffer is used to keep the past values of the signal samples available for a time equal or longer than the trigger decision latency. The input of the buffer is either the raw data signal, or the output of the deconvolution logic. This can be selected by a run parameter. The maximum capacity of the latency buffer is presently 512 elements. When a trigger is accepted, this delay allows the recovery of the associated signal since its very beginning. We usually also include a few samples that have occurred before the signal. The latency buffer is implemented in a dual port random access memory running continuously. The read address is equal to the write address minus the number of clock cycles we want to have the data delayed. The signal data is continuously written in the memory, and the delayed data continuously available on the readout port. When a trigger is accepted, a transfer gate is generated for a duration corresponding to the size of the data segment requested, and the data read out is transferred to the next buffer stage: the segment event buffer.

The segment buffer is a simple 1024 word FIFO that stores the waveform data segments, plus two extra bits indicating the beginning and end of these segments. The FIFO is read out asynchronously by the list formatter. The function of the Segment Buffer is to store a few events in order to deramdomize the data flow. The segment buffer also generates an almost full flag that is transmitted to the master trigger system. This is the mechanism that throttles the trigger rate when the data acquisition becomes throughput limited. When the throughput is significantly lower than the system bandwidth, the data acquisition is dead-timeless.

== Digital Constant Fraction Discriminator==
Analog constant fraction discriminators (CFD) are widely used to minimize the time walk associated with the detection of signals featuring widely varying amplitudes. The same principle can be applied to digital signal samples, with some differences in the physical implementation. In the VF48 firmware, the implementation reproduces exactly the definition of a CFD: The amplitude of the signal is evaluated, and a threshold is calculated with a predefined fraction. The same signal, delayed through a digital delay line (dual port RAM), is then compared with this calculated threshold until the point immediately below, and the point immediately above the threshold are found. Then, a linear interpolation is performed to evaluate the time corresponding to the threshold crossing. We use time units of 1/16 of the ADC sampling clock period for the interpolation. Often, the rise time is not constant from event to event, as it depends on the position where the electron-holes pairs were created in the crystal. So, it is important to clip the incoming signal to a width equal or shorter than the fastest signal rise time envisioned before the CFD logic. This is achieved by subtracting two samples separated by the proper number of sampling clocks. This has the same effect as the clipping delay line of an analog CFD. The digital CFD produces two outputs: a logic signal synchronized with the ADC clock, when the constant fraction threshold is crossed, and a higher precision time stamp word. The logic signal is used by the trigger logic, whilst the time stamp is part of the event data stream.

== Latency and Event Segment Buffers==

In order to accommodate for the latency of the trigger system, a circular latency buffer is used to keep the past values of the signal samples available for a time equal or longer than the trigger decision latency. The input of the buffer is either the raw data signal, or the output of the deconvolution logic. This can be selected by a run parameter. The maximum capacity of the latency buffer is presently 512 elements. When a trigger is accepted, this delay allows the recovery of the associated signal since its very beginning. We usually also include a few samples that have occurred before the signal. The latency buffer is implemented in a dual port random access memory running continuously. The read address is equal to the write address minus the number of clock cycles we want to have the data delayed. The signal data is continuously written in the memory, and the delayed data continuously available on the readout port. When a trigger is accepted, a transfer gate is generated for a duration corresponding to the size of the data segment requested, and the data read out is transferred to the next buffer stage: the segment event buffer.

The segment buffer is a simple 1024 word FIFO that stores the waveform data segments, plus two extra bits indicating the beginning and end of these segments. The FIFO is read out asynchronously by the list formatter. The function of the Segment Buffer is to store a few events in order to deramdomize the data flow. The segment buffer also generates an almost full flag that is transmitted to the master trigger system. This is the mechanism that throttles the trigger rate when the data acquisition becomes throughput limited. When the throughput is significantly lower than the system bandwidth, the data acquisition is dead-timeless.

= Firmware Update=

To do an update, you will need the ByteBlaster II connector connected on the parallel port of your PC and to the connector J3 on the VF48 board. (Or an USB Blaster module)

Then, you must download the programmer on the Altera Website:
https://www.altera.com/support/software/download/programming/quartus2/dnl-quartus2_programmer.jsp

Then, you start the program. You change the mode from JTAG to Active Serial Programming. You push the Hardware Setup button and you select ByteBlaster II. Then, you push the Add File button and you select the pof file that we supplied you. After, you click in the Program/Configure case and finally you push the Start button.

When the firmware has been programmed, you must unplug the ByteBlaster II connector from the VF48 board, shut down the power and put it back.

If the green light is on, programming was completed successfully. If the green light is off, did you forget to unplug the ByteBlaster II connector? If no, restart all the procedure.

== Label Convention==

A label convention is done to name each version that is created. It starts by the firmware main revision. Then, we add respectively the sub revision, the sampling frequency, the system clock frequency and the special features if they exist.

For example, the name VF48_V207_X6_40_20_Alpha.pof is associated to the firmware version 2.0.7 with a sampling frequency of 40 MHz and a system frequency of 20 MHz. The special feature Alpha signifies that this version is done specifically for Alpha project.

== Firmware history ==

VF48

2010-09-16T21:23:42Z

Cpearson: /* Aux Output */

= VF48 - 48 channels@60Msps, 10bits =

== General characteristics ==
The VF48 is a one-unit wide VME 6U housing 48 channels digitized by six fast 10-bit ADCs. For each channel, the input signal (50 Ω impedance) is amplified by a high speed differential amplifier (AD8132) and them converted by the ADCs at a maximum rate of 60 Msps.

The digitized signal goes to a FPGA (Cyclone EPC12) which will calculate the charge of the signal, evaluate the exact trigger time, build an event which will contain all this information and send the event constructed to a local collector. Each FPGA manages eight channels. There are six FPGA connected to the ADCs and one FPGA which collects the data.

The board can be accessed in A24/A32/A40 addressing mode, D16, D32 and MBLT64 data transfer mode.

It has also a board available to access the VF48 throw a LVDS link. This link can transfer the data at a speed up to 100 Mbits/s. This link can afford all the control necessary to run the VF48. It can accept a clock which permits the synchronization of many VF48 units.

The board contains a trigger structure which permits to trigger the data in three different manners. The trigger can come from an external NIM signal, from a software command or from an internal mechanism. The internal mechanism manages multiple channels hit, deadtime, threshold and multiplicity and is totally programmable by the user.

[[Image:blockdigvf48.jpg|Block Diagram of the VF48]]

= VME interface =
The VF48 board can access the VME bus in VME A24. See Table 2.1.1 to have more information about the Address Modifier accepted.

{|style="color:green; background-color:#ffffcc;" cellpadding="10" cellspacing="0" border="1"
|+ Summarizes all the supported address Modifer
|-
!AM||Description
|-
|3F
|A24 supervisory block transfer (BLT)
|-
|3D
|A24 supervisory data access
|-
|3C
|A24 supervisory 64-bit block transfer (MBLT)
|-
|3B
|A24 non privileged block transfer (BLT)
|-
|39
|A24 non privileged data access
|-
|38
|A24 non privileged 64-bit block transfer (MBLT)
|-
|}

=== Base Address ===

The base address of the board is 0xA00000 + n • 0x10000. The number n is defined by the alignment of the switch on the board. For example, if the alignment on the switch is : ID[3..0] = 1011, then the base address will be 0xAB0000.

Every board will manage a window going until 0x00FFFF above the base address. In the previous example, the VME window was from 0xAB0000 to 0xABFFFF.

=== Data Transfer Capabilities ===
The board can access the VME BUS in VME_D16, VME_D32, VME 32-bit and 64-bit block transfers (BLT32 and MBLT64). The VME_D8 is not compatible. D32 is recommended for accessing collector registers and 64-bit block transfer (MBLT64) is recommended for reading data from the VME data FIFO. See VME Mapping to have more details on this.

==VME Mapping==

The Table 2.2.1 describes the VME Mapping of the VF48 collector registers. In the Table 2.2.1, the W column indicates if the register is available for a Write. The R column indicates if the register is available for a Read. The last three columns indicate permitted access modes.

– VME Mapping
{| style="color:green; background-color:#ffffcc;" cellpadding="10" cellspacing="0" border="1"
|-!Offset ||VME Mapping ||Access ||Mode
|-
|0x0000||CSR||R/W||D16/32
|-
|0x0010|| || ||
|-
|0x0020|| || ||
|-
|0x0030||Firmware ID ||R || D16/32
|-
|0x0040|| || ||
|-
|0x0050||Param DAT ||W ||D16/32
|-
|0x0060||Param ID ||W ||D16/32
|-
|0x0070||Soft Trigger ||W ||D16/32
|-
|0x0080|| || ||
|-
|0x0090||Group Enable ||R/W ||D16/32
|-
|0x00A0||NbrFrames ||R ||D16/32
|-
|0x00B0||Global Reset || W ||
|-
|0x01XX||Event Data ||R ||D32/BLT32/MBLT64
|-
|}

===CSR Description ===
Only six bits of the CSR (Control & Status Registry) are used. They are indicated in the Table 2.2.2.

{| style="color:green; background-color:#ffffcc;" cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit ||CSR Description ||Access
|-
|0|| Run ||R/W
|-
|1|| Parameter ID Ready|| R
|-
|2|| Parameter DATA Ready||R
|-
|3|| Event Fifo Empty||R
|-
|4|| ||
|-
|5||CRC Error detected || R
|-
|6|| ||
|-
|7||External Trigger || R/W
|-
|}

The RUN bit allows the system to accept triggers and start the acquisition.

The Parameter ID Ready bit and Parameter DAT Ready bit indicate if parameter is ready to be read. The parameter section will describe more precisely how these bits work.

The Event Fifo Empty bit indicates if the event fifo is empty. When this signal is low, there’s data ready to be read.

The CRC Error Detected bit indicates if a CRC Error has been detected in the serial communication on the board. This bit should never go on.

The External trigger bit selects the external trigger. If this bit is set to 1, the trigger that will start the acquisition must come from the connector on the front panel. If this bit is zero, then a real signal must be detected on one of the 48 channels if you want to have event built.

=== Firmware ID (0x000030) ===
It returns the firmware ID

===Parameter DAT (0x000050)===
Register used to write the parameter. See the section Writing/Reading Parameter for more details.

=== Parameter ID (0x000060)===
Register used to write the parameter. See the section Writing/Reading Parameter for more details.

===Soft Trigger (0x000070)===
It generates a trigger on the front end to force the system to acquire data.

===Group Enable (0x000090)===
It allows enabling a group of channels. Bit 0 enables channel 1 to 8, bit 1 enables channel 9 to 16 until bit 5 which enable channels 41 to 48. By default, they are all enabled.
2.2.7. Nbr Frames (0x0000A0)
It gives the number of data present in the event fifo. See section 4. Triggers & Events for more details.

===Global Reset (0x0000B0)===
It resets all the system.

===Event Data (0x000100-0x00FFFF)===
It reads all the data in the fifo. See section 4. Triggers & Events for more details.

= Writing/Reading Parameter =
To write a parameter, you must write the parameter ID (See Table 3.1.1) followed by the parameter Data. You write the parameter ID by doing a VME Write at the address Param ID and you write the parameter Data by doing a VME Write at the address Param DAT.

During a parameter read, it is necessary to be aware that parameter is not immediately in the register ParamDAT. The bit 2 of the CSR rises up when the parameter is ready and falls down when you read it. So, the procedure to read a parameter is this. First, you send the request by writing the parameter ID (VME Write at the address ParamID) with bit 7 set to 1. You must also send a fake data, because if you don’t send a fake data, the request will never be sent. After, you read bit 2 of the CSR until it has been set. When the bit is set, you do a VME Read at the address ParamDAT .

===Parameter Frame Header===
The first 16 bits of a frame contain information describing the contents of the parameter.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Parameter Frame Header
|-
!15|| || || ||11|| || || ||7||6|| || || || || || 0
|-
|C ||C||C||C|| D||D||D||D||R||V||P||P||P||P||P||P
|}

* C : Destination Card or Port or Cyclone
* D : Destination Channel (0-5)
* R : ReadBit
* V : Version (0- No extension; 1- Param ID 32 bit)
* P : Parameter ID

Description of the fields Parameter Frame Header:
Destination Card
Bits 11 - 8 contain the number of the card where parameter must be sent. The following table describes the direction which has to take parameter according to the number of destination of card, the number of port or the number of cyclone on the board.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Destination Cyclone
|-
!11 ||10|| 9|| 8|| Destination Cyclone ||Port
|-
|0 ||0|| 0|| 0|| Channel 1 to 8 ||0
|-
|0 ||0|| 0|| 1|| Channel 9 to 16 ||1
|-
|0 ||0|| 1|| 0|| Channel 17 to 24|| 2
|-
|0 ||0|| 1|| 1|| Channel 25 to 32|| 3
|-
|0 ||1|| 0|| 0|| Channel 33 to 40|| 4
|-
|0 ||1|| 0|| 1|| Channel 41 to 48|| 5
|-
|0 ||1|| 1|| 0|| Not used ||Not used
|-
|1 ||1|| 1|| 1|| Not used ||Not used
|}
* Destination Channel
This field is not used for the current version. We don’t care of these bits.

* ReadBit
Bit 7 indicates if command is a demand of writing or reading of the parameter. If ReadBit is HIGH, then it is a read and parameter should be sent back to the collector. If ReadBit is LOW, then it is a write and parameter should be recorded.

During a parameter read, it is necessary to be aware that parameter is not immediately in the register ParamDAT. The bit 2 of the CSR rises up when the parameter is ready and falls down when you read it.
Version Bit

This bit must be zero in this version
Parameter ID
The last six bits contains the parameter ID. Each parameter available is displayed in the Table 3.1.3

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Parameter List
|-
!ID# ||Parameter List|| Default Value|| Access
|-
|0 || || ||
|-
|1|| PED ||0x0000 ||R/W
|-
|2|| Hit Det Threshold|| 0x000A ||R/W
|-
|3|| Clip Delay ||0x0028 ||R/W
|-
|4|| PreTrigger ||0x0020 ||R/W
|-
|5|| Segment Size ||0x0100 ||R/W
|-
|6|| K ||0x0190 ||R/W
|-
|7|| L ||0x0200 ||R/W
|-
|8|| M ||0x1000 ||R/W
|-
|9|| Channel Enable ||0x00FF ||R/W
|-
|10|| Mbits 1 - Feature Enable|| 0x0000 ||R/W
|-
|11|| Mbits 2 - Feature Enable|| 0x0000 ||R/W
|-
|12|| Latency ||0x0005 ||R/W
|-
|13|| Firmware ID ||0x0207 ||R/W
|-
|14|| Attenuator ||0x0190 ||R/W
|-
|15|| Trigger Threshold|| 0x000A ||R/W
|}

=== Parameter Description ===
This section is there to describe each parameter.
1 - PED
This parameter is not used yet.
2 – Hit Detection Threshold
This parameter defines the threshold to detect a hit. If the signal given by the ADC is above this threshold value, the system will start to calculate the charge, but if the signal doesn’t reach the trigger threshold, the charge won’t be used.
3 – Clip Delay
This parameter is not used yet.
4 – Pre-Trigger
This parameter defines the number of clock where the data must be recorded before the trigger.
5 – Segment Size
This parameter defines the number of raw data that must be recorded.
6 - K
This parameter defines the peaking time. See the signal processing section for more details.
7 - L
This parameter represents the duration of the peaking time and the flat top together. See the signal processing section for more details.
8 - M
This parameter defines a multiplication factor of the convoluted signal. See the signal processing section for more details.
9 – Channel Enable
This parameter indicates the channels that must be included in the event. Bit 0 enables channel 0, bit 1 enables channel 1, so in succession until channel 7. By default, all channels are enabled.

Note: In version previous to version 2.0.7, the parameter 11 was FeatureDelay_B. This parameter doesn’t exist anymore.
10 – M_Bits
This parameter is a parameter where each bit has a different purpose. The Table 3.2.1 gives information about these bits.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Description of the MBits parameter
|-
!Bit|| Version 2.0 and more|| Version before 2.0
|-
|0|| Data Simulation|| Data Simulation
|-
|1|| Suppress Raw Data|| Supress Raw Data
|-
|2|| Select Corrected Data|| Select Corrected Data
|-
|3|| PolPlus|| PolPlus
|-
|4|| BLR Speed (bit 0)|| Disable ADC
|-
|5|| BLR Speed (bit 1)|| Fake One Data
|-
|6|| Hold BLR ||-
|-
|7|| - ||-
|-
|8|| Disable ADC ||-
|-
|9|| Offset 1 ||-
|-
|10|| Offset 2 ||-
|-
|11|| Low Gain Selection ||-
|-
|12|| Card Revision Number (bit 0) ||-
|-
|13|| Card Revision Number (bit 1) ||-
|-
|14|| Card Revision Number (bit 2) ||-
|-
|15|| Card Revision Number (bit 3) ||-
|}

The bit 0, Data Simulation, enables the simulator. If this bit is set, the simulated data will be continually sent.

The bit 1, Suppress Raw Data, suppresses the raw data independently of the segment size parameter.

The bit 2, Select Corrected Data, is not used in the current version.

The bit 3, PolPlus, is used to invert numerically the input. If the input is 0b0100010001, and the bit PolPlus set then the input will be 0b1011101110.

The bit 8, Disable ADC, disable the ADC.

The bit 5, Fake One Data, has the same use as the bit 0, Data Simulation, but it will be activated for only one valid signal.

All the other bits are reserved for future use. The names indicated represent the function that is reserved for the bit to be compatible with other project.
11 – M_Bits 2
This parameter is a parameter where each bit has a different purpose. The Table 3.2.2 gives information about these bits.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Description of the MBits 2 parameter
|-
!Bit|| Version 2.0 and more|| Version before 2.0
|-
|0|| Enable Channel Suppression ||-
|-
|1|| Doesn't send time evaluation ||-
|-
|2|| Doesn't send charge calculated ||-
|-
|3|| -||-
|-
|4|| -||-
|-
|5|| -||-
|-
|6|| -||-
|-
|7|| -||-
|-
|15..8||Sampling Rate Divider||-
|}

* bit 0, Enable Channel Suppression, disable an entire channel within a group if none of the sample values of that channel is above the hit threshold.

* bit 1, Doesn’t send charge calculated, disables the calculation of the charge. If this bit is set, the charge won’t be calculated.

* bit 2, Doesn’t send time evaluation, disables the evaluation of the time when the signals passes above the threshold. If this bis set, the time won’t be evaluated.

Note: In version previous to version 2.0.7, the parameter 11 was FeatureDelay_B. This parameter doesn’t exist anymore.
12 – Latency
This parameter defines the number of clock to be added to the pre-trigger. This parameter should represent the time between the hit detection and the trigger accepted received by the front end.
13 – Firmware ID
This parameter is firmware ID. For example, if the version is 1.0.0, it will return 0x0100. If the version is 11.12.13, it will return 0x0BCD.
14 – Attenuator
This parameter defines the attenuation of the integration. See the signal processing section for more details.
15 – Trigger Threshold
This parameter defines the threshold to accept a trigger. If the signal given by the ADC is above the threshold value, a trigger request will be sent to the collector.

= Triggers & Events=

When a trigger is accepted, the front end starts to build an event which will be transferred to the collector. Each event has the same format. This section defines this format, but before, let us defines some terms usually used in this section.

A Packet is a word of 32 bits which contains information related with an event.

An Event is a series of packet beginning with a header and ending by a trailer.

== Trigger Detection==
Each channel goes through a comparator in order to trigger the feature evaluation. The hit threshold is a positive difference of 2 ADC values separated by 2 samples (ex: 2,3,4,5,6,7  hit Thr= 6-3).
In the case the input signal has the opposite polarity, you can either reverse the input signal (the VF48 input is bipolar) or reverse the polarity by software. The polarity switch is applied to the digitized ADC values. Currrently no dedicated reverse polarity function is available. Use the example found under midas/examples/Triumf/c/fevmemodules.c/BOR function.
The acceptance of the next trigger is garanteed when there is space for one event or more. A corresponding deadtime is generated for the duration of the capture of the raw data in the frontend buffer. The buffer size is fixed at 1000 samples. Therefore the pipeline advantage starts when the event size is less than 500 samples (this limits is set by the hardware type used on the board).
There is an output signal (busy out signal) available reflecting the non acceptance of trigger by the VF48. This correspond to the "deadtime" from the raw data capture ored with the condition of the frontend buffer having no more room for a complete event.

== Event Description==
An event is broken in many packets which follow a precise order. It always has to begin with a header and end with a trailer. The header and the trailer contain the trigger number and they must be identical. The header is always followed by a timestamp. Then, for each channel enabled, it could contain the raw data, the CFD time evaluated and the charge calculated. The Table 4.2.1 shows the content of an event.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Event’s content
|-
!Packet's Type ||MSB
|-
|Event Header ||0x8
|-
|Time Stamp 1 ||0xA
|-
|Time Stamp 2 ||0xA
|-
|Channel ID ||0xC
|-
|Raw Data (of current channel) ||0x0
|-
|CFD Time (of current channel) ||0x4
|-
|Charge (of current channel) ||0x5
|-
|Channel ID ||0xC
|-
|Raw Data (of current channel) ||0x0
|-
|CFD Time (of current channel) ||0x4
|-
|Charge (of current channel) ||0x5
|-
|… ||
|-
|Channel ID ||0xC
|-
|-
|Raw Data (of current channel) ||0x0
|-
|CFD Time (of current channel) ||0x4
|-
|Charge (of current channel) ||0x5
|-
|Event Trailer ||0xE
|}

The number of raw data is configurable by the parameter Segment Size (Chan Param ID:5). The next section will describe more in detail each of these packets.

== Event Packet Format==
This section describes in detail the contents of each of the packets. Firstly, inside a packet, the 4 MSB indicates the type of packet. The next table makes the association between the MSB and the packets.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Event Packet MSB Association
|-
!Packet's Type ||MSB
|-
|Header ||0x8
|-
|Time Stamp 1 ||0xA
|-
|Time Stamp 2 ||0xA
|-
|Channel ID ||0xC
|-
|Raw Data ||0x0
|-
|CFD Time ||0x4
|-
|Charge ||0x5
|-
|Trailer ||0xE
|-
|Header Error ||0x9
|-
|Error ||0xF
|-
|Header ||0x8xxxxxxx
|}

The packet Header is always the first packet of an event. It contains the trigger number in the bits 23 to 0.

Table 4.3.2 – Header 0x8xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||0||0||0||colspan="4" align="center"|0|| T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T
|}
Trigger Number

Header Error - 0x9xxxxxxx
The Header Error packet occurs when the first packet of a group was not a Header packet. This could be caused by an internal error. If this packet is detected, the current event must be rejected. However, this packet must not happen and if it does, you should contact your supplier.

Table 4.3.3 – Header Error 0x9xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||0||0||1||colspan="4" align="center"|0||colspan="24" align="center"|Trigger Number
|}

Time Stamp - 0xAxxxxxxx
The Time Stamp packet is the second packet and the third packet of en event. It contains a 48 bits time stamps. The time between two steps is of 25 ns . Then, with a 48 bits timestamp, the maximum time measured is 7 036 874,418 seconds. Then, system can count time without completing a buckle during more than 81 days.

Table 4.3.4 – Time Stamp – 0xAxxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||0||1||0||colspan="4" align="center"|0|| colspan="24" align="center"|Time Stamp
|}

The first time stamp packet contains bit 47 to 24 and the second time stamp packet contains bits 23 to 0.
Channel ID - 0xCxxxxxxx
The channel ID packet is the first packet of a sub-event. It contains all the information to be able to identify the channel. Bit 3 to 0 indicates the channel number. This number can go from 0 to 7. It corresponds to the channel of a particular group. Then, bits 6 to 3 identify the group. They can so take a value going from 0 to 5. Bit 7 is not used in this version.

Table 4.3.5 – Channel ID – 0xC0xxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || ||11|| || ||8||7||6|| || ||3|| || ||0
|-
| 1||1||0||0||colspan="4" align="center"|0||0||0||0||0||0||0||0||0||0||0||0||0|| 0||0||0||0||0|| colspan="3" align="center"|Group||colspan="4" align="center"|Channel
|}

Data - 0x0xxxxxxx
The Data packet comes after the channel ID packet. It simply contains two data of 10 bits each. The number of data packet within an event is related to the segment size parameter (Chan Param ID: 5). It could arise problems to have a null value or an odd value of the segment size.

Table 4.3.6 – Data – 0x0xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || ||13|| || || ||9|| || || || || || || || ||0
|-
| 0||0||0||0||colspan="4" align="center"|0|| colspan="10" align="center"|Sampe n+1|| 0||0||0||0|| colspan="10" align="center"|Sample n
|}

Be careful about the position of the second data. It doesn’t start exactly to bit 16. It starts to bit 14. This is done to keep the compatibility with an ADC that would a 14 bits data.
CFD Time - 0x4xxxxxxx
The CFD Time packet is the second packet before the last packet. It contains the CFD Time.

Table 4.3.7 – CFD Time – 0x40xxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 0||1||0||0||colspan="4" align="center"|0|| colspan="24" align="center"| CFD Time
|}

Time algorithm: CDF Equivalent. The input is first clipped with a delay of 3 clocks. If the clipped signal is above the hit threshold then the maximum value of the clipped waveform is evaluated. The CFD time is then evaluated by interpolating the time at 50% charge using the two samples on either side of the 50% fraction.

Charge - 0x5xxxxxxx
The Charge Packet is the first packet before the trailer packet. It contains the charge internally calculated.

Table 4.3.8 – Charge – 0x50xxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 0||1||0||1||colspan="4" align="center"|0|| colspan="24" align="center"|Charge
|}

Trailer - 0xExxxxxxx
The trailer is always the last packet of an event. It contains the trigger number in the bits 23 to 0. The bit 28 indicates an out of sequence flag, then, if this bit is 1, that means that an internal error took place and the packet should be rejected. In theory, system is stable and this type of error should not occur.

Table 4.3.9 – Trailer – 0xExxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||1||1||0||colspan="4" align="center"|0|| colspan="24" align="center"| Trigger Number
|}

Error - 0xFxxxxxxx
The Error packet occurs when a particular packet is not at his right position. This could occur if a timestamp is missing or if a timestamp is not followed by channel. This could be caused by an internal error. If this packet is detected, the entire event must be rejected. However, this packet must not happened and if it does, you should contact your supplier.

Table 4.3.10 – Error 0x9xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||1||1||1|| colspan="28" align="center"|Invalid
|}

== Event Acquisition==
Procedure to read events is very simple. It is a question of reading the number of packet presently available by making a reading on the bus VME at the address NbrFrames. Then, a reading in burst of the number of packet available can be made. The reading of events is done in fifo mode only. This means that the reading is done always at the same address, the Event Data address.

To start the acquisition, you must set the bit 0 of the CSR to 1. To stop the acquisition, you set the bit 0 of the CSR to 0.

The system integrates a signal processing logic which calculates the charge and the precise time where the hit has been detected. In the FE FPGA the continuous flow of digitized signal samples from the ADC is directed to the signal processing logic. The signal processor runs continuously. It performs tasks equivalent to a spectroscopy amplifier connected to an analog multi-channel analyzer.

== Aux Output==
The aux_out front panel output can be set to provide a trigger output, busy output or system clock output, this function is selected by triggerconfig[3..0] and CSR[16] ...

*triggerconfig[0] = 1 sets AuxTrigDisable prevents trigger from reaching aux-out (This was for tactic)
*triggerconfig[1] = 1 Enables the self-trigger Logic (when 0 the logic is just a a simple OR of the 6 Front End trigger requests)
*triggerconfig[2] = 1 selects tigc trigger (rather than the self trigger)
*triggerconfig[3] = 1 sets the system clock to aux_out (rather than trigger)
There is also a "select busy out" signal [CSR[16]] which overrides all the above and puts the busy signal to aux_out

The triggerconfig register is 64bits wide, the remaining 60 bits are used to set the self-trigger logic
*triggerconfig[39.. 4] = GroupThresholds 6 thresholds of 6 bits each (0-63)
*triggerconfig[57..40] = FeGroups 6 groupid's of 3 bits each (0-7)
*triggerconfig[63..58] = GroupCoincidence 6 bits, 1 bit enabling each of the 6 groups

There are 6 frontend FPGAs with 8 channels each, each sends its trigger multiplicity (0-8) to the collector. There are 6 possible groups to assign the frontends to (One simple scheme would be to put all 6 in a single group - the multiplicity from this group would then be the total multiplicity on this VF48, in this case, all 6 groupids would be the same, only 1 bit would be enabled in GroupCoincidence, and only 1 multiplicity(GroupThreshold) would need to be set)

= Signal Processing =

The system integrates a signal processing logic which calculates the charge and the precise time where the hit has been detected. In the FE FPGA the continuous flow of digitized signal samples from the ADC is directed to the signal processing logic. The signal processor runs continuously. It performs tasks equivalent to a spectroscopy amplifier connected to an analog multi-channel analyzer.

[[Image:splogic.jpg]]

== Real-Time Digital Filter and Charge Evaluation==

The filtering involves many steps. The first step is the deconvolution of the exponential tail of the pulse shape within an arbitrary time window. The moving window deconvolution method is well documented in the litterature. It is implemented as a finite impulse response filter (FIR). If D0, D1, … Dn, represent the digitized signal samples, and L the span of the moving window, the nth point of the transformed sequence Fn is given by the relation:

(1) [[Image:f1vf48.jpg]]

where τ is the exponential time constant of the signal in units of data samples. The deconvolution is useful in the case of a germanium detector to compensate for the differences in ballistic deficit as a function of the rise time of the signal. Depending on the position of the photon interaction, the charge collection time may vary from event to event by as much as 150 nanoseconds. With a preamplifier decay time constant of 50 microseconds, this translates into a fluctuation of the raw signal peak amplitude corresponding to 3 Kev for a 1 Mev gamma. With an analog system, this fluctuation is reduced significantly by using a long filter peaking time, but it never vanishes. With the moving window deconvolution method, the tail pulse shape is transformed into a quasi-rectangular pulse shape, with a duration determined by the span of the moving window. The transformed signal has a leading edge reflecting the shape of the original signal (with a slight correction for the exponential decay), and then reaches a constant maximum value that is exactly the same for a given total charge deposited in the detector whatever the rise-time. The processed signal also returns to zero with no tail.

It can be seen from equation (1) that the first two terms will cancel the DC baseline. However, the sum term that cancels exactly the exponential decay will unfortunately respond to a baseline level with a gain of L/τ. The sum term also limits the effectiveness of the low frequency filtering effect of the first two terms. To alleviate this problem, one can resort to double sampling, or use a baseline restoring scheme. We have chosen this later approach. The baseline restoring process is active only when no signal is present.

At this stage, the filtering is not yet complete. Only the low frequency part of the noise spectrum has been attenuated. The high frequency filtering is performed by applying another FIR transformation to the corrected deconvoluted signal. The most efficient filter for the evaluation of the trend of a noisy straight line (the flat part of the rectangular pulse shape) is the simple floating average transformation, commonly called a boxcar filter:

(2) [[Image:f2vf48.jpg]]

K is chosen to be as close as possible to the size of the flat portion of the rectangular pulse Fn . For a theoretical signal having a zero rise time and an exponential decay with time constant equal to τ, the sequence of points Gn represents a trapeze with a rise time of K, a flat portion of L-K, and a fall time of K. Every point of the flat top part of the pulse is a proper evaluation of the charge. Selecting the maximum value is simple, but it generates a small average bias proportional to the noise. We rather select the measurement point at a pre-determined time after the beginning of the pulse, based on the timing information produced by the CFD discriminator. This amounts to selecting the point at random (as far as the amplitude is concerned) in the flat top region, thereby reducing the bias.

Due to constraint design (the division by τ would involve excessive FPGA resources), we multiply both sides of equation (1) by τ (parameter M), and we do not normalize by the number of points. The result appearing in the event list is given by

It can be scaled down by software when the histograms are constructed.

== Digital Constant Fraction Discriminator==
Analog constant fraction discriminators (CFD) are widely used to minimize the time walk associated with the detection of signals featuring widely varying amplitudes. The same principle can be applied to digital signal samples, with some differences in the physical implementation. In the VF48 firmware, the implementation reproduces exactly the definition of a CFD: The amplitude of the signal is evaluated, and a threshold is calculated with a predefined fraction. The same signal, delayed through a digital delay line (dual port RAM), is then compared with this calculated threshold until the point immediately below, and the point immediately above the threshold are found. Then, a linear interpolation is performed to evaluate the time corresponding to the threshold crossing. We use time units of 1/16 of the ADC sampling clock period for the interpolation. Often, the rise time is not constant from event to event, as it depends on the position where the electron-holes pairs were created in the crystal. So, it is important to clip the incoming signal to a width equal or shorter than the fastest signal rise time envisioned before the CFD logic. This is achieved by subtracting two samples separated by the proper number of sampling clocks. This has the same effect as the clipping delay line of an analog CFD. The digital CFD produces two outputs: a logic signal synchronized with the ADC clock, when the constant fraction threshold is crossed, and a higher precision time stamp word. The logic signal is used by the trigger logic, whilst the time stamp is part of the event data stream.

== Latency and Event Segment Buffers==

In order to accommodate for the latency of the trigger system, a circular latency buffer is used to keep the past values of the signal samples available for a time equal or longer than the trigger decision latency. The input of the buffer is either the raw data signal, or the output of the deconvolution logic. This can be selected by a run parameter. The maximum capacity of the latency buffer is presently 512 elements. When a trigger is accepted, this delay allows the recovery of the associated signal since its very beginning. We usually also include a few samples that have occurred before the signal. The latency buffer is implemented in a dual port random access memory running continuously. The read address is equal to the write address minus the number of clock cycles we want to have the data delayed. The signal data is continuously written in the memory, and the delayed data continuously available on the readout port. When a trigger is accepted, a transfer gate is generated for a duration corresponding to the size of the data segment requested, and the data read out is transferred to the next buffer stage: the segment event buffer.

The segment buffer is a simple 1024 word FIFO that stores the waveform data segments, plus two extra bits indicating the beginning and end of these segments. The FIFO is read out asynchronously by the list formatter. The function of the Segment Buffer is to store a few events in order to deramdomize the data flow. The segment buffer also generates an almost full flag that is transmitted to the master trigger system. This is the mechanism that throttles the trigger rate when the data acquisition becomes throughput limited. When the throughput is significantly lower than the system bandwidth, the data acquisition is dead-timeless.

== Digital Constant Fraction Discriminator==
Analog constant fraction discriminators (CFD) are widely used to minimize the time walk associated with the detection of signals featuring widely varying amplitudes. The same principle can be applied to digital signal samples, with some differences in the physical implementation. In the VF48 firmware, the implementation reproduces exactly the definition of a CFD: The amplitude of the signal is evaluated, and a threshold is calculated with a predefined fraction. The same signal, delayed through a digital delay line (dual port RAM), is then compared with this calculated threshold until the point immediately below, and the point immediately above the threshold are found. Then, a linear interpolation is performed to evaluate the time corresponding to the threshold crossing. We use time units of 1/16 of the ADC sampling clock period for the interpolation. Often, the rise time is not constant from event to event, as it depends on the position where the electron-holes pairs were created in the crystal. So, it is important to clip the incoming signal to a width equal or shorter than the fastest signal rise time envisioned before the CFD logic. This is achieved by subtracting two samples separated by the proper number of sampling clocks. This has the same effect as the clipping delay line of an analog CFD. The digital CFD produces two outputs: a logic signal synchronized with the ADC clock, when the constant fraction threshold is crossed, and a higher precision time stamp word. The logic signal is used by the trigger logic, whilst the time stamp is part of the event data stream.

== Latency and Event Segment Buffers==

In order to accommodate for the latency of the trigger system, a circular latency buffer is used to keep the past values of the signal samples available for a time equal or longer than the trigger decision latency. The input of the buffer is either the raw data signal, or the output of the deconvolution logic. This can be selected by a run parameter. The maximum capacity of the latency buffer is presently 512 elements. When a trigger is accepted, this delay allows the recovery of the associated signal since its very beginning. We usually also include a few samples that have occurred before the signal. The latency buffer is implemented in a dual port random access memory running continuously. The read address is equal to the write address minus the number of clock cycles we want to have the data delayed. The signal data is continuously written in the memory, and the delayed data continuously available on the readout port. When a trigger is accepted, a transfer gate is generated for a duration corresponding to the size of the data segment requested, and the data read out is transferred to the next buffer stage: the segment event buffer.

The segment buffer is a simple 1024 word FIFO that stores the waveform data segments, plus two extra bits indicating the beginning and end of these segments. The FIFO is read out asynchronously by the list formatter. The function of the Segment Buffer is to store a few events in order to deramdomize the data flow. The segment buffer also generates an almost full flag that is transmitted to the master trigger system. This is the mechanism that throttles the trigger rate when the data acquisition becomes throughput limited. When the throughput is significantly lower than the system bandwidth, the data acquisition is dead-timeless.

= Firmware Update=

To do an update, you will need the ByteBlaster II connector connected on the parallel port of your PC and to the connector J3 on the VF48 board. (Or an USB Blaster module)

Then, you must download the programmer on the Altera Website:
https://www.altera.com/support/software/download/programming/quartus2/dnl-quartus2_programmer.jsp

Then, you start the program. You change the mode from JTAG to Active Serial Programming. You push the Hardware Setup button and you select ByteBlaster II. Then, you push the Add File button and you select the pof file that we supplied you. After, you click in the Program/Configure case and finally you push the Start button.

When the firmware has been programmed, you must unplug the ByteBlaster II connector from the VF48 board, shut down the power and put it back.

If the green light is on, programming was completed successfully. If the green light is off, did you forget to unplug the ByteBlaster II connector? If no, restart all the procedure.

== Label Convention==

A label convention is done to name each version that is created. It starts by the firmware main revision. Then, we add respectively the sub revision, the sampling frequency, the system clock frequency and the special features if they exist.

For example, the name VF48_V207_X6_40_20_Alpha.pof is associated to the firmware version 2.0.7 with a sampling frequency of 40 MHz and a system frequency of 20 MHz. The special feature Alpha signifies that this version is done specifically for Alpha project.

== Firmware history ==

VF48

2010-09-16T21:23:42Z

Cpearson: /* Aux Output */

= VF48 - 48 channels@60Msps, 10bits =

== General characteristics ==
The VF48 is a one-unit wide VME 6U housing 48 channels digitized by six fast 10-bit ADCs. For each channel, the input signal (50 Ω impedance) is amplified by a high speed differential amplifier (AD8132) and them converted by the ADCs at a maximum rate of 60 Msps.

The digitized signal goes to a FPGA (Cyclone EPC12) which will calculate the charge of the signal, evaluate the exact trigger time, build an event which will contain all this information and send the event constructed to a local collector. Each FPGA manages eight channels. There are six FPGA connected to the ADCs and one FPGA which collects the data.

The board can be accessed in A24/A32/A40 addressing mode, D16, D32 and MBLT64 data transfer mode.

It has also a board available to access the VF48 throw a LVDS link. This link can transfer the data at a speed up to 100 Mbits/s. This link can afford all the control necessary to run the VF48. It can accept a clock which permits the synchronization of many VF48 units.

The board contains a trigger structure which permits to trigger the data in three different manners. The trigger can come from an external NIM signal, from a software command or from an internal mechanism. The internal mechanism manages multiple channels hit, deadtime, threshold and multiplicity and is totally programmable by the user.

[[Image:blockdigvf48.jpg|Block Diagram of the VF48]]

= VME interface =
The VF48 board can access the VME bus in VME A24. See Table 2.1.1 to have more information about the Address Modifier accepted.

{|style="color:green; background-color:#ffffcc;" cellpadding="10" cellspacing="0" border="1"
|+ Summarizes all the supported address Modifer
|-
!AM||Description
|-
|3F
|A24 supervisory block transfer (BLT)
|-
|3D
|A24 supervisory data access
|-
|3C
|A24 supervisory 64-bit block transfer (MBLT)
|-
|3B
|A24 non privileged block transfer (BLT)
|-
|39
|A24 non privileged data access
|-
|38
|A24 non privileged 64-bit block transfer (MBLT)
|-
|}

=== Base Address ===

The base address of the board is 0xA00000 + n • 0x10000. The number n is defined by the alignment of the switch on the board. For example, if the alignment on the switch is : ID[3..0] = 1011, then the base address will be 0xAB0000.

Every board will manage a window going until 0x00FFFF above the base address. In the previous example, the VME window was from 0xAB0000 to 0xABFFFF.

=== Data Transfer Capabilities ===
The board can access the VME BUS in VME_D16, VME_D32, VME 32-bit and 64-bit block transfers (BLT32 and MBLT64). The VME_D8 is not compatible. D32 is recommended for accessing collector registers and 64-bit block transfer (MBLT64) is recommended for reading data from the VME data FIFO. See VME Mapping to have more details on this.

==VME Mapping==

The Table 2.2.1 describes the VME Mapping of the VF48 collector registers. In the Table 2.2.1, the W column indicates if the register is available for a Write. The R column indicates if the register is available for a Read. The last three columns indicate permitted access modes.

– VME Mapping
{| style="color:green; background-color:#ffffcc;" cellpadding="10" cellspacing="0" border="1"
|-!Offset ||VME Mapping ||Access ||Mode
|-
|0x0000||CSR||R/W||D16/32
|-
|0x0010|| || ||
|-
|0x0020|| || ||
|-
|0x0030||Firmware ID ||R || D16/32
|-
|0x0040|| || ||
|-
|0x0050||Param DAT ||W ||D16/32
|-
|0x0060||Param ID ||W ||D16/32
|-
|0x0070||Soft Trigger ||W ||D16/32
|-
|0x0080|| || ||
|-
|0x0090||Group Enable ||R/W ||D16/32
|-
|0x00A0||NbrFrames ||R ||D16/32
|-
|0x00B0||Global Reset || W ||
|-
|0x01XX||Event Data ||R ||D32/BLT32/MBLT64
|-
|}

===CSR Description ===
Only six bits of the CSR (Control & Status Registry) are used. They are indicated in the Table 2.2.2.

{| style="color:green; background-color:#ffffcc;" cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit ||CSR Description ||Access
|-
|0|| Run ||R/W
|-
|1|| Parameter ID Ready|| R
|-
|2|| Parameter DATA Ready||R
|-
|3|| Event Fifo Empty||R
|-
|4|| ||
|-
|5||CRC Error detected || R
|-
|6|| ||
|-
|7||External Trigger || R/W
|-
|}

The RUN bit allows the system to accept triggers and start the acquisition.

The Parameter ID Ready bit and Parameter DAT Ready bit indicate if parameter is ready to be read. The parameter section will describe more precisely how these bits work.

The Event Fifo Empty bit indicates if the event fifo is empty. When this signal is low, there’s data ready to be read.

The CRC Error Detected bit indicates if a CRC Error has been detected in the serial communication on the board. This bit should never go on.

The External trigger bit selects the external trigger. If this bit is set to 1, the trigger that will start the acquisition must come from the connector on the front panel. If this bit is zero, then a real signal must be detected on one of the 48 channels if you want to have event built.

=== Firmware ID (0x000030) ===
It returns the firmware ID

===Parameter DAT (0x000050)===
Register used to write the parameter. See the section Writing/Reading Parameter for more details.

=== Parameter ID (0x000060)===
Register used to write the parameter. See the section Writing/Reading Parameter for more details.

===Soft Trigger (0x000070)===
It generates a trigger on the front end to force the system to acquire data.

===Group Enable (0x000090)===
It allows enabling a group of channels. Bit 0 enables channel 1 to 8, bit 1 enables channel 9 to 16 until bit 5 which enable channels 41 to 48. By default, they are all enabled.
2.2.7. Nbr Frames (0x0000A0)
It gives the number of data present in the event fifo. See section 4. Triggers & Events for more details.

===Global Reset (0x0000B0)===
It resets all the system.

===Event Data (0x000100-0x00FFFF)===
It reads all the data in the fifo. See section 4. Triggers & Events for more details.

= Writing/Reading Parameter =
To write a parameter, you must write the parameter ID (See Table 3.1.1) followed by the parameter Data. You write the parameter ID by doing a VME Write at the address Param ID and you write the parameter Data by doing a VME Write at the address Param DAT.

During a parameter read, it is necessary to be aware that parameter is not immediately in the register ParamDAT. The bit 2 of the CSR rises up when the parameter is ready and falls down when you read it. So, the procedure to read a parameter is this. First, you send the request by writing the parameter ID (VME Write at the address ParamID) with bit 7 set to 1. You must also send a fake data, because if you don’t send a fake data, the request will never be sent. After, you read bit 2 of the CSR until it has been set. When the bit is set, you do a VME Read at the address ParamDAT .

===Parameter Frame Header===
The first 16 bits of a frame contain information describing the contents of the parameter.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Parameter Frame Header
|-
!15|| || || ||11|| || || ||7||6|| || || || || || 0
|-
|C ||C||C||C|| D||D||D||D||R||V||P||P||P||P||P||P
|}

* C : Destination Card or Port or Cyclone
* D : Destination Channel (0-5)
* R : ReadBit
* V : Version (0- No extension; 1- Param ID 32 bit)
* P : Parameter ID

Description of the fields Parameter Frame Header:
Destination Card
Bits 11 - 8 contain the number of the card where parameter must be sent. The following table describes the direction which has to take parameter according to the number of destination of card, the number of port or the number of cyclone on the board.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Destination Cyclone
|-
!11 ||10|| 9|| 8|| Destination Cyclone ||Port
|-
|0 ||0|| 0|| 0|| Channel 1 to 8 ||0
|-
|0 ||0|| 0|| 1|| Channel 9 to 16 ||1
|-
|0 ||0|| 1|| 0|| Channel 17 to 24|| 2
|-
|0 ||0|| 1|| 1|| Channel 25 to 32|| 3
|-
|0 ||1|| 0|| 0|| Channel 33 to 40|| 4
|-
|0 ||1|| 0|| 1|| Channel 41 to 48|| 5
|-
|0 ||1|| 1|| 0|| Not used ||Not used
|-
|1 ||1|| 1|| 1|| Not used ||Not used
|}
* Destination Channel
This field is not used for the current version. We don’t care of these bits.

* ReadBit
Bit 7 indicates if command is a demand of writing or reading of the parameter. If ReadBit is HIGH, then it is a read and parameter should be sent back to the collector. If ReadBit is LOW, then it is a write and parameter should be recorded.

During a parameter read, it is necessary to be aware that parameter is not immediately in the register ParamDAT. The bit 2 of the CSR rises up when the parameter is ready and falls down when you read it.
Version Bit

This bit must be zero in this version
Parameter ID
The last six bits contains the parameter ID. Each parameter available is displayed in the Table 3.1.3

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Parameter List
|-
!ID# ||Parameter List|| Default Value|| Access
|-
|0 || || ||
|-
|1|| PED ||0x0000 ||R/W
|-
|2|| Hit Det Threshold|| 0x000A ||R/W
|-
|3|| Clip Delay ||0x0028 ||R/W
|-
|4|| PreTrigger ||0x0020 ||R/W
|-
|5|| Segment Size ||0x0100 ||R/W
|-
|6|| K ||0x0190 ||R/W
|-
|7|| L ||0x0200 ||R/W
|-
|8|| M ||0x1000 ||R/W
|-
|9|| Channel Enable ||0x00FF ||R/W
|-
|10|| Mbits 1 - Feature Enable|| 0x0000 ||R/W
|-
|11|| Mbits 2 - Feature Enable|| 0x0000 ||R/W
|-
|12|| Latency ||0x0005 ||R/W
|-
|13|| Firmware ID ||0x0207 ||R/W
|-
|14|| Attenuator ||0x0190 ||R/W
|-
|15|| Trigger Threshold|| 0x000A ||R/W
|}

=== Parameter Description ===
This section is there to describe each parameter.
1 - PED
This parameter is not used yet.
2 – Hit Detection Threshold
This parameter defines the threshold to detect a hit. If the signal given by the ADC is above this threshold value, the system will start to calculate the charge, but if the signal doesn’t reach the trigger threshold, the charge won’t be used.
3 – Clip Delay
This parameter is not used yet.
4 – Pre-Trigger
This parameter defines the number of clock where the data must be recorded before the trigger.
5 – Segment Size
This parameter defines the number of raw data that must be recorded.
6 - K
This parameter defines the peaking time. See the signal processing section for more details.
7 - L
This parameter represents the duration of the peaking time and the flat top together. See the signal processing section for more details.
8 - M
This parameter defines a multiplication factor of the convoluted signal. See the signal processing section for more details.
9 – Channel Enable
This parameter indicates the channels that must be included in the event. Bit 0 enables channel 0, bit 1 enables channel 1, so in succession until channel 7. By default, all channels are enabled.

Note: In version previous to version 2.0.7, the parameter 11 was FeatureDelay_B. This parameter doesn’t exist anymore.
10 – M_Bits
This parameter is a parameter where each bit has a different purpose. The Table 3.2.1 gives information about these bits.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Description of the MBits parameter
|-
!Bit|| Version 2.0 and more|| Version before 2.0
|-
|0|| Data Simulation|| Data Simulation
|-
|1|| Suppress Raw Data|| Supress Raw Data
|-
|2|| Select Corrected Data|| Select Corrected Data
|-
|3|| PolPlus|| PolPlus
|-
|4|| BLR Speed (bit 0)|| Disable ADC
|-
|5|| BLR Speed (bit 1)|| Fake One Data
|-
|6|| Hold BLR ||-
|-
|7|| - ||-
|-
|8|| Disable ADC ||-
|-
|9|| Offset 1 ||-
|-
|10|| Offset 2 ||-
|-
|11|| Low Gain Selection ||-
|-
|12|| Card Revision Number (bit 0) ||-
|-
|13|| Card Revision Number (bit 1) ||-
|-
|14|| Card Revision Number (bit 2) ||-
|-
|15|| Card Revision Number (bit 3) ||-
|}

The bit 0, Data Simulation, enables the simulator. If this bit is set, the simulated data will be continually sent.

The bit 1, Suppress Raw Data, suppresses the raw data independently of the segment size parameter.

The bit 2, Select Corrected Data, is not used in the current version.

The bit 3, PolPlus, is used to invert numerically the input. If the input is 0b0100010001, and the bit PolPlus set then the input will be 0b1011101110.

The bit 8, Disable ADC, disable the ADC.

The bit 5, Fake One Data, has the same use as the bit 0, Data Simulation, but it will be activated for only one valid signal.

All the other bits are reserved for future use. The names indicated represent the function that is reserved for the bit to be compatible with other project.
11 – M_Bits 2
This parameter is a parameter where each bit has a different purpose. The Table 3.2.2 gives information about these bits.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Description of the MBits 2 parameter
|-
!Bit|| Version 2.0 and more|| Version before 2.0
|-
|0|| Enable Channel Suppression ||-
|-
|1|| Doesn't send time evaluation ||-
|-
|2|| Doesn't send charge calculated ||-
|-
|3|| -||-
|-
|4|| -||-
|-
|5|| -||-
|-
|6|| -||-
|-
|7|| -||-
|-
|15..8||Sampling Rate Divider||-
|}

* bit 0, Enable Channel Suppression, disable an entire channel within a group if none of the sample values of that channel is above the hit threshold.

* bit 1, Doesn’t send charge calculated, disables the calculation of the charge. If this bit is set, the charge won’t be calculated.

* bit 2, Doesn’t send time evaluation, disables the evaluation of the time when the signals passes above the threshold. If this bis set, the time won’t be evaluated.

Note: In version previous to version 2.0.7, the parameter 11 was FeatureDelay_B. This parameter doesn’t exist anymore.
12 – Latency
This parameter defines the number of clock to be added to the pre-trigger. This parameter should represent the time between the hit detection and the trigger accepted received by the front end.
13 – Firmware ID
This parameter is firmware ID. For example, if the version is 1.0.0, it will return 0x0100. If the version is 11.12.13, it will return 0x0BCD.
14 – Attenuator
This parameter defines the attenuation of the integration. See the signal processing section for more details.
15 – Trigger Threshold
This parameter defines the threshold to accept a trigger. If the signal given by the ADC is above the threshold value, a trigger request will be sent to the collector.

= Triggers & Events=

When a trigger is accepted, the front end starts to build an event which will be transferred to the collector. Each event has the same format. This section defines this format, but before, let us defines some terms usually used in this section.

A Packet is a word of 32 bits which contains information related with an event.

An Event is a series of packet beginning with a header and ending by a trailer.

== Trigger Detection==
Each channel goes through a comparator in order to trigger the feature evaluation. The hit threshold is a positive difference of 2 ADC values separated by 2 samples (ex: 2,3,4,5,6,7  hit Thr= 6-3).
In the case the input signal has the opposite polarity, you can either reverse the input signal (the VF48 input is bipolar) or reverse the polarity by software. The polarity switch is applied to the digitized ADC values. Currrently no dedicated reverse polarity function is available. Use the example found under midas/examples/Triumf/c/fevmemodules.c/BOR function.
The acceptance of the next trigger is garanteed when there is space for one event or more. A corresponding deadtime is generated for the duration of the capture of the raw data in the frontend buffer. The buffer size is fixed at 1000 samples. Therefore the pipeline advantage starts when the event size is less than 500 samples (this limits is set by the hardware type used on the board).
There is an output signal (busy out signal) available reflecting the non acceptance of trigger by the VF48. This correspond to the "deadtime" from the raw data capture ored with the condition of the frontend buffer having no more room for a complete event.

== Event Description==
An event is broken in many packets which follow a precise order. It always has to begin with a header and end with a trailer. The header and the trailer contain the trigger number and they must be identical. The header is always followed by a timestamp. Then, for each channel enabled, it could contain the raw data, the CFD time evaluated and the charge calculated. The Table 4.2.1 shows the content of an event.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Event’s content
|-
!Packet's Type ||MSB
|-
|Event Header ||0x8
|-
|Time Stamp 1 ||0xA
|-
|Time Stamp 2 ||0xA
|-
|Channel ID ||0xC
|-
|Raw Data (of current channel) ||0x0
|-
|CFD Time (of current channel) ||0x4
|-
|Charge (of current channel) ||0x5
|-
|Channel ID ||0xC
|-
|Raw Data (of current channel) ||0x0
|-
|CFD Time (of current channel) ||0x4
|-
|Charge (of current channel) ||0x5
|-
|… ||
|-
|Channel ID ||0xC
|-
|-
|Raw Data (of current channel) ||0x0
|-
|CFD Time (of current channel) ||0x4
|-
|Charge (of current channel) ||0x5
|-
|Event Trailer ||0xE
|}

The number of raw data is configurable by the parameter Segment Size (Chan Param ID:5). The next section will describe more in detail each of these packets.

== Event Packet Format==
This section describes in detail the contents of each of the packets. Firstly, inside a packet, the 4 MSB indicates the type of packet. The next table makes the association between the MSB and the packets.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Event Packet MSB Association
|-
!Packet's Type ||MSB
|-
|Header ||0x8
|-
|Time Stamp 1 ||0xA
|-
|Time Stamp 2 ||0xA
|-
|Channel ID ||0xC
|-
|Raw Data ||0x0
|-
|CFD Time ||0x4
|-
|Charge ||0x5
|-
|Trailer ||0xE
|-
|Header Error ||0x9
|-
|Error ||0xF
|-
|Header ||0x8xxxxxxx
|}

The packet Header is always the first packet of an event. It contains the trigger number in the bits 23 to 0.

Table 4.3.2 – Header 0x8xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||0||0||0||colspan="4" align="center"|0|| T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T
|}
Trigger Number

Header Error - 0x9xxxxxxx
The Header Error packet occurs when the first packet of a group was not a Header packet. This could be caused by an internal error. If this packet is detected, the current event must be rejected. However, this packet must not happen and if it does, you should contact your supplier.

Table 4.3.3 – Header Error 0x9xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||0||0||1||colspan="4" align="center"|0||colspan="24" align="center"|Trigger Number
|}

Time Stamp - 0xAxxxxxxx
The Time Stamp packet is the second packet and the third packet of en event. It contains a 48 bits time stamps. The time between two steps is of 25 ns . Then, with a 48 bits timestamp, the maximum time measured is 7 036 874,418 seconds. Then, system can count time without completing a buckle during more than 81 days.

Table 4.3.4 – Time Stamp – 0xAxxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||0||1||0||colspan="4" align="center"|0|| colspan="24" align="center"|Time Stamp
|}

The first time stamp packet contains bit 47 to 24 and the second time stamp packet contains bits 23 to 0.
Channel ID - 0xCxxxxxxx
The channel ID packet is the first packet of a sub-event. It contains all the information to be able to identify the channel. Bit 3 to 0 indicates the channel number. This number can go from 0 to 7. It corresponds to the channel of a particular group. Then, bits 6 to 3 identify the group. They can so take a value going from 0 to 5. Bit 7 is not used in this version.

Table 4.3.5 – Channel ID – 0xC0xxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || ||11|| || ||8||7||6|| || ||3|| || ||0
|-
| 1||1||0||0||colspan="4" align="center"|0||0||0||0||0||0||0||0||0||0||0||0||0|| 0||0||0||0||0|| colspan="3" align="center"|Group||colspan="4" align="center"|Channel
|}

Data - 0x0xxxxxxx
The Data packet comes after the channel ID packet. It simply contains two data of 10 bits each. The number of data packet within an event is related to the segment size parameter (Chan Param ID: 5). It could arise problems to have a null value or an odd value of the segment size.

Table 4.3.6 – Data – 0x0xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || ||13|| || || ||9|| || || || || || || || ||0
|-
| 0||0||0||0||colspan="4" align="center"|0|| colspan="10" align="center"|Sampe n+1|| 0||0||0||0|| colspan="10" align="center"|Sample n
|}

Be careful about the position of the second data. It doesn’t start exactly to bit 16. It starts to bit 14. This is done to keep the compatibility with an ADC that would a 14 bits data.
CFD Time - 0x4xxxxxxx
The CFD Time packet is the second packet before the last packet. It contains the CFD Time.

Table 4.3.7 – CFD Time – 0x40xxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 0||1||0||0||colspan="4" align="center"|0|| colspan="24" align="center"| CFD Time
|}

Time algorithm: CDF Equivalent. The input is first clipped with a delay of 3 clocks. If the clipped signal is above the hit threshold then the maximum value of the clipped waveform is evaluated. The CFD time is then evaluated by interpolating the time at 50% charge using the two samples on either side of the 50% fraction.

Charge - 0x5xxxxxxx
The Charge Packet is the first packet before the trailer packet. It contains the charge internally calculated.

Table 4.3.8 – Charge – 0x50xxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 0||1||0||1||colspan="4" align="center"|0|| colspan="24" align="center"|Charge
|}

Trailer - 0xExxxxxxx
The trailer is always the last packet of an event. It contains the trigger number in the bits 23 to 0. The bit 28 indicates an out of sequence flag, then, if this bit is 1, that means that an internal error took place and the packet should be rejected. In theory, system is stable and this type of error should not occur.

Table 4.3.9 – Trailer – 0xExxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||1||1||0||colspan="4" align="center"|0|| colspan="24" align="center"| Trigger Number
|}

Error - 0xFxxxxxxx
The Error packet occurs when a particular packet is not at his right position. This could occur if a timestamp is missing or if a timestamp is not followed by channel. This could be caused by an internal error. If this packet is detected, the entire event must be rejected. However, this packet must not happened and if it does, you should contact your supplier.

Table 4.3.10 – Error 0x9xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||1||1||1|| colspan="28" align="center"|Invalid
|}

== Event Acquisition==
Procedure to read events is very simple. It is a question of reading the number of packet presently available by making a reading on the bus VME at the address NbrFrames. Then, a reading in burst of the number of packet available can be made. The reading of events is done in fifo mode only. This means that the reading is done always at the same address, the Event Data address.

To start the acquisition, you must set the bit 0 of the CSR to 1. To stop the acquisition, you set the bit 0 of the CSR to 0.

The system integrates a signal processing logic which calculates the charge and the precise time where the hit has been detected. In the FE FPGA the continuous flow of digitized signal samples from the ADC is directed to the signal processing logic. The signal processor runs continuously. It performs tasks equivalent to a spectroscopy amplifier connected to an analog multi-channel analyzer.

== Aux Output==
The aux_out front panel output can be set to provide a trigger output, busy output or system clock output, this function is selected by triggerconfig[3..0] and CSR[16] ...

*triggerconfig[0] = 1 sets AuxTrigDisable prevents trigger from reaching aux-out (This was for tactic)
*triggerconfig[1] = 1 Enables the self-trigger Logic (when 0 the logic is just a a simple OR of the 6 Front End trigger requests)
*triggerconfig[2] = 1 selects tigc trigger (rather than the self trigger)
*triggerconfig[3] = 1 sets the system clock to aux_out (rather than trigger)
There is also a "select busy out" signal [CSR[16]] which overrides all the above and puts the busy signal to aux_out

The triggerconfig register is 64bits wide, the remaining 60 bits are used to set the self-trigger logic
*triggerconfig[39.. 4] = GroupThresholds 6 thresholds of 6 bits each (0-63)
*triggerconfig[57..40] = FeGroups 6 groupid's of 3 bits each (0-7)
*triggerconfig[63..58] = GroupCoincidence 6 bits, 1 bit enabling each of the 6 groups

There are 6 frontend FPGAs with 8 channels each, each sends its trigger multiplicity (0-8) to the collector. There are 6 possible groups to assign the frontends to (One simple scheme would be to put all 6 in a single group - the multiplicity from this group would then be the total multiplicity on this VF48, in this case, all 6 groupids would be the same, only 1 bit would be enabled in GroupCoincidence, and only 1 multiplicity(GroupThreshold) would need to be set)

= Signal Processing =

The system integrates a signal processing logic which calculates the charge and the precise time where the hit has been detected. In the FE FPGA the continuous flow of digitized signal samples from the ADC is directed to the signal processing logic. The signal processor runs continuously. It performs tasks equivalent to a spectroscopy amplifier connected to an analog multi-channel analyzer.

[[Image:splogic.jpg]]

== Real-Time Digital Filter and Charge Evaluation==

The filtering involves many steps. The first step is the deconvolution of the exponential tail of the pulse shape within an arbitrary time window. The moving window deconvolution method is well documented in the litterature. It is implemented as a finite impulse response filter (FIR). If D0, D1, … Dn, represent the digitized signal samples, and L the span of the moving window, the nth point of the transformed sequence Fn is given by the relation:

(1) [[Image:f1vf48.jpg]]

where τ is the exponential time constant of the signal in units of data samples. The deconvolution is useful in the case of a germanium detector to compensate for the differences in ballistic deficit as a function of the rise time of the signal. Depending on the position of the photon interaction, the charge collection time may vary from event to event by as much as 150 nanoseconds. With a preamplifier decay time constant of 50 microseconds, this translates into a fluctuation of the raw signal peak amplitude corresponding to 3 Kev for a 1 Mev gamma. With an analog system, this fluctuation is reduced significantly by using a long filter peaking time, but it never vanishes. With the moving window deconvolution method, the tail pulse shape is transformed into a quasi-rectangular pulse shape, with a duration determined by the span of the moving window. The transformed signal has a leading edge reflecting the shape of the original signal (with a slight correction for the exponential decay), and then reaches a constant maximum value that is exactly the same for a given total charge deposited in the detector whatever the rise-time. The processed signal also returns to zero with no tail.

It can be seen from equation (1) that the first two terms will cancel the DC baseline. However, the sum term that cancels exactly the exponential decay will unfortunately respond to a baseline level with a gain of L/τ. The sum term also limits the effectiveness of the low frequency filtering effect of the first two terms. To alleviate this problem, one can resort to double sampling, or use a baseline restoring scheme. We have chosen this later approach. The baseline restoring process is active only when no signal is present.

At this stage, the filtering is not yet complete. Only the low frequency part of the noise spectrum has been attenuated. The high frequency filtering is performed by applying another FIR transformation to the corrected deconvoluted signal. The most efficient filter for the evaluation of the trend of a noisy straight line (the flat part of the rectangular pulse shape) is the simple floating average transformation, commonly called a boxcar filter:

(2) [[Image:f2vf48.jpg]]

K is chosen to be as close as possible to the size of the flat portion of the rectangular pulse Fn . For a theoretical signal having a zero rise time and an exponential decay with time constant equal to τ, the sequence of points Gn represents a trapeze with a rise time of K, a flat portion of L-K, and a fall time of K. Every point of the flat top part of the pulse is a proper evaluation of the charge. Selecting the maximum value is simple, but it generates a small average bias proportional to the noise. We rather select the measurement point at a pre-determined time after the beginning of the pulse, based on the timing information produced by the CFD discriminator. This amounts to selecting the point at random (as far as the amplitude is concerned) in the flat top region, thereby reducing the bias.

Due to constraint design (the division by τ would involve excessive FPGA resources), we multiply both sides of equation (1) by τ (parameter M), and we do not normalize by the number of points. The result appearing in the event list is given by

It can be scaled down by software when the histograms are constructed.

== Digital Constant Fraction Discriminator==
Analog constant fraction discriminators (CFD) are widely used to minimize the time walk associated with the detection of signals featuring widely varying amplitudes. The same principle can be applied to digital signal samples, with some differences in the physical implementation. In the VF48 firmware, the implementation reproduces exactly the definition of a CFD: The amplitude of the signal is evaluated, and a threshold is calculated with a predefined fraction. The same signal, delayed through a digital delay line (dual port RAM), is then compared with this calculated threshold until the point immediately below, and the point immediately above the threshold are found. Then, a linear interpolation is performed to evaluate the time corresponding to the threshold crossing. We use time units of 1/16 of the ADC sampling clock period for the interpolation. Often, the rise time is not constant from event to event, as it depends on the position where the electron-holes pairs were created in the crystal. So, it is important to clip the incoming signal to a width equal or shorter than the fastest signal rise time envisioned before the CFD logic. This is achieved by subtracting two samples separated by the proper number of sampling clocks. This has the same effect as the clipping delay line of an analog CFD. The digital CFD produces two outputs: a logic signal synchronized with the ADC clock, when the constant fraction threshold is crossed, and a higher precision time stamp word. The logic signal is used by the trigger logic, whilst the time stamp is part of the event data stream.

== Latency and Event Segment Buffers==

In order to accommodate for the latency of the trigger system, a circular latency buffer is used to keep the past values of the signal samples available for a time equal or longer than the trigger decision latency. The input of the buffer is either the raw data signal, or the output of the deconvolution logic. This can be selected by a run parameter. The maximum capacity of the latency buffer is presently 512 elements. When a trigger is accepted, this delay allows the recovery of the associated signal since its very beginning. We usually also include a few samples that have occurred before the signal. The latency buffer is implemented in a dual port random access memory running continuously. The read address is equal to the write address minus the number of clock cycles we want to have the data delayed. The signal data is continuously written in the memory, and the delayed data continuously available on the readout port. When a trigger is accepted, a transfer gate is generated for a duration corresponding to the size of the data segment requested, and the data read out is transferred to the next buffer stage: the segment event buffer.

The segment buffer is a simple 1024 word FIFO that stores the waveform data segments, plus two extra bits indicating the beginning and end of these segments. The FIFO is read out asynchronously by the list formatter. The function of the Segment Buffer is to store a few events in order to deramdomize the data flow. The segment buffer also generates an almost full flag that is transmitted to the master trigger system. This is the mechanism that throttles the trigger rate when the data acquisition becomes throughput limited. When the throughput is significantly lower than the system bandwidth, the data acquisition is dead-timeless.

== Digital Constant Fraction Discriminator==
Analog constant fraction discriminators (CFD) are widely used to minimize the time walk associated with the detection of signals featuring widely varying amplitudes. The same principle can be applied to digital signal samples, with some differences in the physical implementation. In the VF48 firmware, the implementation reproduces exactly the definition of a CFD: The amplitude of the signal is evaluated, and a threshold is calculated with a predefined fraction. The same signal, delayed through a digital delay line (dual port RAM), is then compared with this calculated threshold until the point immediately below, and the point immediately above the threshold are found. Then, a linear interpolation is performed to evaluate the time corresponding to the threshold crossing. We use time units of 1/16 of the ADC sampling clock period for the interpolation. Often, the rise time is not constant from event to event, as it depends on the position where the electron-holes pairs were created in the crystal. So, it is important to clip the incoming signal to a width equal or shorter than the fastest signal rise time envisioned before the CFD logic. This is achieved by subtracting two samples separated by the proper number of sampling clocks. This has the same effect as the clipping delay line of an analog CFD. The digital CFD produces two outputs: a logic signal synchronized with the ADC clock, when the constant fraction threshold is crossed, and a higher precision time stamp word. The logic signal is used by the trigger logic, whilst the time stamp is part of the event data stream.

== Latency and Event Segment Buffers==

In order to accommodate for the latency of the trigger system, a circular latency buffer is used to keep the past values of the signal samples available for a time equal or longer than the trigger decision latency. The input of the buffer is either the raw data signal, or the output of the deconvolution logic. This can be selected by a run parameter. The maximum capacity of the latency buffer is presently 512 elements. When a trigger is accepted, this delay allows the recovery of the associated signal since its very beginning. We usually also include a few samples that have occurred before the signal. The latency buffer is implemented in a dual port random access memory running continuously. The read address is equal to the write address minus the number of clock cycles we want to have the data delayed. The signal data is continuously written in the memory, and the delayed data continuously available on the readout port. When a trigger is accepted, a transfer gate is generated for a duration corresponding to the size of the data segment requested, and the data read out is transferred to the next buffer stage: the segment event buffer.

The segment buffer is a simple 1024 word FIFO that stores the waveform data segments, plus two extra bits indicating the beginning and end of these segments. The FIFO is read out asynchronously by the list formatter. The function of the Segment Buffer is to store a few events in order to deramdomize the data flow. The segment buffer also generates an almost full flag that is transmitted to the master trigger system. This is the mechanism that throttles the trigger rate when the data acquisition becomes throughput limited. When the throughput is significantly lower than the system bandwidth, the data acquisition is dead-timeless.

= Firmware Update=

To do an update, you will need the ByteBlaster II connector connected on the parallel port of your PC and to the connector J3 on the VF48 board. (Or an USB Blaster module)

Then, you must download the programmer on the Altera Website:
https://www.altera.com/support/software/download/programming/quartus2/dnl-quartus2_programmer.jsp

Then, you start the program. You change the mode from JTAG to Active Serial Programming. You push the Hardware Setup button and you select ByteBlaster II. Then, you push the Add File button and you select the pof file that we supplied you. After, you click in the Program/Configure case and finally you push the Start button.

When the firmware has been programmed, you must unplug the ByteBlaster II connector from the VF48 board, shut down the power and put it back.

If the green light is on, programming was completed successfully. If the green light is off, did you forget to unplug the ByteBlaster II connector? If no, restart all the procedure.

== Label Convention==

A label convention is done to name each version that is created. It starts by the firmware main revision. Then, we add respectively the sub revision, the sampling frequency, the system clock frequency and the special features if they exist.

For example, the name VF48_V207_X6_40_20_Alpha.pof is associated to the firmware version 2.0.7 with a sampling frequency of 40 MHz and a system frequency of 20 MHz. The special feature Alpha signifies that this version is done specifically for Alpha project.

== Firmware history ==

VF48

2010-09-16T21:21:34Z

Cpearson: /* Triggers & Events */

= VF48 - 48 channels@60Msps, 10bits =

== General characteristics ==
The VF48 is a one-unit wide VME 6U housing 48 channels digitized by six fast 10-bit ADCs. For each channel, the input signal (50 Ω impedance) is amplified by a high speed differential amplifier (AD8132) and them converted by the ADCs at a maximum rate of 60 Msps.

The digitized signal goes to a FPGA (Cyclone EPC12) which will calculate the charge of the signal, evaluate the exact trigger time, build an event which will contain all this information and send the event constructed to a local collector. Each FPGA manages eight channels. There are six FPGA connected to the ADCs and one FPGA which collects the data.

The board can be accessed in A24/A32/A40 addressing mode, D16, D32 and MBLT64 data transfer mode.

It has also a board available to access the VF48 throw a LVDS link. This link can transfer the data at a speed up to 100 Mbits/s. This link can afford all the control necessary to run the VF48. It can accept a clock which permits the synchronization of many VF48 units.

The board contains a trigger structure which permits to trigger the data in three different manners. The trigger can come from an external NIM signal, from a software command or from an internal mechanism. The internal mechanism manages multiple channels hit, deadtime, threshold and multiplicity and is totally programmable by the user.

[[Image:blockdigvf48.jpg|Block Diagram of the VF48]]

= VME interface =
The VF48 board can access the VME bus in VME A24. See Table 2.1.1 to have more information about the Address Modifier accepted.

{|style="color:green; background-color:#ffffcc;" cellpadding="10" cellspacing="0" border="1"
|+ Summarizes all the supported address Modifer
|-
!AM||Description
|-
|3F
|A24 supervisory block transfer (BLT)
|-
|3D
|A24 supervisory data access
|-
|3C
|A24 supervisory 64-bit block transfer (MBLT)
|-
|3B
|A24 non privileged block transfer (BLT)
|-
|39
|A24 non privileged data access
|-
|38
|A24 non privileged 64-bit block transfer (MBLT)
|-
|}

=== Base Address ===

The base address of the board is 0xA00000 + n • 0x10000. The number n is defined by the alignment of the switch on the board. For example, if the alignment on the switch is : ID[3..0] = 1011, then the base address will be 0xAB0000.

Every board will manage a window going until 0x00FFFF above the base address. In the previous example, the VME window was from 0xAB0000 to 0xABFFFF.

=== Data Transfer Capabilities ===
The board can access the VME BUS in VME_D16, VME_D32, VME 32-bit and 64-bit block transfers (BLT32 and MBLT64). The VME_D8 is not compatible. D32 is recommended for accessing collector registers and 64-bit block transfer (MBLT64) is recommended for reading data from the VME data FIFO. See VME Mapping to have more details on this.

==VME Mapping==

The Table 2.2.1 describes the VME Mapping of the VF48 collector registers. In the Table 2.2.1, the W column indicates if the register is available for a Write. The R column indicates if the register is available for a Read. The last three columns indicate permitted access modes.

– VME Mapping
{| style="color:green; background-color:#ffffcc;" cellpadding="10" cellspacing="0" border="1"
|-!Offset ||VME Mapping ||Access ||Mode
|-
|0x0000||CSR||R/W||D16/32
|-
|0x0010|| || ||
|-
|0x0020|| || ||
|-
|0x0030||Firmware ID ||R || D16/32
|-
|0x0040|| || ||
|-
|0x0050||Param DAT ||W ||D16/32
|-
|0x0060||Param ID ||W ||D16/32
|-
|0x0070||Soft Trigger ||W ||D16/32
|-
|0x0080|| || ||
|-
|0x0090||Group Enable ||R/W ||D16/32
|-
|0x00A0||NbrFrames ||R ||D16/32
|-
|0x00B0||Global Reset || W ||
|-
|0x01XX||Event Data ||R ||D32/BLT32/MBLT64
|-
|}

===CSR Description ===
Only six bits of the CSR (Control & Status Registry) are used. They are indicated in the Table 2.2.2.

{| style="color:green; background-color:#ffffcc;" cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit ||CSR Description ||Access
|-
|0|| Run ||R/W
|-
|1|| Parameter ID Ready|| R
|-
|2|| Parameter DATA Ready||R
|-
|3|| Event Fifo Empty||R
|-
|4|| ||
|-
|5||CRC Error detected || R
|-
|6|| ||
|-
|7||External Trigger || R/W
|-
|}

The RUN bit allows the system to accept triggers and start the acquisition.

The Parameter ID Ready bit and Parameter DAT Ready bit indicate if parameter is ready to be read. The parameter section will describe more precisely how these bits work.

The Event Fifo Empty bit indicates if the event fifo is empty. When this signal is low, there’s data ready to be read.

The CRC Error Detected bit indicates if a CRC Error has been detected in the serial communication on the board. This bit should never go on.

The External trigger bit selects the external trigger. If this bit is set to 1, the trigger that will start the acquisition must come from the connector on the front panel. If this bit is zero, then a real signal must be detected on one of the 48 channels if you want to have event built.

=== Firmware ID (0x000030) ===
It returns the firmware ID

===Parameter DAT (0x000050)===
Register used to write the parameter. See the section Writing/Reading Parameter for more details.

=== Parameter ID (0x000060)===
Register used to write the parameter. See the section Writing/Reading Parameter for more details.

===Soft Trigger (0x000070)===
It generates a trigger on the front end to force the system to acquire data.

===Group Enable (0x000090)===
It allows enabling a group of channels. Bit 0 enables channel 1 to 8, bit 1 enables channel 9 to 16 until bit 5 which enable channels 41 to 48. By default, they are all enabled.
2.2.7. Nbr Frames (0x0000A0)
It gives the number of data present in the event fifo. See section 4. Triggers & Events for more details.

===Global Reset (0x0000B0)===
It resets all the system.

===Event Data (0x000100-0x00FFFF)===
It reads all the data in the fifo. See section 4. Triggers & Events for more details.

= Writing/Reading Parameter =
To write a parameter, you must write the parameter ID (See Table 3.1.1) followed by the parameter Data. You write the parameter ID by doing a VME Write at the address Param ID and you write the parameter Data by doing a VME Write at the address Param DAT.

During a parameter read, it is necessary to be aware that parameter is not immediately in the register ParamDAT. The bit 2 of the CSR rises up when the parameter is ready and falls down when you read it. So, the procedure to read a parameter is this. First, you send the request by writing the parameter ID (VME Write at the address ParamID) with bit 7 set to 1. You must also send a fake data, because if you don’t send a fake data, the request will never be sent. After, you read bit 2 of the CSR until it has been set. When the bit is set, you do a VME Read at the address ParamDAT .

===Parameter Frame Header===
The first 16 bits of a frame contain information describing the contents of the parameter.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Parameter Frame Header
|-
!15|| || || ||11|| || || ||7||6|| || || || || || 0
|-
|C ||C||C||C|| D||D||D||D||R||V||P||P||P||P||P||P
|}

* C : Destination Card or Port or Cyclone
* D : Destination Channel (0-5)
* R : ReadBit
* V : Version (0- No extension; 1- Param ID 32 bit)
* P : Parameter ID

Description of the fields Parameter Frame Header:
Destination Card
Bits 11 - 8 contain the number of the card where parameter must be sent. The following table describes the direction which has to take parameter according to the number of destination of card, the number of port or the number of cyclone on the board.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Destination Cyclone
|-
!11 ||10|| 9|| 8|| Destination Cyclone ||Port
|-
|0 ||0|| 0|| 0|| Channel 1 to 8 ||0
|-
|0 ||0|| 0|| 1|| Channel 9 to 16 ||1
|-
|0 ||0|| 1|| 0|| Channel 17 to 24|| 2
|-
|0 ||0|| 1|| 1|| Channel 25 to 32|| 3
|-
|0 ||1|| 0|| 0|| Channel 33 to 40|| 4
|-
|0 ||1|| 0|| 1|| Channel 41 to 48|| 5
|-
|0 ||1|| 1|| 0|| Not used ||Not used
|-
|1 ||1|| 1|| 1|| Not used ||Not used
|}
* Destination Channel
This field is not used for the current version. We don’t care of these bits.

* ReadBit
Bit 7 indicates if command is a demand of writing or reading of the parameter. If ReadBit is HIGH, then it is a read and parameter should be sent back to the collector. If ReadBit is LOW, then it is a write and parameter should be recorded.

During a parameter read, it is necessary to be aware that parameter is not immediately in the register ParamDAT. The bit 2 of the CSR rises up when the parameter is ready and falls down when you read it.
Version Bit

This bit must be zero in this version
Parameter ID
The last six bits contains the parameter ID. Each parameter available is displayed in the Table 3.1.3

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Parameter List
|-
!ID# ||Parameter List|| Default Value|| Access
|-
|0 || || ||
|-
|1|| PED ||0x0000 ||R/W
|-
|2|| Hit Det Threshold|| 0x000A ||R/W
|-
|3|| Clip Delay ||0x0028 ||R/W
|-
|4|| PreTrigger ||0x0020 ||R/W
|-
|5|| Segment Size ||0x0100 ||R/W
|-
|6|| K ||0x0190 ||R/W
|-
|7|| L ||0x0200 ||R/W
|-
|8|| M ||0x1000 ||R/W
|-
|9|| Channel Enable ||0x00FF ||R/W
|-
|10|| Mbits 1 - Feature Enable|| 0x0000 ||R/W
|-
|11|| Mbits 2 - Feature Enable|| 0x0000 ||R/W
|-
|12|| Latency ||0x0005 ||R/W
|-
|13|| Firmware ID ||0x0207 ||R/W
|-
|14|| Attenuator ||0x0190 ||R/W
|-
|15|| Trigger Threshold|| 0x000A ||R/W
|}

=== Parameter Description ===
This section is there to describe each parameter.
1 - PED
This parameter is not used yet.
2 – Hit Detection Threshold
This parameter defines the threshold to detect a hit. If the signal given by the ADC is above this threshold value, the system will start to calculate the charge, but if the signal doesn’t reach the trigger threshold, the charge won’t be used.
3 – Clip Delay
This parameter is not used yet.
4 – Pre-Trigger
This parameter defines the number of clock where the data must be recorded before the trigger.
5 – Segment Size
This parameter defines the number of raw data that must be recorded.
6 - K
This parameter defines the peaking time. See the signal processing section for more details.
7 - L
This parameter represents the duration of the peaking time and the flat top together. See the signal processing section for more details.
8 - M
This parameter defines a multiplication factor of the convoluted signal. See the signal processing section for more details.
9 – Channel Enable
This parameter indicates the channels that must be included in the event. Bit 0 enables channel 0, bit 1 enables channel 1, so in succession until channel 7. By default, all channels are enabled.

Note: In version previous to version 2.0.7, the parameter 11 was FeatureDelay_B. This parameter doesn’t exist anymore.
10 – M_Bits
This parameter is a parameter where each bit has a different purpose. The Table 3.2.1 gives information about these bits.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Description of the MBits parameter
|-
!Bit|| Version 2.0 and more|| Version before 2.0
|-
|0|| Data Simulation|| Data Simulation
|-
|1|| Suppress Raw Data|| Supress Raw Data
|-
|2|| Select Corrected Data|| Select Corrected Data
|-
|3|| PolPlus|| PolPlus
|-
|4|| BLR Speed (bit 0)|| Disable ADC
|-
|5|| BLR Speed (bit 1)|| Fake One Data
|-
|6|| Hold BLR ||-
|-
|7|| - ||-
|-
|8|| Disable ADC ||-
|-
|9|| Offset 1 ||-
|-
|10|| Offset 2 ||-
|-
|11|| Low Gain Selection ||-
|-
|12|| Card Revision Number (bit 0) ||-
|-
|13|| Card Revision Number (bit 1) ||-
|-
|14|| Card Revision Number (bit 2) ||-
|-
|15|| Card Revision Number (bit 3) ||-
|}

The bit 0, Data Simulation, enables the simulator. If this bit is set, the simulated data will be continually sent.

The bit 1, Suppress Raw Data, suppresses the raw data independently of the segment size parameter.

The bit 2, Select Corrected Data, is not used in the current version.

The bit 3, PolPlus, is used to invert numerically the input. If the input is 0b0100010001, and the bit PolPlus set then the input will be 0b1011101110.

The bit 8, Disable ADC, disable the ADC.

The bit 5, Fake One Data, has the same use as the bit 0, Data Simulation, but it will be activated for only one valid signal.

All the other bits are reserved for future use. The names indicated represent the function that is reserved for the bit to be compatible with other project.
11 – M_Bits 2
This parameter is a parameter where each bit has a different purpose. The Table 3.2.2 gives information about these bits.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Description of the MBits 2 parameter
|-
!Bit|| Version 2.0 and more|| Version before 2.0
|-
|0|| Enable Channel Suppression ||-
|-
|1|| Doesn't send time evaluation ||-
|-
|2|| Doesn't send charge calculated ||-
|-
|3|| -||-
|-
|4|| -||-
|-
|5|| -||-
|-
|6|| -||-
|-
|7|| -||-
|-
|15..8||Sampling Rate Divider||-
|}

* bit 0, Enable Channel Suppression, disable an entire channel within a group if none of the sample values of that channel is above the hit threshold.

* bit 1, Doesn’t send charge calculated, disables the calculation of the charge. If this bit is set, the charge won’t be calculated.

* bit 2, Doesn’t send time evaluation, disables the evaluation of the time when the signals passes above the threshold. If this bis set, the time won’t be evaluated.

Note: In version previous to version 2.0.7, the parameter 11 was FeatureDelay_B. This parameter doesn’t exist anymore.
12 – Latency
This parameter defines the number of clock to be added to the pre-trigger. This parameter should represent the time between the hit detection and the trigger accepted received by the front end.
13 – Firmware ID
This parameter is firmware ID. For example, if the version is 1.0.0, it will return 0x0100. If the version is 11.12.13, it will return 0x0BCD.
14 – Attenuator
This parameter defines the attenuation of the integration. See the signal processing section for more details.
15 – Trigger Threshold
This parameter defines the threshold to accept a trigger. If the signal given by the ADC is above the threshold value, a trigger request will be sent to the collector.

= Triggers & Events=

When a trigger is accepted, the front end starts to build an event which will be transferred to the collector. Each event has the same format. This section defines this format, but before, let us defines some terms usually used in this section.

A Packet is a word of 32 bits which contains information related with an event.

An Event is a series of packet beginning with a header and ending by a trailer.

== Trigger Detection==
Each channel goes through a comparator in order to trigger the feature evaluation. The hit threshold is a positive difference of 2 ADC values separated by 2 samples (ex: 2,3,4,5,6,7  hit Thr= 6-3).
In the case the input signal has the opposite polarity, you can either reverse the input signal (the VF48 input is bipolar) or reverse the polarity by software. The polarity switch is applied to the digitized ADC values. Currrently no dedicated reverse polarity function is available. Use the example found under midas/examples/Triumf/c/fevmemodules.c/BOR function.
The acceptance of the next trigger is garanteed when there is space for one event or more. A corresponding deadtime is generated for the duration of the capture of the raw data in the frontend buffer. The buffer size is fixed at 1000 samples. Therefore the pipeline advantage starts when the event size is less than 500 samples (this limits is set by the hardware type used on the board).
There is an output signal (busy out signal) available reflecting the non acceptance of trigger by the VF48. This correspond to the "deadtime" from the raw data capture ored with the condition of the frontend buffer having no more room for a complete event.

== Event Description==
An event is broken in many packets which follow a precise order. It always has to begin with a header and end with a trailer. The header and the trailer contain the trigger number and they must be identical. The header is always followed by a timestamp. Then, for each channel enabled, it could contain the raw data, the CFD time evaluated and the charge calculated. The Table 4.2.1 shows the content of an event.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Event’s content
|-
!Packet's Type ||MSB
|-
|Event Header ||0x8
|-
|Time Stamp 1 ||0xA
|-
|Time Stamp 2 ||0xA
|-
|Channel ID ||0xC
|-
|Raw Data (of current channel) ||0x0
|-
|CFD Time (of current channel) ||0x4
|-
|Charge (of current channel) ||0x5
|-
|Channel ID ||0xC
|-
|Raw Data (of current channel) ||0x0
|-
|CFD Time (of current channel) ||0x4
|-
|Charge (of current channel) ||0x5
|-
|… ||
|-
|Channel ID ||0xC
|-
|-
|Raw Data (of current channel) ||0x0
|-
|CFD Time (of current channel) ||0x4
|-
|Charge (of current channel) ||0x5
|-
|Event Trailer ||0xE
|}

The number of raw data is configurable by the parameter Segment Size (Chan Param ID:5). The next section will describe more in detail each of these packets.

== Event Packet Format==
This section describes in detail the contents of each of the packets. Firstly, inside a packet, the 4 MSB indicates the type of packet. The next table makes the association between the MSB and the packets.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Event Packet MSB Association
|-
!Packet's Type ||MSB
|-
|Header ||0x8
|-
|Time Stamp 1 ||0xA
|-
|Time Stamp 2 ||0xA
|-
|Channel ID ||0xC
|-
|Raw Data ||0x0
|-
|CFD Time ||0x4
|-
|Charge ||0x5
|-
|Trailer ||0xE
|-
|Header Error ||0x9
|-
|Error ||0xF
|-
|Header ||0x8xxxxxxx
|}

The packet Header is always the first packet of an event. It contains the trigger number in the bits 23 to 0.

Table 4.3.2 – Header 0x8xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||0||0||0||colspan="4" align="center"|0|| T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T
|}
Trigger Number

Header Error - 0x9xxxxxxx
The Header Error packet occurs when the first packet of a group was not a Header packet. This could be caused by an internal error. If this packet is detected, the current event must be rejected. However, this packet must not happen and if it does, you should contact your supplier.

Table 4.3.3 – Header Error 0x9xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||0||0||1||colspan="4" align="center"|0||colspan="24" align="center"|Trigger Number
|}

Time Stamp - 0xAxxxxxxx
The Time Stamp packet is the second packet and the third packet of en event. It contains a 48 bits time stamps. The time between two steps is of 25 ns . Then, with a 48 bits timestamp, the maximum time measured is 7 036 874,418 seconds. Then, system can count time without completing a buckle during more than 81 days.

Table 4.3.4 – Time Stamp – 0xAxxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||0||1||0||colspan="4" align="center"|0|| colspan="24" align="center"|Time Stamp
|}

The first time stamp packet contains bit 47 to 24 and the second time stamp packet contains bits 23 to 0.
Channel ID - 0xCxxxxxxx
The channel ID packet is the first packet of a sub-event. It contains all the information to be able to identify the channel. Bit 3 to 0 indicates the channel number. This number can go from 0 to 7. It corresponds to the channel of a particular group. Then, bits 6 to 3 identify the group. They can so take a value going from 0 to 5. Bit 7 is not used in this version.

Table 4.3.5 – Channel ID – 0xC0xxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || ||11|| || ||8||7||6|| || ||3|| || ||0
|-
| 1||1||0||0||colspan="4" align="center"|0||0||0||0||0||0||0||0||0||0||0||0||0|| 0||0||0||0||0|| colspan="3" align="center"|Group||colspan="4" align="center"|Channel
|}

Data - 0x0xxxxxxx
The Data packet comes after the channel ID packet. It simply contains two data of 10 bits each. The number of data packet within an event is related to the segment size parameter (Chan Param ID: 5). It could arise problems to have a null value or an odd value of the segment size.

Table 4.3.6 – Data – 0x0xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || ||13|| || || ||9|| || || || || || || || ||0
|-
| 0||0||0||0||colspan="4" align="center"|0|| colspan="10" align="center"|Sampe n+1|| 0||0||0||0|| colspan="10" align="center"|Sample n
|}

Be careful about the position of the second data. It doesn’t start exactly to bit 16. It starts to bit 14. This is done to keep the compatibility with an ADC that would a 14 bits data.
CFD Time - 0x4xxxxxxx
The CFD Time packet is the second packet before the last packet. It contains the CFD Time.

Table 4.3.7 – CFD Time – 0x40xxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 0||1||0||0||colspan="4" align="center"|0|| colspan="24" align="center"| CFD Time
|}

Time algorithm: CDF Equivalent. The input is first clipped with a delay of 3 clocks. If the clipped signal is above the hit threshold then the maximum value of the clipped waveform is evaluated. The CFD time is then evaluated by interpolating the time at 50% charge using the two samples on either side of the 50% fraction.

Charge - 0x5xxxxxxx
The Charge Packet is the first packet before the trailer packet. It contains the charge internally calculated.

Table 4.3.8 – Charge – 0x50xxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 0||1||0||1||colspan="4" align="center"|0|| colspan="24" align="center"|Charge
|}

Trailer - 0xExxxxxxx
The trailer is always the last packet of an event. It contains the trigger number in the bits 23 to 0. The bit 28 indicates an out of sequence flag, then, if this bit is 1, that means that an internal error took place and the packet should be rejected. In theory, system is stable and this type of error should not occur.

Table 4.3.9 – Trailer – 0xExxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||1||1||0||colspan="4" align="center"|0|| colspan="24" align="center"| Trigger Number
|}

Error - 0xFxxxxxxx
The Error packet occurs when a particular packet is not at his right position. This could occur if a timestamp is missing or if a timestamp is not followed by channel. This could be caused by an internal error. If this packet is detected, the entire event must be rejected. However, this packet must not happened and if it does, you should contact your supplier.

Table 4.3.10 – Error 0x9xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||1||1||1|| colspan="28" align="center"|Invalid
|}

== Event Acquisition==
Procedure to read events is very simple. It is a question of reading the number of packet presently available by making a reading on the bus VME at the address NbrFrames. Then, a reading in burst of the number of packet available can be made. The reading of events is done in fifo mode only. This means that the reading is done always at the same address, the Event Data address.

To start the acquisition, you must set the bit 0 of the CSR to 1. To stop the acquisition, you set the bit 0 of the CSR to 0.

The system integrates a signal processing logic which calculates the charge and the precise time where the hit has been detected. In the FE FPGA the continuous flow of digitized signal samples from the ADC is directed to the signal processing logic. The signal processor runs continuously. It performs tasks equivalent to a spectroscopy amplifier connected to an analog multi-channel analyzer.

== Aux Output==
The aux_out front panel output can be set to provide a trigger output, busy output or system clock output, this function is selected by triggerconfig[3..0] and CSR[16] ...

triggerconfig[0] = 1 sets AuxTrigDisable prevents trigger from reaching aux-out (This was for tactic)
triggerconfig[1] = 1 Enables the self-trigger Logic (when 0 the logic is just a a simple OR of the 6 Front End trigger requests)
triggerconfig[2] = 1 selects tigc trigger (rather than the self trigger)
triggerconfig[3] = 1 sets the system clock to aux_out (rather than trigger)
There is also a "select busy out" signal [CSR[16]] which overrides all the above and puts the busy signal to aux_out

The triggerconfig register is 64bits wide, the remaining 60 bits are used to set the self-trigger logic
triggerconfig[39.. 4] = GroupThresholds 6 thresholds of 6 bits each (0-63)
triggerconfig[57..40] = FeGroups 6 groupid's of 3 bits each (0-7)
triggerconfig[63..58] = GroupCoincidence 6 bits, 1 bit enabling each of the 6 groups

There are 6 frontend FPGAs with 8 channels each, each sends its trigger multiplicity (0-8) to the collector. There are 6 possible groups to assign the frontends to (One simple scheme would be to put all 6 in a single group - the multiplicity from this group would then be the total multiplicity on this VF48, in this case, all 6 groupids would be the same, only 1 bit would be enabled in GroupCoincidence, and only 1 multiplicity(GroupThreshold) would need to be set)

= Signal Processing =

The system integrates a signal processing logic which calculates the charge and the precise time where the hit has been detected. In the FE FPGA the continuous flow of digitized signal samples from the ADC is directed to the signal processing logic. The signal processor runs continuously. It performs tasks equivalent to a spectroscopy amplifier connected to an analog multi-channel analyzer.

[[Image:splogic.jpg]]

== Real-Time Digital Filter and Charge Evaluation==

The filtering involves many steps. The first step is the deconvolution of the exponential tail of the pulse shape within an arbitrary time window. The moving window deconvolution method is well documented in the litterature. It is implemented as a finite impulse response filter (FIR). If D0, D1, … Dn, represent the digitized signal samples, and L the span of the moving window, the nth point of the transformed sequence Fn is given by the relation:

(1) [[Image:f1vf48.jpg]]

where τ is the exponential time constant of the signal in units of data samples. The deconvolution is useful in the case of a germanium detector to compensate for the differences in ballistic deficit as a function of the rise time of the signal. Depending on the position of the photon interaction, the charge collection time may vary from event to event by as much as 150 nanoseconds. With a preamplifier decay time constant of 50 microseconds, this translates into a fluctuation of the raw signal peak amplitude corresponding to 3 Kev for a 1 Mev gamma. With an analog system, this fluctuation is reduced significantly by using a long filter peaking time, but it never vanishes. With the moving window deconvolution method, the tail pulse shape is transformed into a quasi-rectangular pulse shape, with a duration determined by the span of the moving window. The transformed signal has a leading edge reflecting the shape of the original signal (with a slight correction for the exponential decay), and then reaches a constant maximum value that is exactly the same for a given total charge deposited in the detector whatever the rise-time. The processed signal also returns to zero with no tail.

It can be seen from equation (1) that the first two terms will cancel the DC baseline. However, the sum term that cancels exactly the exponential decay will unfortunately respond to a baseline level with a gain of L/τ. The sum term also limits the effectiveness of the low frequency filtering effect of the first two terms. To alleviate this problem, one can resort to double sampling, or use a baseline restoring scheme. We have chosen this later approach. The baseline restoring process is active only when no signal is present.

At this stage, the filtering is not yet complete. Only the low frequency part of the noise spectrum has been attenuated. The high frequency filtering is performed by applying another FIR transformation to the corrected deconvoluted signal. The most efficient filter for the evaluation of the trend of a noisy straight line (the flat part of the rectangular pulse shape) is the simple floating average transformation, commonly called a boxcar filter:

(2) [[Image:f2vf48.jpg]]

K is chosen to be as close as possible to the size of the flat portion of the rectangular pulse Fn . For a theoretical signal having a zero rise time and an exponential decay with time constant equal to τ, the sequence of points Gn represents a trapeze with a rise time of K, a flat portion of L-K, and a fall time of K. Every point of the flat top part of the pulse is a proper evaluation of the charge. Selecting the maximum value is simple, but it generates a small average bias proportional to the noise. We rather select the measurement point at a pre-determined time after the beginning of the pulse, based on the timing information produced by the CFD discriminator. This amounts to selecting the point at random (as far as the amplitude is concerned) in the flat top region, thereby reducing the bias.

Due to constraint design (the division by τ would involve excessive FPGA resources), we multiply both sides of equation (1) by τ (parameter M), and we do not normalize by the number of points. The result appearing in the event list is given by

It can be scaled down by software when the histograms are constructed.

== Digital Constant Fraction Discriminator==
Analog constant fraction discriminators (CFD) are widely used to minimize the time walk associated with the detection of signals featuring widely varying amplitudes. The same principle can be applied to digital signal samples, with some differences in the physical implementation. In the VF48 firmware, the implementation reproduces exactly the definition of a CFD: The amplitude of the signal is evaluated, and a threshold is calculated with a predefined fraction. The same signal, delayed through a digital delay line (dual port RAM), is then compared with this calculated threshold until the point immediately below, and the point immediately above the threshold are found. Then, a linear interpolation is performed to evaluate the time corresponding to the threshold crossing. We use time units of 1/16 of the ADC sampling clock period for the interpolation. Often, the rise time is not constant from event to event, as it depends on the position where the electron-holes pairs were created in the crystal. So, it is important to clip the incoming signal to a width equal or shorter than the fastest signal rise time envisioned before the CFD logic. This is achieved by subtracting two samples separated by the proper number of sampling clocks. This has the same effect as the clipping delay line of an analog CFD. The digital CFD produces two outputs: a logic signal synchronized with the ADC clock, when the constant fraction threshold is crossed, and a higher precision time stamp word. The logic signal is used by the trigger logic, whilst the time stamp is part of the event data stream.

== Latency and Event Segment Buffers==

In order to accommodate for the latency of the trigger system, a circular latency buffer is used to keep the past values of the signal samples available for a time equal or longer than the trigger decision latency. The input of the buffer is either the raw data signal, or the output of the deconvolution logic. This can be selected by a run parameter. The maximum capacity of the latency buffer is presently 512 elements. When a trigger is accepted, this delay allows the recovery of the associated signal since its very beginning. We usually also include a few samples that have occurred before the signal. The latency buffer is implemented in a dual port random access memory running continuously. The read address is equal to the write address minus the number of clock cycles we want to have the data delayed. The signal data is continuously written in the memory, and the delayed data continuously available on the readout port. When a trigger is accepted, a transfer gate is generated for a duration corresponding to the size of the data segment requested, and the data read out is transferred to the next buffer stage: the segment event buffer.

The segment buffer is a simple 1024 word FIFO that stores the waveform data segments, plus two extra bits indicating the beginning and end of these segments. The FIFO is read out asynchronously by the list formatter. The function of the Segment Buffer is to store a few events in order to deramdomize the data flow. The segment buffer also generates an almost full flag that is transmitted to the master trigger system. This is the mechanism that throttles the trigger rate when the data acquisition becomes throughput limited. When the throughput is significantly lower than the system bandwidth, the data acquisition is dead-timeless.

== Digital Constant Fraction Discriminator==
Analog constant fraction discriminators (CFD) are widely used to minimize the time walk associated with the detection of signals featuring widely varying amplitudes. The same principle can be applied to digital signal samples, with some differences in the physical implementation. In the VF48 firmware, the implementation reproduces exactly the definition of a CFD: The amplitude of the signal is evaluated, and a threshold is calculated with a predefined fraction. The same signal, delayed through a digital delay line (dual port RAM), is then compared with this calculated threshold until the point immediately below, and the point immediately above the threshold are found. Then, a linear interpolation is performed to evaluate the time corresponding to the threshold crossing. We use time units of 1/16 of the ADC sampling clock period for the interpolation. Often, the rise time is not constant from event to event, as it depends on the position where the electron-holes pairs were created in the crystal. So, it is important to clip the incoming signal to a width equal or shorter than the fastest signal rise time envisioned before the CFD logic. This is achieved by subtracting two samples separated by the proper number of sampling clocks. This has the same effect as the clipping delay line of an analog CFD. The digital CFD produces two outputs: a logic signal synchronized with the ADC clock, when the constant fraction threshold is crossed, and a higher precision time stamp word. The logic signal is used by the trigger logic, whilst the time stamp is part of the event data stream.

== Latency and Event Segment Buffers==

In order to accommodate for the latency of the trigger system, a circular latency buffer is used to keep the past values of the signal samples available for a time equal or longer than the trigger decision latency. The input of the buffer is either the raw data signal, or the output of the deconvolution logic. This can be selected by a run parameter. The maximum capacity of the latency buffer is presently 512 elements. When a trigger is accepted, this delay allows the recovery of the associated signal since its very beginning. We usually also include a few samples that have occurred before the signal. The latency buffer is implemented in a dual port random access memory running continuously. The read address is equal to the write address minus the number of clock cycles we want to have the data delayed. The signal data is continuously written in the memory, and the delayed data continuously available on the readout port. When a trigger is accepted, a transfer gate is generated for a duration corresponding to the size of the data segment requested, and the data read out is transferred to the next buffer stage: the segment event buffer.

The segment buffer is a simple 1024 word FIFO that stores the waveform data segments, plus two extra bits indicating the beginning and end of these segments. The FIFO is read out asynchronously by the list formatter. The function of the Segment Buffer is to store a few events in order to deramdomize the data flow. The segment buffer also generates an almost full flag that is transmitted to the master trigger system. This is the mechanism that throttles the trigger rate when the data acquisition becomes throughput limited. When the throughput is significantly lower than the system bandwidth, the data acquisition is dead-timeless.

= Firmware Update=

To do an update, you will need the ByteBlaster II connector connected on the parallel port of your PC and to the connector J3 on the VF48 board. (Or an USB Blaster module)

Then, you must download the programmer on the Altera Website:
https://www.altera.com/support/software/download/programming/quartus2/dnl-quartus2_programmer.jsp

Then, you start the program. You change the mode from JTAG to Active Serial Programming. You push the Hardware Setup button and you select ByteBlaster II. Then, you push the Add File button and you select the pof file that we supplied you. After, you click in the Program/Configure case and finally you push the Start button.

When the firmware has been programmed, you must unplug the ByteBlaster II connector from the VF48 board, shut down the power and put it back.

If the green light is on, programming was completed successfully. If the green light is off, did you forget to unplug the ByteBlaster II connector? If no, restart all the procedure.

== Label Convention==

A label convention is done to name each version that is created. It starts by the firmware main revision. Then, we add respectively the sub revision, the sampling frequency, the system clock frequency and the special features if they exist.

For example, the name VF48_V207_X6_40_20_Alpha.pof is associated to the firmware version 2.0.7 with a sampling frequency of 40 MHz and a system frequency of 20 MHz. The special feature Alpha signifies that this version is done specifically for Alpha project.

== Firmware history ==

VF48

2010-09-16T21:21:34Z

Cpearson: /* Triggers & Events */

= VF48 - 48 channels@60Msps, 10bits =

== General characteristics ==
The VF48 is a one-unit wide VME 6U housing 48 channels digitized by six fast 10-bit ADCs. For each channel, the input signal (50 Ω impedance) is amplified by a high speed differential amplifier (AD8132) and them converted by the ADCs at a maximum rate of 60 Msps.

The digitized signal goes to a FPGA (Cyclone EPC12) which will calculate the charge of the signal, evaluate the exact trigger time, build an event which will contain all this information and send the event constructed to a local collector. Each FPGA manages eight channels. There are six FPGA connected to the ADCs and one FPGA which collects the data.

The board can be accessed in A24/A32/A40 addressing mode, D16, D32 and MBLT64 data transfer mode.

It has also a board available to access the VF48 throw a LVDS link. This link can transfer the data at a speed up to 100 Mbits/s. This link can afford all the control necessary to run the VF48. It can accept a clock which permits the synchronization of many VF48 units.

The board contains a trigger structure which permits to trigger the data in three different manners. The trigger can come from an external NIM signal, from a software command or from an internal mechanism. The internal mechanism manages multiple channels hit, deadtime, threshold and multiplicity and is totally programmable by the user.

[[Image:blockdigvf48.jpg|Block Diagram of the VF48]]

= VME interface =
The VF48 board can access the VME bus in VME A24. See Table 2.1.1 to have more information about the Address Modifier accepted.

{|style="color:green; background-color:#ffffcc;" cellpadding="10" cellspacing="0" border="1"
|+ Summarizes all the supported address Modifer
|-
!AM||Description
|-
|3F
|A24 supervisory block transfer (BLT)
|-
|3D
|A24 supervisory data access
|-
|3C
|A24 supervisory 64-bit block transfer (MBLT)
|-
|3B
|A24 non privileged block transfer (BLT)
|-
|39
|A24 non privileged data access
|-
|38
|A24 non privileged 64-bit block transfer (MBLT)
|-
|}

=== Base Address ===

The base address of the board is 0xA00000 + n • 0x10000. The number n is defined by the alignment of the switch on the board. For example, if the alignment on the switch is : ID[3..0] = 1011, then the base address will be 0xAB0000.

Every board will manage a window going until 0x00FFFF above the base address. In the previous example, the VME window was from 0xAB0000 to 0xABFFFF.

=== Data Transfer Capabilities ===
The board can access the VME BUS in VME_D16, VME_D32, VME 32-bit and 64-bit block transfers (BLT32 and MBLT64). The VME_D8 is not compatible. D32 is recommended for accessing collector registers and 64-bit block transfer (MBLT64) is recommended for reading data from the VME data FIFO. See VME Mapping to have more details on this.

==VME Mapping==

The Table 2.2.1 describes the VME Mapping of the VF48 collector registers. In the Table 2.2.1, the W column indicates if the register is available for a Write. The R column indicates if the register is available for a Read. The last three columns indicate permitted access modes.

– VME Mapping
{| style="color:green; background-color:#ffffcc;" cellpadding="10" cellspacing="0" border="1"
|-!Offset ||VME Mapping ||Access ||Mode
|-
|0x0000||CSR||R/W||D16/32
|-
|0x0010|| || ||
|-
|0x0020|| || ||
|-
|0x0030||Firmware ID ||R || D16/32
|-
|0x0040|| || ||
|-
|0x0050||Param DAT ||W ||D16/32
|-
|0x0060||Param ID ||W ||D16/32
|-
|0x0070||Soft Trigger ||W ||D16/32
|-
|0x0080|| || ||
|-
|0x0090||Group Enable ||R/W ||D16/32
|-
|0x00A0||NbrFrames ||R ||D16/32
|-
|0x00B0||Global Reset || W ||
|-
|0x01XX||Event Data ||R ||D32/BLT32/MBLT64
|-
|}

===CSR Description ===
Only six bits of the CSR (Control & Status Registry) are used. They are indicated in the Table 2.2.2.

{| style="color:green; background-color:#ffffcc;" cellpadding="10" cellspacing="0" border="1"
|+CSR Description
|-
!Bit ||CSR Description ||Access
|-
|0|| Run ||R/W
|-
|1|| Parameter ID Ready|| R
|-
|2|| Parameter DATA Ready||R
|-
|3|| Event Fifo Empty||R
|-
|4|| ||
|-
|5||CRC Error detected || R
|-
|6|| ||
|-
|7||External Trigger || R/W
|-
|}

The RUN bit allows the system to accept triggers and start the acquisition.

The Parameter ID Ready bit and Parameter DAT Ready bit indicate if parameter is ready to be read. The parameter section will describe more precisely how these bits work.

The Event Fifo Empty bit indicates if the event fifo is empty. When this signal is low, there’s data ready to be read.

The CRC Error Detected bit indicates if a CRC Error has been detected in the serial communication on the board. This bit should never go on.

The External trigger bit selects the external trigger. If this bit is set to 1, the trigger that will start the acquisition must come from the connector on the front panel. If this bit is zero, then a real signal must be detected on one of the 48 channels if you want to have event built.

=== Firmware ID (0x000030) ===
It returns the firmware ID

===Parameter DAT (0x000050)===
Register used to write the parameter. See the section Writing/Reading Parameter for more details.

=== Parameter ID (0x000060)===
Register used to write the parameter. See the section Writing/Reading Parameter for more details.

===Soft Trigger (0x000070)===
It generates a trigger on the front end to force the system to acquire data.

===Group Enable (0x000090)===
It allows enabling a group of channels. Bit 0 enables channel 1 to 8, bit 1 enables channel 9 to 16 until bit 5 which enable channels 41 to 48. By default, they are all enabled.
2.2.7. Nbr Frames (0x0000A0)
It gives the number of data present in the event fifo. See section 4. Triggers & Events for more details.

===Global Reset (0x0000B0)===
It resets all the system.

===Event Data (0x000100-0x00FFFF)===
It reads all the data in the fifo. See section 4. Triggers & Events for more details.

= Writing/Reading Parameter =
To write a parameter, you must write the parameter ID (See Table 3.1.1) followed by the parameter Data. You write the parameter ID by doing a VME Write at the address Param ID and you write the parameter Data by doing a VME Write at the address Param DAT.

During a parameter read, it is necessary to be aware that parameter is not immediately in the register ParamDAT. The bit 2 of the CSR rises up when the parameter is ready and falls down when you read it. So, the procedure to read a parameter is this. First, you send the request by writing the parameter ID (VME Write at the address ParamID) with bit 7 set to 1. You must also send a fake data, because if you don’t send a fake data, the request will never be sent. After, you read bit 2 of the CSR until it has been set. When the bit is set, you do a VME Read at the address ParamDAT .

===Parameter Frame Header===
The first 16 bits of a frame contain information describing the contents of the parameter.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Parameter Frame Header
|-
!15|| || || ||11|| || || ||7||6|| || || || || || 0
|-
|C ||C||C||C|| D||D||D||D||R||V||P||P||P||P||P||P
|}

* C : Destination Card or Port or Cyclone
* D : Destination Channel (0-5)
* R : ReadBit
* V : Version (0- No extension; 1- Param ID 32 bit)
* P : Parameter ID

Description of the fields Parameter Frame Header:
Destination Card
Bits 11 - 8 contain the number of the card where parameter must be sent. The following table describes the direction which has to take parameter according to the number of destination of card, the number of port or the number of cyclone on the board.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Destination Cyclone
|-
!11 ||10|| 9|| 8|| Destination Cyclone ||Port
|-
|0 ||0|| 0|| 0|| Channel 1 to 8 ||0
|-
|0 ||0|| 0|| 1|| Channel 9 to 16 ||1
|-
|0 ||0|| 1|| 0|| Channel 17 to 24|| 2
|-
|0 ||0|| 1|| 1|| Channel 25 to 32|| 3
|-
|0 ||1|| 0|| 0|| Channel 33 to 40|| 4
|-
|0 ||1|| 0|| 1|| Channel 41 to 48|| 5
|-
|0 ||1|| 1|| 0|| Not used ||Not used
|-
|1 ||1|| 1|| 1|| Not used ||Not used
|}
* Destination Channel
This field is not used for the current version. We don’t care of these bits.

* ReadBit
Bit 7 indicates if command is a demand of writing or reading of the parameter. If ReadBit is HIGH, then it is a read and parameter should be sent back to the collector. If ReadBit is LOW, then it is a write and parameter should be recorded.

During a parameter read, it is necessary to be aware that parameter is not immediately in the register ParamDAT. The bit 2 of the CSR rises up when the parameter is ready and falls down when you read it.
Version Bit

This bit must be zero in this version
Parameter ID
The last six bits contains the parameter ID. Each parameter available is displayed in the Table 3.1.3

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Parameter List
|-
!ID# ||Parameter List|| Default Value|| Access
|-
|0 || || ||
|-
|1|| PED ||0x0000 ||R/W
|-
|2|| Hit Det Threshold|| 0x000A ||R/W
|-
|3|| Clip Delay ||0x0028 ||R/W
|-
|4|| PreTrigger ||0x0020 ||R/W
|-
|5|| Segment Size ||0x0100 ||R/W
|-
|6|| K ||0x0190 ||R/W
|-
|7|| L ||0x0200 ||R/W
|-
|8|| M ||0x1000 ||R/W
|-
|9|| Channel Enable ||0x00FF ||R/W
|-
|10|| Mbits 1 - Feature Enable|| 0x0000 ||R/W
|-
|11|| Mbits 2 - Feature Enable|| 0x0000 ||R/W
|-
|12|| Latency ||0x0005 ||R/W
|-
|13|| Firmware ID ||0x0207 ||R/W
|-
|14|| Attenuator ||0x0190 ||R/W
|-
|15|| Trigger Threshold|| 0x000A ||R/W
|}

=== Parameter Description ===
This section is there to describe each parameter.
1 - PED
This parameter is not used yet.
2 – Hit Detection Threshold
This parameter defines the threshold to detect a hit. If the signal given by the ADC is above this threshold value, the system will start to calculate the charge, but if the signal doesn’t reach the trigger threshold, the charge won’t be used.
3 – Clip Delay
This parameter is not used yet.
4 – Pre-Trigger
This parameter defines the number of clock where the data must be recorded before the trigger.
5 – Segment Size
This parameter defines the number of raw data that must be recorded.
6 - K
This parameter defines the peaking time. See the signal processing section for more details.
7 - L
This parameter represents the duration of the peaking time and the flat top together. See the signal processing section for more details.
8 - M
This parameter defines a multiplication factor of the convoluted signal. See the signal processing section for more details.
9 – Channel Enable
This parameter indicates the channels that must be included in the event. Bit 0 enables channel 0, bit 1 enables channel 1, so in succession until channel 7. By default, all channels are enabled.

Note: In version previous to version 2.0.7, the parameter 11 was FeatureDelay_B. This parameter doesn’t exist anymore.
10 – M_Bits
This parameter is a parameter where each bit has a different purpose. The Table 3.2.1 gives information about these bits.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Description of the MBits parameter
|-
!Bit|| Version 2.0 and more|| Version before 2.0
|-
|0|| Data Simulation|| Data Simulation
|-
|1|| Suppress Raw Data|| Supress Raw Data
|-
|2|| Select Corrected Data|| Select Corrected Data
|-
|3|| PolPlus|| PolPlus
|-
|4|| BLR Speed (bit 0)|| Disable ADC
|-
|5|| BLR Speed (bit 1)|| Fake One Data
|-
|6|| Hold BLR ||-
|-
|7|| - ||-
|-
|8|| Disable ADC ||-
|-
|9|| Offset 1 ||-
|-
|10|| Offset 2 ||-
|-
|11|| Low Gain Selection ||-
|-
|12|| Card Revision Number (bit 0) ||-
|-
|13|| Card Revision Number (bit 1) ||-
|-
|14|| Card Revision Number (bit 2) ||-
|-
|15|| Card Revision Number (bit 3) ||-
|}

The bit 0, Data Simulation, enables the simulator. If this bit is set, the simulated data will be continually sent.

The bit 1, Suppress Raw Data, suppresses the raw data independently of the segment size parameter.

The bit 2, Select Corrected Data, is not used in the current version.

The bit 3, PolPlus, is used to invert numerically the input. If the input is 0b0100010001, and the bit PolPlus set then the input will be 0b1011101110.

The bit 8, Disable ADC, disable the ADC.

The bit 5, Fake One Data, has the same use as the bit 0, Data Simulation, but it will be activated for only one valid signal.

All the other bits are reserved for future use. The names indicated represent the function that is reserved for the bit to be compatible with other project.
11 – M_Bits 2
This parameter is a parameter where each bit has a different purpose. The Table 3.2.2 gives information about these bits.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Description of the MBits 2 parameter
|-
!Bit|| Version 2.0 and more|| Version before 2.0
|-
|0|| Enable Channel Suppression ||-
|-
|1|| Doesn't send time evaluation ||-
|-
|2|| Doesn't send charge calculated ||-
|-
|3|| -||-
|-
|4|| -||-
|-
|5|| -||-
|-
|6|| -||-
|-
|7|| -||-
|-
|15..8||Sampling Rate Divider||-
|}

* bit 0, Enable Channel Suppression, disable an entire channel within a group if none of the sample values of that channel is above the hit threshold.

* bit 1, Doesn’t send charge calculated, disables the calculation of the charge. If this bit is set, the charge won’t be calculated.

* bit 2, Doesn’t send time evaluation, disables the evaluation of the time when the signals passes above the threshold. If this bis set, the time won’t be evaluated.

Note: In version previous to version 2.0.7, the parameter 11 was FeatureDelay_B. This parameter doesn’t exist anymore.
12 – Latency
This parameter defines the number of clock to be added to the pre-trigger. This parameter should represent the time between the hit detection and the trigger accepted received by the front end.
13 – Firmware ID
This parameter is firmware ID. For example, if the version is 1.0.0, it will return 0x0100. If the version is 11.12.13, it will return 0x0BCD.
14 – Attenuator
This parameter defines the attenuation of the integration. See the signal processing section for more details.
15 – Trigger Threshold
This parameter defines the threshold to accept a trigger. If the signal given by the ADC is above the threshold value, a trigger request will be sent to the collector.

= Triggers & Events=

When a trigger is accepted, the front end starts to build an event which will be transferred to the collector. Each event has the same format. This section defines this format, but before, let us defines some terms usually used in this section.

A Packet is a word of 32 bits which contains information related with an event.

An Event is a series of packet beginning with a header and ending by a trailer.

== Trigger Detection==
Each channel goes through a comparator in order to trigger the feature evaluation. The hit threshold is a positive difference of 2 ADC values separated by 2 samples (ex: 2,3,4,5,6,7  hit Thr= 6-3).
In the case the input signal has the opposite polarity, you can either reverse the input signal (the VF48 input is bipolar) or reverse the polarity by software. The polarity switch is applied to the digitized ADC values. Currrently no dedicated reverse polarity function is available. Use the example found under midas/examples/Triumf/c/fevmemodules.c/BOR function.
The acceptance of the next trigger is garanteed when there is space for one event or more. A corresponding deadtime is generated for the duration of the capture of the raw data in the frontend buffer. The buffer size is fixed at 1000 samples. Therefore the pipeline advantage starts when the event size is less than 500 samples (this limits is set by the hardware type used on the board).
There is an output signal (busy out signal) available reflecting the non acceptance of trigger by the VF48. This correspond to the "deadtime" from the raw data capture ored with the condition of the frontend buffer having no more room for a complete event.

== Event Description==
An event is broken in many packets which follow a precise order. It always has to begin with a header and end with a trailer. The header and the trailer contain the trigger number and they must be identical. The header is always followed by a timestamp. Then, for each channel enabled, it could contain the raw data, the CFD time evaluated and the charge calculated. The Table 4.2.1 shows the content of an event.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Event’s content
|-
!Packet's Type ||MSB
|-
|Event Header ||0x8
|-
|Time Stamp 1 ||0xA
|-
|Time Stamp 2 ||0xA
|-
|Channel ID ||0xC
|-
|Raw Data (of current channel) ||0x0
|-
|CFD Time (of current channel) ||0x4
|-
|Charge (of current channel) ||0x5
|-
|Channel ID ||0xC
|-
|Raw Data (of current channel) ||0x0
|-
|CFD Time (of current channel) ||0x4
|-
|Charge (of current channel) ||0x5
|-
|… ||
|-
|Channel ID ||0xC
|-
|-
|Raw Data (of current channel) ||0x0
|-
|CFD Time (of current channel) ||0x4
|-
|Charge (of current channel) ||0x5
|-
|Event Trailer ||0xE
|}

The number of raw data is configurable by the parameter Segment Size (Chan Param ID:5). The next section will describe more in detail each of these packets.

== Event Packet Format==
This section describes in detail the contents of each of the packets. Firstly, inside a packet, the 4 MSB indicates the type of packet. The next table makes the association between the MSB and the packets.

{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
|+Event Packet MSB Association
|-
!Packet's Type ||MSB
|-
|Header ||0x8
|-
|Time Stamp 1 ||0xA
|-
|Time Stamp 2 ||0xA
|-
|Channel ID ||0xC
|-
|Raw Data ||0x0
|-
|CFD Time ||0x4
|-
|Charge ||0x5
|-
|Trailer ||0xE
|-
|Header Error ||0x9
|-
|Error ||0xF
|-
|Header ||0x8xxxxxxx
|}

The packet Header is always the first packet of an event. It contains the trigger number in the bits 23 to 0.

Table 4.3.2 – Header 0x8xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||0||0||0||colspan="4" align="center"|0|| T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T||T
|}
Trigger Number

Header Error - 0x9xxxxxxx
The Header Error packet occurs when the first packet of a group was not a Header packet. This could be caused by an internal error. If this packet is detected, the current event must be rejected. However, this packet must not happen and if it does, you should contact your supplier.

Table 4.3.3 – Header Error 0x9xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||0||0||1||colspan="4" align="center"|0||colspan="24" align="center"|Trigger Number
|}

Time Stamp - 0xAxxxxxxx
The Time Stamp packet is the second packet and the third packet of en event. It contains a 48 bits time stamps. The time between two steps is of 25 ns . Then, with a 48 bits timestamp, the maximum time measured is 7 036 874,418 seconds. Then, system can count time without completing a buckle during more than 81 days.

Table 4.3.4 – Time Stamp – 0xAxxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||0||1||0||colspan="4" align="center"|0|| colspan="24" align="center"|Time Stamp
|}

The first time stamp packet contains bit 47 to 24 and the second time stamp packet contains bits 23 to 0.
Channel ID - 0xCxxxxxxx
The channel ID packet is the first packet of a sub-event. It contains all the information to be able to identify the channel. Bit 3 to 0 indicates the channel number. This number can go from 0 to 7. It corresponds to the channel of a particular group. Then, bits 6 to 3 identify the group. They can so take a value going from 0 to 5. Bit 7 is not used in this version.

Table 4.3.5 – Channel ID – 0xC0xxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || ||11|| || ||8||7||6|| || ||3|| || ||0
|-
| 1||1||0||0||colspan="4" align="center"|0||0||0||0||0||0||0||0||0||0||0||0||0|| 0||0||0||0||0|| colspan="3" align="center"|Group||colspan="4" align="center"|Channel
|}

Data - 0x0xxxxxxx
The Data packet comes after the channel ID packet. It simply contains two data of 10 bits each. The number of data packet within an event is related to the segment size parameter (Chan Param ID: 5). It could arise problems to have a null value or an odd value of the segment size.

Table 4.3.6 – Data – 0x0xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || ||13|| || || ||9|| || || || || || || || ||0
|-
| 0||0||0||0||colspan="4" align="center"|0|| colspan="10" align="center"|Sampe n+1|| 0||0||0||0|| colspan="10" align="center"|Sample n
|}

Be careful about the position of the second data. It doesn’t start exactly to bit 16. It starts to bit 14. This is done to keep the compatibility with an ADC that would a 14 bits data.
CFD Time - 0x4xxxxxxx
The CFD Time packet is the second packet before the last packet. It contains the CFD Time.

Table 4.3.7 – CFD Time – 0x40xxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 0||1||0||0||colspan="4" align="center"|0|| colspan="24" align="center"| CFD Time
|}

Time algorithm: CDF Equivalent. The input is first clipped with a delay of 3 clocks. If the clipped signal is above the hit threshold then the maximum value of the clipped waveform is evaluated. The CFD time is then evaluated by interpolating the time at 50% charge using the two samples on either side of the 50% fraction.

Charge - 0x5xxxxxxx
The Charge Packet is the first packet before the trailer packet. It contains the charge internally calculated.

Table 4.3.8 – Charge – 0x50xxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 0||1||0||1||colspan="4" align="center"|0|| colspan="24" align="center"|Charge
|}

Trailer - 0xExxxxxxx
The trailer is always the last packet of an event. It contains the trigger number in the bits 23 to 0. The bit 28 indicates an out of sequence flag, then, if this bit is 1, that means that an internal error took place and the packet should be rejected. In theory, system is stable and this type of error should not occur.

Table 4.3.9 – Trailer – 0xExxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||1||1||0||colspan="4" align="center"|0|| colspan="24" align="center"| Trigger Number
|}

Error - 0xFxxxxxxx
The Error packet occurs when a particular packet is not at his right position. This could occur if a timestamp is missing or if a timestamp is not followed by channel. This could be caused by an internal error. If this packet is detected, the entire event must be rejected. However, this packet must not happened and if it does, you should contact your supplier.

Table 4.3.10 – Error 0x9xxxxxxx
{| style="color:black; background-color:#00ffcc;" cellpadding="10" cellspacing="0" border="1"
!31|| || || || || || || ||23|| || || || || || || || || || || || || || || || || || || || || || ||0
|-
| 1||1||1||1|| colspan="28" align="center"|Invalid
|}

== Event Acquisition==
Procedure to read events is very simple. It is a question of reading the number of packet presently available by making a reading on the bus VME at the address NbrFrames. Then, a reading in burst of the number of packet available can be made. The reading of events is done in fifo mode only. This means that the reading is done always at the same address, the Event Data address.

To start the acquisition, you must set the bit 0 of the CSR to 1. To stop the acquisition, you set the bit 0 of the CSR to 0.

The system integrates a signal processing logic which calculates the charge and the precise time where the hit has been detected. In the FE FPGA the continuous flow of digitized signal samples from the ADC is directed to the signal processing logic. The signal processor runs continuously. It performs tasks equivalent to a spectroscopy amplifier connected to an analog multi-channel analyzer.

== Aux Output==
The aux_out front panel output can be set to provide a trigger output, busy output or system clock output, this function is selected by triggerconfig[3..0] and CSR[16] ...

triggerconfig[0] = 1 sets AuxTrigDisable prevents trigger from reaching aux-out (This was for tactic)
triggerconfig[1] = 1 Enables the self-trigger Logic (when 0 the logic is just a a simple OR of the 6 Front End trigger requests)
triggerconfig[2] = 1 selects tigc trigger (rather than the self trigger)
triggerconfig[3] = 1 sets the system clock to aux_out (rather than trigger)
There is also a "select busy out" signal [CSR[16]] which overrides all the above and puts the busy signal to aux_out

The triggerconfig register is 64bits wide, the remaining 60 bits are used to set the self-trigger logic
triggerconfig[39.. 4] = GroupThresholds 6 thresholds of 6 bits each (0-63)
triggerconfig[57..40] = FeGroups 6 groupid's of 3 bits each (0-7)
triggerconfig[63..58] = GroupCoincidence 6 bits, 1 bit enabling each of the 6 groups

There are 6 frontend FPGAs with 8 channels each, each sends its trigger multiplicity (0-8) to the collector. There are 6 possible groups to assign the frontends to (One simple scheme would be to put all 6 in a single group - the multiplicity from this group would then be the total multiplicity on this VF48, in this case, all 6 groupids would be the same, only 1 bit would be enabled in GroupCoincidence, and only 1 multiplicity(GroupThreshold) would need to be set)

= Signal Processing =

The system integrates a signal processing logic which calculates the charge and the precise time where the hit has been detected. In the FE FPGA the continuous flow of digitized signal samples from the ADC is directed to the signal processing logic. The signal processor runs continuously. It performs tasks equivalent to a spectroscopy amplifier connected to an analog multi-channel analyzer.

[[Image:splogic.jpg]]

== Real-Time Digital Filter and Charge Evaluation==

The filtering involves many steps. The first step is the deconvolution of the exponential tail of the pulse shape within an arbitrary time window. The moving window deconvolution method is well documented in the litterature. It is implemented as a finite impulse response filter (FIR). If D0, D1, … Dn, represent the digitized signal samples, and L the span of the moving window, the nth point of the transformed sequence Fn is given by the relation:

(1) [[Image:f1vf48.jpg]]

where τ is the exponential time constant of the signal in units of data samples. The deconvolution is useful in the case of a germanium detector to compensate for the differences in ballistic deficit as a function of the rise time of the signal. Depending on the position of the photon interaction, the charge collection time may vary from event to event by as much as 150 nanoseconds. With a preamplifier decay time constant of 50 microseconds, this translates into a fluctuation of the raw signal peak amplitude corresponding to 3 Kev for a 1 Mev gamma. With an analog system, this fluctuation is reduced significantly by using a long filter peaking time, but it never vanishes. With the moving window deconvolution method, the tail pulse shape is transformed into a quasi-rectangular pulse shape, with a duration determined by the span of the moving window. The transformed signal has a leading edge reflecting the shape of the original signal (with a slight correction for the exponential decay), and then reaches a constant maximum value that is exactly the same for a given total charge deposited in the detector whatever the rise-time. The processed signal also returns to zero with no tail.

It can be seen from equation (1) that the first two terms will cancel the DC baseline. However, the sum term that cancels exactly the exponential decay will unfortunately respond to a baseline level with a gain of L/τ. The sum term also limits the effectiveness of the low frequency filtering effect of the first two terms. To alleviate this problem, one can resort to double sampling, or use a baseline restoring scheme. We have chosen this later approach. The baseline restoring process is active only when no signal is present.

At this stage, the filtering is not yet complete. Only the low frequency part of the noise spectrum has been attenuated. The high frequency filtering is performed by applying another FIR transformation to the corrected deconvoluted signal. The most efficient filter for the evaluation of the trend of a noisy straight line (the flat part of the rectangular pulse shape) is the simple floating average transformation, commonly called a boxcar filter:

(2) [[Image:f2vf48.jpg]]

K is chosen to be as close as possible to the size of the flat portion of the rectangular pulse Fn . For a theoretical signal having a zero rise time and an exponential decay with time constant equal to τ, the sequence of points Gn represents a trapeze with a rise time of K, a flat portion of L-K, and a fall time of K. Every point of the flat top part of the pulse is a proper evaluation of the charge. Selecting the maximum value is simple, but it generates a small average bias proportional to the noise. We rather select the measurement point at a pre-determined time after the beginning of the pulse, based on the timing information produced by the CFD discriminator. This amounts to selecting the point at random (as far as the amplitude is concerned) in the flat top region, thereby reducing the bias.

Due to constraint design (the division by τ would involve excessive FPGA resources), we multiply both sides of equation (1) by τ (parameter M), and we do not normalize by the number of points. The result appearing in the event list is given by

It can be scaled down by software when the histograms are constructed.

== Digital Constant Fraction Discriminator==
Analog constant fraction discriminators (CFD) are widely used to minimize the time walk associated with the detection of signals featuring widely varying amplitudes. The same principle can be applied to digital signal samples, with some differences in the physical implementation. In the VF48 firmware, the implementation reproduces exactly the definition of a CFD: The amplitude of the signal is evaluated, and a threshold is calculated with a predefined fraction. The same signal, delayed through a digital delay line (dual port RAM), is then compared with this calculated threshold until the point immediately below, and the point immediately above the threshold are found. Then, a linear interpolation is performed to evaluate the time corresponding to the threshold crossing. We use time units of 1/16 of the ADC sampling clock period for the interpolation. Often, the rise time is not constant from event to event, as it depends on the position where the electron-holes pairs were created in the crystal. So, it is important to clip the incoming signal to a width equal or shorter than the fastest signal rise time envisioned before the CFD logic. This is achieved by subtracting two samples separated by the proper number of sampling clocks. This has the same effect as the clipping delay line of an analog CFD. The digital CFD produces two outputs: a logic signal synchronized with the ADC clock, when the constant fraction threshold is crossed, and a higher precision time stamp word. The logic signal is used by the trigger logic, whilst the time stamp is part of the event data stream.

== Latency and Event Segment Buffers==

In order to accommodate for the latency of the trigger system, a circular latency buffer is used to keep the past values of the signal samples available for a time equal or longer than the trigger decision latency. The input of the buffer is either the raw data signal, or the output of the deconvolution logic. This can be selected by a run parameter. The maximum capacity of the latency buffer is presently 512 elements. When a trigger is accepted, this delay allows the recovery of the associated signal since its very beginning. We usually also include a few samples that have occurred before the signal. The latency buffer is implemented in a dual port random access memory running continuously. The read address is equal to the write address minus the number of clock cycles we want to have the data delayed. The signal data is continuously written in the memory, and the delayed data continuously available on the readout port. When a trigger is accepted, a transfer gate is generated for a duration corresponding to the size of the data segment requested, and the data read out is transferred to the next buffer stage: the segment event buffer.

The segment buffer is a simple 1024 word FIFO that stores the waveform data segments, plus two extra bits indicating the beginning and end of these segments. The FIFO is read out asynchronously by the list formatter. The function of the Segment Buffer is to store a few events in order to deramdomize the data flow. The segment buffer also generates an almost full flag that is transmitted to the master trigger system. This is the mechanism that throttles the trigger rate when the data acquisition becomes throughput limited. When the throughput is significantly lower than the system bandwidth, the data acquisition is dead-timeless.

== Digital Constant Fraction Discriminator==
Analog constant fraction discriminators (CFD) are widely used to minimize the time walk associated with the detection of signals featuring widely varying amplitudes. The same principle can be applied to digital signal samples, with some differences in the physical implementation. In the VF48 firmware, the implementation reproduces exactly the definition of a CFD: The amplitude of the signal is evaluated, and a threshold is calculated with a predefined fraction. The same signal, delayed through a digital delay line (dual port RAM), is then compared with this calculated threshold until the point immediately below, and the point immediately above the threshold are found. Then, a linear interpolation is performed to evaluate the time corresponding to the threshold crossing. We use time units of 1/16 of the ADC sampling clock period for the interpolation. Often, the rise time is not constant from event to event, as it depends on the position where the electron-holes pairs were created in the crystal. So, it is important to clip the incoming signal to a width equal or shorter than the fastest signal rise time envisioned before the CFD logic. This is achieved by subtracting two samples separated by the proper number of sampling clocks. This has the same effect as the clipping delay line of an analog CFD. The digital CFD produces two outputs: a logic signal synchronized with the ADC clock, when the constant fraction threshold is crossed, and a higher precision time stamp word. The logic signal is used by the trigger logic, whilst the time stamp is part of the event data stream.

== Latency and Event Segment Buffers==

In order to accommodate for the latency of the trigger system, a circular latency buffer is used to keep the past values of the signal samples available for a time equal or longer than the trigger decision latency. The input of the buffer is either the raw data signal, or the output of the deconvolution logic. This can be selected by a run parameter. The maximum capacity of the latency buffer is presently 512 elements. When a trigger is accepted, this delay allows the recovery of the associated signal since its very beginning. We usually also include a few samples that have occurred before the signal. The latency buffer is implemented in a dual port random access memory running continuously. The read address is equal to the write address minus the number of clock cycles we want to have the data delayed. The signal data is continuously written in the memory, and the delayed data continuously available on the readout port. When a trigger is accepted, a transfer gate is generated for a duration corresponding to the size of the data segment requested, and the data read out is transferred to the next buffer stage: the segment event buffer.

The segment buffer is a simple 1024 word FIFO that stores the waveform data segments, plus two extra bits indicating the beginning and end of these segments. The FIFO is read out asynchronously by the list formatter. The function of the Segment Buffer is to store a few events in order to deramdomize the data flow. The segment buffer also generates an almost full flag that is transmitted to the master trigger system. This is the mechanism that throttles the trigger rate when the data acquisition becomes throughput limited. When the throughput is significantly lower than the system bandwidth, the data acquisition is dead-timeless.

= Firmware Update=

To do an update, you will need the ByteBlaster II connector connected on the parallel port of your PC and to the connector J3 on the VF48 board. (Or an USB Blaster module)

Then, you must download the programmer on the Altera Website:
https://www.altera.com/support/software/download/programming/quartus2/dnl-quartus2_programmer.jsp

Then, you start the program. You change the mode from JTAG to Active Serial Programming. You push the Hardware Setup button and you select ByteBlaster II. Then, you push the Add File button and you select the pof file that we supplied you. After, you click in the Program/Configure case and finally you push the Start button.

When the firmware has been programmed, you must unplug the ByteBlaster II connector from the VF48 board, shut down the power and put it back.

If the green light is on, programming was completed successfully. If the green light is off, did you forget to unplug the ByteBlaster II connector? If no, restart all the procedure.

== Label Convention==

A label convention is done to name each version that is created. It starts by the firmware main revision. Then, we add respectively the sub revision, the sampling frequency, the system clock frequency and the special features if they exist.

For example, the name VF48_V207_X6_40_20_Alpha.pof is associated to the firmware version 2.0.7 with a sampling frequency of 40 MHz and a system frequency of 20 MHz. The special feature Alpha signifies that this version is done specifically for Alpha project.

== Firmware history ==