DaqWiki - User contributions [en]

File:DAQ-network-01.jpg

2024-07-25T21:43:29Z

Midas: Midas uploaded a new version of File:DAQ-network-01.jpg

IntroDAQ

2021-10-31T04:16:41Z

Midas: /* Experiment */

== Welcome to the Triumf DAQ Wiki site ==

The TRIUMF DAQ group provides support for the data acquisition systems used by experimenters to collect data.

Members of the TRIUMF DAQ group:

* Pierre-André Amaudruz (group leader) - http://www.triumf.ca/profiles/20
* Konstantin Olchanski - http://www.triumf.ca/profiles/3103
* Christopher J Pearson - http://www.triumf.ca/profiles/3648
* Thomas Lindner - http://www.triumf.ca/profiles/4937
* Benjamin Smith - http://www.triumf.ca/profiles/5446

== Experiment ==
{| cellpadding="5" cellspacing="0" border="1"
! Group || DAQ Primary Contact || DAQ Secondary contact || Experiment liaison || Experiment liaison Leader || Host machines || Notes
|-
| BNMR/BNQR || Ben Smith || Konstantin Olchanski || G Morris || A. Mac Farlane || isdaq01, isdaq06, lxbnmr, lxbnqr || local
|-
| MUSR || Ben Smith || Konstantin Olchanski || Donald Arseneau || Syd Kreitzman || musr00, midm15, midm9a, midm9b, midm20c, midm20d, midm20, linm15, linm9a, linm20, lxm9a, lxm9b, lxm20c, lxm20d, lxm15 || local
|-
| POL || Ben Smith || ... || Matt Pearson || Phil Levy || isdaq06, lxpol || local
|-
| Dragon || Konstantin Olchanski || ... || Chris Ruiz ||Chris Ruiz || isdaq04 || local
|-
| GPS || Chris Pearson ||Konstantin Olchanski || Gordon Ball || G.Ball || midtis06 || local
|-
| Titan (MPET) || Ben Smith || ... || ... || Jens Dilling || titan01, lxmpet || local
|-
| Titan (EBIT) || Ben Smith || Chris Pearson || ... || Jens Dilling || titan03, lxebit || local
|-
| Titan (CPET) || Ben Smith || ... || ... || Jens Dilling || titan01, lxcpet || local
|-
| Trinat || Konstrantin Olchanski || ... || ... || John Behr || midtis01, isdaq01 || local
|-
| EMMA || Konstantin Olchanski|| Thomas Lindner || ... || Barry Davids || ... || local
|-
| Tigress || Chris Pearson || Konstantin Olchanski || ... || Greg Hackman || Midtig01/02/03 || local
|-
| IRIS || Pierre-A. Amaudruz || Konstantin Olchanski || ... || Rituparna Kanungo || iris00..02, lxiris01..02 || local
|-
| UCN || Thomas Lindner || ... || ... || ... || ... || local
|-
| PTF || Thomas Lindner || ... || ... || ... || midptf01 || local
|-
| Griffin || Chris Pearson || Konstantin Olchanski || ... || Adam Garthworthy || ... || local
|-
| Alpha-II || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Makoto Fujiwara || ... || CERN
|-
| Alpha-g || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Makoto Fujiwara || ... || CERN
|-
| Hyper-K || Thomas Lindner || ... || ... || Fabrice Retiere || ... || J-Parc
|-
| SuperCDMS || Thomas Lindner || Ben Smith || ... || Scott Oser || ... || Snolab
|-
| DarkSide-20K || Pierre-A. Amaudruz || Ben Smith || ... || ... || dsvslice, dsfe01..04, dsts01..05 || LNGS
|-
| T2K - FGD (completed) || Pierre-A. Amaudruz || Konstantin Olchanski || ... || Scott Oser || ladd10 || J-Parc
|-
| DEAP (completed) || Pierre-A. Amaudruz || Konstantin Olchanski || Fabrice Retiere || ... || ... || Snolab
|-
| CCS (completed) || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Rolf Keitle || arm || local
|-
| Liquid Xe (retired)|| Pierre-A. Amaudruz || Konstantin Olchanski || ... || doug Bryman || xenon01, xenon02 || local
|-
| Atlas ThinChamber (retired) || Pierre-A. Amaudruz || ... || ... || ... || lxcamac01 || local
|-
| G-2 (retired) || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Glen Marshall || ... || local
|-
| SMD (retired) || Pierre-A. Amaudruz || ... || ... || Ewart Blackmore || ... || local
|-
| Tuda (retired) || Pierre-A. Amaudruz || Chris Pearson || ... || T.Davidson || tuda01..03 || local
|-
| Beast/Belle2 (retired) || Pierre-A. Amaudruz || ... || ... || ... || ... || KEK
|-
| Pingu (retired) || Pierre-A. Amaudruz || ... || ... || Fabrice Retiere || ... || South Pole
|
|}

IntroDAQ

2021-10-31T04:14:15Z

Midas: /* Experiment */

== Welcome to the Triumf DAQ Wiki site ==

The TRIUMF DAQ group provides support for the data acquisition systems used by experimenters to collect data.

Members of the TRIUMF DAQ group:

* Pierre-André Amaudruz (group leader) - http://www.triumf.ca/profiles/20
* Konstantin Olchanski - http://www.triumf.ca/profiles/3103
* Christopher J Pearson - http://www.triumf.ca/profiles/3648
* Thomas Lindner - http://www.triumf.ca/profiles/4937
* Benjamin Smith - http://www.triumf.ca/profiles/5446

== Experiment ==
{| cellpadding="5" cellspacing="0" border="1"
! Group || DAQ Primary Contact || DAQ Secondary contact || Experiment liaison || Experiment liaison Leader || Host machines || Notes
|-
| BNMR/BNQR || Ben Smith || Konstantin Olchanski || G Morris || A. Mac Farlane || isdaq01, isdaq06, lxbnmr, lxbnqr || local
|-
| MUSR || Ben Smith || Konstantin Olchanski || Donald Arseneau || Syd Kreitzman || musr00, midm15, midm9a, midm9b, midm20c, midm20d, midm20, linm15, linm9a, linm20, lxm9a, lxm9b, lxm20c, lxm20d, lxm15 || local
|-
| POL || Ben Smith || ... || Matt Pearson || Phil Levy || isdaq06, lxpol || local
|-
| Dragon || Konstantin Olchanski || ... || Chris Ruiz ||Chris Ruiz || isdaq04 || local
|-
| GPS || Chris Pearson ||Konstantin Olchanski || Gordon Ball || G.Ball || midtis06 || local
|-
| Titan (MPET) || Ben Smith || ... || ... || Jens Dilling || titan01, lxmpet || local
|-
| Titan (EBIT) || Ben Smith || Chris Pearson || ... || Jens Dilling || titan03, lxebit || local
|-
| Titan (CPET) || Ben Smith || ... || ... || Jens Dilling || titan01, lxcpet || local
|-
| Trinat || Konstrantin Olchanski || ... || ... || John Behr || midtis01, isdaq01 || local
|-
| EMMA || Konstantin Olchanski|| Thomas Lindner || ... || Barry Davids || ... || local
|-
| Tigress || Chris Pearson || Konstantin Olchanski || ... || Greg Hackman || Midtig01/02/03 || local
|-
| IRIS || Pierre-A. Amaudruz || Konstantin Olchanski || ... || Rituparna Kanungo || iris00..02, lxiris01..02 || local
|-
| UCN || Thomas Lindner || ... || ... || ... || ... || local
|-
| PTF || Thomas Lindner || ... || ... || ... || midptf01 || local
|-
| Griffin || Chris Pearson || Konstantin Olchanski || ... || Adam Garthworthy || ... || local
|-
| CCS (completed) || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Rolf Keitle || arm || local
|-
| Liquid Xe (retired)|| Pierre-A. Amaudruz || Konstantin Olchanski || ... || doug Bryman || xenon01, xenon02 || local
|-
| Alpha-II || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Makoto Fujiwara || ... || CERN
|-
| Alpha-g || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Makoto Fujiwara || ... || CERN
|-
| Hyper-K || Thomas Lindner || ... || ... || Fabrice Retiere || ... || J-Parc
|-
| SuperCDMS || Thomas Lindner || Ben Smith || ... || Scott Oser || ... || Snolab
|-
| DarkSide-20K || Pierre-A. Amaudruz || Ben Smith || ... || ... || dsvslice, dsfe01..04, dsts01..05 || LNGS
|-
| T2K - FGD (completed) || Pierre-A. Amaudruz || Konstantin Olchanski || ... || Scott Oser || ladd10 || J-Parc
|-
| DEAP (completed) || Pierre-A. Amaudruz || Konstantin Olchanski || Fabrice Retiere || ... || ... || Snolab
|-
| Atlas ThinChamber (retired) || Pierre-A. Amaudruz || ... || ... || ... || lxcamac01 || local
|-
| G-2 (retired) || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Glen Marshall || ... || local
|-
| SMD (retired) || Pierre-A. Amaudruz || ... || ... || Ewart Blackmore || ... || local
|-
| Tuda (retired) || Pierre-A. Amaudruz || Chris Pearson || ... || T.Davidson || tuda01..03 || local
|-
| Beast/Belle2 (retired) || Pierre-A. Amaudruz || ... || ... || ... || ... || KEK
|-
| Pingu (retired) || Pierre-A. Amaudruz || ... || ... || Fabrice Retiere || ... || South Pole
|
|}

IntroDAQ

2021-10-31T04:12:29Z

Midas: /* Experiment */

== Welcome to the Triumf DAQ Wiki site ==

The TRIUMF DAQ group provides support for the data acquisition systems used by experimenters to collect data.

Members of the TRIUMF DAQ group:

* Pierre-André Amaudruz (group leader) - http://www.triumf.ca/profiles/20
* Konstantin Olchanski - http://www.triumf.ca/profiles/3103
* Christopher J Pearson - http://www.triumf.ca/profiles/3648
* Thomas Lindner - http://www.triumf.ca/profiles/4937
* Benjamin Smith - http://www.triumf.ca/profiles/5446

== Experiment ==
{| cellpadding="5" cellspacing="0" border="1"
! Group || DAQ Primary Contact || DAQ Secondary contact || Experiment liaison || Experiment liaison Leader || Host machines || Notes
|-
| BNMR/BNQR || Ben Smith || Konstantin Olchanski || G Morris || A. Mac Farlane || isdaq01, isdaq06, lxbnmr, lxbnqr || local
|-
| MUSR || Ben Smith || ... || Donald Arseneau || Syd Kreitzman || musr00, midm15, midm9a, midm9b, midm20c, midm20d, midm20, linm15, linm9a, linm20, lxm9a, lxm9b, lxm20c, lxm20d, lxm15 || local
|-
| POL || Ben Smith || Pierre-A. Amaudruz || Matt Pearson || Phil Levy || isdaq06, lxpol || local
|-
| Dragon || Konstantin Olchanski || Pierre-A. Amaudruz || Chris Ruiz ||Chris Ruiz || isdaq04 || local
|-
| GPS || Chris Pearson ||Konstantin Olchanski || Gordon Ball || G.Ball || midtis06 || local
|-
| Titan (MPET) || Ben Smith || ... || ... || Jens Dilling || titan01, lxmpet || local
|-
| Titan (EBIT) || Ben Smith || Chris Pearson || ... || Jens Dilling || titan03, lxebit || local
|-
| Titan (CPET) || Ben Smith || ... || ... || Jens Dilling || titan01, lxcpet || local
|-
| Trinat || Konstrantin Olchanski || ... || ... || John Behr || midtis01, isdaq01 || local
|-
| EMMA || Konstantin Olchanski|| Thomas Lindner || ... || Barry Davids || ... || local
|-
| Tigress || Chris Pearson || Konstantin Olchanski || ... || Greg Hackman || Midtig01/02/03 || local
|-
| IRIS || Pierre-A. Amaudruz || Konstantin Olchanski || ... || Rituparna Kanungo || iris00..02, lxiris01..02 || local
|-
| UCN || Thomas Lindner || ... || ... || ... || ... || local
|-
| PTF || Thomas Lindner || ... || ... || ... || midptf01 || local
|-
| Griffin || Chris Pearson || Konstantin Olchanski || ... || Adam Garthworthy || ... || local
|-
| CCS (completed) || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Rolf Keitle || arm || local
|-
| Liquid Xe (retired)|| Pierre-A. Amaudruz || Konstantin Olchanski || ... || doug Bryman || xenon01, xenon02 || local
|-
| Alpha-II || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Makoto Fujiwara || ... || CERN
|-
| Alpha-g || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Makoto Fujiwara || ... || CERN
|-
| Hyper-K || Thomas Lindner || Pierre-A. Amaudruz || ... || Fabrice Retiere || ... || J-Parc
|-
| SuperCDMS || Thomas Lindner || Ben Smith || ... || Scott Oser || ... || Snolab
|-
| DarkSide-20K || Pierre-A. Amaudruz || Ben Smith || ... || ... || dsvslice, dsfe01..04, dsts01..05 || LNGS
|-
| T2K - FGD (completed) || Pierre-A. Amaudruz || Konstantin Olchanski || ... || Scott Oser || ladd10 || J-Parc
|-
| DEAP (completed) || Pierre-A. Amaudruz || Konstantin Olchanski || Fabrice Retiere || ... || ... || Snolab
|-
| Atlas ThinChamber (retired) || Pierre-A. Amaudruz || ... || ... || ... || lxcamac01 || local
|-
| G-2 (retired) || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Glen Marshall || ... || local
|-
| SMD (retired) || Pierre-A. Amaudruz || ... || ... || Ewart Blackmore || ... || local
|-
| Tuda (retired) || Pierre-A. Amaudruz || Chris Pearson || ... || T.Davidson || tuda01..03 || local
|-
| Beast/Belle2 (retired) || Pierre-A. Amaudruz || ... || ... || ... || ... || KEK
|-
| Pingu (retired) || Pierre-A. Amaudruz || ... || ... || Fabrice Retiere || ... || South Pole
|
|}

IntroDAQ

2021-09-23T17:41:22Z

Midas: /* Experiment */

== Welcome to the Triumf DAQ Wiki site ==

The TRIUMF DAQ group provides support for the data acquisition systems used by experimenters to collect data.

Members of the TRIUMF DAQ group:

* Pierre-André Amaudruz (group leader) - http://www.triumf.ca/profiles/20
* Konstantin Olchanski - http://www.triumf.ca/profiles/3103
* Christopher J Pearson - http://www.triumf.ca/profiles/3648
* Thomas Lindner - http://www.triumf.ca/profiles/4937
* Benjamin Smith - http://www.triumf.ca/profiles/5446

== Experiment ==
{| cellpadding="5" cellspacing="0" border="1"
! Group || DAQ Primary Contact || DAQ Secondary contact || Experiment liaison || Experiment liaison Leader || Host machines || Notes
|-
| BNMR/BNQR || Ben Smith || Konstantin Olchanski || G Morris || A. Mac Farlane || isdaq01, isdaq06, lxbnmr, lxbnqr || local
|-
| MUSR || Ben Smith || ... || Donald Arseneau || Syd Kreitzman || musr00, midm15, midm9a, midm9b, midm20c, midm20d, midm20, linm15, linm9a, linm20, lxm9a, lxm9b, lxm20c, lxm20d, lxm15 || local
|-
| POL || Ben Smith || Pierre-A. Amaudruz || Matt Pearson || Phil Levy || isdaq06, lxpol || local
|-
| Dragon || Konstantin Olchanski || Pierre-A. Amaudruz || Chris Ruiz ||Chris Ruiz || isdaq04 || local
|-
| GPS || Chris Pearson ||Konstantin Olchanski || Gordon Ball || G.Ball || midtis06 || local
|-
| Titan (MPET) || Ben Smith || ... || ... || Jens Dilling || titan01, lxmpet || local
|-
| Titan (EBIT) || Ben Smith || Chris Pearson || ... || Jens Dilling || titan03, lxebit || local
|-
| Titan (CPET) || Ben Smith || ... || ... || Jens Dilling || titan01, lxcpet || local
|-
| Trinat || Konstrantin Olchanski || ... || ... || John Behr || midtis01, isdaq01 || local
|-
| EMMA || Konstantin Olchanski|| Thomas Lindner || ... || Barry Davids || ... || local
|-
| Tigress || Chris Pearson || Konstantin Olchanski || ... || Greg Hackman || Midtig01/02/03 || local
|-
| IRIS || Pierre-A. Amaudruz || Konstantin Olchanski || ... || Rituparna Kanungo || iris00..02, lxiris01..02 || local
|-
| UCN || Thomas Lindner || ... || ... || ... || ... || local
|-
| PTF || Thomas Lindner || Pierre-A. Amaudruz || ... || ... || midptf01 || local
|-
| Griffin || Chris Pearson || Konstantin Olchanski || ... || Adam Garthworthy || ... || local
|-
| CCS (completed) || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Rolf Keitle || arm || local
|-
| Liquid Xe (retired)|| Pierre-A. Amaudruz || Konstantin Olchanski || ... || doug Bryman || xenon01, xenon02 || local
|-
| Alpha-II || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Makoto Fujiwara || ... || CERN
|-
| Alpha-g || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Makoto Fujiwara || ... || CERN
|-
| Hyper-K || Thomas Lindner || Pierre-A. Amaudruz || ... || Fabrice Retiere || ... || J-Parc
|-
| SuperCDMS || Thomas Lindner || Ben Smith || ... || Scott Oser || ... || Snolab
|-
| DarkSide-20K || Pierre-A. Amaudruz || Ben Smith || ... || ... || dsvslice, dsfe01..04, dsts01..05 || LNGS
|-
| T2K - FGD (completed) || Pierre-A. Amaudruz || Konstantin Olchanski || ... || Scott Oser || ladd10 || J-Parc
|-
| DEAP (completed) || Pierre-A. Amaudruz || Konstantin Olchanski || Fabrice Retiere || ... || ... || Snolab
|-
| Atlas ThinChamber (retired) || Pierre-A. Amaudruz || ... || ... || ... || lxcamac01 || local
|-
| G-2 (retired) || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Glen Marshall || ... || local
|-
| SMD (retired) || Pierre-A. Amaudruz || ... || ... || Ewart Blackmore || ... || local
|-
| Tuda (retired) || Pierre-A. Amaudruz || Chris Pearson || ... || T.Davidson || tuda01..03 || local
|-
| Beast/Belle2 (retired) || Pierre-A. Amaudruz || ... || ... || ... || ... || KEK
|-
| Pingu (retired) || Pierre-A. Amaudruz || ... || ... || Fabrice Retiere || ... || South Pole
|
|}

IntroDAQ

2021-09-23T17:40:53Z

Midas: /* Experiment */

== Welcome to the Triumf DAQ Wiki site ==

The TRIUMF DAQ group provides support for the data acquisition systems used by experimenters to collect data.

Members of the TRIUMF DAQ group:

* Pierre-André Amaudruz (group leader) - http://www.triumf.ca/profiles/20
* Konstantin Olchanski - http://www.triumf.ca/profiles/3103
* Christopher J Pearson - http://www.triumf.ca/profiles/3648
* Thomas Lindner - http://www.triumf.ca/profiles/4937
* Benjamin Smith - http://www.triumf.ca/profiles/5446

== Experiment ==
{| cellpadding="5" cellspacing="0" border="1"
! Group || DAQ Primary Contact || DAQ Secondary contact || Experiment liaison || Experiment liaison Leader || Host machines || Notes
|-
| BNMR/BNQR || Ben Smith || Konstantin Olchanski || G Morris || A. Mac Farlane || isdaq01, isdaq06, lxbnmr, lxbnqr || local
|-
| MUSR || Ben Smith || ... || Donald Arseneau || Syd Kreitzman || musr00, midm15, midm9a, midm9b, midm20c, midm20d, midm20, linm15, linm9a, linm20, lxm9a, lxm9b, lxm20c, lxm20d, lxm15 || local
|-
| POL || Ben Smith || Pierre-A. Amaudruz || Matt Pearson || Phil Levy || isdaq06, lxpol || local
|-
| Dragon || Konstantin Olchanski || Pierre-A. Amaudruz || Chris Ruiz ||Chris Ruiz || isdaq04 || local
|-
| GPS || Chris Pearson ||Konstantin Olchanski || Gordon Ball || G.Ball || midtis06 || local
|-
| Titan (MPET) || Ben Smith || ... || ... || Jens Dilling || titan01, lxmpet || local
|-
| Titan (EBIT) || Ben Smith || Chris Pearson || ... || Jens Dilling || titan03, lxebit || local
|-
| Titan (CPET) || Ben Smith || ... || ... || Jens Dilling || titan01, lxcpet || local
|-
| Trinat || Konstrantin Olchanski || ... || ... || John Behr || midtis01, isdaq01 || local
|-
| EMMA || Konstantin Olchanski|| Thomas Lindner || ... || Barry Davids || ... || local
|-
| Tigress || Chris Pearson || Konstantin Olchanski || ... || Greg Hackman || Midtig01/02/03 || local
|-
| IRIS || Pierre-A. Amaudruz || Konstantin Olchanski || ... || Rituparna Kanungo || iris00..02, lxiris01..02 || local
|-
| UCN || Thomas Lindner || ... || ... || ... || ... || local
|-
| PTF || Thomas Lindner || Pierre-A. Amaudruz || ... || ... || midptf01 || local
|-
| Griffin || Chris Pearson || Konstantin Olchanski || ... || Adam Garthworthy || ... || local
|-
| CCS (completed) || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Rolf Keitle || arm || local
|-
| Liquid Xe (retired)|| Pierre-A. Amaudruz || Konstantin Olchanski || ... || doug Bryman || xenon01, xenon02 || local
|-
| Alpha-II || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Makoto Fujiwara || ... || CERN
|-
| Alpha-g || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Makoto Fujiwara || ... || CERN
|-
| Hyper-K || Thomas Lindner || Pierre-A. Amaudruz || ... || Fabrice Retiere || ... || J-Parc
|-
| SuperCDMS || Thomas Lindner || Ben Smith || ... || Scott Oser || ... || Snolab
|-
| DarkSide-20K || Pierre-A. Amaudruz || Ben Smith || ... || ... || dsvslice, dsfe01..04, dsts01.05 || LNGS
|-
| T2K - FGD (completed) || Pierre-A. Amaudruz || Konstantin Olchanski || ... || Scott Oser || ladd10 || J-Parc
|-
| DEAP (completed) || Pierre-A. Amaudruz || Konstantin Olchanski || Fabrice Retiere || ... || ... || Snolab
|-
| Atlas ThinChamber (retired) || Pierre-A. Amaudruz || ... || ... || ... || lxcamac01 || local
|-
| G-2 (retired) || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Glen Marshall || ... || local
|-
| SMD (retired) || Pierre-A. Amaudruz || ... || ... || Ewart Blackmore || ... || local
|-
| Tuda (retired) || Pierre-A. Amaudruz || Chris Pearson || ... || T.Davidson || tuda01..03 || local
|-
| Beast/Belle2 (retired) || Pierre-A. Amaudruz || ... || ... || ... || ... || KEK
|-
| Pingu (retired) || Pierre-A. Amaudruz || ... || ... || Fabrice Retiere || ... || South Pole
|
|}

IntroDAQ

2021-09-23T17:38:49Z

Midas: /* Experiment */

== Welcome to the Triumf DAQ Wiki site ==

The TRIUMF DAQ group provides support for the data acquisition systems used by experimenters to collect data.

Members of the TRIUMF DAQ group:

* Pierre-André Amaudruz (group leader) - http://www.triumf.ca/profiles/20
* Konstantin Olchanski - http://www.triumf.ca/profiles/3103
* Christopher J Pearson - http://www.triumf.ca/profiles/3648
* Thomas Lindner - http://www.triumf.ca/profiles/4937
* Benjamin Smith - http://www.triumf.ca/profiles/5446

== Experiment ==
{| cellpadding="5" cellspacing="0" border="1"
! Group || DAQ Primary Contact || DAQ Secondary contact || Experiment liaison || Experiment liaison Leader || Host machines || Notes
|-
| BNMR/BNQR || Ben Smith || Konstantin Olchanski || G Morris || A. Mac Farlane || isdaq01, isdaq06, lxbnmr, lxbnqr || local
|-
| MUSR || Ben Smith || ... || Donald Arseneau || Syd Kreitzman || musr00, midm15, midm9a, midm9b, midm20c, midm20d, midm20, linm15, linm9a, linm20, lxm9a, lxm9b, lxm20c, lxm20d, lxm15 || local
|-
| POL || Ben Smith || Pierre-A. Amaudruz || Matt Pearson || Phil Levy || isdaq06, lxpol || local
|-
| Dragon || Konstantin Olchanski || Pierre-A. Amaudruz || Chris Ruiz ||Chris Ruiz || isdaq04 || local
|-
| GPS || Chris Pearson ||Konstantin Olchanski || Gordon Ball || G.Ball || midtis06 || local
|-
| Titan (MPET) || Ben Smith || ... || ... || Jens Dilling || titan01, lxmpet || local
|-
| Titan (EBIT) || Ben Smith || Chris Pearson || ... || Jens Dilling || titan03, lxebit || local
|-
| Titan (CPET) || Ben Smith || ... || ... || Jens Dilling || titan01, lxcpet || local
|-
| Trinat || Konstrantin Olchanski || ... || ... || John Behr || midtis01, isdaq01 || local
|-
| EMMA || Konstantin Olchanski|| Thomas Lindner || ... || Barry Davids || ... || local
|-
| Tigress || Chris Pearson || Konstantin Olchanski || ... || Greg Hackman || Midtig01/02/03 || local
|-
| IRIS || Pierre-A. Amaudruz || Konstantin Olchanski || ... || Rituparna Kanungo || iris00..02, lxiris01..02 || local
|-
| UCN || Thomas Lindner || ... || ... || ... || ... || local
|-
| PTF || Thomas Lindner || Pierre-A. Amaudruz || ... || ... || midptf01 || local
|-
| Griffin || Chris Pearson || Konstantin Olchanski || ... || Adam Garthworthy || ... || local
|-
| CCS (completed) || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Rolf Keitle || arm || local
|-
| Liquid Xe (retired)|| Pierre-A. Amaudruz || Konstantin Olchanski || ... || doug Bryman || xenon01, xenon02 || local
|-
| Alpha-II || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Makoto Fujiwara || ... || CERN
|-
| Alpha-g || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Makoto Fujiwara || ... || CERN
|-
| Hyper-K || Thomas Lindner || Pierre-A. Amaudruz || ... || Fabrice Retiere || ... || J-Parc
|-
| SuperCDMS || Thomas Lindner || Ben Smith || ... || Scott Oser || ... || Snolab
|-
| DarkSide-20K || Pierre-A. Amaudruz || Ben Smith || ... || ... || ... || LNGS
|-
| T2K - FGD (completed) || Pierre-A. Amaudruz || Konstantin Olchanski || ... || Scott Oser || ladd10 || J-Parc
|-
| DEAP (completed) || Pierre-A. Amaudruz || Konstantin Olchanski || Fabrice Retiere || ... || ... || Snolab
|-
| Atlas ThinChamber (retired) || Pierre-A. Amaudruz || ... || ... || ... || lxcamac01 || local
|-
| G-2 (retired) || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Glen Marshall || ... || local
|-
| SMD (retired) || Pierre-A. Amaudruz || ... || ... || Ewart Blackmore || ... || local
|-
| Tuda (retired) || Pierre-A. Amaudruz || Chris Pearson || ... || T.Davidson || tuda01..03 || local
|-
| Beast/Belle2 (retired) || Pierre-A. Amaudruz || ... || ... || ... || ... || KEK
|-
| Pingu (retired) || Pierre-A. Amaudruz || ... || ... || Fabrice Retiere || ... || South Pole
|
|}

IntroDAQ

2021-09-23T16:55:58Z

Midas: /* Experiment */

== Welcome to the Triumf DAQ Wiki site ==

The TRIUMF DAQ group provides support for the data acquisition systems used by experimenters to collect data.

Members of the TRIUMF DAQ group:

* Pierre-André Amaudruz (group leader) - http://www.triumf.ca/profiles/20
* Konstantin Olchanski - http://www.triumf.ca/profiles/3103
* Christopher J Pearson - http://www.triumf.ca/profiles/3648
* Thomas Lindner - http://www.triumf.ca/profiles/4937
* Benjamin Smith - http://www.triumf.ca/profiles/5446

== Experiment ==
{| cellpadding="5" cellspacing="0" border="1"
! Group || DAQ Primary Contact || DAQ Secondary contact || Experiment liaison || Experiment liaison Leader || Host machines || Notes
|-
| BNMR/BNQR || Ben Smith || Konstantin Olchanski || G Morris || A. Mac Farlane || isdaq01, isdaq06, lxbnmr, lxbnqr ||
|-
| MUSR || Ben Smith || ... || Donald Arseneau || Syd Kreitzman || musr00, midm15, midm9a, midm9b, midm20c, midm20d, midm20, linm15, linm9a, linm20, lxm9a, lxm9b, lxm20c, lxm20d, lxm15 ||
|-
| POL || Ben Smith || Pierre-A. Amaudruz || Matt Pearson || Phil Levy || isdaq06, lxpol ||
|-
| Dragon || Konstantin Olchanski || Pierre-A. Amaudruz || Chris Ruiz ||Chris Ruiz || isdaq04 ||
|-
| GPS || Chris Pearson ||Konstantin Olchanski || Gordon Ball || G.Ball || midtis06 ||
|-
| Titan (MPET) || Ben Smith || ... || ... || Jens Dilling || titan01, lxmpet ||
|-
| Titan (EBIT) || Ben Smith || Chris Pearson || ... || Jens Dilling || titan03, lxebit ||
|-
| Titan (CPET) || Ben Smith || ... || ... || Jens Dilling || titan01, lxcpet ||
|-
| Trinat || Konstrantin Olchanski || ... || ... || John Behr || midtis01, isdaq01 ||
|-
| Tuda (retired) || Pierre-A. Amaudruz || Chris Pearson || ... || T.Davidson || tuda01..03 ||
|-
| EMMA || Konstantin Olchanski|| Thomas Lindner || ... || Barry Davids || ... ||
|-
| Tigress || Chris Pearson || Konstantin Olchanski || ... || Greg Hackman || Midtig01/02/03 ||
|-
| IRIS || Pierre-A. Amaudruz || Konstantin Olchanski || ... || Rituparna Kanungo || iris00..02, lxiris01..02 ||
|-
| UCN || Thomas Lindner || ... || ... || ... || ... ||
|-
| Alpha-II || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Makoto Fujiwara || ... ||
|-
| Alpha-g || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Makoto Fujiwara || ... ||
|-
| Hyper-K || Thomas Lindner || Pierre-A. Amaudruz || ... || Fabrice Retiere || ... ||
|-
| SuperCDMS || Thomas Lindner || Ben Smith || ... || Scott Oser || ... ||
|-
| PTF || Thomas Lindner || Pierre-A. Amaudruz || ... || ... || midptf01 ||
|-
| Griffin || Chris Pearson || Konstantin Olchanski || ... || Adam Garthworthy || ... ||
|-
| T2K - FGD (completed) || Pierre-A. Amaudruz || Konstantin Olchanski || ... || Scott Oser || ladd10 ||
|-
| DEAP (completed) || Pierre-A. Amaudruz || Konstantin Olchanski || Fabrice Retiere || ... || ... ||
|-
| CCS (completed) || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Rolf Keitle || arm ||
|-
| Liquid Xe (retired)|| Pierre-A. Amaudruz || Konstantin Olchanski || ... || doug Bryman || xenon01, xenon02 ||
|-
| Pingu (retired) || Pierre-A. Amaudruz || ... || ... || Fabrice Retiere || ... ||
|-
| Atlas ThinChamber (retired) || Pierre-A. Amaudruz || ... || ... || ... || lxcamac01 ||
|-
| Beast/Belle2 (retired) || Pierre-A. Amaudruz || ... || ... || Paul Poffenberger || ... ||
|-
| G-2 (retired) || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Glen Marshall || ... ||
|-
| SMD (retired) || Pierre-A. Amaudruz || ... || ... || Ewart Blackmore || ... ||
|-
| DarkSide-20K || Pierre-A. Amaudruz || Ben Smith || ... || ... || ... ||
|-
|
|}

IntroDAQ

2020-09-04T22:28:14Z

Midas: adjust listing

== Welcome to the Triumf DAQ Wiki site ==

The TRIUMF DAQ group provides support for the data acquisition systems used by experimenters to collect data.

Members of the TRIUMF DAQ group:

* Pierre-André Amaudruz (group leader) - http://www.triumf.ca/profiles/20
* Konstantin Olchanski - http://www.triumf.ca/profiles/3103
* Christopher J Pearson - http://www.triumf.ca/profiles/3648
* Thomas Lindner - http://www.triumf.ca/profiles/4937
* Benjamin Smith - http://www.triumf.ca/profiles/5446

== Experiment ==
{| cellpadding="5" cellspacing="0" border="1"
! Group || DAQ Primary Contact || DAQ Secondary contact || Experiment liaison || Experiment liaison Leader || Host machines || Notes
|-
| BNMR/BNQR || Ben Smith || Konstantin Olchanski || G Morris || A. Mac Farlane || isdaq01, isdaq06, lxbnmr, lxbnqr ||
|-
| MUSR || Ben Smith || ... || Donald Arseneau || Syd Kreitzman || musr00, midm15, midm9a, midm9b, midm20c, midm20d, midm20, linm15, linm9a, linm20, lxm9a, lxm9b, lxm20c, lxm20d, lxm15 ||
|-
| POL || Ben Smith || Pierre-A. Amaudruz || Matt Pearson || Phil Levy || isdaq06, lxpol ||
|-
| Dragon || Konstantin Olchanski || Pierre-A. Amaudruz || Chris Ruiz ||Chris Ruiz || isdaq04 ||
|-
| GPS || Chris Pearson ||Konstantin Olchanski || Gordon Ball || G.Ball || midtis06 ||
|-
| Titan (MPET) || Ben Smith || ... || ... || Jens Dilling || titan01, lxmpet ||
|-
| Titan (EBIT) || Ben Smith || Chris Pearson || ... || Jens Dilling || titan03, lxebit ||
|-
| Titan (CPET) || Ben Smith || ... || ... || Jens Dilling || titan01, lxcpet ||
|-
| Trinat || Konstrantin Olchanski || ... || ... || John Behr || midtis01, isdaq01 ||
|-
| Tuda || Pierre-A. Amaudruz || Chris Pearson || ... || T.Davidson || tuda01..03 ||
|-
| EMMA || Konstantin Olchanski|| Thomas Lindner || ... || Barry Davids || ... ||
|-
| Tigress || Chris Pearson || Konstantin Olchanski || ... || Greg Hackman || Midtig01/02/03 ||
|-
| IRIS || Pierre-A. Amaudruz || Konstantin Olchanski || ... || Rituparna Kanungo || iris00..02, lxiris01..02 ||
|-
| UCN || Thomas Lindner || ... || ... || ... || ... ||
|-
| Alpha-II || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Makoto Fujiwara || ... ||
|-
| Alpha-g || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Makoto Fujiwara || ... ||
|-
| Hyper-K || Thomas Lindner || Pierre-A. Amaudruz || ... || Fabrice Retiere || ... ||
|-
| SuperCDMS || Thomas Lindner || Ben Smith || ... || Scott Oser || ... ||
|-
| PTF || Thomas Lindner || Pierre-A. Amaudruz || ... || ... || midptf01 ||
|-
| Griffin || Chris Pearson || Konstantin Olchanski || ... || Adam Garthworthy || ... ||
|-
| T2K - FGD (completed) || Pierre-A. Amaudruz || Konstantin Olchanski || ... || Scott Oser || ladd10 ||
|-
| DEAP (completed) || Pierre-A. Amaudruz || Konstantin Olchanski || Fabrice Retiere || ... || ... ||
|-
| CCS (completed) || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Rolf Keitle || arm ||
|-
| Liquid Xe (retired)|| Pierre-A. Amaudruz || Konstantin Olchanski || ... || doug Bryman || xenon01, xenon02 ||
|-
| Pingu (retired) || Pierre-A. Amaudruz || ... || ... || Fabrice Retiere || ... ||
|-
| Atlas ThinChamber (retired) || Pierre-A. Amaudruz || ... || ... || ... || lxcamac01 ||
|-
| Beast/Belle2 (retired) || Pierre-A. Amaudruz || ... || ... || Paul Poffenberger || ... ||
|-
| G-2 (retired) || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Glen Marshall || ... ||
|-
| SMD (retired) || Pierre-A. Amaudruz || ... || ... || Ewart Blackmore || ... ||
|-
|
|}

IntroDAQ

2020-09-04T22:25:31Z

Midas: Adjust listing

== Welcome to the Triumf DAQ Wiki site ==

The TRIUMF DAQ group provides support for the data acquisition systems used by experimenters to collect data.

Members of the TRIUMF DAQ group:

* Pierre-André Amaudruz (group leader) - http://www.triumf.ca/profiles/20
* Konstantin Olchanski - http://www.triumf.ca/profiles/3103
* Christopher J Pearson - http://www.triumf.ca/profiles/3648
* Thomas Lindner - http://www.triumf.ca/profiles/4937
* Benjamin Smith - http://www.triumf.ca/profiles/5446

== Experiment ==
{| cellpadding="5" cellspacing="0" border="1"
! Group || DAQ Primary Contact || DAQ Secondary contact || Experiment liaison || Experiment liaison Leader || Host machines || Notes
|-
| BNMR/BNQR || Ben Smith || Konstantin Olchanski || G Morris || A. Mac Farlane || isdaq01, isdaq06, lxbnmr, lxbnqr ||
|-
| MUSR || Ben Smith || ... || Donald Arseneau || Syd Kreitzman || musr00, midm15, midm9a, midm9b, midm20c, midm20d, midm20, linm15, linm9a, linm20, lxm9a, lxm9b, lxm20c, lxm20d, lxm15 ||
|-
| POL || Ben Smith || Pierre-A. Amaudruz || Matt Pearson || Phil Levy || isdaq06, lxpol ||
|-
| Dragon || Konstantin Olchanski || Pierre-A. Amaudruz || Chris Ruiz ||Chris Ruiz || isdaq04 ||
|-
| GPS || Chris Pearson ||Konstantin Olchanski || Gordon Ball || G.Ball || midtis06 ||
|-
| Titan (MPET) || Ben Smith || ... || ... || Jens Dilling || titan01, lxmpet ||
|-
| Titan (EBIT) || Ben Smith || Chris Pearson || ... || Jens Dilling || titan03, lxebit ||
|-
| Titan (CPET) || Ben Smith || ... || ... || Jens Dilling || titan01, lxcpet ||
|-
| Trinat || Konstrantin Olchanski || ... || ... || John Behr || midtis01, isdaq01 ||
|-
| Tuda || Pierre-A. Amaudruz || Chris Pearson || ... || T.Davidson || tuda01..03 ||
|-
| EMMA || Konstantin Olchanski|| Thomas Lindner || ... || Barry Davids || ... ||
|-
| Tigress || Chris Pearson || Konstantin Olchanski || ... || Greg Hackman || Midtig01/02/03 ||
|-
| IRIS || Pierre-A. Amaudruz || Konstantin Olchanski || ... || Rituparna Kanungo || iris00..02, lxiris01..02 ||
|-
| Alpha-II || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Makoto Fujiwara || ... ||
|-
| Alpha-g || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Makoto Fujiwara || ... ||
|-
| SuperCDMS || Thomas Lindner || Ben Smith || ... || Scott Oser || ... ||
|-
| PTF || Thomas Lindner || Pierre-A. Amaudruz || ... || ... || midptf01 ||
|-
| Hyper-K || Thomas Lindner || Pierre-A. Amaudruz || ... || Fabrice Retiere || ... ||
|-
| CCS || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Rolf Keitle || arm ||
|-
| UCN || Thomas Lindner || ... || ... || ... || ... ||
|-
| Griffin || Chris Pearson || Konstantin Olchanski || ... || Adam Garthworthy || ... ||
|-
| T2K - FGD (completed) || Konstantin Olchanski || Thomas Lindner || Fabrice Retiere || Scott Oser || ladd10 ||
|-
| DEAP (completed) || Pierre-A. Amaudruz || Konstantin Olchanski || Fabrice Retiere || ... || ... ||
|-
| Liquid Xe (retired)|| Pierre-A. Amaudruz || Konstantin Olchanski || ... || doug Bryman || xenon01, xenon02 ||
|-
| Pingu (retired) || Pierre-A. Amaudruz || ... || ... || Fabrice Retiere || ... ||
|-
| Atlas ThinChamber (retired) || Pierre-A. Amaudruz || ... || ... || ... || lxcamac01 ||
|-
| Beast/Belle2 (retired) || Pierre-A. Amaudruz || ... || ... || Paul Poffenberger || ... ||
|-
| G-2 (retired) || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Glen Marshall || ... ||
|-
| SMD (retired) || Pierre-A. Amaudruz || ... || ... || Ewart Blackmore || ... ||
|-
|
|}

IntroDAQ

2020-09-04T22:21:03Z

Midas: Experiments

== Welcome to the Triumf DAQ Wiki site ==

The TRIUMF DAQ group provides support for the data acquisition systems used by experimenters to collect data.

Members of the TRIUMF DAQ group:

* Pierre-André Amaudruz (group leader) - http://www.triumf.ca/profiles/20
* Konstantin Olchanski - http://www.triumf.ca/profiles/3103
* Christopher J Pearson - http://www.triumf.ca/profiles/3648
* Thomas Lindner - http://www.triumf.ca/profiles/4937
* Benjamin Smith - http://www.triumf.ca/profiles/5446

== Experiment ==
{| cellpadding="5" cellspacing="0" border="1"
! Group || DAQ Primary Contact || DAQ Secondary contact || Experiment liaison || Experiment liaison Leader || Host machines || Notes
|-
| BNMR/BNQR || Ben Smith || Konstantin Olchanski || G Morris || A. Mac Farlane || isdaq01, isdaq06, lxbnmr, lxbnqr ||
|-
| MUSR || Ben Smith || ... || Donald Arseneau || Syd Kreitzman || musr00, midm15, midm9a, midm9b, midm20c, midm20d, midm20, linm15, linm9a, linm20, lxm9a, lxm9b, lxm20c, lxm20d, lxm15 ||
|-
| POL || Ben Smith || Pierre-A. Amaudruz || Matt Pearson || Phil Levy || isdaq06, lxpol ||
|-
| Dragon || Konstantin Olchanski || Pierre-A. Amaudruz || Chris Ruiz ||Chris Ruiz || isdaq04 ||
|-
| GPS || Chris Pearson ||Konstantin Olchanski || Gordon Ball || G.Ball || midtis06 ||
|-
| Titan (MPET) || Ben Smith || ... || ?? || Jens Dilling || titan01, lxmpet ||
|-
| Titan (EBIT) || Ben Smith || Chris Pearson || ?? || Jens Dilling || titan03, lxebit ||
|-
| Titan (CPET) || Ben Smith || ... || ?? || Jens Dilling || titan01, lxcpet ||
|-
| Trinat || Konstrantin Olchanski || ... || .. || John Behr || midtis01, isdaq01 ||
|-
| Tuda || Pierre-A. Amaudruz || Chris Pearson || ... || T.Davidson || tuda01..03 ||
|-
| EMMA || Konstantin Olchanski|| Thomas Lindner || .. || Barry Davids || .. ||
|-
| Tigress || Chris Pearson || Konstantin Olchanski || ... || Greg Hackman || Midtig01/02/03 ||
|-
| IRIS || Pierre-A. Amaudruz || Konstantin Olchanski || ... || Rituparna Kanungo || iris00..02, lxiris01..02 ||
|-
| T2K - FGD (completed) || Konstantin Olchanski || Thomas Lindner || Fabrice Retiere || Scott Oser || ladd10 ||
|-
| Alpha-II || Konstantin Olchanski || Pierre-A. Amaudruz || .. || Makoto Fujiwara || ... ||
|-
| Alpha-g || Konstantin Olchanski || Pierre-A. Amaudruz || .. || Makoto Fujiwara || ... ||
|-
| Liquid Xe (retired)|| Pierre-A. Amaudruz || Konstantin Olchanski || ... || doug Bryman || xenon01, xenon02 ||
|-
| DEAP (completed) || Pierre-A. Amaudruz || Konstantin Olchanski || Fabrice Retiere || ... || ... ||
|-
| SuperCDMS || Thomas Lindner || Ben Smith || ... || Scott Oser || ... ||
|-
| PTF || Thomas Lindner || Pierre-A. Amaudruz || ... || ... || midptf01 ||
|-
| CCS || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Rolf Keitle || arm ||
|-
| UCN || Thomas Lindner || ... || ... || .. || ... ||
|-
| G-2 (retired) || Konstantin Olchanski || Pierre-A. Amaudruz || .. || Glen Marshall || .. ||
|-
| SMD (retired) || Pierre-A. Amaudruz || .. || .. || Ewart Blackmore || .. ||
|-
| Griffin || Chris Pearson || Konstantin Olchanski || .. || Adam Garthworthy || .. ||
|-
| Pingu (retired) || Pierre-A. Amaudruz || .. || .. || Fabrice Retiere || .. ||
|-
| Atlas ThinChamber (retired) || Pierre-A. Amaudruz || .. || .. || .. || lxcamac01 ||
|-
| Beast/Belle2 (retired) || Pierre-A. Amaudruz || .. || .. || Paul Poffenberger || .. ||
|-
| Hyper-K || Thomas Lindner || Pierre-A. Amaudruz || .. || Fabrice Retiere || .. ||
|-
|
|}

IntroDAQ

2020-09-04T22:20:23Z

Midas: Intro

IntroDAQ

2020-09-04T22:19:01Z

Midas: Experiements

== Welcome to the Triumf DAQ Wiki site ==

The TRIUMF DAQ group provides support for the data acquisition systems used by experimenters to collect data.

Members of the TRIUMF DAQ group:

* Pierre-André Amaudruz (group leader) - http://www.triumf.ca/profiles/20
* Konstantin Olchanski - http://www.triumf.ca/profiles/3103
* Christopher J Pearson - http://www.triumf.ca/profiles/3648
* Thomas Lindner - http://www.triumf.ca/profiles/4937
* Benjamin Smith - http://www.triumf.ca/profiles/5446

= Experiment ==
{| cellpadding="10" cellspacing="0" border="1"
! Group || DAQ Primary Contact || DAQ Secondary contact || Experiment liaison || Experiment liaison Leader || Host machines || Notes
|-
| BNMR/BNQR || Ben Smith || Konstantin Olchanski || G Morris || A. Mac Farlane || isdaq01, isdaq06, lxbnmr, lxbnqr ||
|-
| MUSR || Ben Smith || ... || Donald Arseneau || Syd Kreitzman || musr00, midm15, midm9a, midm9b, midm20c, midm20d, midm20, linm15, linm9a, linm20, lxm9a, lxm9b, lxm20c, lxm20d, lxm15 ||
|-
| POL || Ben Smith || Pierre-A. Amaudruz || Matt Pearson || Phil Levy || isdaq06, lxpol ||
|-
| Dragon || Konstantin Olchanski || Pierre-A. Amaudruz || Chris Ruiz ||Chris Ruiz || isdaq04 ||
|-
| GPS || Chris Pearson ||Konstantin Olchanski || Gordon Ball || G.Ball || midtis06 ||
|-
| Titan (MPET) || Ben Smith || ... || ?? || Jens Dilling || titan01, lxmpet ||
|-
| Titan (EBIT) || Ben Smith || Chris Pearson || ?? || Jens Dilling || titan03, lxebit ||
|-
| Titan (CPET) || Ben Smith || ... || ?? || Jens Dilling || titan01, lxcpet ||
|-
| Trinat || Konstrantin Olchanski || ... || .. || John Behr || midtis01, isdaq01 ||
|-
| Tuda || Pierre-A. Amaudruz || Chris Pearson || ... || T.Davidson || tuda01..03 ||
|-
| EMMA || Konstantin Olchanski|| Thomas Lindner || .. || Barry Davids || .. ||
|-
| Tigress || Chris Pearson || Konstantin Olchanski || ... || Greg Hackman || Midtig01/02/03 ||
|-
| IRIS || Pierre-A. Amaudruz || Konstantin Olchanski || ... || Rituparna Kanungo || iris00..02, lxiris01..02 ||
|-
| T2K - FGD (completed) || Konstantin Olchanski || Thomas Lindner || Fabrice Retiere || Scott Oser || ladd10 ||
|-
| Alpha-II || Konstantin Olchanski || Pierre-A. Amaudruz || .. || Makoto Fujiwara || ... ||
|-
| Alpha-g || Konstantin Olchanski || Pierre-A. Amaudruz || .. || Makoto Fujiwara || ... ||
|-
| Liquid Xe (retired)|| Pierre-A. Amaudruz || Konstantin Olchanski || ... || doug Bryman || xenon01, xenon02 ||
|-
| DEAP (completed) || Pierre-A. Amaudruz || Konstantin Olchanski || Fabrice Retiere || ... || ... ||
|-
| SuperCDMS || Thomas Lindner || Ben Smith || ... || Scott Oser || ... ||
|-
| PTF || Thomas Lindner || Pierre-A. Amaudruz || ... || ... || midptf01 ||
|-
| CCS || Konstantin Olchanski || Pierre-A. Amaudruz || ... || Rolf Keitle || arm ||
|-
| UCN || Thomas Lindner || ... || ... || .. || ... ||
|-
| G-2 (retired) || Konstantin Olchanski || Pierre-A. Amaudruz || .. || Glen Marshall || .. ||
|-
| SMD (retired) || Pierre-A. Amaudruz || .. || .. || Ewart Blackmore || .. ||
|-
| Griffin || Chris Pearson || Konstantin Olchanski || .. || Adam Garthworthy || .. ||
|-
| Pingu (retired) || Pierre-A. Amaudruz || .. || .. || Fabrice Retiere || .. ||
|-
| Atlas ThinChamber (retired) || Pierre-A. Amaudruz || .. || .. || .. || lxcamac01 ||
|-
| Beast/Belle2 (retired) || Pierre-A. Amaudruz || .. || .. || Paul Poffenberger || .. ||
|-
| Hyper-K || Thomas Lindner || Pierre-A. Amaudruz || .. || Fabrice Retiere || .. ||
|-
|
|}

IntroDAQ

2020-09-04T22:17:49Z

Midas: Intro

Ubuntu

2020-07-29T22:05:33Z

Midas: Addition request from Queen's for DarkSide

= About Ubuntu =

AAA

= Ubuntu version =

<pre>
lsb_release -a
uname -a
</pre>

= Ubuntu installer =

* download the latest Ubuntu LTS desktoip installer iso image
* dd the image to a USB key
* boot from USB key in legacy mode (NOT UEFI - may have to select this in the BIOS boot menu - F8 for ASUS, F11 for Supermicro)
* follow the instruction
* create user "wheel" with the usual root password
* run through the installation, reboot
* login as user wheel
* open terminal, run "sudo /bin/bash", enter the root password, you now have the root shell
* run nm-connection-editor to configure the network
* after network is up (can ping ladd00), continue with post-installation steps below

= Install instructions =

== prepare ==
<pre>
apt-get update
apt-get upgrade
</pre>

== install time synchronization ==
<pre>
apt-get -y install chrony
echo server time1 iburst >> /etc/chrony/chrony.conf
echo server time2 iburst >> /etc/chrony/chrony.conf
echo server time3 iburst >> /etc/chrony/chrony.conf
systemctl disable systemd-timesyncd.service
systemctl stop systemd-timesyncd.service
systemctl disable ntp
systemctl stop ntp
systemctl enable chrony
systemctl restart chrony
chronyc sources
chronyc tracking
</pre>

== install email server ==
<pre>
dpkg-reconfigure postfix ### or
apt-get install postfix ### select "satellite system", enter full hostname "xxx.triumf.ca", enter "smtp.triumf.ca"
echo olchansk@triumf.ca >> ~root/.forward
apt-get install -y mailutils
mailx root
test
^D
</pre>

== install missing packages ==
<pre>
yes | apt-get -y install ssh
yes | apt-get -y install git subversion g++
yes | apt-get -y install libz-dev sqlite sqlite3 libsqlite3-dev libmysqlclient-dev unixodbc-dev
yes | apt-get -y install sqliteman
yes | apt-get -y install libssl-dev
yes | apt-get -y install sysstat smartmontools # also installs postfix
yes | apt-get -y install emacs xemacs21
yes | apt-get -y install mutt # email client
yes | apt-get -y install liblz4-tool pbzip2
yes | apt-get -y install libc6-dev-i386 # otherwise no /usr/include/sys/types.h
yes | apt-get -y install libreadline-dev
yes | apt-get -y install chromium-browser chromium-codecs-ffmpeg-extra
yes | apt-get -y install ubuntu-mate-themes
yes | apt-get -y install minicom
yes | apt-get -y install screen
yes | apt-get -y install rsync strace net-tools
yes | apt-get -y install emacs xemacs21
yes | apt-get -y install xfig gsfonts-x11 gsfonts-other # install fonts for xfig
yes | apt-get -y install time # /usr/bin/time
yes | apt-get -y install libgsl-dev # additional GNU Scientific Library
</pre>

== install ganglia ==

<pre>
yes | apt-get -y install ganglia-monitor
systemctl enable ganglia-monitor
cd ~root/git/scripts
git pull
cp etc/gmond-ubuntu.conf /etc/ganglia/gmond.conf
systemctl restart ganglia-monitor
systemctl status ganglia-monitor
ps -efw | grep gmond
</pre>

== install gonodeinfo ==

* go to https://bitbucket.org/dd1/gonodeinfo follow instructions:
<pre>
yes | apt-get -y install golang
mkdir ~/git
cd ~/git
git clone https://bitbucket.org/dd1/gonodeinfo.git
cd gonodeinfo
git pull
make
make install # install gonodeinfo agent
cd ~ # this is important
</pre>
* edit /etc/gonodeinfo.conf
* change "Description", "Location", "User" and "Administrator" as appropriate (or delete them)
* change "Servers" to read: Servers: ladd00.triumf.ca:8601
* run gonodeinfo
* if error is "connection refused". go to the nodeinfo server to add this client to the access control list:
* on the gonodeinfo server: run gonodereceive -a daq13
* try gonodeinfo again, there should be no error
* on the gonodeinfo server: run gonodereport, look at the web pages, the new machine should be listed now

== install libz.so.1 for CentOS compatibility ==

<pre>
yes | apt-get -y install zlib1g
yes | apt-get -y install zlib1g:i386 libc6:i386 libgcc1:i386 gcc-6-base:i386
</pre>

== install libpng12.so.0 for Quartus compatibility ==

(does not work anymore!!!)

<pre>
wget http://ftp.ca.debian.org/debian/pool/main/libp/libpng/libpng12-0_1.2.50-2+deb8u2_amd64.deb
dpkg --install libpng12-0_1.2.50-2+deb8u2_amd64.deb
</pre>

== install packages for building ROOT ==

<pre>
apt-get -y install libx11-dev libxpm-dev libxft-dev libxext-dev libpng-dev libjpeg-dev xlibmesa-glu-dev libxml2-dev libgsl-dev cmake
</pre>

== install desktop environments ==

* install MATE desktop

<pre>
yes | apt-get -y install ubuntu-mate-core ubuntu-mate-desktop
yes | apt-get -y install ubuntu-mate-themes
</pre>

* install Cinnamon desktop

<pre>
### not needed 18.04 LTS ### add-apt-repository ppa:embrosyn/cinnamon
yes | apt update
yes | apt-get -y install cinnamon
</pre>

* install KDE desktop

<pre>
yes | apt-get -y install kubuntu-desktop
</pre>

* install Lxqt desktop

<pre>
yes | apt-get -y install lxqt
</pre>

* install Xfce4 desktop
<pre>
yes | apt-get -y install xfce4
</pre>

== install ROOT ==

Please install ROOT per instructions at http://root.cern.ch.

NOTE1: The ROOT package available from Ubuntu repositories is severely out of date and cannot be used with MIDAS and ROOTANA. ### DO NOT DO THIS! apt-get install root-system

NOTE2: as of 2017-Jan-09, ROOT binary kits for Ubuntu do not work (use GCC 5 instead of GCC6), build from source instead.

== Install x2go ==

x2go instructions, thanks to Art O.

<pre>
add-apt-repository ppa:x2go/stable
apt-get update
apt-get install x2goserver x2goserver-xsession
</pre>

== Post installation ==

* setup hostname
<pre>
xemacs -nw /etc/hostname ### add .triumf.ca to the hostname if it is missing
</pre>

* install Konstantin's scripts
<pre>
mkdir ~root/git
cd ~root/git
git clone https://ladd00.triumf.ca/~olchansk/git/scripts.git
cd scripts
git pull
</pre>

* enable root login from ladd00
<pre>
ssh localhost
CTRL-C
/bin/cp ~root/git/scripts/etc/authorized_keys ~root/.ssh/
</pre>

* enable automatic updates 1
<pre>
apt-get install unattended-upgrades
xemacs -nw /etc/apt/apt.conf.d/50unattended-upgrades ### uncomment Allowed-Origins "-security" and "-updates", uncomment/add "::Mail "root"",
</pre>

* enable automatic updates 2

add this to: xemacs -nw /etc/apt/apt.conf.d/10periodic
<pre>
APT::Periodic::Update-Package-Lists "1";
APT::Periodic::Download-Upgradeable-Packages "1";
APT::Periodic::AutocleanInterval "7";
APT::Periodic::Unattended-Upgrade "1";
</pre>

= IPMI instructions =

IPMI is the board management hardware on Supermicro and other server motherboards. This includes hardware sensors - fan rotation speed, temperatures and power supply voltages.

* apt-get install ipmi-tool
* systemctl enable ipmievd

Run:
* ipmitool sel list ### event list
* ipmitool sel elist ### event list
* ipmitool sel clear ### clear event list (if it becomes full)
* ipmitool sensors ### report hardware sensors

= NIS instructions =

* apt-get -y install portmap nis ### will ask for NIS domain (LADD-NIS)
* dpkg-reconfigure nis ### reconfigure if already installed
* ypwhich -m
* edit /etc/default/nis
** set "NISSERVER=slave"
** set "YPSERVARGS=-p800"
** Ubuntu LTS 20.04, check that "YPBINDARGS=" is blank, remove "-no-dbus" if it is there
* edit /etc/yp.conf", comment-out everything, add "domain LADD-NIS server localhost"
* /usr/lib/yp/ypinit -s ladd00
* systemctl restart nis
* ypwhich -m
* ypcat -k passwd
* apt-get -y install autofs
* systemctl enable autofs
* vi /etc/nsswitch.conf ### add the automount line, modify the passwd, group and shadow lines to read this:
<pre>
# begin get data from nis
passwd: files nis
group: files nis
shadow: files nis
automount: files nis
# end get data from nis
</pre>
* systemctl restart autofs
* enable hourly update of NIS maps
<pre>
cd ~/git/scripts/etc
git pull
ln -s $PWD/ypxfr-cron-hourly /etc/cron.hourly
</pre>
* ### NOT NEEDED sudo vi /etc/idmapd.conf ### add line: "Domain = triumf.ca"
* reboot

= Fix systemd NIS breakage =

!!! THIS IS NOT NEEDED FOR UBUNTU LTS 20.04 !!!

there is a delay in ssh logins for normal users. "ssh -v" shows the delay is after "pledge...". this
fix removes the delay.

systemd developers think that we should not use NIS and made sure there are
problems if we do. To give them credit, they do offer a workaround. Read this:
https://github.com/poettering/systemd/commit/695fe4078f0df6564a1be1c4a6a9e8a640d23b67

<pre>
mkdir /etc/systemd/system/systemd-logind.service.d
echo -e "[Service]\nIPAddressDeny=\n" > /etc/systemd/system/systemd-logind.service.d/local.conf
systemctl daemon-reload
systemctl cat systemd-logind.service
</pre>

= Install sddm display manager (DO NOT DO THIS) =

* apt-get install sddm
* apt-get install sddm-theme-"*"
* create sddm.conf:
<pre>
root@daqubuntu:~# more /etc/sddm.conf
[Theme]
Current=maldives
root@daqubuntu:~#
</pre>
* dpkg-reconfigure lightdm (select sddm)
* reboot

= Configure lightdm display manager =

* enable it
<pre>
systemctl disable gdm
systemctl disable sddm
systemctl enable lightdm
</pre>

* make the MATE desktop as default
<pre>
cd ~root/git/scripts/
git pull
/bin/cp -v etc/lightdm_default_mate.conf /etc/lightdm/lightdm.conf.d/
</pre>

* enable login by NIS users
<pre>
/bin/cp -v etc/lightdm_enable_nis_login.conf /etc/lightdm/lightdm.conf.d/
</pre>

* restart lightdm
<pre>
systemctl restart lightdm
</pre>

= Install libpng12.so.0 =

Quartus 16 needs libpng12:

<pre>
wget http://mirrors.kernel.org/ubuntu/pool/main/libp/libpng/libpng12-0_1.2.54-1ubuntu1_amd64.deb
dpkg --install libpng12-0_1.2.54-1ubuntu1_amd64.deb
</pre>

= Install google-chrome =

Instructions from here:
https://www.ubuntuupdates.org/ppa/google_chrome?dist=stable

<pre>
wget -q -O - https://dl-ssl.google.com/linux/linux_signing_key.pub | apt-key add -
sh -c 'echo "deb [arch=amd64] http://dl.google.com/linux/chrome/deb/ stable main" >> /etc/apt/sources.list.d/google.list'
apt-get update
apt-get install google-chrome-stable
</pre>

= Disable unwanted services =

<pre>
systemctl disable mpd
systemctl disable snapd
systemctl disable ModemManager
</pre>

= Install apache httpd proxy for midas and elog =

This will configure the HTTPS/SSL certificate using "certbot" and "letsencrypt" and configure an HTTPS web server using apache2.

First, configure apache2:

* execute these commands:
<pre>
apt install apache2
cd /etc/apache2
</pre>
* create new file conf-available/ssl-daq14.conf # use actual hostname instead of daq14
<pre>
SSLSessionCache shmcb:/run/httpd/sslcache(512000)
SSLSessionCacheTimeout 300
SSLRandomSeed startup file:/dev/urandom 256
SSLRandomSeed connect builtin
SSLCryptoDevice builtin
</pre>
* create new file sites-available/daq14-ssl.conf # use actual hostname instead of daq14
<pre>
<IfModule mod_ssl.c>
<VirtualHost *:443>
ServerName daq14.triumf.ca
DocumentRoot /var/www/html
ErrorLog /var/log/apache2/daq14.log
SSLEngine on
# note SSLProtocol, SSLCipherSuite and some other settings are overwritten by /etc/letsencrypt/options-ssl-apache.conf
SSLProtocol all -SSLv2 -SSLv3 -TLSv1 -TLSv1.1
SSLCipherSuite HIGH:MEDIUM:!aNULL:!MD5:!SEED:!IDEA:!RC4
## use port specified in elogd.cfg
#ProxyPass /elog/ http://localhost:8082/ retry=1
## use mhttpd port
#ProxyPass / http://localhost:8080/ retry=1
Header always set Strict-Transport-Security "max-age=31536000; includeSubDomains"
<Location />
SSLRequireSSL
AuthType Basic
AuthName "DAQ password protected site"
Require valid-user
# create password file: touch /etc/apache2/htpasswd
# to add new user or change password: htpasswd /etc/apache2/htpasswd username
AuthUserFile /etc/apache2/htpasswd
</Location>
</VirtualHost>
</IfModule>
</pre>
* stop apache2 from listening on port 80: edit /etc/apache2/ports.conf, comment-out the line "Listen 80"
* stop apache2 from listening on port 80: edit /etc/apache2/ports.conf, comment-out the line "Listen 80"
* enable ssl module
* enable new configurations
* check that there are no syntax problems
<pre>
a2enmod ssl
a2enmod headers
a2enmod proxy
a2enmod proxy_http
a2enconf ssl-daq14
a2ensite daq14-ssl
apache2ctl configtest
</pre>
* enable and start apache2:
<pre>
systemctl enable apache2
systemctl restart apache2
systemctl status apache2
</pre>
* apache2 may fail to start, look in /var/log/apache2/error.log and /var/log/apache2/daq14.log
* if it says "Failed to configure ... certificate", proceed to the step for setting certbot.
* try to access https://daq14.triumf.ca
** you should see a complaint about self-signed certificate
** you should see a request for password (do not login yet)
** if you get "connection refused", HTTPS port 443 may need to be enabled in the local firewall, look at documentation for ufw.
Second, configure certbot:

(Note: as of 2018-01-18 certbot requires use of http port 80 to get the initial https certificate,
renewal can continue to use the https port 443)

(Note: as of 2019-01-?? certbot requires use of port 80 for renewals)

* check that port 80 is not used by anything:
* netstat -an | grep LISTEN | grep ^tcp | grep 80
* lsof -P | grep -i tcp | grep LISTEN | grep 80
* if lsof reports that apache2 is listening on port 80, follow the apache2 instructions above (remove "listen 80" from apache2.conf

* install certbot (if necessary open tcp port 80 in the firewall, see documentation for ufw):
<pre>
apt install certbot python3-certbot-apache
certbot certonly --standalone --installer apache
</pre>
* then answer questions:
* "activate HTTPS for daq14.triumf.ca" - say ok
* "enter email address" - enter your own email address
* "please read terms..." - read the terms and say "agree"
* it will take a few moments...
* "congratulations..." - say ok.
<pre>
certbot install --apache --cert-name daq14.triumf.ca
</pre>
* then answer questions:
* "choose redirect..." - say "1" (no redirect)
* look inside /etc/apache2/sites-enabled/ssl-daq14.conf to see that SSLCertificateFile & co point to certbot certificates in
/etc/letsencrypt/live/daq14.triumf.ca/
* to check current renewal and to update the certbot config file in /etc/letsencrypt/renewal, run this:
<pre>
certbot renew --standalone --installer apache --force-renewal
</pre>

NOTE: this certificate will expire in 3 months, automatic renewal should work with current version of certbot

Third, activate password protection:

* as shown in the config file above, create password file and initial user: (replace "midas" with specific username)
<pre>
touch /etc/apache2/htpasswd
htpasswd /etc/apache2/htpasswd midas
</pre>

* restart apache2
<pre>
systemctl restart apache2
systemctl status apache2
</pre>

From here:
* enable proxy for MIDAS mhttpd - uncomment redirect in the config file above
* enable proxy for ELOG - ditto
<pre>
a2enmod proxy
a2enmod proxy_http
apache2ctl configtest
systemctl restart apache2
</pre>

From here:
* enable proxy for MIDAS mhttpd - uncomment redirect in the config file above
* enable proxy for ELOG - ditto
<pre>
a2enmod proxy
a2enmod proxy_http
apache2ctl configtest
systemctl restart apache2
</pre>
* try accessing MIDAS https://daq14.triumf.ca/ (make sure mhttpd is running)
* if it's not working, check odb setting FIXME!
* try accessing ELog https://daq14.triumf.ca/elog/ (make sure elogd is running)
* if it's not working, check elogd.cfg file and make sure
<pre>
SSL = 0
</pre>

NOTE: if certbot fails with errors about 'module' object has no attribute 'pyopenssl',
try this: pip install requests==2.6.0

= Update packages =

* apt-get update # update package list
* apt-get dist-upgrade # install updated packages and update "kept back" packages
* apt-get autoremove # remove packages that apt thinks should be removed

= Finish installation =

* reboot
<pre>
shutdown -r now
</pre>

= Install ZFS =

!!! after installing all the packages, after updating the system, after updating the linux kernel, after rebooting into latest kernel !!!

<pre>
apt-get install zfsutils-linux
</pre>

Follow generic ZFS instructions: [[ZFS]]

= Update to new version of Ubuntu =

<pre>
vi /etc/update-manager/release-upgrades # set "Prompt=normal"
do-release-upgrade
</pre>

= Ubuntu package manager =

* apt-get install xxx # install package xxx
* apt-get update
* apt-get upgrade
* apt-get dist-upgrade
* apt-get autoremove # remove automatically installed packages required by a removed package
* apt-get remove xxx # remove package xxx
* apt-cache search . # list all available packages
* apt-cache show "." | grep ^Package # list al available packages
* apt-cache madison root-system # show all available versions of package root-system
* apt list # list all installed packages
* dpkg --listfiles libpng16-16 # list all files from this package
* apt list --installed # list all installed packages

= Ubuntu grub boot loader =

* edit /etc/default/grub
<pre>
GRUB_DEFAULT=0
#GRUB_TIMEOUT_STYLE=hidden
GRUB_TIMEOUT=10
GRUB_DISTRIBUTOR=`lsb_release -i -s 2> /dev/null || echo Debian`
GRUB_CMDLINE_LINUX_DEFAULT="vga=769 video=640x480"
GRUB_CMDLINE_LINUX=""
GRUB_GFXMODE=640x480
</pre>
* grub-mkconfig -o /boot/grub/grub.cfg
* update-initramfs -v -u
* grub-install /dev/sda

= Setup ubuntu as gateway to private network =

See also:
* https://daq.triumf.ca/DaqWiki/index.php/VME-CPU#Setup_the_boot_host_computer_.28el7.29
* http://www.triumf.info/wiki/DAQwiki/index.php/Dhcpd_on_eth1

== Steps to do ==

* assign network numbers to the private network, i.e. 192.168.1.x, 192.168.2.x, etc
* (on the gateway machine, each private network interface has to have a different network number)
* (each network interface can have multiple networks attached, via VLANs or via eth0:0, eth0:1 constructs)
* assign IP addresses on the private network, save them in /etc/hosts i.e. "hvps 192.168.1.10"
* (for simplicity, assign 192.168.1.1 to the gateway machine itself)
* (IP addresses 192.168.1.0 and 192.168.1.255 are "special", do not use them)
* setup DNS server (dnsmasq) to serve contents of /etc/hosts via DNS (otherwise, many programs will see inconsistent name to IP address mapping)
* setup DHCP server (ISC dhcpd or dnsmasq) to give out the IP addresses
* setup tftp, pxelinux and NFS for diskless booting
* setup time server (chronyd) to provide common time to all devices
* setup NAT so machines on private network can access the internet (to get OS updates, etc)
* setup NIS and NFS so machines on the private network can use common home directories
* setup rsync backup of machines on the private network

== setup hosts ==

* edit /etc/hosts
<pre>
192.168.1.101 dsfe01
... and so forth
</pre>

== setup dns and dhcp ==

* apt-get install dnsmasq
* edit /etc/dnsmasq.conf
<pre>
# /etc/dnsmasq.conf
# DNS settings
#port=0 # disable DNS function
port=53
domain-needed
bogus-priv
no-resolv
server=142.90.100.19
# DHCP settings
interface=enp1s0f0 # DHCP interface
#dhcp-range=192.168.1.50,192.168.1.150,infinite
dhcp-range=192.168.1.0,static
dhcp-boot=pxelinux.0
#dhcp-host=ac:1f:6b:9e:7f:4a,192.168.1.100,10m
dhcp-host=ac:1f:6b:9e:7f:4a,dsfe01,infinite
# TFTP settings
enable-tftp
tftp-root=/zssd/tftpboot
</pre>
* mkdir /zssd/tftpboot ### per tftp-root
* systemctl enable dnsmasq
* systemctl restart dnsmasq

== setup chronyd ==

* enable ntp server:
* configure and enable chronyd per instructions above
* emacs -nw /etc/chrony/chrony.conf
** add "allow 192.168.1.0/24" at the end
* systemctl restart chronyd
* chronyc tracking ### wait until time is synchronized (a few seconds)

== setup diskless network booting ==

=== setup pxelinux ===
<pre>
cd ~
wget https://www.kernel.org/pub/linux/utils/boot/syslinux/4.xx/syslinux-4.03.tar.bz2
tar xjvf syslinux-4.03.tar.bz2
cd syslinux-4.03
cp -pv ./core/pxelinux.0 ./com32/hdt/hdt.c32 ./memdisk/memdisk ./com32/menu/menu.c32 /zssd/tftpboot/
</pre>
* cd /zssd/tftpboot
<pre>
wget http://ladd00.triumf.ca/tftpboot/memtest86+-4.20.iso.zip
wget http://ladd00.triumf.ca/tftpboot/memtest86+-5.01.iso.gz
wget http://ladd00.triumf.ca/tftpboot/modules.alias
wget http://ladd00.triumf.ca/tftpboot/modules.pcimap
wget http://ladd00.triumf.ca/tftpboot/pci.ids
</pre>
* mkdir pxelinux.cfg
* emacs -nw pxelinux.cfg/default
<pre>
default menu.c32
prompt 0

menu title Welcome to the DSVSLICE PXE boot menu

timeout 50

label hdt
kernel hdt.c32

label memtest86+-5.01
kernel memdisk iso initrd=memtest86+-5.01.iso.gz

label memtest86+-4.20
kernel memdisk iso initrd=memtest86+-4.20.iso.zip

label vmlinuz-5.3.0-26-generic
menu default
kernel vmlinuz-5.3.0-26-generic
append initrd=initrd.img-5.3.0-26-generic boot=nfs root=/dev/nfs netboot=nfs nfsroot=192.168.1.1:/zssd/nfsroot/dsfe01 toram ip=dhcp panic=60 BOOTIF=enp1s0f0

#end
</pre>

=== setup linux kernel ===

* copy the kernel files
<pre>
cd /boot
rsync -av config* initrd* System.map* vmlinuz* /zssd/tftpboot/
</pre>
* cd /zssd/tftpboot
* chmod a+r *

=== setup nfs ===

* apt-get install nfs-kernel-server
* emacs -nw /etc/exports
<pre>
/zssd/nfsroot/dsfe01 dsfe01(rw,no_root_squash,async,no_subtree_check)
</pre>
* enable services
<pre>
systemctl enable nfs-server
systemctl enable nfs-mountd
systemctl enable nfs-idmapd
systemctl restart nfs-server
systemctl restart nfs-mountd
systemctl restart nfs-idmapd
</pre>
* after editing /etc/exports, run
<pre>
exportfs -av
</pre>

=== setup userland ===

* zfs create zssd/nfsroot
* zfs set dedup=verify zssd/nfsroot ### enable deduplication to save disk space because most linux images have mostly identical files
* clone ubuntu
<pre>
mkdir /zssd/nfsroot/dsfe01
cd /
rsync -avx . /zssd/nfsroot/dsfe01
</pre>
* edit config files:
* cd /zssd/nfsroot/dsfe01
* emacs -nw etc/hostname ### change to dsfe01
* emacs -nw etc/fstab ### add this
<pre>
192.168.1.1:/zssd/nfsroot/dsfe01 / nfs defaults,nolock 0 0
</pre>
* emacs -nw etc/chrony/chrony.conf
** comment-out all "pool" and "server" entries
** add entry "server 192.168.1.1 iburst"

After dsfe01 is booted:

* disable services:
<pre>
systemctl disable apache2
systemctl disable dnsmasq
systemctl disable zfs-import-cache
</pre>

To setup additional machines, clone dsfe01 instead of cloning the gateway machine

== setup shared home directory ==

=== on the gateway machine ===
* define netgroups
* emacs -nw /etc/netgroup
<pre>
dsfe (dsfe01,,) (dsfe02,,)
</pre>
* emacs -nw /etc/nsswitch.conf ### edit the netgroup line to read:
<pre>
netgroup: files
</pre>
* export the home directories:
* emacs -nw /etc/exports ### add this:
<pre>
/zssd/home1 @dsfe(rw,no_root_squash,async,no_subtree_check)
</pre>
* exportfs -rc

=== on the frontend machine ===

* mkdir /home
* emacs -nw /etc/fstab ### add this:
<pre>
192.168.1.1:/zssd/home1 /home nfs defaults 0 0
</pre>
* mount -a

== setup NAT ==

NAT allows machines on the private network to connect to the internet: https://en.wikipedia.org/wiki/Network_address_translation

* emacs -nw /etc/rc.local ### add this:
<pre>
# /etc/rc.local

/sbin/iptables -t nat -A POSTROUTING -o eno1 -j MASQUERADE
iptables -L -v

#/sbin/iptables -A FORWARD -i eth0 -o eth1 -m state --state RELATED,ESTABLISHED -j ACCEPT
#/sbin/iptables -A FORWARD -i eth1 -o eth0 -j ACCEPT
#iptables -L -v

iptables -L -v
sysctl -w net.ipv4.ip_forward=1
#sysctl -a | grep forward

/etc/firewall-rfc1918.sh

# end
</pre>

Documentation

2018-06-05T22:39:43Z

Midas:

Back to [[Alpha-g]]

General information about the Alpha-g Radial Time Projection Chamber (rTPC)

* [[Detector Overview]] : Design note
* [[Detector Simulations]] : Simulation and track recontruction
* [[Mechanical Design]] : Mechanical design of the rTPC
* [[Detector Data Acquistion]] : Computer and Back-end considerations
* [[Detector Calibration]] : Laser calibration scheme
* [[Detector Electronics]] : Front-end and digitizers
* [[Detector Services]] : Gas, Water cooling, Power distribution
* [[Barrel Scintillator]] : Cosmic veto detector
* [[Electronics Documentation]] : PWB

Detector Electronics

2017-11-19T22:07:19Z

Midas: /* Cathode Pad Circuit */

Back to [[Documentation]]

= Table of Figures =

[[#_Toc493676266|Figure 1 - Overall Data Acquisition scheme 7]]

[[#_Toc493676267|Figure 2 - Anode wire pre-amplification block diagram 8]]

[[#_Toc493676268|Figure 3 - Anode Wire Board (AWB), 16 channels pre-amplifier 9]]

[[#_Toc493676269|Figure 4 - 4 consecutive anode wire signals 9]]

[[#_Toc493676270|Figure 5 - Anode wire pre-amp gain map for half the chamber circumference 10]]

[[#_Toc493676271|Figure 6 - Alpha16 Data Acquisition Board 12]]

[[#_Toc493676272|Figure 7 - Grif16 Acquisition Module Block Diagram on which the Alpha-16 is based 12]]

[[#_Toc493676273|Figure 8 - Model of the new 32channels 12bit @ 65Msps FMC produced in 2016. 13]]

[[#_Toc493676274|Figure 9 - FMC Alpha-ADC32 Block Diagram 13]]

[[#_Toc493676275|Figure 10 - Cathode Pad Board readout for 288 channels at 62.5Msps, visible 4 AFTER chips, 3 copper bars running under the central board for power distribution 15]]

[[#_Toc493676276|Figure 11 – Thermal image of the FEAM with hot spot temperature: without cooling plate (78°C), with cooling plate (45°C), with cooling plate & water cooling (36°C) 16]]

[[#_Toc493676277|Figure 12 - Block diagram of AFTER amplifier 17]]

[[#_Toc493676278|Figure 13 - 4 x 72 cathode pad signals, overall time width corresponds to the drift time 17]]

[[#_Toc493676279|Figure 14 - Block diagram of one channel of SiPM amplifier 18]]

[[#_Toc493676280|Figure 15 - Trigger Card Adapter and Trigger Card 19]]

[[#_Toc493676281|Figure 16 Trigger Card to FEAM 19]]

[[#_Toc493676282|Figure 17 - Clock Distribution Module 20]]

[[#_Toc493676283|Figure 18 - IO Block Diagram 21]]

[[#_Toc493676284|Figure 19 - ALPHA-16 and CDM board in front with the Trigger/Clock distribution cables 22]]

[[#_Toc493676285|Figure 20 - Hit Detector for the Anode wire and scintillators in ALPHA-16 24]]

[[#_Toc493676286|Figure 21 - AFTER chip WFD on the PADWINGS 25]]

[[#_Toc493676287|Figure 22 - Trigger decision on ALPHA-T 26]]

[[#_Toc493676288|Figure 23 - ESPER Web Display. Test pulse recorded by the FEAM cards. Individual AFTER chip configuration is visible (gain change, delay). 27]]

= Introduction =

This design note describes the electronics chain and components for the readout of the ALPHA-g TPC and barrel scintillator bars.

= Scope =

The Detector Electronics is composed of 3 independent signal sources:

# Anode Wire signals path
# Cathode Pad signals path
# Barrel Scintillator signals path.

All 3 sources provide a similar function such as signal amplification and conditioning (shaping).

= Definitions and Abbreviations =

General acronyms or terms used for the ALPHA-g experiment

{|
! TPC
! Radial Time projection Chamber
|-
| Pads
| PCB surface seeing the induced anode wire signal
|-
| SiPM
| Si photomultipliers used to detect scintillation light
|-
| ADC
| Analog to digital converter
|-
| ASIC
| Application specific integrated circuit
|-
| SCA
| Switch Capacitor Array ( A type of Waveform Digitizer)
|-
| TDC
| Time to digital converter
|-
| BSM
| Barrel Scintillator Module (64 bars sub-assembly)
|-
| FEAM, Padwing
| Cathode strip acquisition board
|-
| CDM
| Clock Distribution Module
|-
| BSB
| Barrel Scintillator Board
|-
| WFD
| Waveform Digitizer
|}

Table 1 – ALPHA-g Abbreviations

= References and related Document =

* AFTER manual
* SensL SPM data sheet
* Edev-group.triumf.ca: contains the FW information on all the Alpha-g custom cards ([https://edev-group.triumf.ca/fw/exp/alphag/feam/rev0/wikis/feam-test-packet-format https://edev-group.triumf.ca/fw/exp/alphag])

* ''' 
'''

= Overall Detector Signal Path =

The Alpha-g detector provides 3 analog signals that are collected for the track reconstruction to help on the annihilation location in the trap.

* The anode wire signal providing the drift time of the electron through the detector for an angular position.
* The cathode pad signal, which are in-time correlated to the anode wire signal, providing the amplitude of these signals from which the longitudinal position (Z) can be extracted.
* The Barrel Scintillator bar signals provide the time and amplitude of the particle crossing the detector. The Barrel Scintillator is mainly to reject cosmic events. For that purpose, the timing resolution is important. Therefore the BSM analog signal is split early in the chain to record the amplitude and time separately.

The anode wires and the barrel scintillator bars are read out from both ends to provide a coarse Z-position as well. The Data acquisition is therefore made for reading 2x256 anode wire channels, 2x64 barrel scintillator bars and 18432 channels of cathode pads covering the outer detector cylinder.

[[File:image2daq.png|876x559px]]

Figure 1 - Overall Data Acquisition scheme

= Anode wire signal path =

The design for the anode wires pre-amplifier is based on work done for several other projects used at TRIUMF and other labs.

Each of the 256 anode wires is read-out from two ends. The signals are used to (1) determine phi-position of ionization track; (2) reconstruct its z-position by weighting signals from two wire ends; (3) generate trigger signal. The pre-amplifiers convert the induced current to voltage that is digitized and processed in the readout system. The main requirements for the amplifier circuit are:

# Input impedance must be low enough so detected charge is sensitive to position of event along wire;
# The shape of signal is optimized for sampling frequency (16 ns) and for fast trigger timing (few ns accuracy);
# Linearity range adjusted for ADC used;
# Gain is adjusted for gas amplification of 105
# Amplifier noise is low enough to detect single-electron cluster.

[[File:image3daq.png|576x204px]]

Figure 2 - Anode wire pre-amplification block diagram

Anode wires are HV-decoupled before connected to the amplifier, but additional (not HV) decoupling is needed at amplifier input to accommodate non-zero potential of the input stage. Protection of the amplifier input is using a standard bi-diode configuration. The first stage is a current-sensitive loop with input impedance defined by resistor Rin and trans-impedance (gain) by feedback resistor Rf. The second stage is 2-pole shaper with shaping time constant defined by components Rs and Cs. The last stage is a cable driver.

Overall gain, transfer function and input impedance of the circuit can be adjusted by changing passive components. This adjustment will be done by studying the TPC prototypes.

Amplifiers are deployed on 16-channel cards, 16 boards serve each end of TPC. They are powered by standard +5V and -5V linear supplies. Each card has a test input that is used to measure amplifiers response and to check for malfunction.

[[File:image4daq.jpg|273x283px]] [[File:image5daq.png|269x284px]]

Figure 3 - Anode Wire Board (AWB), 16 channels pre-amplifier

The AWB schematic allows for bipolar signal input. This has the advantage to reproduce the full anode wire signal development including the inverted induced pulse from neighbouring wires as seen Figure 4.

[[File:image6daq.jpg|512x358px]]

Figure 4 - 4 consecutive anode wire signals

The anode pre-amps have an individual test pulse input to provide a quick functional test. It can also be used for calibration purpose. Several tests have been done in this regard, but the overall chain gain is dependent on many variables (chamber geometry, environmental condition (Gas mixture, T, P), pre-amp (layout, components)). Another more common test pulse injection is available by pulsing all the field wires at once (at the boundary of the drift and multiplication region). This technique has the advantage to produce an induced signal on all the anode wires and cathode pads together at the “same” time. Figure 5 shows the gain variation by wire seen when pulsed through the field wire. 2 interesting features are visible:

a) An overall negative slope, indicated by the linear fit. This slope is explained by the pulse attenuation through the field wires distribution.

b) A clear increase in gain for the wires near the anode wire card boundaries, indicated by the cyan lines is not yet well understood. A further test is planned.

[[File:image7daq.png[497x389px]]

Figure 5 - Anode wire pre-amp gain map for half the chamber circumference

== Anode Wire Waveform digitizer (Alpha-16) ==

The output of the AWB is presented to the Alpha-16 waveform digitizer sampling the analog signal at 62.5Msps.

'''''Note:''''' At the time of this report, the WFD 62.5Msps is not yet available. We use the WFD at 100Msps to perform the tests. The firmware is similar to the 62.5Msps and the final test will be reproduced later.

This module provides 16 channels 14bit ADC @100Msps for 50Ohms single-ended analog signal for the barrel scintillator. It also supports a dedicated mezzanine card (FMC) handling 32 channels 12bit ADC @ 65Msps for single-ended 50Ohms analog signals for the Anode wires.

The Alpha-16 board outputs (16ch.@100Msps and 32ch.@62.5Msps) are collected on the main carrier FPGA for transmission through Ethernet to the backend computer.

The board carries multiple I/O connections required for the module configuration, communication, data transfer, signal inputs, see Figure 7.

* Front panel SFP Gbit Ethernet (copper/fiber)
* Front panel eSATA: clock and sync inputs
* Front panel dual LEMO: Diagnostic DAC outputs (250Msps)
* Front panel MCX connector for 16 x ADC inputs
* Rear entry P2 connector for 16 x ADC inputs
* A24/D16 VME interface to MAXV configuration CPLD
** VME configuration flash updates
** VME bridge to FPGA
* FMC custom module connections.
** Dual MiniSAS for Acquisition setup
** 10 x5Gibt Link
** JESD204B Clocks
** Supports 32 Channel ADC LVDS interface
* Amplifier input switches: Front panel MCX connector, Rear Transition Card SMA connector
* Amplifier Gain x1 and x4
* Switch selectable LEMO NIM Input/ DAC outputs
* Micro SD Flash
* DDR3 DRAM – 667MHz – 128M x 23'''(MT41J128M16HA-15E)'''
* FPGA - Arria V '''(5AGXFB3H4F35C4N)'''
* MAXV CPLD controller '''(5M2210ZF256C5N)''' for USB JTAG and VME access

[[File:image8daq.jpg|218x380px]]

Figure 6. Alpha16 Data Acquisition Board

[[File:image9daq.png|264x383px]]

Figure 7. Grif16 Acquisition Module Block Diagram on which the Alpha-16 is based

== FMC – Alpha ADC32 ==

<blockquote>The FMC – ALPHA ADC32 provides single-stage amplification of up to 32 single-ended 50<math>\Omega</math> analog signals, from the Anode Wire Board Pre-Amplifier, to drive two 16 channel 14bit differential, analog to digital converters sampling at 65MSPS. Further, each ADC will provide a 0.9V common mode offset voltage to be fed into the differential driver

A 16 channel 12 bit digital-to-analog (DAC) converter is used to individually apply an appropriate offset voltage to each of the differential amplifier pairs. The Offset voltages span <math>\pm</math>2.5Vat 1.22mV increments and will output 0V upon power cycle. The DAC is configurable via an SPI interface via the FMC connector.

ADC32 board has the capability to receive and transmit an LVDS clock signal through the eSATA connector which is fed to the FMC connector
</blockquote>
[[File:image10daq.png|318x307px]]

Figure 8 - Model of the new 32channels 12bit @ 65Msps FMC produced in 2016.

[[File:image11daq.png|420x285px]]

Figure 9 - FMC Alpha-ADC32 Block Diagram

<blockquote>''These notes are for the current revision of the Alpha ADC32, a new revision is currently being talked about''
</blockquote>
The board is composed of the following elements:

* 400 Pin FMC connector
** Provides SPI interface
** ADC Synchronization
** Support for 32 LVDS analog signals
** Supply voltage of fused +12V, Switched 3.3V and 1.2-3.3V adjustable
* 32 channel Analog inputs via Hirose connector '''[FX2-40S-1.27DS(71)] 
'''
* 1V analog reference voltage '''[LTC6655BHMS8-3#PBF]'''
** ±2ppm
* Differential ADC Driver '''[ADA4950'''-'''2YCPZ]'''
** ±0.2mV Offset
** 9.2nHz / √Hz Output voltage Noise at Gain=1
** Adjustable output common-mode voltage
** Hardware programmable gain of 1x, 2x and 3x
* Dual 16 channel 14bit Analog to Digital converter '''[AD9249BBCZ-65]'''
** 2Vp-p input range
** 65MSPS
** ±0.6LSB
** Input Clock of 10-520MHz
* 16 channel 12bit Digital to Analog converter '''[ADA4950-2YCPZ]'''
** Programmable offset voltage
** SPI configurable outputs
** Output range ±2.5V, 0V upon reset
** 1.22mV/LSB
* 1 x eSATA Clk-In / Clk-out to and from FMC connector

= Cathode pad signal path =

The 18432 cathode pads covering the inner surface of the outer wall of the detector are individually connected to a signal acquisition chain. This collected signals will provide the position of the electron avalanche at the anode wire. Combining them in charge, permit the reconstruction of the track passing through the longitudinal direction the detector. While the cathode pads cover a large area (2.7m2), the actual footprint per channel is limited (3.8mmx37.1mm). Therefore a high-density waveform digitizer chain has been chosen based on our previous experience with the T2K experiment, we opted for the AFTER Switched Capacitor Array (SCA) ASIC. The analog signal path is short as the pads themselves are on the backside the physical outer cylinder of the detector and the input signal connectors to the AFTER chips are on the opposite side of the outer cylinder.

A custom frontend board (FEAM) see Figure 10 handling 288 individual cathode pads has been designed. It is composed of 4 ASIC AFTER (72 channels) with associated waveform digitizer for the individual signal on 512 cells at 20Msps. In addition, an FPGA manages the board services and the data collection and transmission through a 1 gigabit/sec optical link to the Ethernet using the UDP protocol.

While the power consumption per channel at the ASIC level is low, the power requirement is in the order of 15W per board for a total at the detector level approaching 1000W. This required proper cooling to maintain a reliable operation of the electronics. Figure 11 shows the board temperature with and without cooling plate. Thermal images have been taken to confirm the temperature reduction of the main heat source (Clock cleaner, FPGA, ADC, AFTER in that order). We can guarantee a chip temperature below 60°C to keep the default chip MTBF.

[[File:image12daq.jpg|858x546px]]

Figure 10 - Cathode Pad Board readout for 288 channels at 62.5Msps, visible 4 AFTER chips, 3 copper bars running under the central board for power distribution

[[File:image13daq.png|249x185px]]
[[File:image14daq.png|247x186px]]
[[File:image15daq.jpg|248x186px]]

Figure 11 – Thermal image of the FEAM with hot spot temperature: without cooling plate (78°C), with cooling plate (45°C), with cooling plate & water cooling (36°C)

== Cathode Pad Circuit ==

The cathode pads are read-out by AFTER ASIC which diagram is presented in Figure 12. Each channel consists of a charge-sensitive preamplifier, pole-zero cancellation of preamplifier decay time, RC2 shaper and 512-cell SCA to store the waveform. Amplifier gain, pole-zero time constant and shaping time are programmable.

{|
|
[[File:image16daq.png[561x371px]]

Figure 12 - Block diagram of AFTER amplifier
| [[File:image17daq.png|415x399px]]
|}

The acquisition of the FEAM cards is operational and initial waveforms can be displayed as seen in Figure 13. This visualization is for monitoring the individual channels only. The data acquisition is using a different path for fast data collection. Figure 13 shows cathode signal examples collected by the FEAM card. The signal shape is consistent with avalanches occurring from a cosmic track going through the detector. The initial pulse corresponds to the early avalanches when the track crosses the amplification region (near the anode wire). The remaining pulses show the later electron avalanches reaching the same anode wire from the drift region due to the track angle. The complex pulse shape from the drift region reflects the convolution in this time base of the arrival of the electron to the amplification region and the induced pulse from the resulting electron avalanche.

= Barrel Scintillator signal path =

'''''Note''''': While the Barrel Scintillator is part of the Alpha-g detector for cosmic rejection purpose, this section is still under development. The initial concept and implementation are therefore not final. The volume allocated for it in the other hand well defined due to external to the detector constraints.

Light at both ends of each bar of the barrel scintillator is collected for a rough position detection of the crossing particle and timing information. To improve the detection information (maximize photon collection), 6 individual SiPM light detector (SensL) are mounted on both ends of the individual scintillator bar for a coverage of 50% of the bar. This assembly is in a light-tight and gas-tight enclosure. A cold gas flows through the box to lower the SiPM temperature operation in order to reduce the dark noise of the device. A shaper/amplifier board (BSB) will be mounted on the outside of the enclosure. Each of the board will acquire the signals of 4 adjacent scintillator bars. In total 64 scintillator bars are read out by 16 boards at each end. A block diagram of one bar readout is shown in Figure 14. The signal gathering of the 6 sensors is based on an analog sum.

[[File:image18daq.png|480x296px]]

Figure 14 - Block diagram of one channel of SiPM amplifier

The 6 pre-amplifier outputs are combined to provide the sum of 6 signals. This resulting signal is further amplified and shaped (if necessary) on a second stage post-amplifier/discriminator. This signal sent to the readout system through a cable driver. Two signals will be acquired from each bar: (1) Analog sum fed to a waveform digitizer with proper digital processing to determine event position and timing; (2) LVDS signal fed to a TDC for off-line precise timing measurement purposes. For the LVDS signal, the post-amplifier will have a controlled threshold voltage to the signal comparator.

The BSB will be powered by standard +5V and -5V linear supplies. Each board has a test input to allow individual board measure of the amplifier response, malfunction test and to provide the necessary services to the light sensors device (Voltage bias, temperature sensor, etc).

The output of the analog output of the BSB will be shaped for the 100Msps WFD and in parallel will issue a digital signal for timing information to a TDC.

= Trigger Distribution =

On the full-length detector, the FEAM boards will receive trigger and clock signals from the CDM through the Trigger Card Adapter. The adapter receives signals from the CDM via a 7 pin SATA connector. The signals can be re-driven by repeaters on the adapter and are sent down a chain of 7 Trigger Cards with the adapter forming the first link.

While there are other elegant means of distributing the common clock and trigger to all the electronics boards, this method is the most simple and robust.

[[File:image19daq.png|195x575px|Adapter]]

[[File:image20daq.png|573x43px|Trigger_Board]]

Figure 15 - Trigger Card Adapter and Trigger Card

[[File:image21daq.jpg|216x294px|20170914_101103_resized]]

Figure 16 Trigger Card to FEAM

A Samtec SFM-110 connects each card to a FEAM board and also provides through holes pins where another card can be overlapped and soldered. In this manner the chain of Trigger Distribution Cards is formed, providing a shared clock and trigger signal to a column of 8 FEAM boards.

= Clock Distribution Module =

[[File:image22daq.png|231x356px]]

Figure 17 - Clock Distribution Module

* 6x LEMO Connectors [2 Output, 4 Input]
* 6x Mini-SAS providing up to 24 channels of clock and synchronization breakout
* 1x Combination eSATA/USB connector
** eSATA provides CLK and SYNC
** USB provides USB to Serial communication 115200 BAUD
* 1x 10/100 Base-TX Ethernet
* Optional Atomic Clock module support, 10MHz and 1PPS '''[CSAC - SA.45s]'''
** Short term Stability <1E-11
** over 1000 seconds (100μHz / 1000s)
** Aging rate of <9E-10 per month '''('''9mHz/month)
* Onboard 10MHz Crystal Oscillator '''[FOX924B-10.000]'''
** ±2.5ppm
** ±1ppm per year
* JTAG ARM Support
* SmartFusion2 SoC '''[MS2-FG484]'''
* Ultra-low noise clock jitter cleaner 3:15 input to output support '''[LMK04821] '''
** Min/Max VCO Frequency 2750/3072MHz
** 0.111RMS Jitter
* TTL and NIM signal compatibility for external CLK and SYNC
* VME - 6U - 3Row
* Approximate Current Draw 1.837A at 5V

The Clock Distribution Module ('''CDM)''' has the capability to distribute two externally sourced clock and synchronization signals to six mini-SAS connections for total 24 signal signals. The external signals are provided through the eSATA and LEMO 1A/B Connectors. The module also has the capability to add an Atomic clock that outputs a 10Mhz signal and a 1 Pulse Per Second (PPS), as well as user-defined synchronization signal. Lastly, the module can be configured to output the external clock signals to the LEMO 2B connector or VME bus.

[[File:image23daq.png|509x348px]]

Figure 18 - IO Block Diagram

[[File:image24daq.png|299x412px]]

Figure 19 - ALPHA-16 and CDM board in front with the Trigger/Clock distribution cables

= Frontend Board Firmware =

The firmware (FW) refers to the embedded code running on the Field Programmable Gate Arrays (FPGAs) and microcontrollers (MCUs) located on the various modules within the experiment. These devices store, load, and run the programs required for operation of the different digital electronic components within the experiment.

Firmware code is essential to the operation of the detector as it provides the mechanism to configure the hardware for its particular purpose. Such as analog-to-digital conversion, data filtering, data trigger composition, transport of the data, and orchestration of all the different hardware modules to succeed in acquiring meaningful information across the overall system. Some of the firmware tasks are:

<ol style="list-style-type: upper-roman;">
<li>Low-level acquisition of the 3 different WFDigitizers (Anode wire, Cathode pad, Barrel Scintillator)</li>
<li>Links all the electronics boards to the DAQ system.</li>
<li>Collected in real-time information for trigger decision making.</li>
<li>Distribute synchronization signals and trigger to all the acquisition boards.</li>
<li>Provides to the user; configurable board and operation parameters settings.</li>
<li>Provides board monitoring and debugging tools.</li></ol>

Most of the FW code base has been based off of prior code developed for the currently running GRIFFIN experiment, with some exceptions, such as the Trigger Master Module which needed custom code specific to ALPHA-g, and the PADWING, which contained the AFTER SCA chip not present in GRIFFIN.



The firmware code is loaded onto the hardware board where an FPGA or MCU is present. Each firmware module has specific firmware capabilities, detailed as follows:

* Hit Detector firmware Module (ALPHA-16 carrier board)
** Anode Wire and Barrel Scint. signal waveform digitizers acquisition
** Local data filtering for Trigger purpose
** Transmission of summary data to Trigger Module for trigger decision
** Data compression/filtering and retention for transmission to backend on Trigger reception
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Pad Acquisition firmware Module (PADWING board)
** Cathode pad signal waveform digitizers acquisition
** Data compression/filtering and retention for transmission to backend on Trigger reception
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Master Trigger firmware Module (ALPHA-T board)
** Summary data reception of the multiple GRIF-16 boards
** Trigger decision algorithm
** Packaging of Trigger decision information and transmission to the backend.
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Clock and Trigger Distribution firmware Module (CDM board)
** Monitoring of hardware functions (U,I,T,Clock Frequency)
** Configuration of hardware mechanism for clock and trigger distribution
** Update of firmware code mechanism

== '''Hit Detector Module (ALPHA-16)''' ==

The Hit Detector firmware module handles the acquisition of the analog input signals from the anode wires and scintillators, the digital conversion of that data, and then the transfer of that data to both the DAQ and the Trigger Master. The first implementation of the hit detection is based on hit multiplicity. Later on, a more sophisticated algorithm will be implemented to determine in real time the timing and charge collected for each channel. This information will be transferred to the Trigger Master for more efficient trigger filtering.

The ADC data is acquired from both the FMC ADC32 ADCs and the onboard 16ch 14-bit ADCs using the FPGAs hardware SERDES modules. These modules de-serialize the data stream from the ADCs into a format suitable for internal analysis for hit detection, and for transfer to the MIDAS DAQ.

Once one or more hits are detected, the ALPHA-16 transmits the hit count to the ALPHA-T for a hit multiplicity test, and then waits for a trigger response to decide to discard or transmit the waveform data associated with the detected hit to the DAQ.

Currently, when a trigger is fired by the Trigger Decision module, all channels transmit their captured waveforms to the DAQ. In the future, only channels that have detected a hit will send waveforms on a trigger.

System monitoring and configuration of the Hit Detector module is handled by ESPER running on a NIOS-II soft-core processor instantiated within the FPGA. The OS used is Micrium µC/OS-II, a small real-time OS licensed by Altera for use with their NIOS-II processor. ESPER performs the remote upgrading of the Hit Detector, viewing of the captured waveforms, and diagnostic reading and writing of all firmware settings and counters via a simple JSON-based interface, or an HTML based webpage.

[[File:image25daq.png|517x318px]]

Figure 20 - Hit Detector for the Anode wire and scintillators in ALPHA-16

== '''Pad Acquisition Module (FEAM)''' ==

The pad acquisition firmware module handles the collection of the PAD analog signals captured by the four AFTER ASICs on the module. Capture occurs upon receiving a trigger signal from the Trigger Decision module. Once captured, the AFTER data is transmitted to the MIDAS DAQ over ethernet. No pad information is provided back to the Trigger Decision module.

Each of the AFTER ASICs transmits its captured analog data to a 12-bit ADC which in turn converts the analog signal into digital data and transmits that to the FPGA. The FPGA uses its internal SERDES hardware to de-serialize this data and process it. Once captured, channels that do not contain data of interest are suppressed, and the data is packaged up and sent out over UDP to the MIDAS DAQ.

In the event that the SFP module that provides ethernet connectivity fails, each PAD acquisition module is connected to one other PAD acquisition module via a secondary gigabit link. While currently unused, this link will be used in the future to support a backup link to the DAQ, in the event of a failure of the primary gigabit link.

System monitoring and configuration of the PAD acquisition module is handled by ESPER running on a NIOS-II soft-core processor instantiated within the FPGA. The OS used is Micrium µC/OS-II, a small real-time OS licensed by Altera for use with their NIOS-II processor. ESPER performs the remote upgrading of the Hit Detector, viewing of the captured waveforms, and diagnostic reading and writing of all firmware settings and counters via a simple JSON-based interface, or an HTML based webpage.

[[File:image26daq.png|490x299px]]

Figure 21 - AFTER chip WFD on the PADWINGS

== '''Trigger Master module (ALPHA-T)''' ==

The Trigger Master firmware module is to collect information from the anode wires and scintillators to make a real-time decision if the current physics event is to be recorded. That decision is fed to all the readout boards to trigger the storage of this particular event.

Initial trigger decision will be based on hit multiplicity of each of the ALPHA-16 boards. As the ALPHA-16 is acquiring the anode wire and the barrel scintillator signals, both of these 2 pieces of equipment will contribute to the trigger decision. Dedicated link from each of the ALPHA-16 (hit detector) to the Trigger module will be gathering the overall information for a final decision. Hardware trigger signal is then sent from the ALPHA-T to the CDM for distribution to all the acquisition modules to initiate the transmission of their data to the backend computer through UDP. The trigger board will compose a summary of the trigger information which will also be transferred to the backend.

The Trigger Master module contains two Mini-SAS FMCs, and one ‘communication’ FMC, that consists of a SATA, an SFP, and a Mini-SAS connector. This configuration of FMCs allows for up to twenty (20) 1G/2.5G/5G links via the Mini-SAS, in addition to a 1 Gbit/sec Ethernet connection via the SFP, and clock+trigger over the SATA.

[[File:image27daq.png|576x304px]]

Figure 22 - Trigger decision on ALPHA-T

== System Monitoring and debugging capability ==

The system monitoring is based on the ESPER protocol provided by the Electronics Development group at TRIUMF. Featuring a built-in web server, with real-time digitizer display, remote upgrade, and JSON-accessible parameters. ESPER allows for real-time diagnostics and testing to be performed on the various electronic modules using either JSON-based requests or a built-in webpage.

[[File:image28daq.png|800x400px]]

Figure 23 - ESPER Web Display. Test pulse recorded by the FEAM cards. Individual AFTER chip configuration is visible (gain change, delay).

= Safety and Hazard considerations =

There are no safety or hazard issues in FE system. All amplifiers are low-voltage and low-power circuits built with standard electronics components.

Detector Electronics

2017-11-19T22:06:05Z

Midas: /* Cathode pad signal path */

Back to [[Documentation]]

= Table of Figures =

[[#_Toc493676266|Figure 1 - Overall Data Acquisition scheme 7]]

[[#_Toc493676267|Figure 2 - Anode wire pre-amplification block diagram 8]]

[[#_Toc493676268|Figure 3 - Anode Wire Board (AWB), 16 channels pre-amplifier 9]]

[[#_Toc493676269|Figure 4 - 4 consecutive anode wire signals 9]]

[[#_Toc493676270|Figure 5 - Anode wire pre-amp gain map for half the chamber circumference 10]]

[[#_Toc493676271|Figure 6 - Alpha16 Data Acquisition Board 12]]

[[#_Toc493676272|Figure 7 - Grif16 Acquisition Module Block Diagram on which the Alpha-16 is based 12]]

[[#_Toc493676273|Figure 8 - Model of the new 32channels 12bit @ 65Msps FMC produced in 2016. 13]]

[[#_Toc493676274|Figure 9 - FMC Alpha-ADC32 Block Diagram 13]]

[[#_Toc493676275|Figure 10 - Cathode Pad Board readout for 288 channels at 62.5Msps, visible 4 AFTER chips, 3 copper bars running under the central board for power distribution 15]]

[[#_Toc493676276|Figure 11 – Thermal image of the FEAM with hot spot temperature: without cooling plate (78°C), with cooling plate (45°C), with cooling plate & water cooling (36°C) 16]]

[[#_Toc493676277|Figure 12 - Block diagram of AFTER amplifier 17]]

[[#_Toc493676278|Figure 13 - 4 x 72 cathode pad signals, overall time width corresponds to the drift time 17]]

[[#_Toc493676279|Figure 14 - Block diagram of one channel of SiPM amplifier 18]]

[[#_Toc493676280|Figure 15 - Trigger Card Adapter and Trigger Card 19]]

[[#_Toc493676281|Figure 16 Trigger Card to FEAM 19]]

[[#_Toc493676282|Figure 17 - Clock Distribution Module 20]]

[[#_Toc493676283|Figure 18 - IO Block Diagram 21]]

[[#_Toc493676284|Figure 19 - ALPHA-16 and CDM board in front with the Trigger/Clock distribution cables 22]]

[[#_Toc493676285|Figure 20 - Hit Detector for the Anode wire and scintillators in ALPHA-16 24]]

[[#_Toc493676286|Figure 21 - AFTER chip WFD on the PADWINGS 25]]

[[#_Toc493676287|Figure 22 - Trigger decision on ALPHA-T 26]]

[[#_Toc493676288|Figure 23 - ESPER Web Display. Test pulse recorded by the FEAM cards. Individual AFTER chip configuration is visible (gain change, delay). 27]]

= Introduction =

This design note describes the electronics chain and components for the readout of the ALPHA-g TPC and barrel scintillator bars.

= Scope =

The Detector Electronics is composed of 3 independent signal sources:

# Anode Wire signals path
# Cathode Pad signals path
# Barrel Scintillator signals path.

All 3 sources provide a similar function such as signal amplification and conditioning (shaping).

= Definitions and Abbreviations =

General acronyms or terms used for the ALPHA-g experiment

{|
! TPC
! Radial Time projection Chamber
|-
| Pads
| PCB surface seeing the induced anode wire signal
|-
| SiPM
| Si photomultipliers used to detect scintillation light
|-
| ADC
| Analog to digital converter
|-
| ASIC
| Application specific integrated circuit
|-
| SCA
| Switch Capacitor Array ( A type of Waveform Digitizer)
|-
| TDC
| Time to digital converter
|-
| BSM
| Barrel Scintillator Module (64 bars sub-assembly)
|-
| FEAM, Padwing
| Cathode strip acquisition board
|-
| CDM
| Clock Distribution Module
|-
| BSB
| Barrel Scintillator Board
|-
| WFD
| Waveform Digitizer
|}

Table 1 – ALPHA-g Abbreviations

= References and related Document =

* AFTER manual
* SensL SPM data sheet
* Edev-group.triumf.ca: contains the FW information on all the Alpha-g custom cards ([https://edev-group.triumf.ca/fw/exp/alphag/feam/rev0/wikis/feam-test-packet-format https://edev-group.triumf.ca/fw/exp/alphag])

* ''' 
'''

= Overall Detector Signal Path =

The Alpha-g detector provides 3 analog signals that are collected for the track reconstruction to help on the annihilation location in the trap.

* The anode wire signal providing the drift time of the electron through the detector for an angular position.
* The cathode pad signal, which are in-time correlated to the anode wire signal, providing the amplitude of these signals from which the longitudinal position (Z) can be extracted.
* The Barrel Scintillator bar signals provide the time and amplitude of the particle crossing the detector. The Barrel Scintillator is mainly to reject cosmic events. For that purpose, the timing resolution is important. Therefore the BSM analog signal is split early in the chain to record the amplitude and time separately.

The anode wires and the barrel scintillator bars are read out from both ends to provide a coarse Z-position as well. The Data acquisition is therefore made for reading 2x256 anode wire channels, 2x64 barrel scintillator bars and 18432 channels of cathode pads covering the outer detector cylinder.

[[File:image2daq.png|876x559px]]

Figure 1 - Overall Data Acquisition scheme

= Anode wire signal path =

The design for the anode wires pre-amplifier is based on work done for several other projects used at TRIUMF and other labs.

Each of the 256 anode wires is read-out from two ends. The signals are used to (1) determine phi-position of ionization track; (2) reconstruct its z-position by weighting signals from two wire ends; (3) generate trigger signal. The pre-amplifiers convert the induced current to voltage that is digitized and processed in the readout system. The main requirements for the amplifier circuit are:

# Input impedance must be low enough so detected charge is sensitive to position of event along wire;
# The shape of signal is optimized for sampling frequency (16 ns) and for fast trigger timing (few ns accuracy);
# Linearity range adjusted for ADC used;
# Gain is adjusted for gas amplification of 105
# Amplifier noise is low enough to detect single-electron cluster.

[[File:image3daq.png|576x204px]]

Figure 2 - Anode wire pre-amplification block diagram

Anode wires are HV-decoupled before connected to the amplifier, but additional (not HV) decoupling is needed at amplifier input to accommodate non-zero potential of the input stage. Protection of the amplifier input is using a standard bi-diode configuration. The first stage is a current-sensitive loop with input impedance defined by resistor Rin and trans-impedance (gain) by feedback resistor Rf. The second stage is 2-pole shaper with shaping time constant defined by components Rs and Cs. The last stage is a cable driver.

Overall gain, transfer function and input impedance of the circuit can be adjusted by changing passive components. This adjustment will be done by studying the TPC prototypes.

Amplifiers are deployed on 16-channel cards, 16 boards serve each end of TPC. They are powered by standard +5V and -5V linear supplies. Each card has a test input that is used to measure amplifiers response and to check for malfunction.

[[File:image4daq.jpg|273x283px]] [[File:image5daq.png|269x284px]]

Figure 3 - Anode Wire Board (AWB), 16 channels pre-amplifier

The AWB schematic allows for bipolar signal input. This has the advantage to reproduce the full anode wire signal development including the inverted induced pulse from neighbouring wires as seen Figure 4.

[[File:image6daq.jpg|512x358px]]

Figure 4 - 4 consecutive anode wire signals

The anode pre-amps have an individual test pulse input to provide a quick functional test. It can also be used for calibration purpose. Several tests have been done in this regard, but the overall chain gain is dependent on many variables (chamber geometry, environmental condition (Gas mixture, T, P), pre-amp (layout, components)). Another more common test pulse injection is available by pulsing all the field wires at once (at the boundary of the drift and multiplication region). This technique has the advantage to produce an induced signal on all the anode wires and cathode pads together at the “same” time. Figure 5 shows the gain variation by wire seen when pulsed through the field wire. 2 interesting features are visible:

a) An overall negative slope, indicated by the linear fit. This slope is explained by the pulse attenuation through the field wires distribution.

b) A clear increase in gain for the wires near the anode wire card boundaries, indicated by the cyan lines is not yet well understood. A further test is planned.

[[File:image7daq.png[497x389px]]

Figure 5 - Anode wire pre-amp gain map for half the chamber circumference

== Anode Wire Waveform digitizer (Alpha-16) ==

The output of the AWB is presented to the Alpha-16 waveform digitizer sampling the analog signal at 62.5Msps.

'''''Note:''''' At the time of this report, the WFD 62.5Msps is not yet available. We use the WFD at 100Msps to perform the tests. The firmware is similar to the 62.5Msps and the final test will be reproduced later.

This module provides 16 channels 14bit ADC @100Msps for 50Ohms single-ended analog signal for the barrel scintillator. It also supports a dedicated mezzanine card (FMC) handling 32 channels 12bit ADC @ 65Msps for single-ended 50Ohms analog signals for the Anode wires.

The Alpha-16 board outputs (16ch.@100Msps and 32ch.@62.5Msps) are collected on the main carrier FPGA for transmission through Ethernet to the backend computer.

The board carries multiple I/O connections required for the module configuration, communication, data transfer, signal inputs, see Figure 7.

* Front panel SFP Gbit Ethernet (copper/fiber)
* Front panel eSATA: clock and sync inputs
* Front panel dual LEMO: Diagnostic DAC outputs (250Msps)
* Front panel MCX connector for 16 x ADC inputs
* Rear entry P2 connector for 16 x ADC inputs
* A24/D16 VME interface to MAXV configuration CPLD
** VME configuration flash updates
** VME bridge to FPGA
* FMC custom module connections.
** Dual MiniSAS for Acquisition setup
** 10 x5Gibt Link
** JESD204B Clocks
** Supports 32 Channel ADC LVDS interface
* Amplifier input switches: Front panel MCX connector, Rear Transition Card SMA connector
* Amplifier Gain x1 and x4
* Switch selectable LEMO NIM Input/ DAC outputs
* Micro SD Flash
* DDR3 DRAM – 667MHz – 128M x 23'''(MT41J128M16HA-15E)'''
* FPGA - Arria V '''(5AGXFB3H4F35C4N)'''
* MAXV CPLD controller '''(5M2210ZF256C5N)''' for USB JTAG and VME access

[[File:image8daq.jpg|218x380px]]

Figure 6. Alpha16 Data Acquisition Board

[[File:image9daq.png|264x383px]]

Figure 7. Grif16 Acquisition Module Block Diagram on which the Alpha-16 is based

== FMC – Alpha ADC32 ==

<blockquote>The FMC – ALPHA ADC32 provides single-stage amplification of up to 32 single-ended 50<math>\Omega</math> analog signals, from the Anode Wire Board Pre-Amplifier, to drive two 16 channel 14bit differential, analog to digital converters sampling at 65MSPS. Further, each ADC will provide a 0.9V common mode offset voltage to be fed into the differential driver

A 16 channel 12 bit digital-to-analog (DAC) converter is used to individually apply an appropriate offset voltage to each of the differential amplifier pairs. The Offset voltages span <math>\pm</math>2.5Vat 1.22mV increments and will output 0V upon power cycle. The DAC is configurable via an SPI interface via the FMC connector.

ADC32 board has the capability to receive and transmit an LVDS clock signal through the eSATA connector which is fed to the FMC connector
</blockquote>
[[File:image10daq.png|318x307px]]

Figure 8 - Model of the new 32channels 12bit @ 65Msps FMC produced in 2016.

[[File:image11daq.png|420x285px]]

Figure 9 - FMC Alpha-ADC32 Block Diagram

<blockquote>''These notes are for the current revision of the Alpha ADC32, a new revision is currently being talked about''
</blockquote>
The board is composed of the following elements:

* 400 Pin FMC connector
** Provides SPI interface
** ADC Synchronization
** Support for 32 LVDS analog signals
** Supply voltage of fused +12V, Switched 3.3V and 1.2-3.3V adjustable
* 32 channel Analog inputs via Hirose connector '''[FX2-40S-1.27DS(71)] 
'''
* 1V analog reference voltage '''[LTC6655BHMS8-3#PBF]'''
** ±2ppm
* Differential ADC Driver '''[ADA4950'''-'''2YCPZ]'''
** ±0.2mV Offset
** 9.2nHz / √Hz Output voltage Noise at Gain=1
** Adjustable output common-mode voltage
** Hardware programmable gain of 1x, 2x and 3x
* Dual 16 channel 14bit Analog to Digital converter '''[AD9249BBCZ-65]'''
** 2Vp-p input range
** 65MSPS
** ±0.6LSB
** Input Clock of 10-520MHz
* 16 channel 12bit Digital to Analog converter '''[ADA4950-2YCPZ]'''
** Programmable offset voltage
** SPI configurable outputs
** Output range ±2.5V, 0V upon reset
** 1.22mV/LSB
* 1 x eSATA Clk-In / Clk-out to and from FMC connector

= Cathode pad signal path =

The 18432 cathode pads covering the inner surface of the outer wall of the detector are individually connected to a signal acquisition chain. This collected signals will provide the position of the electron avalanche at the anode wire. Combining them in charge, permit the reconstruction of the track passing through the longitudinal direction the detector. While the cathode pads cover a large area (2.7m2), the actual footprint per channel is limited (3.8mmx37.1mm). Therefore a high-density waveform digitizer chain has been chosen based on our previous experience with the T2K experiment, we opted for the AFTER Switched Capacitor Array (SCA) ASIC. The analog signal path is short as the pads themselves are on the backside the physical outer cylinder of the detector and the input signal connectors to the AFTER chips are on the opposite side of the outer cylinder.

A custom frontend board (FEAM) see Figure 10 handling 288 individual cathode pads has been designed. It is composed of 4 ASIC AFTER (72 channels) with associated waveform digitizer for the individual signal on 512 cells at 20Msps. In addition, an FPGA manages the board services and the data collection and transmission through a 1 gigabit/sec optical link to the Ethernet using the UDP protocol.

While the power consumption per channel at the ASIC level is low, the power requirement is in the order of 15W per board for a total at the detector level approaching 1000W. This required proper cooling to maintain a reliable operation of the electronics. Figure 11 shows the board temperature with and without cooling plate. Thermal images have been taken to confirm the temperature reduction of the main heat source (Clock cleaner, FPGA, ADC, AFTER in that order). We can guarantee a chip temperature below 60°C to keep the default chip MTBF.

[[File:image12daq.jpg|858x546px]]

Figure 10 - Cathode Pad Board readout for 288 channels at 62.5Msps, visible 4 AFTER chips, 3 copper bars running under the central board for power distribution

[[File:image13daq.png|249x185px]]
[[File:image14daq.png|247x186px]]
[[File:image15daq.jpg|248x186px]]

Figure 11 – Thermal image of the FEAM with hot spot temperature: without cooling plate (78°C), with cooling plate (45°C), with cooling plate & water cooling (36°C)

== Cathode Pad Circuit ==

The cathode pads are read-out by AFTER ASIC which diagram is presented in Figure 12. Each channel consists of a charge-sensitive preamplifier, pole-zero cancellation of preamplifier decay time, RC2 shaper and 512-cell SCA to store the waveform. Amplifier gain, pole-zero time constant and shaping time are programmable.

{|
|
[[File:image16daq.png|361x171px]]

Figure 12 - Block diagram of AFTER amplifier
| [[File:image17daq.png|215x199px]]
|}

The acquisition of the FEAM cards is operational and initial waveforms can be displayed as seen in Figure 13. This visualization is for monitoring the individual channels only. The data acquisition is using a different path for fast data collection. Figure 13 shows cathode signal examples collected by the FEAM card. The signal shape is consistent with avalanches occurring from a cosmic track going through the detector. The initial pulse corresponds to the early avalanches when the track crosses the amplification region (near the anode wire). The remaining pulses show the later electron avalanches reaching the same anode wire from the drift region due to the track angle. The complex pulse shape from the drift region reflects the convolution in this time base of the arrival of the electron to the amplification region and the induced pulse from the resulting electron avalanche.

= Barrel Scintillator signal path =

'''''Note''''': While the Barrel Scintillator is part of the Alpha-g detector for cosmic rejection purpose, this section is still under development. The initial concept and implementation are therefore not final. The volume allocated for it in the other hand well defined due to external to the detector constraints.

Light at both ends of each bar of the barrel scintillator is collected for a rough position detection of the crossing particle and timing information. To improve the detection information (maximize photon collection), 6 individual SiPM light detector (SensL) are mounted on both ends of the individual scintillator bar for a coverage of 50% of the bar. This assembly is in a light-tight and gas-tight enclosure. A cold gas flows through the box to lower the SiPM temperature operation in order to reduce the dark noise of the device. A shaper/amplifier board (BSB) will be mounted on the outside of the enclosure. Each of the board will acquire the signals of 4 adjacent scintillator bars. In total 64 scintillator bars are read out by 16 boards at each end. A block diagram of one bar readout is shown in Figure 14. The signal gathering of the 6 sensors is based on an analog sum.

[[File:image18daq.png|480x296px]]

Figure 14 - Block diagram of one channel of SiPM amplifier

The 6 pre-amplifier outputs are combined to provide the sum of 6 signals. This resulting signal is further amplified and shaped (if necessary) on a second stage post-amplifier/discriminator. This signal sent to the readout system through a cable driver. Two signals will be acquired from each bar: (1) Analog sum fed to a waveform digitizer with proper digital processing to determine event position and timing; (2) LVDS signal fed to a TDC for off-line precise timing measurement purposes. For the LVDS signal, the post-amplifier will have a controlled threshold voltage to the signal comparator.

The BSB will be powered by standard +5V and -5V linear supplies. Each board has a test input to allow individual board measure of the amplifier response, malfunction test and to provide the necessary services to the light sensors device (Voltage bias, temperature sensor, etc).

The output of the analog output of the BSB will be shaped for the 100Msps WFD and in parallel will issue a digital signal for timing information to a TDC.

= Trigger Distribution =

On the full-length detector, the FEAM boards will receive trigger and clock signals from the CDM through the Trigger Card Adapter. The adapter receives signals from the CDM via a 7 pin SATA connector. The signals can be re-driven by repeaters on the adapter and are sent down a chain of 7 Trigger Cards with the adapter forming the first link.

While there are other elegant means of distributing the common clock and trigger to all the electronics boards, this method is the most simple and robust.

[[File:image19daq.png|195x575px|Adapter]]

[[File:image20daq.png|573x43px|Trigger_Board]]

Figure 15 - Trigger Card Adapter and Trigger Card

[[File:image21daq.jpg|216x294px|20170914_101103_resized]]

Figure 16 Trigger Card to FEAM

A Samtec SFM-110 connects each card to a FEAM board and also provides through holes pins where another card can be overlapped and soldered. In this manner the chain of Trigger Distribution Cards is formed, providing a shared clock and trigger signal to a column of 8 FEAM boards.

= Clock Distribution Module =

[[File:image22daq.png|231x356px]]

Figure 17 - Clock Distribution Module

* 6x LEMO Connectors [2 Output, 4 Input]
* 6x Mini-SAS providing up to 24 channels of clock and synchronization breakout
* 1x Combination eSATA/USB connector
** eSATA provides CLK and SYNC
** USB provides USB to Serial communication 115200 BAUD
* 1x 10/100 Base-TX Ethernet
* Optional Atomic Clock module support, 10MHz and 1PPS '''[CSAC - SA.45s]'''
** Short term Stability <1E-11
** over 1000 seconds (100μHz / 1000s)
** Aging rate of <9E-10 per month '''('''9mHz/month)
* Onboard 10MHz Crystal Oscillator '''[FOX924B-10.000]'''
** ±2.5ppm
** ±1ppm per year
* JTAG ARM Support
* SmartFusion2 SoC '''[MS2-FG484]'''
* Ultra-low noise clock jitter cleaner 3:15 input to output support '''[LMK04821] '''
** Min/Max VCO Frequency 2750/3072MHz
** 0.111RMS Jitter
* TTL and NIM signal compatibility for external CLK and SYNC
* VME - 6U - 3Row
* Approximate Current Draw 1.837A at 5V

The Clock Distribution Module ('''CDM)''' has the capability to distribute two externally sourced clock and synchronization signals to six mini-SAS connections for total 24 signal signals. The external signals are provided through the eSATA and LEMO 1A/B Connectors. The module also has the capability to add an Atomic clock that outputs a 10Mhz signal and a 1 Pulse Per Second (PPS), as well as user-defined synchronization signal. Lastly, the module can be configured to output the external clock signals to the LEMO 2B connector or VME bus.

[[File:image23daq.png|509x348px]]

Figure 18 - IO Block Diagram

[[File:image24daq.png|299x412px]]

Figure 19 - ALPHA-16 and CDM board in front with the Trigger/Clock distribution cables

= Frontend Board Firmware =

The firmware (FW) refers to the embedded code running on the Field Programmable Gate Arrays (FPGAs) and microcontrollers (MCUs) located on the various modules within the experiment. These devices store, load, and run the programs required for operation of the different digital electronic components within the experiment.

Firmware code is essential to the operation of the detector as it provides the mechanism to configure the hardware for its particular purpose. Such as analog-to-digital conversion, data filtering, data trigger composition, transport of the data, and orchestration of all the different hardware modules to succeed in acquiring meaningful information across the overall system. Some of the firmware tasks are:

<ol style="list-style-type: upper-roman;">
<li>Low-level acquisition of the 3 different WFDigitizers (Anode wire, Cathode pad, Barrel Scintillator)</li>
<li>Links all the electronics boards to the DAQ system.</li>
<li>Collected in real-time information for trigger decision making.</li>
<li>Distribute synchronization signals and trigger to all the acquisition boards.</li>
<li>Provides to the user; configurable board and operation parameters settings.</li>
<li>Provides board monitoring and debugging tools.</li></ol>

Most of the FW code base has been based off of prior code developed for the currently running GRIFFIN experiment, with some exceptions, such as the Trigger Master Module which needed custom code specific to ALPHA-g, and the PADWING, which contained the AFTER SCA chip not present in GRIFFIN.



The firmware code is loaded onto the hardware board where an FPGA or MCU is present. Each firmware module has specific firmware capabilities, detailed as follows:

* Hit Detector firmware Module (ALPHA-16 carrier board)
** Anode Wire and Barrel Scint. signal waveform digitizers acquisition
** Local data filtering for Trigger purpose
** Transmission of summary data to Trigger Module for trigger decision
** Data compression/filtering and retention for transmission to backend on Trigger reception
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Pad Acquisition firmware Module (PADWING board)
** Cathode pad signal waveform digitizers acquisition
** Data compression/filtering and retention for transmission to backend on Trigger reception
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Master Trigger firmware Module (ALPHA-T board)
** Summary data reception of the multiple GRIF-16 boards
** Trigger decision algorithm
** Packaging of Trigger decision information and transmission to the backend.
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Clock and Trigger Distribution firmware Module (CDM board)
** Monitoring of hardware functions (U,I,T,Clock Frequency)
** Configuration of hardware mechanism for clock and trigger distribution
** Update of firmware code mechanism

== '''Hit Detector Module (ALPHA-16)''' ==

The Hit Detector firmware module handles the acquisition of the analog input signals from the anode wires and scintillators, the digital conversion of that data, and then the transfer of that data to both the DAQ and the Trigger Master. The first implementation of the hit detection is based on hit multiplicity. Later on, a more sophisticated algorithm will be implemented to determine in real time the timing and charge collected for each channel. This information will be transferred to the Trigger Master for more efficient trigger filtering.

The ADC data is acquired from both the FMC ADC32 ADCs and the onboard 16ch 14-bit ADCs using the FPGAs hardware SERDES modules. These modules de-serialize the data stream from the ADCs into a format suitable for internal analysis for hit detection, and for transfer to the MIDAS DAQ.

Once one or more hits are detected, the ALPHA-16 transmits the hit count to the ALPHA-T for a hit multiplicity test, and then waits for a trigger response to decide to discard or transmit the waveform data associated with the detected hit to the DAQ.

Currently, when a trigger is fired by the Trigger Decision module, all channels transmit their captured waveforms to the DAQ. In the future, only channels that have detected a hit will send waveforms on a trigger.

System monitoring and configuration of the Hit Detector module is handled by ESPER running on a NIOS-II soft-core processor instantiated within the FPGA. The OS used is Micrium µC/OS-II, a small real-time OS licensed by Altera for use with their NIOS-II processor. ESPER performs the remote upgrading of the Hit Detector, viewing of the captured waveforms, and diagnostic reading and writing of all firmware settings and counters via a simple JSON-based interface, or an HTML based webpage.

[[File:image25daq.png|517x318px]]

Figure 20 - Hit Detector for the Anode wire and scintillators in ALPHA-16

== '''Pad Acquisition Module (FEAM)''' ==

The pad acquisition firmware module handles the collection of the PAD analog signals captured by the four AFTER ASICs on the module. Capture occurs upon receiving a trigger signal from the Trigger Decision module. Once captured, the AFTER data is transmitted to the MIDAS DAQ over ethernet. No pad information is provided back to the Trigger Decision module.

Each of the AFTER ASICs transmits its captured analog data to a 12-bit ADC which in turn converts the analog signal into digital data and transmits that to the FPGA. The FPGA uses its internal SERDES hardware to de-serialize this data and process it. Once captured, channels that do not contain data of interest are suppressed, and the data is packaged up and sent out over UDP to the MIDAS DAQ.

In the event that the SFP module that provides ethernet connectivity fails, each PAD acquisition module is connected to one other PAD acquisition module via a secondary gigabit link. While currently unused, this link will be used in the future to support a backup link to the DAQ, in the event of a failure of the primary gigabit link.

System monitoring and configuration of the PAD acquisition module is handled by ESPER running on a NIOS-II soft-core processor instantiated within the FPGA. The OS used is Micrium µC/OS-II, a small real-time OS licensed by Altera for use with their NIOS-II processor. ESPER performs the remote upgrading of the Hit Detector, viewing of the captured waveforms, and diagnostic reading and writing of all firmware settings and counters via a simple JSON-based interface, or an HTML based webpage.

[[File:image26daq.png|490x299px]]

Figure 21 - AFTER chip WFD on the PADWINGS

== '''Trigger Master module (ALPHA-T)''' ==

The Trigger Master firmware module is to collect information from the anode wires and scintillators to make a real-time decision if the current physics event is to be recorded. That decision is fed to all the readout boards to trigger the storage of this particular event.

Initial trigger decision will be based on hit multiplicity of each of the ALPHA-16 boards. As the ALPHA-16 is acquiring the anode wire and the barrel scintillator signals, both of these 2 pieces of equipment will contribute to the trigger decision. Dedicated link from each of the ALPHA-16 (hit detector) to the Trigger module will be gathering the overall information for a final decision. Hardware trigger signal is then sent from the ALPHA-T to the CDM for distribution to all the acquisition modules to initiate the transmission of their data to the backend computer through UDP. The trigger board will compose a summary of the trigger information which will also be transferred to the backend.

The Trigger Master module contains two Mini-SAS FMCs, and one ‘communication’ FMC, that consists of a SATA, an SFP, and a Mini-SAS connector. This configuration of FMCs allows for up to twenty (20) 1G/2.5G/5G links via the Mini-SAS, in addition to a 1 Gbit/sec Ethernet connection via the SFP, and clock+trigger over the SATA.

[[File:image27daq.png|576x304px]]

Figure 22 - Trigger decision on ALPHA-T

== System Monitoring and debugging capability ==

The system monitoring is based on the ESPER protocol provided by the Electronics Development group at TRIUMF. Featuring a built-in web server, with real-time digitizer display, remote upgrade, and JSON-accessible parameters. ESPER allows for real-time diagnostics and testing to be performed on the various electronic modules using either JSON-based requests or a built-in webpage.

[[File:image28daq.png|800x400px]]

Figure 23 - ESPER Web Display. Test pulse recorded by the FEAM cards. Individual AFTER chip configuration is visible (gain change, delay).

= Safety and Hazard considerations =

There are no safety or hazard issues in FE system. All amplifiers are low-voltage and low-power circuits built with standard electronics components.

Detector Electronics

2017-11-19T22:05:30Z

Midas: /* Anode wire signal path */

Back to [[Documentation]]

= Table of Figures =

[[#_Toc493676266|Figure 1 - Overall Data Acquisition scheme 7]]

[[#_Toc493676267|Figure 2 - Anode wire pre-amplification block diagram 8]]

[[#_Toc493676268|Figure 3 - Anode Wire Board (AWB), 16 channels pre-amplifier 9]]

[[#_Toc493676269|Figure 4 - 4 consecutive anode wire signals 9]]

[[#_Toc493676270|Figure 5 - Anode wire pre-amp gain map for half the chamber circumference 10]]

[[#_Toc493676271|Figure 6 - Alpha16 Data Acquisition Board 12]]

[[#_Toc493676272|Figure 7 - Grif16 Acquisition Module Block Diagram on which the Alpha-16 is based 12]]

[[#_Toc493676273|Figure 8 - Model of the new 32channels 12bit @ 65Msps FMC produced in 2016. 13]]

[[#_Toc493676274|Figure 9 - FMC Alpha-ADC32 Block Diagram 13]]

[[#_Toc493676275|Figure 10 - Cathode Pad Board readout for 288 channels at 62.5Msps, visible 4 AFTER chips, 3 copper bars running under the central board for power distribution 15]]

[[#_Toc493676276|Figure 11 – Thermal image of the FEAM with hot spot temperature: without cooling plate (78°C), with cooling plate (45°C), with cooling plate & water cooling (36°C) 16]]

[[#_Toc493676277|Figure 12 - Block diagram of AFTER amplifier 17]]

[[#_Toc493676278|Figure 13 - 4 x 72 cathode pad signals, overall time width corresponds to the drift time 17]]

[[#_Toc493676279|Figure 14 - Block diagram of one channel of SiPM amplifier 18]]

[[#_Toc493676280|Figure 15 - Trigger Card Adapter and Trigger Card 19]]

[[#_Toc493676281|Figure 16 Trigger Card to FEAM 19]]

[[#_Toc493676282|Figure 17 - Clock Distribution Module 20]]

[[#_Toc493676283|Figure 18 - IO Block Diagram 21]]

[[#_Toc493676284|Figure 19 - ALPHA-16 and CDM board in front with the Trigger/Clock distribution cables 22]]

[[#_Toc493676285|Figure 20 - Hit Detector for the Anode wire and scintillators in ALPHA-16 24]]

[[#_Toc493676286|Figure 21 - AFTER chip WFD on the PADWINGS 25]]

[[#_Toc493676287|Figure 22 - Trigger decision on ALPHA-T 26]]

[[#_Toc493676288|Figure 23 - ESPER Web Display. Test pulse recorded by the FEAM cards. Individual AFTER chip configuration is visible (gain change, delay). 27]]

= Introduction =

This design note describes the electronics chain and components for the readout of the ALPHA-g TPC and barrel scintillator bars.

= Scope =

The Detector Electronics is composed of 3 independent signal sources:

# Anode Wire signals path
# Cathode Pad signals path
# Barrel Scintillator signals path.

All 3 sources provide a similar function such as signal amplification and conditioning (shaping).

= Definitions and Abbreviations =

General acronyms or terms used for the ALPHA-g experiment

{|
! TPC
! Radial Time projection Chamber
|-
| Pads
| PCB surface seeing the induced anode wire signal
|-
| SiPM
| Si photomultipliers used to detect scintillation light
|-
| ADC
| Analog to digital converter
|-
| ASIC
| Application specific integrated circuit
|-
| SCA
| Switch Capacitor Array ( A type of Waveform Digitizer)
|-
| TDC
| Time to digital converter
|-
| BSM
| Barrel Scintillator Module (64 bars sub-assembly)
|-
| FEAM, Padwing
| Cathode strip acquisition board
|-
| CDM
| Clock Distribution Module
|-
| BSB
| Barrel Scintillator Board
|-
| WFD
| Waveform Digitizer
|}

Table 1 – ALPHA-g Abbreviations

= References and related Document =

* AFTER manual
* SensL SPM data sheet
* Edev-group.triumf.ca: contains the FW information on all the Alpha-g custom cards ([https://edev-group.triumf.ca/fw/exp/alphag/feam/rev0/wikis/feam-test-packet-format https://edev-group.triumf.ca/fw/exp/alphag])

* ''' 
'''

= Overall Detector Signal Path =

The Alpha-g detector provides 3 analog signals that are collected for the track reconstruction to help on the annihilation location in the trap.

* The anode wire signal providing the drift time of the electron through the detector for an angular position.
* The cathode pad signal, which are in-time correlated to the anode wire signal, providing the amplitude of these signals from which the longitudinal position (Z) can be extracted.
* The Barrel Scintillator bar signals provide the time and amplitude of the particle crossing the detector. The Barrel Scintillator is mainly to reject cosmic events. For that purpose, the timing resolution is important. Therefore the BSM analog signal is split early in the chain to record the amplitude and time separately.

The anode wires and the barrel scintillator bars are read out from both ends to provide a coarse Z-position as well. The Data acquisition is therefore made for reading 2x256 anode wire channels, 2x64 barrel scintillator bars and 18432 channels of cathode pads covering the outer detector cylinder.

[[File:image2daq.png|876x559px]]

Figure 1 - Overall Data Acquisition scheme

= Anode wire signal path =

The design for the anode wires pre-amplifier is based on work done for several other projects used at TRIUMF and other labs.

Each of the 256 anode wires is read-out from two ends. The signals are used to (1) determine phi-position of ionization track; (2) reconstruct its z-position by weighting signals from two wire ends; (3) generate trigger signal. The pre-amplifiers convert the induced current to voltage that is digitized and processed in the readout system. The main requirements for the amplifier circuit are:

# Input impedance must be low enough so detected charge is sensitive to position of event along wire;
# The shape of signal is optimized for sampling frequency (16 ns) and for fast trigger timing (few ns accuracy);
# Linearity range adjusted for ADC used;
# Gain is adjusted for gas amplification of 105
# Amplifier noise is low enough to detect single-electron cluster.

[[File:image3daq.png|576x204px]]

Figure 2 - Anode wire pre-amplification block diagram

Anode wires are HV-decoupled before connected to the amplifier, but additional (not HV) decoupling is needed at amplifier input to accommodate non-zero potential of the input stage. Protection of the amplifier input is using a standard bi-diode configuration. The first stage is a current-sensitive loop with input impedance defined by resistor Rin and trans-impedance (gain) by feedback resistor Rf. The second stage is 2-pole shaper with shaping time constant defined by components Rs and Cs. The last stage is a cable driver.

Overall gain, transfer function and input impedance of the circuit can be adjusted by changing passive components. This adjustment will be done by studying the TPC prototypes.

Amplifiers are deployed on 16-channel cards, 16 boards serve each end of TPC. They are powered by standard +5V and -5V linear supplies. Each card has a test input that is used to measure amplifiers response and to check for malfunction.

[[File:image4daq.jpg|273x283px]] [[File:image5daq.png|269x284px]]

Figure 3 - Anode Wire Board (AWB), 16 channels pre-amplifier

The AWB schematic allows for bipolar signal input. This has the advantage to reproduce the full anode wire signal development including the inverted induced pulse from neighbouring wires as seen Figure 4.

[[File:image6daq.jpg|512x358px]]

Figure 4 - 4 consecutive anode wire signals

The anode pre-amps have an individual test pulse input to provide a quick functional test. It can also be used for calibration purpose. Several tests have been done in this regard, but the overall chain gain is dependent on many variables (chamber geometry, environmental condition (Gas mixture, T, P), pre-amp (layout, components)). Another more common test pulse injection is available by pulsing all the field wires at once (at the boundary of the drift and multiplication region). This technique has the advantage to produce an induced signal on all the anode wires and cathode pads together at the “same” time. Figure 5 shows the gain variation by wire seen when pulsed through the field wire. 2 interesting features are visible:

a) An overall negative slope, indicated by the linear fit. This slope is explained by the pulse attenuation through the field wires distribution.

b) A clear increase in gain for the wires near the anode wire card boundaries, indicated by the cyan lines is not yet well understood. A further test is planned.

[[File:image7daq.png[497x389px]]

Figure 5 - Anode wire pre-amp gain map for half the chamber circumference

== Anode Wire Waveform digitizer (Alpha-16) ==

The output of the AWB is presented to the Alpha-16 waveform digitizer sampling the analog signal at 62.5Msps.

'''''Note:''''' At the time of this report, the WFD 62.5Msps is not yet available. We use the WFD at 100Msps to perform the tests. The firmware is similar to the 62.5Msps and the final test will be reproduced later.

This module provides 16 channels 14bit ADC @100Msps for 50Ohms single-ended analog signal for the barrel scintillator. It also supports a dedicated mezzanine card (FMC) handling 32 channels 12bit ADC @ 65Msps for single-ended 50Ohms analog signals for the Anode wires.

The Alpha-16 board outputs (16ch.@100Msps and 32ch.@62.5Msps) are collected on the main carrier FPGA for transmission through Ethernet to the backend computer.

The board carries multiple I/O connections required for the module configuration, communication, data transfer, signal inputs, see Figure 7.

* Front panel SFP Gbit Ethernet (copper/fiber)
* Front panel eSATA: clock and sync inputs
* Front panel dual LEMO: Diagnostic DAC outputs (250Msps)
* Front panel MCX connector for 16 x ADC inputs
* Rear entry P2 connector for 16 x ADC inputs
* A24/D16 VME interface to MAXV configuration CPLD
** VME configuration flash updates
** VME bridge to FPGA
* FMC custom module connections.
** Dual MiniSAS for Acquisition setup
** 10 x5Gibt Link
** JESD204B Clocks
** Supports 32 Channel ADC LVDS interface
* Amplifier input switches: Front panel MCX connector, Rear Transition Card SMA connector
* Amplifier Gain x1 and x4
* Switch selectable LEMO NIM Input/ DAC outputs
* Micro SD Flash
* DDR3 DRAM – 667MHz – 128M x 23'''(MT41J128M16HA-15E)'''
* FPGA - Arria V '''(5AGXFB3H4F35C4N)'''
* MAXV CPLD controller '''(5M2210ZF256C5N)''' for USB JTAG and VME access

[[File:image8daq.jpg|218x380px]]

Figure 6. Alpha16 Data Acquisition Board

[[File:image9daq.png|264x383px]]

Figure 7. Grif16 Acquisition Module Block Diagram on which the Alpha-16 is based

== FMC – Alpha ADC32 ==

<blockquote>The FMC – ALPHA ADC32 provides single-stage amplification of up to 32 single-ended 50<math>\Omega</math> analog signals, from the Anode Wire Board Pre-Amplifier, to drive two 16 channel 14bit differential, analog to digital converters sampling at 65MSPS. Further, each ADC will provide a 0.9V common mode offset voltage to be fed into the differential driver

A 16 channel 12 bit digital-to-analog (DAC) converter is used to individually apply an appropriate offset voltage to each of the differential amplifier pairs. The Offset voltages span <math>\pm</math>2.5Vat 1.22mV increments and will output 0V upon power cycle. The DAC is configurable via an SPI interface via the FMC connector.

ADC32 board has the capability to receive and transmit an LVDS clock signal through the eSATA connector which is fed to the FMC connector
</blockquote>
[[File:image10daq.png|318x307px]]

Figure 8 - Model of the new 32channels 12bit @ 65Msps FMC produced in 2016.

[[File:image11daq.png|420x285px]]

Figure 9 - FMC Alpha-ADC32 Block Diagram

<blockquote>''These notes are for the current revision of the Alpha ADC32, a new revision is currently being talked about''
</blockquote>
The board is composed of the following elements:

* 400 Pin FMC connector
** Provides SPI interface
** ADC Synchronization
** Support for 32 LVDS analog signals
** Supply voltage of fused +12V, Switched 3.3V and 1.2-3.3V adjustable
* 32 channel Analog inputs via Hirose connector '''[FX2-40S-1.27DS(71)] 
'''
* 1V analog reference voltage '''[LTC6655BHMS8-3#PBF]'''
** ±2ppm
* Differential ADC Driver '''[ADA4950'''-'''2YCPZ]'''
** ±0.2mV Offset
** 9.2nHz / √Hz Output voltage Noise at Gain=1
** Adjustable output common-mode voltage
** Hardware programmable gain of 1x, 2x and 3x
* Dual 16 channel 14bit Analog to Digital converter '''[AD9249BBCZ-65]'''
** 2Vp-p input range
** 65MSPS
** ±0.6LSB
** Input Clock of 10-520MHz
* 16 channel 12bit Digital to Analog converter '''[ADA4950-2YCPZ]'''
** Programmable offset voltage
** SPI configurable outputs
** Output range ±2.5V, 0V upon reset
** 1.22mV/LSB
* 1 x eSATA Clk-In / Clk-out to and from FMC connector

= Cathode pad signal path =

The 18432 cathode pads covering the inner surface of the outer wall of the detector are individually connected to a signal acquisition chain. This collected signals will provide the position of the electron avalanche at the anode wire. Combining them in charge, permit the reconstruction of the track passing through the longitudinal direction the detector. While the cathode pads cover a large area (2.7m2), the actual footprint per channel is limited (3.8mmx37.1mm). Therefore a high-density waveform digitizer chain has been chosen based on our previous experience with the T2K experiment, we opted for the AFTER Switched Capacitor Array (SCA) ASIC. The analog signal path is short as the pads themselves are on the backside the physical outer cylinder of the detector and the input signal connectors to the AFTER chips are on the opposite side of the outer cylinder.

A custom frontend board (FEAM) see Figure 10 handling 288 individual cathode pads has been designed. It is composed of 4 ASIC AFTER (72 channels) with associated waveform digitizer for the individual signal on 512 cells at 20Msps. In addition, an FPGA manages the board services and the data collection and transmission through a 1 gigabit/sec optical link to the Ethernet using the UDP protocol.

While the power consumption per channel at the ASIC level is low, the power requirement is in the order of 15W per board for a total at the detector level approaching 1000W. This required proper cooling to maintain a reliable operation of the electronics. Figure 11 shows the board temperature with and without cooling plate. Thermal images have been taken to confirm the temperature reduction of the main heat source (Clock cleaner, FPGA, ADC, AFTER in that order). We can guarantee a chip temperature below 60°C to keep the default chip MTBF.

[[File:image12daq.jpg|558x246px]]

Figure 10 - Cathode Pad Board readout for 288 channels at 62.5Msps, visible 4 AFTER chips, 3 copper bars running under the central board for power distribution

[[File:image13daq.png|249x185px]]
[[File:image14daq.png|247x186px]]
[[File:image15daq.jpg|248x186px]]

Figure 11 – Thermal image of the FEAM with hot spot temperature: without cooling plate (78°C), with cooling plate (45°C), with cooling plate & water cooling (36°C)

== Cathode Pad Circuit ==

The cathode pads are read-out by AFTER ASIC which diagram is presented in Figure 12. Each channel consists of a charge-sensitive preamplifier, pole-zero cancellation of preamplifier decay time, RC2 shaper and 512-cell SCA to store the waveform. Amplifier gain, pole-zero time constant and shaping time are programmable.

{|
|
[[File:image16daq.png|361x171px]]

Figure 12 - Block diagram of AFTER amplifier
| [[File:image17daq.png|215x199px]]
|}

The acquisition of the FEAM cards is operational and initial waveforms can be displayed as seen in Figure 13. This visualization is for monitoring the individual channels only. The data acquisition is using a different path for fast data collection. Figure 13 shows cathode signal examples collected by the FEAM card. The signal shape is consistent with avalanches occurring from a cosmic track going through the detector. The initial pulse corresponds to the early avalanches when the track crosses the amplification region (near the anode wire). The remaining pulses show the later electron avalanches reaching the same anode wire from the drift region due to the track angle. The complex pulse shape from the drift region reflects the convolution in this time base of the arrival of the electron to the amplification region and the induced pulse from the resulting electron avalanche.

= Barrel Scintillator signal path =

'''''Note''''': While the Barrel Scintillator is part of the Alpha-g detector for cosmic rejection purpose, this section is still under development. The initial concept and implementation are therefore not final. The volume allocated for it in the other hand well defined due to external to the detector constraints.

Light at both ends of each bar of the barrel scintillator is collected for a rough position detection of the crossing particle and timing information. To improve the detection information (maximize photon collection), 6 individual SiPM light detector (SensL) are mounted on both ends of the individual scintillator bar for a coverage of 50% of the bar. This assembly is in a light-tight and gas-tight enclosure. A cold gas flows through the box to lower the SiPM temperature operation in order to reduce the dark noise of the device. A shaper/amplifier board (BSB) will be mounted on the outside of the enclosure. Each of the board will acquire the signals of 4 adjacent scintillator bars. In total 64 scintillator bars are read out by 16 boards at each end. A block diagram of one bar readout is shown in Figure 14. The signal gathering of the 6 sensors is based on an analog sum.

[[File:image18daq.png|480x296px]]

Figure 14 - Block diagram of one channel of SiPM amplifier

The 6 pre-amplifier outputs are combined to provide the sum of 6 signals. This resulting signal is further amplified and shaped (if necessary) on a second stage post-amplifier/discriminator. This signal sent to the readout system through a cable driver. Two signals will be acquired from each bar: (1) Analog sum fed to a waveform digitizer with proper digital processing to determine event position and timing; (2) LVDS signal fed to a TDC for off-line precise timing measurement purposes. For the LVDS signal, the post-amplifier will have a controlled threshold voltage to the signal comparator.

The BSB will be powered by standard +5V and -5V linear supplies. Each board has a test input to allow individual board measure of the amplifier response, malfunction test and to provide the necessary services to the light sensors device (Voltage bias, temperature sensor, etc).

The output of the analog output of the BSB will be shaped for the 100Msps WFD and in parallel will issue a digital signal for timing information to a TDC.

= Trigger Distribution =

On the full-length detector, the FEAM boards will receive trigger and clock signals from the CDM through the Trigger Card Adapter. The adapter receives signals from the CDM via a 7 pin SATA connector. The signals can be re-driven by repeaters on the adapter and are sent down a chain of 7 Trigger Cards with the adapter forming the first link.

While there are other elegant means of distributing the common clock and trigger to all the electronics boards, this method is the most simple and robust.

[[File:image19daq.png|195x575px|Adapter]]

[[File:image20daq.png|573x43px|Trigger_Board]]

Figure 15 - Trigger Card Adapter and Trigger Card

[[File:image21daq.jpg|216x294px|20170914_101103_resized]]

Figure 16 Trigger Card to FEAM

A Samtec SFM-110 connects each card to a FEAM board and also provides through holes pins where another card can be overlapped and soldered. In this manner the chain of Trigger Distribution Cards is formed, providing a shared clock and trigger signal to a column of 8 FEAM boards.

= Clock Distribution Module =

[[File:image22daq.png|231x356px]]

Figure 17 - Clock Distribution Module

* 6x LEMO Connectors [2 Output, 4 Input]
* 6x Mini-SAS providing up to 24 channels of clock and synchronization breakout
* 1x Combination eSATA/USB connector
** eSATA provides CLK and SYNC
** USB provides USB to Serial communication 115200 BAUD
* 1x 10/100 Base-TX Ethernet
* Optional Atomic Clock module support, 10MHz and 1PPS '''[CSAC - SA.45s]'''
** Short term Stability <1E-11
** over 1000 seconds (100μHz / 1000s)
** Aging rate of <9E-10 per month '''('''9mHz/month)
* Onboard 10MHz Crystal Oscillator '''[FOX924B-10.000]'''
** ±2.5ppm
** ±1ppm per year
* JTAG ARM Support
* SmartFusion2 SoC '''[MS2-FG484]'''
* Ultra-low noise clock jitter cleaner 3:15 input to output support '''[LMK04821] '''
** Min/Max VCO Frequency 2750/3072MHz
** 0.111RMS Jitter
* TTL and NIM signal compatibility for external CLK and SYNC
* VME - 6U - 3Row
* Approximate Current Draw 1.837A at 5V

The Clock Distribution Module ('''CDM)''' has the capability to distribute two externally sourced clock and synchronization signals to six mini-SAS connections for total 24 signal signals. The external signals are provided through the eSATA and LEMO 1A/B Connectors. The module also has the capability to add an Atomic clock that outputs a 10Mhz signal and a 1 Pulse Per Second (PPS), as well as user-defined synchronization signal. Lastly, the module can be configured to output the external clock signals to the LEMO 2B connector or VME bus.

[[File:image23daq.png|509x348px]]

Figure 18 - IO Block Diagram

[[File:image24daq.png|299x412px]]

Figure 19 - ALPHA-16 and CDM board in front with the Trigger/Clock distribution cables

= Frontend Board Firmware =

The firmware (FW) refers to the embedded code running on the Field Programmable Gate Arrays (FPGAs) and microcontrollers (MCUs) located on the various modules within the experiment. These devices store, load, and run the programs required for operation of the different digital electronic components within the experiment.

Firmware code is essential to the operation of the detector as it provides the mechanism to configure the hardware for its particular purpose. Such as analog-to-digital conversion, data filtering, data trigger composition, transport of the data, and orchestration of all the different hardware modules to succeed in acquiring meaningful information across the overall system. Some of the firmware tasks are:

<ol style="list-style-type: upper-roman;">
<li>Low-level acquisition of the 3 different WFDigitizers (Anode wire, Cathode pad, Barrel Scintillator)</li>
<li>Links all the electronics boards to the DAQ system.</li>
<li>Collected in real-time information for trigger decision making.</li>
<li>Distribute synchronization signals and trigger to all the acquisition boards.</li>
<li>Provides to the user; configurable board and operation parameters settings.</li>
<li>Provides board monitoring and debugging tools.</li></ol>

Most of the FW code base has been based off of prior code developed for the currently running GRIFFIN experiment, with some exceptions, such as the Trigger Master Module which needed custom code specific to ALPHA-g, and the PADWING, which contained the AFTER SCA chip not present in GRIFFIN.



The firmware code is loaded onto the hardware board where an FPGA or MCU is present. Each firmware module has specific firmware capabilities, detailed as follows:

* Hit Detector firmware Module (ALPHA-16 carrier board)
** Anode Wire and Barrel Scint. signal waveform digitizers acquisition
** Local data filtering for Trigger purpose
** Transmission of summary data to Trigger Module for trigger decision
** Data compression/filtering and retention for transmission to backend on Trigger reception
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Pad Acquisition firmware Module (PADWING board)
** Cathode pad signal waveform digitizers acquisition
** Data compression/filtering and retention for transmission to backend on Trigger reception
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Master Trigger firmware Module (ALPHA-T board)
** Summary data reception of the multiple GRIF-16 boards
** Trigger decision algorithm
** Packaging of Trigger decision information and transmission to the backend.
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Clock and Trigger Distribution firmware Module (CDM board)
** Monitoring of hardware functions (U,I,T,Clock Frequency)
** Configuration of hardware mechanism for clock and trigger distribution
** Update of firmware code mechanism

== '''Hit Detector Module (ALPHA-16)''' ==

The Hit Detector firmware module handles the acquisition of the analog input signals from the anode wires and scintillators, the digital conversion of that data, and then the transfer of that data to both the DAQ and the Trigger Master. The first implementation of the hit detection is based on hit multiplicity. Later on, a more sophisticated algorithm will be implemented to determine in real time the timing and charge collected for each channel. This information will be transferred to the Trigger Master for more efficient trigger filtering.

The ADC data is acquired from both the FMC ADC32 ADCs and the onboard 16ch 14-bit ADCs using the FPGAs hardware SERDES modules. These modules de-serialize the data stream from the ADCs into a format suitable for internal analysis for hit detection, and for transfer to the MIDAS DAQ.

Once one or more hits are detected, the ALPHA-16 transmits the hit count to the ALPHA-T for a hit multiplicity test, and then waits for a trigger response to decide to discard or transmit the waveform data associated with the detected hit to the DAQ.

Currently, when a trigger is fired by the Trigger Decision module, all channels transmit their captured waveforms to the DAQ. In the future, only channels that have detected a hit will send waveforms on a trigger.

System monitoring and configuration of the Hit Detector module is handled by ESPER running on a NIOS-II soft-core processor instantiated within the FPGA. The OS used is Micrium µC/OS-II, a small real-time OS licensed by Altera for use with their NIOS-II processor. ESPER performs the remote upgrading of the Hit Detector, viewing of the captured waveforms, and diagnostic reading and writing of all firmware settings and counters via a simple JSON-based interface, or an HTML based webpage.

[[File:image25daq.png|517x318px]]

Figure 20 - Hit Detector for the Anode wire and scintillators in ALPHA-16

== '''Pad Acquisition Module (FEAM)''' ==

The pad acquisition firmware module handles the collection of the PAD analog signals captured by the four AFTER ASICs on the module. Capture occurs upon receiving a trigger signal from the Trigger Decision module. Once captured, the AFTER data is transmitted to the MIDAS DAQ over ethernet. No pad information is provided back to the Trigger Decision module.

Each of the AFTER ASICs transmits its captured analog data to a 12-bit ADC which in turn converts the analog signal into digital data and transmits that to the FPGA. The FPGA uses its internal SERDES hardware to de-serialize this data and process it. Once captured, channels that do not contain data of interest are suppressed, and the data is packaged up and sent out over UDP to the MIDAS DAQ.

In the event that the SFP module that provides ethernet connectivity fails, each PAD acquisition module is connected to one other PAD acquisition module via a secondary gigabit link. While currently unused, this link will be used in the future to support a backup link to the DAQ, in the event of a failure of the primary gigabit link.

System monitoring and configuration of the PAD acquisition module is handled by ESPER running on a NIOS-II soft-core processor instantiated within the FPGA. The OS used is Micrium µC/OS-II, a small real-time OS licensed by Altera for use with their NIOS-II processor. ESPER performs the remote upgrading of the Hit Detector, viewing of the captured waveforms, and diagnostic reading and writing of all firmware settings and counters via a simple JSON-based interface, or an HTML based webpage.

[[File:image26daq.png|490x299px]]

Figure 21 - AFTER chip WFD on the PADWINGS

== '''Trigger Master module (ALPHA-T)''' ==

The Trigger Master firmware module is to collect information from the anode wires and scintillators to make a real-time decision if the current physics event is to be recorded. That decision is fed to all the readout boards to trigger the storage of this particular event.

Initial trigger decision will be based on hit multiplicity of each of the ALPHA-16 boards. As the ALPHA-16 is acquiring the anode wire and the barrel scintillator signals, both of these 2 pieces of equipment will contribute to the trigger decision. Dedicated link from each of the ALPHA-16 (hit detector) to the Trigger module will be gathering the overall information for a final decision. Hardware trigger signal is then sent from the ALPHA-T to the CDM for distribution to all the acquisition modules to initiate the transmission of their data to the backend computer through UDP. The trigger board will compose a summary of the trigger information which will also be transferred to the backend.

The Trigger Master module contains two Mini-SAS FMCs, and one ‘communication’ FMC, that consists of a SATA, an SFP, and a Mini-SAS connector. This configuration of FMCs allows for up to twenty (20) 1G/2.5G/5G links via the Mini-SAS, in addition to a 1 Gbit/sec Ethernet connection via the SFP, and clock+trigger over the SATA.

[[File:image27daq.png|576x304px]]

Figure 22 - Trigger decision on ALPHA-T

== System Monitoring and debugging capability ==

The system monitoring is based on the ESPER protocol provided by the Electronics Development group at TRIUMF. Featuring a built-in web server, with real-time digitizer display, remote upgrade, and JSON-accessible parameters. ESPER allows for real-time diagnostics and testing to be performed on the various electronic modules using either JSON-based requests or a built-in webpage.

[[File:image28daq.png|800x400px]]

Figure 23 - ESPER Web Display. Test pulse recorded by the FEAM cards. Individual AFTER chip configuration is visible (gain change, delay).

= Safety and Hazard considerations =

There are no safety or hazard issues in FE system. All amplifiers are low-voltage and low-power circuits built with standard electronics components.

Detector Electronics

2017-11-19T22:04:35Z

Midas: /* Anode wire signal path */

Back to [[Documentation]]

= Table of Figures =

[[#_Toc493676266|Figure 1 - Overall Data Acquisition scheme 7]]

[[#_Toc493676267|Figure 2 - Anode wire pre-amplification block diagram 8]]

[[#_Toc493676268|Figure 3 - Anode Wire Board (AWB), 16 channels pre-amplifier 9]]

[[#_Toc493676269|Figure 4 - 4 consecutive anode wire signals 9]]

[[#_Toc493676270|Figure 5 - Anode wire pre-amp gain map for half the chamber circumference 10]]

[[#_Toc493676271|Figure 6 - Alpha16 Data Acquisition Board 12]]

[[#_Toc493676272|Figure 7 - Grif16 Acquisition Module Block Diagram on which the Alpha-16 is based 12]]

[[#_Toc493676273|Figure 8 - Model of the new 32channels 12bit @ 65Msps FMC produced in 2016. 13]]

[[#_Toc493676274|Figure 9 - FMC Alpha-ADC32 Block Diagram 13]]

[[#_Toc493676275|Figure 10 - Cathode Pad Board readout for 288 channels at 62.5Msps, visible 4 AFTER chips, 3 copper bars running under the central board for power distribution 15]]

[[#_Toc493676276|Figure 11 – Thermal image of the FEAM with hot spot temperature: without cooling plate (78°C), with cooling plate (45°C), with cooling plate & water cooling (36°C) 16]]

[[#_Toc493676277|Figure 12 - Block diagram of AFTER amplifier 17]]

[[#_Toc493676278|Figure 13 - 4 x 72 cathode pad signals, overall time width corresponds to the drift time 17]]

[[#_Toc493676279|Figure 14 - Block diagram of one channel of SiPM amplifier 18]]

[[#_Toc493676280|Figure 15 - Trigger Card Adapter and Trigger Card 19]]

[[#_Toc493676281|Figure 16 Trigger Card to FEAM 19]]

[[#_Toc493676282|Figure 17 - Clock Distribution Module 20]]

[[#_Toc493676283|Figure 18 - IO Block Diagram 21]]

[[#_Toc493676284|Figure 19 - ALPHA-16 and CDM board in front with the Trigger/Clock distribution cables 22]]

[[#_Toc493676285|Figure 20 - Hit Detector for the Anode wire and scintillators in ALPHA-16 24]]

[[#_Toc493676286|Figure 21 - AFTER chip WFD on the PADWINGS 25]]

[[#_Toc493676287|Figure 22 - Trigger decision on ALPHA-T 26]]

[[#_Toc493676288|Figure 23 - ESPER Web Display. Test pulse recorded by the FEAM cards. Individual AFTER chip configuration is visible (gain change, delay). 27]]

= Introduction =

This design note describes the electronics chain and components for the readout of the ALPHA-g TPC and barrel scintillator bars.

= Scope =

The Detector Electronics is composed of 3 independent signal sources:

# Anode Wire signals path
# Cathode Pad signals path
# Barrel Scintillator signals path.

All 3 sources provide a similar function such as signal amplification and conditioning (shaping).

= Definitions and Abbreviations =

General acronyms or terms used for the ALPHA-g experiment

{|
! TPC
! Radial Time projection Chamber
|-
| Pads
| PCB surface seeing the induced anode wire signal
|-
| SiPM
| Si photomultipliers used to detect scintillation light
|-
| ADC
| Analog to digital converter
|-
| ASIC
| Application specific integrated circuit
|-
| SCA
| Switch Capacitor Array ( A type of Waveform Digitizer)
|-
| TDC
| Time to digital converter
|-
| BSM
| Barrel Scintillator Module (64 bars sub-assembly)
|-
| FEAM, Padwing
| Cathode strip acquisition board
|-
| CDM
| Clock Distribution Module
|-
| BSB
| Barrel Scintillator Board
|-
| WFD
| Waveform Digitizer
|}

Table 1 – ALPHA-g Abbreviations

= References and related Document =

* AFTER manual
* SensL SPM data sheet
* Edev-group.triumf.ca: contains the FW information on all the Alpha-g custom cards ([https://edev-group.triumf.ca/fw/exp/alphag/feam/rev0/wikis/feam-test-packet-format https://edev-group.triumf.ca/fw/exp/alphag])

* ''' 
'''

= Overall Detector Signal Path =

The Alpha-g detector provides 3 analog signals that are collected for the track reconstruction to help on the annihilation location in the trap.

* The anode wire signal providing the drift time of the electron through the detector for an angular position.
* The cathode pad signal, which are in-time correlated to the anode wire signal, providing the amplitude of these signals from which the longitudinal position (Z) can be extracted.
* The Barrel Scintillator bar signals provide the time and amplitude of the particle crossing the detector. The Barrel Scintillator is mainly to reject cosmic events. For that purpose, the timing resolution is important. Therefore the BSM analog signal is split early in the chain to record the amplitude and time separately.

The anode wires and the barrel scintillator bars are read out from both ends to provide a coarse Z-position as well. The Data acquisition is therefore made for reading 2x256 anode wire channels, 2x64 barrel scintillator bars and 18432 channels of cathode pads covering the outer detector cylinder.

[[File:image2daq.png|876x559px]]

Figure 1 - Overall Data Acquisition scheme

= Anode wire signal path =

The design for the anode wires pre-amplifier is based on work done for several other projects used at TRIUMF and other labs.

Each of the 256 anode wires is read-out from two ends. The signals are used to (1) determine phi-position of ionization track; (2) reconstruct its z-position by weighting signals from two wire ends; (3) generate trigger signal. The pre-amplifiers convert the induced current to voltage that is digitized and processed in the readout system. The main requirements for the amplifier circuit are:

# Input impedance must be low enough so detected charge is sensitive to position of event along wire;
# The shape of signal is optimized for sampling frequency (16 ns) and for fast trigger timing (few ns accuracy);
# Linearity range adjusted for ADC used;
# Gain is adjusted for gas amplification of 105
# Amplifier noise is low enough to detect single-electron cluster.

[[File:image3daq.png|576x204px]]

Figure 2 - Anode wire pre-amplification block diagram

Anode wires are HV-decoupled before connected to the amplifier, but additional (not HV) decoupling is needed at amplifier input to accommodate non-zero potential of the input stage. Protection of the amplifier input is using a standard bi-diode configuration. The first stage is a current-sensitive loop with input impedance defined by resistor Rin and trans-impedance (gain) by feedback resistor Rf. The second stage is 2-pole shaper with shaping time constant defined by components Rs and Cs. The last stage is a cable driver.

Overall gain, transfer function and input impedance of the circuit can be adjusted by changing passive components. This adjustment will be done by studying the TPC prototypes.

Amplifiers are deployed on 16-channel cards, 16 boards serve each end of TPC. They are powered by standard +5V and -5V linear supplies. Each card has a test input that is used to measure amplifiers response and to check for malfunction.

[[File:image4daq.jpg|273x283px]] [[File:image5daq.png|269x284px]]

Figure 3 - Anode Wire Board (AWB), 16 channels pre-amplifier

The AWB schematic allows for bipolar signal input. This has the advantage to reproduce the full anode wire signal development including the inverted induced pulse from neighbouring wires as seen Figure 4.

[[File:image6daq.jpg|512x358px]]

Figure 4 - 4 consecutive anode wire signals

The anode pre-amps have an individual test pulse input to provide a quick functional test. It can also be used for calibration purpose. Several tests have been done in this regard, but the overall chain gain is dependent on many variables (chamber geometry, environmental condition (Gas mixture, T, P), pre-amp (layout, components)). Another more common test pulse injection is available by pulsing all the field wires at once (at the boundary of the drift and multiplication region). This technique has the advantage to produce an induced signal on all the anode wires and cathode pads together at the “same” time. Figure 5 shows the gain variation by wire seen when pulsed through the field wire. 2 interesting features are visible:

a) An overall negative slope, indicated by the linear fit. This slope is explained by the pulse attenuation through the field wires distribution.

b) A clear increase in gain for the wires near the anode wire card boundaries, indicated by the cyan lines is not yet well understood. A further test is planned.

[[File:image7daq.png|397x289px]]

Figure 5 - Anode wire pre-amp gain map for half the chamber circumference

== Anode Wire Waveform digitizer (Alpha-16) ==

The output of the AWB is presented to the Alpha-16 waveform digitizer sampling the analog signal at 62.5Msps.

'''''Note:''''' At the time of this report, the WFD 62.5Msps is not yet available. We use the WFD at 100Msps to perform the tests. The firmware is similar to the 62.5Msps and the final test will be reproduced later.

This module provides 16 channels 14bit ADC @100Msps for 50Ohms single-ended analog signal for the barrel scintillator. It also supports a dedicated mezzanine card (FMC) handling 32 channels 12bit ADC @ 65Msps for single-ended 50Ohms analog signals for the Anode wires.

The Alpha-16 board outputs (16ch.@100Msps and 32ch.@62.5Msps) are collected on the main carrier FPGA for transmission through Ethernet to the backend computer.

The board carries multiple I/O connections required for the module configuration, communication, data transfer, signal inputs, see Figure 7.

* Front panel SFP Gbit Ethernet (copper/fiber)
* Front panel eSATA: clock and sync inputs
* Front panel dual LEMO: Diagnostic DAC outputs (250Msps)
* Front panel MCX connector for 16 x ADC inputs
* Rear entry P2 connector for 16 x ADC inputs
* A24/D16 VME interface to MAXV configuration CPLD
** VME configuration flash updates
** VME bridge to FPGA
* FMC custom module connections.
** Dual MiniSAS for Acquisition setup
** 10 x5Gibt Link
** JESD204B Clocks
** Supports 32 Channel ADC LVDS interface
* Amplifier input switches: Front panel MCX connector, Rear Transition Card SMA connector
* Amplifier Gain x1 and x4
* Switch selectable LEMO NIM Input/ DAC outputs
* Micro SD Flash
* DDR3 DRAM – 667MHz – 128M x 23'''(MT41J128M16HA-15E)'''
* FPGA - Arria V '''(5AGXFB3H4F35C4N)'''
* MAXV CPLD controller '''(5M2210ZF256C5N)''' for USB JTAG and VME access

[[File:image8daq.jpg|218x380px]]

Figure 6. Alpha16 Data Acquisition Board

[[File:image9daq.png|264x383px]]

Figure 7. Grif16 Acquisition Module Block Diagram on which the Alpha-16 is based

== FMC – Alpha ADC32 ==

<blockquote>The FMC – ALPHA ADC32 provides single-stage amplification of up to 32 single-ended 50<math>\Omega</math> analog signals, from the Anode Wire Board Pre-Amplifier, to drive two 16 channel 14bit differential, analog to digital converters sampling at 65MSPS. Further, each ADC will provide a 0.9V common mode offset voltage to be fed into the differential driver

A 16 channel 12 bit digital-to-analog (DAC) converter is used to individually apply an appropriate offset voltage to each of the differential amplifier pairs. The Offset voltages span <math>\pm</math>2.5Vat 1.22mV increments and will output 0V upon power cycle. The DAC is configurable via an SPI interface via the FMC connector.

ADC32 board has the capability to receive and transmit an LVDS clock signal through the eSATA connector which is fed to the FMC connector
</blockquote>
[[File:image10daq.png|318x307px]]

Figure 8 - Model of the new 32channels 12bit @ 65Msps FMC produced in 2016.

[[File:image11daq.png|420x285px]]

Figure 9 - FMC Alpha-ADC32 Block Diagram

<blockquote>''These notes are for the current revision of the Alpha ADC32, a new revision is currently being talked about''
</blockquote>
The board is composed of the following elements:

* 400 Pin FMC connector
** Provides SPI interface
** ADC Synchronization
** Support for 32 LVDS analog signals
** Supply voltage of fused +12V, Switched 3.3V and 1.2-3.3V adjustable
* 32 channel Analog inputs via Hirose connector '''[FX2-40S-1.27DS(71)] 
'''
* 1V analog reference voltage '''[LTC6655BHMS8-3#PBF]'''
** ±2ppm
* Differential ADC Driver '''[ADA4950'''-'''2YCPZ]'''
** ±0.2mV Offset
** 9.2nHz / √Hz Output voltage Noise at Gain=1
** Adjustable output common-mode voltage
** Hardware programmable gain of 1x, 2x and 3x
* Dual 16 channel 14bit Analog to Digital converter '''[AD9249BBCZ-65]'''
** 2Vp-p input range
** 65MSPS
** ±0.6LSB
** Input Clock of 10-520MHz
* 16 channel 12bit Digital to Analog converter '''[ADA4950-2YCPZ]'''
** Programmable offset voltage
** SPI configurable outputs
** Output range ±2.5V, 0V upon reset
** 1.22mV/LSB
* 1 x eSATA Clk-In / Clk-out to and from FMC connector

= Cathode pad signal path =

The 18432 cathode pads covering the inner surface of the outer wall of the detector are individually connected to a signal acquisition chain. This collected signals will provide the position of the electron avalanche at the anode wire. Combining them in charge, permit the reconstruction of the track passing through the longitudinal direction the detector. While the cathode pads cover a large area (2.7m2), the actual footprint per channel is limited (3.8mmx37.1mm). Therefore a high-density waveform digitizer chain has been chosen based on our previous experience with the T2K experiment, we opted for the AFTER Switched Capacitor Array (SCA) ASIC. The analog signal path is short as the pads themselves are on the backside the physical outer cylinder of the detector and the input signal connectors to the AFTER chips are on the opposite side of the outer cylinder.

A custom frontend board (FEAM) see Figure 10 handling 288 individual cathode pads has been designed. It is composed of 4 ASIC AFTER (72 channels) with associated waveform digitizer for the individual signal on 512 cells at 20Msps. In addition, an FPGA manages the board services and the data collection and transmission through a 1 gigabit/sec optical link to the Ethernet using the UDP protocol.

While the power consumption per channel at the ASIC level is low, the power requirement is in the order of 15W per board for a total at the detector level approaching 1000W. This required proper cooling to maintain a reliable operation of the electronics. Figure 11 shows the board temperature with and without cooling plate. Thermal images have been taken to confirm the temperature reduction of the main heat source (Clock cleaner, FPGA, ADC, AFTER in that order). We can guarantee a chip temperature below 60°C to keep the default chip MTBF.

[[File:image12daq.jpg|558x246px]]

Figure 10 - Cathode Pad Board readout for 288 channels at 62.5Msps, visible 4 AFTER chips, 3 copper bars running under the central board for power distribution

[[File:image13daq.png|249x185px]]
[[File:image14daq.png|247x186px]]
[[File:image15daq.jpg|248x186px]]

Figure 11 – Thermal image of the FEAM with hot spot temperature: without cooling plate (78°C), with cooling plate (45°C), with cooling plate & water cooling (36°C)

== Cathode Pad Circuit ==

The cathode pads are read-out by AFTER ASIC which diagram is presented in Figure 12. Each channel consists of a charge-sensitive preamplifier, pole-zero cancellation of preamplifier decay time, RC2 shaper and 512-cell SCA to store the waveform. Amplifier gain, pole-zero time constant and shaping time are programmable.

{|
|
[[File:image16daq.png|361x171px]]

Figure 12 - Block diagram of AFTER amplifier
| [[File:image17daq.png|215x199px]]
|}

The acquisition of the FEAM cards is operational and initial waveforms can be displayed as seen in Figure 13. This visualization is for monitoring the individual channels only. The data acquisition is using a different path for fast data collection. Figure 13 shows cathode signal examples collected by the FEAM card. The signal shape is consistent with avalanches occurring from a cosmic track going through the detector. The initial pulse corresponds to the early avalanches when the track crosses the amplification region (near the anode wire). The remaining pulses show the later electron avalanches reaching the same anode wire from the drift region due to the track angle. The complex pulse shape from the drift region reflects the convolution in this time base of the arrival of the electron to the amplification region and the induced pulse from the resulting electron avalanche.

= Barrel Scintillator signal path =

'''''Note''''': While the Barrel Scintillator is part of the Alpha-g detector for cosmic rejection purpose, this section is still under development. The initial concept and implementation are therefore not final. The volume allocated for it in the other hand well defined due to external to the detector constraints.

Light at both ends of each bar of the barrel scintillator is collected for a rough position detection of the crossing particle and timing information. To improve the detection information (maximize photon collection), 6 individual SiPM light detector (SensL) are mounted on both ends of the individual scintillator bar for a coverage of 50% of the bar. This assembly is in a light-tight and gas-tight enclosure. A cold gas flows through the box to lower the SiPM temperature operation in order to reduce the dark noise of the device. A shaper/amplifier board (BSB) will be mounted on the outside of the enclosure. Each of the board will acquire the signals of 4 adjacent scintillator bars. In total 64 scintillator bars are read out by 16 boards at each end. A block diagram of one bar readout is shown in Figure 14. The signal gathering of the 6 sensors is based on an analog sum.

[[File:image18daq.png|480x296px]]

Figure 14 - Block diagram of one channel of SiPM amplifier

The 6 pre-amplifier outputs are combined to provide the sum of 6 signals. This resulting signal is further amplified and shaped (if necessary) on a second stage post-amplifier/discriminator. This signal sent to the readout system through a cable driver. Two signals will be acquired from each bar: (1) Analog sum fed to a waveform digitizer with proper digital processing to determine event position and timing; (2) LVDS signal fed to a TDC for off-line precise timing measurement purposes. For the LVDS signal, the post-amplifier will have a controlled threshold voltage to the signal comparator.

The BSB will be powered by standard +5V and -5V linear supplies. Each board has a test input to allow individual board measure of the amplifier response, malfunction test and to provide the necessary services to the light sensors device (Voltage bias, temperature sensor, etc).

The output of the analog output of the BSB will be shaped for the 100Msps WFD and in parallel will issue a digital signal for timing information to a TDC.

= Trigger Distribution =

On the full-length detector, the FEAM boards will receive trigger and clock signals from the CDM through the Trigger Card Adapter. The adapter receives signals from the CDM via a 7 pin SATA connector. The signals can be re-driven by repeaters on the adapter and are sent down a chain of 7 Trigger Cards with the adapter forming the first link.

While there are other elegant means of distributing the common clock and trigger to all the electronics boards, this method is the most simple and robust.

[[File:image19daq.png|195x575px|Adapter]]

[[File:image20daq.png|573x43px|Trigger_Board]]

Figure 15 - Trigger Card Adapter and Trigger Card

[[File:image21daq.jpg|216x294px|20170914_101103_resized]]

Figure 16 Trigger Card to FEAM

A Samtec SFM-110 connects each card to a FEAM board and also provides through holes pins where another card can be overlapped and soldered. In this manner the chain of Trigger Distribution Cards is formed, providing a shared clock and trigger signal to a column of 8 FEAM boards.

= Clock Distribution Module =

[[File:image22daq.png|231x356px]]

Figure 17 - Clock Distribution Module

* 6x LEMO Connectors [2 Output, 4 Input]
* 6x Mini-SAS providing up to 24 channels of clock and synchronization breakout
* 1x Combination eSATA/USB connector
** eSATA provides CLK and SYNC
** USB provides USB to Serial communication 115200 BAUD
* 1x 10/100 Base-TX Ethernet
* Optional Atomic Clock module support, 10MHz and 1PPS '''[CSAC - SA.45s]'''
** Short term Stability <1E-11
** over 1000 seconds (100μHz / 1000s)
** Aging rate of <9E-10 per month '''('''9mHz/month)
* Onboard 10MHz Crystal Oscillator '''[FOX924B-10.000]'''
** ±2.5ppm
** ±1ppm per year
* JTAG ARM Support
* SmartFusion2 SoC '''[MS2-FG484]'''
* Ultra-low noise clock jitter cleaner 3:15 input to output support '''[LMK04821] '''
** Min/Max VCO Frequency 2750/3072MHz
** 0.111RMS Jitter
* TTL and NIM signal compatibility for external CLK and SYNC
* VME - 6U - 3Row
* Approximate Current Draw 1.837A at 5V

The Clock Distribution Module ('''CDM)''' has the capability to distribute two externally sourced clock and synchronization signals to six mini-SAS connections for total 24 signal signals. The external signals are provided through the eSATA and LEMO 1A/B Connectors. The module also has the capability to add an Atomic clock that outputs a 10Mhz signal and a 1 Pulse Per Second (PPS), as well as user-defined synchronization signal. Lastly, the module can be configured to output the external clock signals to the LEMO 2B connector or VME bus.

[[File:image23daq.png|509x348px]]

Figure 18 - IO Block Diagram

[[File:image24daq.png|299x412px]]

Figure 19 - ALPHA-16 and CDM board in front with the Trigger/Clock distribution cables

= Frontend Board Firmware =

The firmware (FW) refers to the embedded code running on the Field Programmable Gate Arrays (FPGAs) and microcontrollers (MCUs) located on the various modules within the experiment. These devices store, load, and run the programs required for operation of the different digital electronic components within the experiment.

Firmware code is essential to the operation of the detector as it provides the mechanism to configure the hardware for its particular purpose. Such as analog-to-digital conversion, data filtering, data trigger composition, transport of the data, and orchestration of all the different hardware modules to succeed in acquiring meaningful information across the overall system. Some of the firmware tasks are:

<ol style="list-style-type: upper-roman;">
<li>Low-level acquisition of the 3 different WFDigitizers (Anode wire, Cathode pad, Barrel Scintillator)</li>
<li>Links all the electronics boards to the DAQ system.</li>
<li>Collected in real-time information for trigger decision making.</li>
<li>Distribute synchronization signals and trigger to all the acquisition boards.</li>
<li>Provides to the user; configurable board and operation parameters settings.</li>
<li>Provides board monitoring and debugging tools.</li></ol>

Most of the FW code base has been based off of prior code developed for the currently running GRIFFIN experiment, with some exceptions, such as the Trigger Master Module which needed custom code specific to ALPHA-g, and the PADWING, which contained the AFTER SCA chip not present in GRIFFIN.



The firmware code is loaded onto the hardware board where an FPGA or MCU is present. Each firmware module has specific firmware capabilities, detailed as follows:

* Hit Detector firmware Module (ALPHA-16 carrier board)
** Anode Wire and Barrel Scint. signal waveform digitizers acquisition
** Local data filtering for Trigger purpose
** Transmission of summary data to Trigger Module for trigger decision
** Data compression/filtering and retention for transmission to backend on Trigger reception
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Pad Acquisition firmware Module (PADWING board)
** Cathode pad signal waveform digitizers acquisition
** Data compression/filtering and retention for transmission to backend on Trigger reception
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Master Trigger firmware Module (ALPHA-T board)
** Summary data reception of the multiple GRIF-16 boards
** Trigger decision algorithm
** Packaging of Trigger decision information and transmission to the backend.
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Clock and Trigger Distribution firmware Module (CDM board)
** Monitoring of hardware functions (U,I,T,Clock Frequency)
** Configuration of hardware mechanism for clock and trigger distribution
** Update of firmware code mechanism

== '''Hit Detector Module (ALPHA-16)''' ==

The Hit Detector firmware module handles the acquisition of the analog input signals from the anode wires and scintillators, the digital conversion of that data, and then the transfer of that data to both the DAQ and the Trigger Master. The first implementation of the hit detection is based on hit multiplicity. Later on, a more sophisticated algorithm will be implemented to determine in real time the timing and charge collected for each channel. This information will be transferred to the Trigger Master for more efficient trigger filtering.

The ADC data is acquired from both the FMC ADC32 ADCs and the onboard 16ch 14-bit ADCs using the FPGAs hardware SERDES modules. These modules de-serialize the data stream from the ADCs into a format suitable for internal analysis for hit detection, and for transfer to the MIDAS DAQ.

Once one or more hits are detected, the ALPHA-16 transmits the hit count to the ALPHA-T for a hit multiplicity test, and then waits for a trigger response to decide to discard or transmit the waveform data associated with the detected hit to the DAQ.

Currently, when a trigger is fired by the Trigger Decision module, all channels transmit their captured waveforms to the DAQ. In the future, only channels that have detected a hit will send waveforms on a trigger.

System monitoring and configuration of the Hit Detector module is handled by ESPER running on a NIOS-II soft-core processor instantiated within the FPGA. The OS used is Micrium µC/OS-II, a small real-time OS licensed by Altera for use with their NIOS-II processor. ESPER performs the remote upgrading of the Hit Detector, viewing of the captured waveforms, and diagnostic reading and writing of all firmware settings and counters via a simple JSON-based interface, or an HTML based webpage.

[[File:image25daq.png|517x318px]]

Figure 20 - Hit Detector for the Anode wire and scintillators in ALPHA-16

== '''Pad Acquisition Module (FEAM)''' ==

The pad acquisition firmware module handles the collection of the PAD analog signals captured by the four AFTER ASICs on the module. Capture occurs upon receiving a trigger signal from the Trigger Decision module. Once captured, the AFTER data is transmitted to the MIDAS DAQ over ethernet. No pad information is provided back to the Trigger Decision module.

Each of the AFTER ASICs transmits its captured analog data to a 12-bit ADC which in turn converts the analog signal into digital data and transmits that to the FPGA. The FPGA uses its internal SERDES hardware to de-serialize this data and process it. Once captured, channels that do not contain data of interest are suppressed, and the data is packaged up and sent out over UDP to the MIDAS DAQ.

In the event that the SFP module that provides ethernet connectivity fails, each PAD acquisition module is connected to one other PAD acquisition module via a secondary gigabit link. While currently unused, this link will be used in the future to support a backup link to the DAQ, in the event of a failure of the primary gigabit link.

System monitoring and configuration of the PAD acquisition module is handled by ESPER running on a NIOS-II soft-core processor instantiated within the FPGA. The OS used is Micrium µC/OS-II, a small real-time OS licensed by Altera for use with their NIOS-II processor. ESPER performs the remote upgrading of the Hit Detector, viewing of the captured waveforms, and diagnostic reading and writing of all firmware settings and counters via a simple JSON-based interface, or an HTML based webpage.

[[File:image26daq.png|490x299px]]

Figure 21 - AFTER chip WFD on the PADWINGS

== '''Trigger Master module (ALPHA-T)''' ==

The Trigger Master firmware module is to collect information from the anode wires and scintillators to make a real-time decision if the current physics event is to be recorded. That decision is fed to all the readout boards to trigger the storage of this particular event.

Initial trigger decision will be based on hit multiplicity of each of the ALPHA-16 boards. As the ALPHA-16 is acquiring the anode wire and the barrel scintillator signals, both of these 2 pieces of equipment will contribute to the trigger decision. Dedicated link from each of the ALPHA-16 (hit detector) to the Trigger module will be gathering the overall information for a final decision. Hardware trigger signal is then sent from the ALPHA-T to the CDM for distribution to all the acquisition modules to initiate the transmission of their data to the backend computer through UDP. The trigger board will compose a summary of the trigger information which will also be transferred to the backend.

The Trigger Master module contains two Mini-SAS FMCs, and one ‘communication’ FMC, that consists of a SATA, an SFP, and a Mini-SAS connector. This configuration of FMCs allows for up to twenty (20) 1G/2.5G/5G links via the Mini-SAS, in addition to a 1 Gbit/sec Ethernet connection via the SFP, and clock+trigger over the SATA.

[[File:image27daq.png|576x304px]]

Figure 22 - Trigger decision on ALPHA-T

== System Monitoring and debugging capability ==

The system monitoring is based on the ESPER protocol provided by the Electronics Development group at TRIUMF. Featuring a built-in web server, with real-time digitizer display, remote upgrade, and JSON-accessible parameters. ESPER allows for real-time diagnostics and testing to be performed on the various electronic modules using either JSON-based requests or a built-in webpage.

[[File:image28daq.png|800x400px]]

Figure 23 - ESPER Web Display. Test pulse recorded by the FEAM cards. Individual AFTER chip configuration is visible (gain change, delay).

= Safety and Hazard considerations =

There are no safety or hazard issues in FE system. All amplifiers are low-voltage and low-power circuits built with standard electronics components.

Detector Electronics

2017-11-19T22:02:38Z

Midas: /* Overall Detector Signal Path */

Back to [[Documentation]]

= Table of Figures =

[[#_Toc493676266|Figure 1 - Overall Data Acquisition scheme 7]]

[[#_Toc493676267|Figure 2 - Anode wire pre-amplification block diagram 8]]

[[#_Toc493676268|Figure 3 - Anode Wire Board (AWB), 16 channels pre-amplifier 9]]

[[#_Toc493676269|Figure 4 - 4 consecutive anode wire signals 9]]

[[#_Toc493676270|Figure 5 - Anode wire pre-amp gain map for half the chamber circumference 10]]

[[#_Toc493676271|Figure 6 - Alpha16 Data Acquisition Board 12]]

[[#_Toc493676272|Figure 7 - Grif16 Acquisition Module Block Diagram on which the Alpha-16 is based 12]]

[[#_Toc493676273|Figure 8 - Model of the new 32channels 12bit @ 65Msps FMC produced in 2016. 13]]

[[#_Toc493676274|Figure 9 - FMC Alpha-ADC32 Block Diagram 13]]

[[#_Toc493676275|Figure 10 - Cathode Pad Board readout for 288 channels at 62.5Msps, visible 4 AFTER chips, 3 copper bars running under the central board for power distribution 15]]

[[#_Toc493676276|Figure 11 – Thermal image of the FEAM with hot spot temperature: without cooling plate (78°C), with cooling plate (45°C), with cooling plate & water cooling (36°C) 16]]

[[#_Toc493676277|Figure 12 - Block diagram of AFTER amplifier 17]]

[[#_Toc493676278|Figure 13 - 4 x 72 cathode pad signals, overall time width corresponds to the drift time 17]]

[[#_Toc493676279|Figure 14 - Block diagram of one channel of SiPM amplifier 18]]

[[#_Toc493676280|Figure 15 - Trigger Card Adapter and Trigger Card 19]]

[[#_Toc493676281|Figure 16 Trigger Card to FEAM 19]]

[[#_Toc493676282|Figure 17 - Clock Distribution Module 20]]

[[#_Toc493676283|Figure 18 - IO Block Diagram 21]]

[[#_Toc493676284|Figure 19 - ALPHA-16 and CDM board in front with the Trigger/Clock distribution cables 22]]

[[#_Toc493676285|Figure 20 - Hit Detector for the Anode wire and scintillators in ALPHA-16 24]]

[[#_Toc493676286|Figure 21 - AFTER chip WFD on the PADWINGS 25]]

[[#_Toc493676287|Figure 22 - Trigger decision on ALPHA-T 26]]

[[#_Toc493676288|Figure 23 - ESPER Web Display. Test pulse recorded by the FEAM cards. Individual AFTER chip configuration is visible (gain change, delay). 27]]

= Introduction =

This design note describes the electronics chain and components for the readout of the ALPHA-g TPC and barrel scintillator bars.

= Scope =

The Detector Electronics is composed of 3 independent signal sources:

# Anode Wire signals path
# Cathode Pad signals path
# Barrel Scintillator signals path.

All 3 sources provide a similar function such as signal amplification and conditioning (shaping).

= Definitions and Abbreviations =

General acronyms or terms used for the ALPHA-g experiment

{|
! TPC
! Radial Time projection Chamber
|-
| Pads
| PCB surface seeing the induced anode wire signal
|-
| SiPM
| Si photomultipliers used to detect scintillation light
|-
| ADC
| Analog to digital converter
|-
| ASIC
| Application specific integrated circuit
|-
| SCA
| Switch Capacitor Array ( A type of Waveform Digitizer)
|-
| TDC
| Time to digital converter
|-
| BSM
| Barrel Scintillator Module (64 bars sub-assembly)
|-
| FEAM, Padwing
| Cathode strip acquisition board
|-
| CDM
| Clock Distribution Module
|-
| BSB
| Barrel Scintillator Board
|-
| WFD
| Waveform Digitizer
|}

Table 1 – ALPHA-g Abbreviations

= References and related Document =

* AFTER manual
* SensL SPM data sheet
* Edev-group.triumf.ca: contains the FW information on all the Alpha-g custom cards ([https://edev-group.triumf.ca/fw/exp/alphag/feam/rev0/wikis/feam-test-packet-format https://edev-group.triumf.ca/fw/exp/alphag])

* ''' 
'''

= Overall Detector Signal Path =

The Alpha-g detector provides 3 analog signals that are collected for the track reconstruction to help on the annihilation location in the trap.

* The anode wire signal providing the drift time of the electron through the detector for an angular position.
* The cathode pad signal, which are in-time correlated to the anode wire signal, providing the amplitude of these signals from which the longitudinal position (Z) can be extracted.
* The Barrel Scintillator bar signals provide the time and amplitude of the particle crossing the detector. The Barrel Scintillator is mainly to reject cosmic events. For that purpose, the timing resolution is important. Therefore the BSM analog signal is split early in the chain to record the amplitude and time separately.

The anode wires and the barrel scintillator bars are read out from both ends to provide a coarse Z-position as well. The Data acquisition is therefore made for reading 2x256 anode wire channels, 2x64 barrel scintillator bars and 18432 channels of cathode pads covering the outer detector cylinder.

[[File:image2daq.png|876x559px]]

Figure 1 - Overall Data Acquisition scheme

= Anode wire signal path =

The design for the anode wires pre-amplifier is based on work done for several other projects used at TRIUMF and other labs.

Each of the 256 anode wires are read-out from two ends. The signals are used to (1) determine phi-position of ionization track; (2) reconstruct its z-position by weighting signals from two wire ends; (3) generate trigger signal. The pre-amplifiers convert the induced current to voltage that is digitized and processed in the readout system. The main requirements for the amplifier circuit are:

# Input impedance must be low enough so detected charge is sensitive to position of event along wire;
# The shape of signal is optimized for sampling frequency (16 ns) and for fast trigger timing (few ns accuracy);
# Linearity range adjusted for ADC used;
# Gain is adjusted for gas amplification of 105
# Amplifier noise is low enough to detect single-electron cluster.

[[File:image3daq.png|576x204px]]

Figure 2 - Anode wire pre-amplification block diagram

Anode wires are HV-decoupled before connected to the amplifier, but additional (not HV) decoupling is needed at amplifier input to accommodate non-zero potential of the input stage. Protection of the amplifier input is using a standard bi-diode configuration. The first stage is a current-sensitive loop with input impedance defined by resistor Rin and trans-impedance (gain) by feedback resistor Rf. The second stage is 2-pole shaper with shaping time constant defined by components Rs and Cs. The last stage is a cable driver.

Overall gain, transfer function and input impedance of the circuit can be adjusted by changing passive components. This adjustment will be done with studying the TPC prototypes.

Amplifiers are deployed on 16-channel cards, 16 boards serve each end of TPC. They are powered by standard +5V and -5V linear supplies. Each card has a test input that is used to measure amplifiers response and to check for malfunction.

[[File:image4daq.jpg|173x183px]] [[File:image5daq.png|169x184px]]

Figure 3 - Anode Wire Board (AWB), 16 channels pre-amplifier

The AWB schematic allows for bipolar signal input. This has the advantage to reproduce the full anode wire signal development including the inverted induced pulse from neighbouring wires as seen Figure 4.

[[File:image6daq.jpg|512x358px]]

Figure 4 - 4 consecutive anode wire signals

The anode pre-amps have an individual test pulse input to provide a quick functional test. It can also be used for calibration purpose. Several tests have been done in this regard, but the overall chain gain is dependent on many variables (chamber geometry, environmental condition (Gas mixture, T, P), pre-amp (layout, components)). Another more common test pulse injection is available by pulsing all the field wires at once (at the boundary of the drift and multiplication region). This technique has the advantage to produce an induced signal on all the anode wires and cathode pads together at the “same” time. Figure 5 shows the gain variation by wire seen when pulsed through the field wire. 2 interesting features are visible:

a) An overall negative slope, indicated by the linear fit. This slope is explained by the pulse attenuation through the field wires distribution.

b) A clear increase in gain for the wires near the anode wire card boundaries, indicated by the cyan lines is not yet well understood. A further test is planned.

[[File:image7daq.png|397x289px]]

Figure 5 - Anode wire pre-amp gain map for half the chamber circumference

== Anode Wire Waveform digitizer (Alpha-16) ==

The output of the AWB is presented to the Alpha-16 waveform digitizer sampling the analog signal at 62.5Msps.

'''''Note:''''' At the time of this report, the WFD 62.5Msps is not yet available. We use the WFD at 100Msps to perform the tests. The firmware is similar to the 62.5Msps and the final test will be reproduced later.

This module provides 16 channels 14bit ADC @100Msps for 50Ohms single-ended analog signal for the barrel scintillator. It also supports a dedicated mezzanine card (FMC) handling 32 channels 12bit ADC @ 65Msps for single-ended 50Ohms analog signals for the Anode wires.

The Alpha-16 board outputs (16ch.@100Msps and 32ch.@62.5Msps) are collected on the main carrier FPGA for transmission through Ethernet to the backend computer.

The board carries multiple I/O connections required for the module configuration, communication, data transfer, signal inputs, see Figure 7.

* Front panel SFP Gbit Ethernet (copper/fiber)
* Front panel eSATA: clock and sync inputs
* Front panel dual LEMO: Diagnostic DAC outputs (250Msps)
* Front panel MCX connector for 16 x ADC inputs
* Rear entry P2 connector for 16 x ADC inputs
* A24/D16 VME interface to MAXV configuration CPLD
** VME configuration flash updates
** VME bridge to FPGA
* FMC custom module connections.
** Dual MiniSAS for Acquisition setup
** 10 x5Gibt Link
** JESD204B Clocks
** Supports 32 Channel ADC LVDS interface
* Amplifier input switches: Front panel MCX connector, Rear Transition Card SMA connector
* Amplifier Gain x1 and x4
* Switch selectable LEMO NIM Input/ DAC outputs
* Micro SD Flash
* DDR3 DRAM – 667MHz – 128M x 23'''(MT41J128M16HA-15E)'''
* FPGA - Arria V '''(5AGXFB3H4F35C4N)'''
* MAXV CPLD controller '''(5M2210ZF256C5N)''' for USB JTAG and VME access

[[File:image8daq.jpg|218x380px]]

Figure 6. Alpha16 Data Acquisition Board

[[File:image9daq.png|264x383px]]

Figure 7. Grif16 Acquisition Module Block Diagram on which the Alpha-16 is based

== FMC – Alpha ADC32 ==

<blockquote>The FMC – ALPHA ADC32 provides single-stage amplification of up to 32 single-ended 50<math>\Omega</math> analog signals, from the Anode Wire Board Pre-Amplifier, to drive two 16 channel 14bit differential, analog to digital converters sampling at 65MSPS. Further, each ADC will provide a 0.9V common mode offset voltage to be fed into the differential driver

A 16 channel 12 bit digital-to-analog (DAC) converter is used to individually apply an appropriate offset voltage to each of the differential amplifier pairs. The Offset voltages span <math>\pm</math>2.5Vat 1.22mV increments and will output 0V upon power cycle. The DAC is configurable via an SPI interface via the FMC connector.

ADC32 board has the capability to receive and transmit an LVDS clock signal through the eSATA connector which is fed to the FMC connector
</blockquote>
[[File:image10daq.png|318x307px]]

Figure 8 - Model of the new 32channels 12bit @ 65Msps FMC produced in 2016.

[[File:image11daq.png|420x285px]]

Figure 9 - FMC Alpha-ADC32 Block Diagram

<blockquote>''These notes are for the current revision of the Alpha ADC32, a new revision is currently being talked about''
</blockquote>
The board is composed of the following elements:

* 400 Pin FMC connector
** Provides SPI interface
** ADC Synchronization
** Support for 32 LVDS analog signals
** Supply voltage of fused +12V, Switched 3.3V and 1.2-3.3V adjustable
* 32 channel Analog inputs via Hirose connector '''[FX2-40S-1.27DS(71)] 
'''
* 1V analog reference voltage '''[LTC6655BHMS8-3#PBF]'''
** ±2ppm
* Differential ADC Driver '''[ADA4950'''-'''2YCPZ]'''
** ±0.2mV Offset
** 9.2nHz / √Hz Output voltage Noise at Gain=1
** Adjustable output common-mode voltage
** Hardware programmable gain of 1x, 2x and 3x
* Dual 16 channel 14bit Analog to Digital converter '''[AD9249BBCZ-65]'''
** 2Vp-p input range
** 65MSPS
** ±0.6LSB
** Input Clock of 10-520MHz
* 16 channel 12bit Digital to Analog converter '''[ADA4950-2YCPZ]'''
** Programmable offset voltage
** SPI configurable outputs
** Output range ±2.5V, 0V upon reset
** 1.22mV/LSB
* 1 x eSATA Clk-In / Clk-out to and from FMC connector

= Cathode pad signal path =

The 18432 cathode pads covering the inner surface of the outer wall of the detector are individually connected to a signal acquisition chain. This collected signals will provide the position of the electron avalanche at the anode wire. Combining them in charge, permit the reconstruction of the track passing through the longitudinal direction the detector. While the cathode pads cover a large area (2.7m2), the actual footprint per channel is limited (3.8mmx37.1mm). Therefore a high-density waveform digitizer chain has been chosen based on our previous experience with the T2K experiment, we opted for the AFTER Switched Capacitor Array (SCA) ASIC. The analog signal path is short as the pads themselves are on the backside the physical outer cylinder of the detector and the input signal connectors to the AFTER chips are on the opposite side of the outer cylinder.

A custom frontend board (FEAM) see Figure 10 handling 288 individual cathode pads has been designed. It is composed of 4 ASIC AFTER (72 channels) with associated waveform digitizer for the individual signal on 512 cells at 20Msps. In addition, an FPGA manages the board services and the data collection and transmission through a 1 gigabit/sec optical link to the Ethernet using the UDP protocol.

While the power consumption per channel at the ASIC level is low, the power requirement is in the order of 15W per board for a total at the detector level approaching 1000W. This required proper cooling to maintain a reliable operation of the electronics. Figure 11 shows the board temperature with and without cooling plate. Thermal images have been taken to confirm the temperature reduction of the main heat source (Clock cleaner, FPGA, ADC, AFTER in that order). We can guarantee a chip temperature below 60°C to keep the default chip MTBF.

[[File:image12daq.jpg|558x246px]]

Figure 10 - Cathode Pad Board readout for 288 channels at 62.5Msps, visible 4 AFTER chips, 3 copper bars running under the central board for power distribution

[[File:image13daq.png|249x185px]]
[[File:image14daq.png|247x186px]]
[[File:image15daq.jpg|248x186px]]

Figure 11 – Thermal image of the FEAM with hot spot temperature: without cooling plate (78°C), with cooling plate (45°C), with cooling plate & water cooling (36°C)

== Cathode Pad Circuit ==

The cathode pads are read-out by AFTER ASIC which diagram is presented in Figure 12. Each channel consists of a charge-sensitive preamplifier, pole-zero cancellation of preamplifier decay time, RC2 shaper and 512-cell SCA to store the waveform. Amplifier gain, pole-zero time constant and shaping time are programmable.

{|
|
[[File:image16daq.png|361x171px]]

Figure 12 - Block diagram of AFTER amplifier
| [[File:image17daq.png|215x199px]]
|}

The acquisition of the FEAM cards is operational and initial waveforms can be displayed as seen in Figure 13. This visualization is for monitoring the individual channels only. The data acquisition is using a different path for fast data collection. Figure 13 shows cathode signal examples collected by the FEAM card. The signal shape is consistent with avalanches occurring from a cosmic track going through the detector. The initial pulse corresponds to the early avalanches when the track crosses the amplification region (near the anode wire). The remaining pulses show the later electron avalanches reaching the same anode wire from the drift region due to the track angle. The complex pulse shape from the drift region reflects the convolution in this time base of the arrival of the electron to the amplification region and the induced pulse from the resulting electron avalanche.

= Barrel Scintillator signal path =

'''''Note''''': While the Barrel Scintillator is part of the Alpha-g detector for cosmic rejection purpose, this section is still under development. The initial concept and implementation are therefore not final. The volume allocated for it in the other hand well defined due to external to the detector constraints.

Light at both ends of each bar of the barrel scintillator is collected for a rough position detection of the crossing particle and timing information. To improve the detection information (maximize photon collection), 6 individual SiPM light detector (SensL) are mounted on both ends of the individual scintillator bar for a coverage of 50% of the bar. This assembly is in a light-tight and gas-tight enclosure. A cold gas flows through the box to lower the SiPM temperature operation in order to reduce the dark noise of the device. A shaper/amplifier board (BSB) will be mounted on the outside of the enclosure. Each of the board will acquire the signals of 4 adjacent scintillator bars. In total 64 scintillator bars are read out by 16 boards at each end. A block diagram of one bar readout is shown in Figure 14. The signal gathering of the 6 sensors is based on an analog sum.

[[File:image18daq.png|480x296px]]

Figure 14 - Block diagram of one channel of SiPM amplifier

The 6 pre-amplifier outputs are combined to provide the sum of 6 signals. This resulting signal is further amplified and shaped (if necessary) on a second stage post-amplifier/discriminator. This signal sent to the readout system through a cable driver. Two signals will be acquired from each bar: (1) Analog sum fed to a waveform digitizer with proper digital processing to determine event position and timing; (2) LVDS signal fed to a TDC for off-line precise timing measurement purposes. For the LVDS signal, the post-amplifier will have a controlled threshold voltage to the signal comparator.

The BSB will be powered by standard +5V and -5V linear supplies. Each board has a test input to allow individual board measure of the amplifier response, malfunction test and to provide the necessary services to the light sensors device (Voltage bias, temperature sensor, etc).

The output of the analog output of the BSB will be shaped for the 100Msps WFD and in parallel will issue a digital signal for timing information to a TDC.

= Trigger Distribution =

On the full-length detector, the FEAM boards will receive trigger and clock signals from the CDM through the Trigger Card Adapter. The adapter receives signals from the CDM via a 7 pin SATA connector. The signals can be re-driven by repeaters on the adapter and are sent down a chain of 7 Trigger Cards with the adapter forming the first link.

While there are other elegant means of distributing the common clock and trigger to all the electronics boards, this method is the most simple and robust.

[[File:image19daq.png|195x575px|Adapter]]

[[File:image20daq.png|573x43px|Trigger_Board]]

Figure 15 - Trigger Card Adapter and Trigger Card

[[File:image21daq.jpg|216x294px|20170914_101103_resized]]

Figure 16 Trigger Card to FEAM

A Samtec SFM-110 connects each card to a FEAM board and also provides through holes pins where another card can be overlapped and soldered. In this manner the chain of Trigger Distribution Cards is formed, providing a shared clock and trigger signal to a column of 8 FEAM boards.

= Clock Distribution Module =

[[File:image22daq.png|231x356px]]

Figure 17 - Clock Distribution Module

* 6x LEMO Connectors [2 Output, 4 Input]
* 6x Mini-SAS providing up to 24 channels of clock and synchronization breakout
* 1x Combination eSATA/USB connector
** eSATA provides CLK and SYNC
** USB provides USB to Serial communication 115200 BAUD
* 1x 10/100 Base-TX Ethernet
* Optional Atomic Clock module support, 10MHz and 1PPS '''[CSAC - SA.45s]'''
** Short term Stability <1E-11
** over 1000 seconds (100μHz / 1000s)
** Aging rate of <9E-10 per month '''('''9mHz/month)
* Onboard 10MHz Crystal Oscillator '''[FOX924B-10.000]'''
** ±2.5ppm
** ±1ppm per year
* JTAG ARM Support
* SmartFusion2 SoC '''[MS2-FG484]'''
* Ultra-low noise clock jitter cleaner 3:15 input to output support '''[LMK04821] '''
** Min/Max VCO Frequency 2750/3072MHz
** 0.111RMS Jitter
* TTL and NIM signal compatibility for external CLK and SYNC
* VME - 6U - 3Row
* Approximate Current Draw 1.837A at 5V

The Clock Distribution Module ('''CDM)''' has the capability to distribute two externally sourced clock and synchronization signals to six mini-SAS connections for total 24 signal signals. The external signals are provided through the eSATA and LEMO 1A/B Connectors. The module also has the capability to add an Atomic clock that outputs a 10Mhz signal and a 1 Pulse Per Second (PPS), as well as user-defined synchronization signal. Lastly, the module can be configured to output the external clock signals to the LEMO 2B connector or VME bus.

[[File:image23daq.png|509x348px]]

Figure 18 - IO Block Diagram

[[File:image24daq.png|299x412px]]

Figure 19 - ALPHA-16 and CDM board in front with the Trigger/Clock distribution cables

= Frontend Board Firmware =

The firmware (FW) refers to the embedded code running on the Field Programmable Gate Arrays (FPGAs) and microcontrollers (MCUs) located on the various modules within the experiment. These devices store, load, and run the programs required for operation of the different digital electronic components within the experiment.

Firmware code is essential to the operation of the detector as it provides the mechanism to configure the hardware for its particular purpose. Such as analog-to-digital conversion, data filtering, data trigger composition, transport of the data, and orchestration of all the different hardware modules to succeed in acquiring meaningful information across the overall system. Some of the firmware tasks are:

<ol style="list-style-type: upper-roman;">
<li>Low-level acquisition of the 3 different WFDigitizers (Anode wire, Cathode pad, Barrel Scintillator)</li>
<li>Links all the electronics boards to the DAQ system.</li>
<li>Collected in real-time information for trigger decision making.</li>
<li>Distribute synchronization signals and trigger to all the acquisition boards.</li>
<li>Provides to the user; configurable board and operation parameters settings.</li>
<li>Provides board monitoring and debugging tools.</li></ol>

Most of the FW code base has been based off of prior code developed for the currently running GRIFFIN experiment, with some exceptions, such as the Trigger Master Module which needed custom code specific to ALPHA-g, and the PADWING, which contained the AFTER SCA chip not present in GRIFFIN.



The firmware code is loaded onto the hardware board where an FPGA or MCU is present. Each firmware module has specific firmware capabilities, detailed as follows:

* Hit Detector firmware Module (ALPHA-16 carrier board)
** Anode Wire and Barrel Scint. signal waveform digitizers acquisition
** Local data filtering for Trigger purpose
** Transmission of summary data to Trigger Module for trigger decision
** Data compression/filtering and retention for transmission to backend on Trigger reception
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Pad Acquisition firmware Module (PADWING board)
** Cathode pad signal waveform digitizers acquisition
** Data compression/filtering and retention for transmission to backend on Trigger reception
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Master Trigger firmware Module (ALPHA-T board)
** Summary data reception of the multiple GRIF-16 boards
** Trigger decision algorithm
** Packaging of Trigger decision information and transmission to the backend.
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Clock and Trigger Distribution firmware Module (CDM board)
** Monitoring of hardware functions (U,I,T,Clock Frequency)
** Configuration of hardware mechanism for clock and trigger distribution
** Update of firmware code mechanism

== '''Hit Detector Module (ALPHA-16)''' ==

The Hit Detector firmware module handles the acquisition of the analog input signals from the anode wires and scintillators, the digital conversion of that data, and then the transfer of that data to both the DAQ and the Trigger Master. The first implementation of the hit detection is based on hit multiplicity. Later on, a more sophisticated algorithm will be implemented to determine in real time the timing and charge collected for each channel. This information will be transferred to the Trigger Master for more efficient trigger filtering.

The ADC data is acquired from both the FMC ADC32 ADCs and the onboard 16ch 14-bit ADCs using the FPGAs hardware SERDES modules. These modules de-serialize the data stream from the ADCs into a format suitable for internal analysis for hit detection, and for transfer to the MIDAS DAQ.

Once one or more hits are detected, the ALPHA-16 transmits the hit count to the ALPHA-T for a hit multiplicity test, and then waits for a trigger response to decide to discard or transmit the waveform data associated with the detected hit to the DAQ.

Currently, when a trigger is fired by the Trigger Decision module, all channels transmit their captured waveforms to the DAQ. In the future, only channels that have detected a hit will send waveforms on a trigger.

System monitoring and configuration of the Hit Detector module is handled by ESPER running on a NIOS-II soft-core processor instantiated within the FPGA. The OS used is Micrium µC/OS-II, a small real-time OS licensed by Altera for use with their NIOS-II processor. ESPER performs the remote upgrading of the Hit Detector, viewing of the captured waveforms, and diagnostic reading and writing of all firmware settings and counters via a simple JSON-based interface, or an HTML based webpage.

[[File:image25daq.png|517x318px]]

Figure 20 - Hit Detector for the Anode wire and scintillators in ALPHA-16

== '''Pad Acquisition Module (FEAM)''' ==

The pad acquisition firmware module handles the collection of the PAD analog signals captured by the four AFTER ASICs on the module. Capture occurs upon receiving a trigger signal from the Trigger Decision module. Once captured, the AFTER data is transmitted to the MIDAS DAQ over ethernet. No pad information is provided back to the Trigger Decision module.

Each of the AFTER ASICs transmits its captured analog data to a 12-bit ADC which in turn converts the analog signal into digital data and transmits that to the FPGA. The FPGA uses its internal SERDES hardware to de-serialize this data and process it. Once captured, channels that do not contain data of interest are suppressed, and the data is packaged up and sent out over UDP to the MIDAS DAQ.

In the event that the SFP module that provides ethernet connectivity fails, each PAD acquisition module is connected to one other PAD acquisition module via a secondary gigabit link. While currently unused, this link will be used in the future to support a backup link to the DAQ, in the event of a failure of the primary gigabit link.

System monitoring and configuration of the PAD acquisition module is handled by ESPER running on a NIOS-II soft-core processor instantiated within the FPGA. The OS used is Micrium µC/OS-II, a small real-time OS licensed by Altera for use with their NIOS-II processor. ESPER performs the remote upgrading of the Hit Detector, viewing of the captured waveforms, and diagnostic reading and writing of all firmware settings and counters via a simple JSON-based interface, or an HTML based webpage.

[[File:image26daq.png|490x299px]]

Figure 21 - AFTER chip WFD on the PADWINGS

== '''Trigger Master module (ALPHA-T)''' ==

The Trigger Master firmware module is to collect information from the anode wires and scintillators to make a real-time decision if the current physics event is to be recorded. That decision is fed to all the readout boards to trigger the storage of this particular event.

Initial trigger decision will be based on hit multiplicity of each of the ALPHA-16 boards. As the ALPHA-16 is acquiring the anode wire and the barrel scintillator signals, both of these 2 pieces of equipment will contribute to the trigger decision. Dedicated link from each of the ALPHA-16 (hit detector) to the Trigger module will be gathering the overall information for a final decision. Hardware trigger signal is then sent from the ALPHA-T to the CDM for distribution to all the acquisition modules to initiate the transmission of their data to the backend computer through UDP. The trigger board will compose a summary of the trigger information which will also be transferred to the backend.

The Trigger Master module contains two Mini-SAS FMCs, and one ‘communication’ FMC, that consists of a SATA, an SFP, and a Mini-SAS connector. This configuration of FMCs allows for up to twenty (20) 1G/2.5G/5G links via the Mini-SAS, in addition to a 1 Gbit/sec Ethernet connection via the SFP, and clock+trigger over the SATA.

[[File:image27daq.png|576x304px]]

Figure 22 - Trigger decision on ALPHA-T

== System Monitoring and debugging capability ==

The system monitoring is based on the ESPER protocol provided by the Electronics Development group at TRIUMF. Featuring a built-in web server, with real-time digitizer display, remote upgrade, and JSON-accessible parameters. ESPER allows for real-time diagnostics and testing to be performed on the various electronic modules using either JSON-based requests or a built-in webpage.

[[File:image28daq.png|800x400px]]

Figure 23 - ESPER Web Display. Test pulse recorded by the FEAM cards. Individual AFTER chip configuration is visible (gain change, delay).

= Safety and Hazard considerations =

There are no safety or hazard issues in FE system. All amplifiers are low-voltage and low-power circuits built with standard electronics components.

Detector Electronics

2017-11-19T21:06:48Z

Midas: /* System Monitoring and debugging capability */

Back to [[Documentation]]

= Table of Figures =

[[#_Toc493676266|Figure 1 - Overall Data Acquisition scheme 7]]

[[#_Toc493676267|Figure 2 - Anode wire pre-amplification block diagram 8]]

[[#_Toc493676268|Figure 3 - Anode Wire Board (AWB), 16 channels pre-amplifier 9]]

[[#_Toc493676269|Figure 4 - 4 consecutive anode wire signals 9]]

[[#_Toc493676270|Figure 5 - Anode wire pre-amp gain map for half the chamber circumference 10]]

[[#_Toc493676271|Figure 6 - Alpha16 Data Acquisition Board 12]]

[[#_Toc493676272|Figure 7 - Grif16 Acquisition Module Block Diagram on which the Alpha-16 is based 12]]

[[#_Toc493676273|Figure 8 - Model of the new 32channels 12bit @ 65Msps FMC produced in 2016. 13]]

[[#_Toc493676274|Figure 9 - FMC Alpha-ADC32 Block Diagram 13]]

[[#_Toc493676275|Figure 10 - Cathode Pad Board readout for 288 channels at 62.5Msps, visible 4 AFTER chips, 3 copper bars running under the central board for power distribution 15]]

[[#_Toc493676276|Figure 11 – Thermal image of the FEAM with hot spot temperature: without cooling plate (78°C), with cooling plate (45°C), with cooling plate & water cooling (36°C) 16]]

[[#_Toc493676277|Figure 12 - Block diagram of AFTER amplifier 17]]

[[#_Toc493676278|Figure 13 - 4 x 72 cathode pad signals, overall time width corresponds to the drift time 17]]

[[#_Toc493676279|Figure 14 - Block diagram of one channel of SiPM amplifier 18]]

[[#_Toc493676280|Figure 15 - Trigger Card Adapter and Trigger Card 19]]

[[#_Toc493676281|Figure 16 Trigger Card to FEAM 19]]

[[#_Toc493676282|Figure 17 - Clock Distribution Module 20]]

[[#_Toc493676283|Figure 18 - IO Block Diagram 21]]

[[#_Toc493676284|Figure 19 - ALPHA-16 and CDM board in front with the Trigger/Clock distribution cables 22]]

[[#_Toc493676285|Figure 20 - Hit Detector for the Anode wire and scintillators in ALPHA-16 24]]

[[#_Toc493676286|Figure 21 - AFTER chip WFD on the PADWINGS 25]]

[[#_Toc493676287|Figure 22 - Trigger decision on ALPHA-T 26]]

[[#_Toc493676288|Figure 23 - ESPER Web Display. Test pulse recorded by the FEAM cards. Individual AFTER chip configuration is visible (gain change, delay). 27]]

= Introduction =

This design note describes the electronics chain and components for the readout of the ALPHA-g TPC and barrel scintillator bars.

= Scope =

The Detector Electronics is composed of 3 independent signal sources:

# Anode Wire signals path
# Cathode Pad signals path
# Barrel Scintillator signals path.

All 3 sources provide a similar function such as signal amplification and conditioning (shaping).

= Definitions and Abbreviations =

General acronyms or terms used for the ALPHA-g experiment

{|
! TPC
! Radial Time projection Chamber
|-
| Pads
| PCB surface seeing the induced anode wire signal
|-
| SiPM
| Si photomultipliers used to detect scintillation light
|-
| ADC
| Analog to digital converter
|-
| ASIC
| Application specific integrated circuit
|-
| SCA
| Switch Capacitor Array ( A type of Waveform Digitizer)
|-
| TDC
| Time to digital converter
|-
| BSM
| Barrel Scintillator Module (64 bars sub-assembly)
|-
| FEAM, Padwing
| Cathode strip acquisition board
|-
| CDM
| Clock Distribution Module
|-
| BSB
| Barrel Scintillator Board
|-
| WFD
| Waveform Digitizer
|}

Table 1 – ALPHA-g Abbreviations

= References and related Document =

* AFTER manual
* SensL SPM data sheet
* Edev-group.triumf.ca: contains the FW information on all the Alpha-g custom cards ([https://edev-group.triumf.ca/fw/exp/alphag/feam/rev0/wikis/feam-test-packet-format https://edev-group.triumf.ca/fw/exp/alphag])

* ''' 
'''

= Overall Detector Signal Path =

The Alpha-g detector provides 3 analog signals that are collected for the track reconstruction to help on the annihilation location in the trap.

* The anode wire signal providing the drift time of the electron through the detector for an angular position.
* The cathode pad signal, which are in-time correlated to the anode wire signal, providing the amplitude of these signals from which the longitudinal position (Z) can be extracted.
* The Barrel Scintillator bar signals provide the time and amplitude of the particle crossing the detector. The Barrel Scintillator is mainly to reject cosmic events. For that purpose, the timing resolution is important. Therefore the BSM analog signal is split early in the chain to record the amplitude and time separately.

The anode wires and the barrel scintillator bars are read out from both ends to provide a coarse Z-position as well. The Data acquisition is therefore made for reading 2x256 anode wire channels, 2x64 barrel scintillator bars and 18432 channels of cathode pads covering the outer detector cylinder.

[[File:image2daq.png|576x379px]]

Figure 1 - Overall Data Acquisition scheme

= Anode wire signal path =

The design for the anode wires pre-amplifier is based on work done for several other projects used at TRIUMF and other labs.

Each of the 256 anode wires are read-out from two ends. The signals are used to (1) determine phi-position of ionization track; (2) reconstruct its z-position by weighting signals from two wire ends; (3) generate trigger signal. The pre-amplifiers convert the induced current to voltage that is digitized and processed in the readout system. The main requirements for the amplifier circuit are:

# Input impedance must be low enough so detected charge is sensitive to position of event along wire;
# The shape of signal is optimized for sampling frequency (16 ns) and for fast trigger timing (few ns accuracy);
# Linearity range adjusted for ADC used;
# Gain is adjusted for gas amplification of 105
# Amplifier noise is low enough to detect single-electron cluster.

[[File:image3daq.png|576x204px]]

Figure 2 - Anode wire pre-amplification block diagram

Anode wires are HV-decoupled before connected to the amplifier, but additional (not HV) decoupling is needed at amplifier input to accommodate non-zero potential of the input stage. Protection of the amplifier input is using a standard bi-diode configuration. The first stage is a current-sensitive loop with input impedance defined by resistor Rin and trans-impedance (gain) by feedback resistor Rf. The second stage is 2-pole shaper with shaping time constant defined by components Rs and Cs. The last stage is a cable driver.

Overall gain, transfer function and input impedance of the circuit can be adjusted by changing passive components. This adjustment will be done with studying the TPC prototypes.

Amplifiers are deployed on 16-channel cards, 16 boards serve each end of TPC. They are powered by standard +5V and -5V linear supplies. Each card has a test input that is used to measure amplifiers response and to check for malfunction.

[[File:image4daq.jpg|173x183px]] [[File:image5daq.png|169x184px]]

Figure 3 - Anode Wire Board (AWB), 16 channels pre-amplifier

The AWB schematic allows for bipolar signal input. This has the advantage to reproduce the full anode wire signal development including the inverted induced pulse from neighbouring wires as seen Figure 4.

[[File:image6daq.jpg|512x358px]]

Figure 4 - 4 consecutive anode wire signals

The anode pre-amps have an individual test pulse input to provide a quick functional test. It can also be used for calibration purpose. Several tests have been done in this regard, but the overall chain gain is dependent on many variables (chamber geometry, environmental condition (Gas mixture, T, P), pre-amp (layout, components)). Another more common test pulse injection is available by pulsing all the field wires at once (at the boundary of the drift and multiplication region). This technique has the advantage to produce an induced signal on all the anode wires and cathode pads together at the “same” time. Figure 5 shows the gain variation by wire seen when pulsed through the field wire. 2 interesting features are visible:

a) An overall negative slope, indicated by the linear fit. This slope is explained by the pulse attenuation through the field wires distribution.

b) A clear increase in gain for the wires near the anode wire card boundaries, indicated by the cyan lines is not yet well understood. A further test is planned.

[[File:image7daq.png|397x289px]]

Figure 5 - Anode wire pre-amp gain map for half the chamber circumference

== Anode Wire Waveform digitizer (Alpha-16) ==

The output of the AWB is presented to the Alpha-16 waveform digitizer sampling the analog signal at 62.5Msps.

'''''Note:''''' At the time of this report, the WFD 62.5Msps is not yet available. We use the WFD at 100Msps to perform the tests. The firmware is similar to the 62.5Msps and the final test will be reproduced later.

This module provides 16 channels 14bit ADC @100Msps for 50Ohms single-ended analog signal for the barrel scintillator. It also supports a dedicated mezzanine card (FMC) handling 32 channels 12bit ADC @ 65Msps for single-ended 50Ohms analog signals for the Anode wires.

The Alpha-16 board outputs (16ch.@100Msps and 32ch.@62.5Msps) are collected on the main carrier FPGA for transmission through Ethernet to the backend computer.

The board carries multiple I/O connections required for the module configuration, communication, data transfer, signal inputs, see Figure 7.

* Front panel SFP Gbit Ethernet (copper/fiber)
* Front panel eSATA: clock and sync inputs
* Front panel dual LEMO: Diagnostic DAC outputs (250Msps)
* Front panel MCX connector for 16 x ADC inputs
* Rear entry P2 connector for 16 x ADC inputs
* A24/D16 VME interface to MAXV configuration CPLD
** VME configuration flash updates
** VME bridge to FPGA
* FMC custom module connections.
** Dual MiniSAS for Acquisition setup
** 10 x5Gibt Link
** JESD204B Clocks
** Supports 32 Channel ADC LVDS interface
* Amplifier input switches: Front panel MCX connector, Rear Transition Card SMA connector
* Amplifier Gain x1 and x4
* Switch selectable LEMO NIM Input/ DAC outputs
* Micro SD Flash
* DDR3 DRAM – 667MHz – 128M x 23'''(MT41J128M16HA-15E)'''
* FPGA - Arria V '''(5AGXFB3H4F35C4N)'''
* MAXV CPLD controller '''(5M2210ZF256C5N)''' for USB JTAG and VME access

[[File:image8daq.jpg|218x380px]]

Figure 6. Alpha16 Data Acquisition Board

[[File:image9daq.png|264x383px]]

Figure 7. Grif16 Acquisition Module Block Diagram on which the Alpha-16 is based

== FMC – Alpha ADC32 ==

<blockquote>The FMC – ALPHA ADC32 provides single-stage amplification of up to 32 single-ended 50<math>\Omega</math> analog signals, from the Anode Wire Board Pre-Amplifier, to drive two 16 channel 14bit differential, analog to digital converters sampling at 65MSPS. Further, each ADC will provide a 0.9V common mode offset voltage to be fed into the differential driver

A 16 channel 12 bit digital-to-analog (DAC) converter is used to individually apply an appropriate offset voltage to each of the differential amplifier pairs. The Offset voltages span <math>\pm</math>2.5Vat 1.22mV increments and will output 0V upon power cycle. The DAC is configurable via an SPI interface via the FMC connector.

ADC32 board has the capability to receive and transmit an LVDS clock signal through the eSATA connector which is fed to the FMC connector
</blockquote>
[[File:image10daq.png|318x307px]]

Figure 8 - Model of the new 32channels 12bit @ 65Msps FMC produced in 2016.

[[File:image11daq.png|420x285px]]

Figure 9 - FMC Alpha-ADC32 Block Diagram

<blockquote>''These notes are for the current revision of the Alpha ADC32, a new revision is currently being talked about''
</blockquote>
The board is composed of the following elements:

* 400 Pin FMC connector
** Provides SPI interface
** ADC Synchronization
** Support for 32 LVDS analog signals
** Supply voltage of fused +12V, Switched 3.3V and 1.2-3.3V adjustable
* 32 channel Analog inputs via Hirose connector '''[FX2-40S-1.27DS(71)] 
'''
* 1V analog reference voltage '''[LTC6655BHMS8-3#PBF]'''
** ±2ppm
* Differential ADC Driver '''[ADA4950'''-'''2YCPZ]'''
** ±0.2mV Offset
** 9.2nHz / √Hz Output voltage Noise at Gain=1
** Adjustable output common-mode voltage
** Hardware programmable gain of 1x, 2x and 3x
* Dual 16 channel 14bit Analog to Digital converter '''[AD9249BBCZ-65]'''
** 2Vp-p input range
** 65MSPS
** ±0.6LSB
** Input Clock of 10-520MHz
* 16 channel 12bit Digital to Analog converter '''[ADA4950-2YCPZ]'''
** Programmable offset voltage
** SPI configurable outputs
** Output range ±2.5V, 0V upon reset
** 1.22mV/LSB
* 1 x eSATA Clk-In / Clk-out to and from FMC connector

= Cathode pad signal path =

The 18432 cathode pads covering the inner surface of the outer wall of the detector are individually connected to a signal acquisition chain. This collected signals will provide the position of the electron avalanche at the anode wire. Combining them in charge, permit the reconstruction of the track passing through the longitudinal direction the detector. While the cathode pads cover a large area (2.7m2), the actual footprint per channel is limited (3.8mmx37.1mm). Therefore a high-density waveform digitizer chain has been chosen based on our previous experience with the T2K experiment, we opted for the AFTER Switched Capacitor Array (SCA) ASIC. The analog signal path is short as the pads themselves are on the backside the physical outer cylinder of the detector and the input signal connectors to the AFTER chips are on the opposite side of the outer cylinder.

A custom frontend board (FEAM) see Figure 10 handling 288 individual cathode pads has been designed. It is composed of 4 ASIC AFTER (72 channels) with associated waveform digitizer for the individual signal on 512 cells at 20Msps. In addition, an FPGA manages the board services and the data collection and transmission through a 1 gigabit/sec optical link to the Ethernet using the UDP protocol.

While the power consumption per channel at the ASIC level is low, the power requirement is in the order of 15W per board for a total at the detector level approaching 1000W. This required proper cooling to maintain a reliable operation of the electronics. Figure 11 shows the board temperature with and without cooling plate. Thermal images have been taken to confirm the temperature reduction of the main heat source (Clock cleaner, FPGA, ADC, AFTER in that order). We can guarantee a chip temperature below 60°C to keep the default chip MTBF.

[[File:image12daq.jpg|558x246px]]

Figure 10 - Cathode Pad Board readout for 288 channels at 62.5Msps, visible 4 AFTER chips, 3 copper bars running under the central board for power distribution

[[File:image13daq.png|249x185px]]
[[File:image14daq.png|247x186px]]
[[File:image15daq.jpg|248x186px]]

Figure 11 – Thermal image of the FEAM with hot spot temperature: without cooling plate (78°C), with cooling plate (45°C), with cooling plate & water cooling (36°C)

== Cathode Pad Circuit ==

The cathode pads are read-out by AFTER ASIC which diagram is presented in Figure 12. Each channel consists of a charge-sensitive preamplifier, pole-zero cancellation of preamplifier decay time, RC2 shaper and 512-cell SCA to store the waveform. Amplifier gain, pole-zero time constant and shaping time are programmable.

{|
|
[[File:image16daq.png|361x171px]]

Figure 12 - Block diagram of AFTER amplifier
| [[File:image17daq.png|215x199px]]
|}

The acquisition of the FEAM cards is operational and initial waveforms can be displayed as seen in Figure 13. This visualization is for monitoring the individual channels only. The data acquisition is using a different path for fast data collection. Figure 13 shows cathode signal examples collected by the FEAM card. The signal shape is consistent with avalanches occurring from a cosmic track going through the detector. The initial pulse corresponds to the early avalanches when the track crosses the amplification region (near the anode wire). The remaining pulses show the later electron avalanches reaching the same anode wire from the drift region due to the track angle. The complex pulse shape from the drift region reflects the convolution in this time base of the arrival of the electron to the amplification region and the induced pulse from the resulting electron avalanche.

= Barrel Scintillator signal path =

'''''Note''''': While the Barrel Scintillator is part of the Alpha-g detector for cosmic rejection purpose, this section is still under development. The initial concept and implementation are therefore not final. The volume allocated for it in the other hand well defined due to external to the detector constraints.

Light at both ends of each bar of the barrel scintillator is collected for a rough position detection of the crossing particle and timing information. To improve the detection information (maximize photon collection), 6 individual SiPM light detector (SensL) are mounted on both ends of the individual scintillator bar for a coverage of 50% of the bar. This assembly is in a light-tight and gas-tight enclosure. A cold gas flows through the box to lower the SiPM temperature operation in order to reduce the dark noise of the device. A shaper/amplifier board (BSB) will be mounted on the outside of the enclosure. Each of the board will acquire the signals of 4 adjacent scintillator bars. In total 64 scintillator bars are read out by 16 boards at each end. A block diagram of one bar readout is shown in Figure 14. The signal gathering of the 6 sensors is based on an analog sum.

[[File:image18daq.png|480x296px]]

Figure 14 - Block diagram of one channel of SiPM amplifier

The 6 pre-amplifier outputs are combined to provide the sum of 6 signals. This resulting signal is further amplified and shaped (if necessary) on a second stage post-amplifier/discriminator. This signal sent to the readout system through a cable driver. Two signals will be acquired from each bar: (1) Analog sum fed to a waveform digitizer with proper digital processing to determine event position and timing; (2) LVDS signal fed to a TDC for off-line precise timing measurement purposes. For the LVDS signal, the post-amplifier will have a controlled threshold voltage to the signal comparator.

The BSB will be powered by standard +5V and -5V linear supplies. Each board has a test input to allow individual board measure of the amplifier response, malfunction test and to provide the necessary services to the light sensors device (Voltage bias, temperature sensor, etc).

The output of the analog output of the BSB will be shaped for the 100Msps WFD and in parallel will issue a digital signal for timing information to a TDC.

= Trigger Distribution =

On the full-length detector, the FEAM boards will receive trigger and clock signals from the CDM through the Trigger Card Adapter. The adapter receives signals from the CDM via a 7 pin SATA connector. The signals can be re-driven by repeaters on the adapter and are sent down a chain of 7 Trigger Cards with the adapter forming the first link.

While there are other elegant means of distributing the common clock and trigger to all the electronics boards, this method is the most simple and robust.

[[File:image19daq.png|195x575px|Adapter]]

[[File:image20daq.png|573x43px|Trigger_Board]]

Figure 15 - Trigger Card Adapter and Trigger Card

[[File:image21daq.jpg|216x294px|20170914_101103_resized]]

Figure 16 Trigger Card to FEAM

A Samtec SFM-110 connects each card to a FEAM board and also provides through holes pins where another card can be overlapped and soldered. In this manner the chain of Trigger Distribution Cards is formed, providing a shared clock and trigger signal to a column of 8 FEAM boards.

= Clock Distribution Module =

[[File:image22daq.png|231x356px]]

Figure 17 - Clock Distribution Module

* 6x LEMO Connectors [2 Output, 4 Input]
* 6x Mini-SAS providing up to 24 channels of clock and synchronization breakout
* 1x Combination eSATA/USB connector
** eSATA provides CLK and SYNC
** USB provides USB to Serial communication 115200 BAUD
* 1x 10/100 Base-TX Ethernet
* Optional Atomic Clock module support, 10MHz and 1PPS '''[CSAC - SA.45s]'''
** Short term Stability <1E-11
** over 1000 seconds (100μHz / 1000s)
** Aging rate of <9E-10 per month '''('''9mHz/month)
* Onboard 10MHz Crystal Oscillator '''[FOX924B-10.000]'''
** ±2.5ppm
** ±1ppm per year
* JTAG ARM Support
* SmartFusion2 SoC '''[MS2-FG484]'''
* Ultra-low noise clock jitter cleaner 3:15 input to output support '''[LMK04821] '''
** Min/Max VCO Frequency 2750/3072MHz
** 0.111RMS Jitter
* TTL and NIM signal compatibility for external CLK and SYNC
* VME - 6U - 3Row
* Approximate Current Draw 1.837A at 5V

The Clock Distribution Module ('''CDM)''' has the capability to distribute two externally sourced clock and synchronization signals to six mini-SAS connections for total 24 signal signals. The external signals are provided through the eSATA and LEMO 1A/B Connectors. The module also has the capability to add an Atomic clock that outputs a 10Mhz signal and a 1 Pulse Per Second (PPS), as well as user-defined synchronization signal. Lastly, the module can be configured to output the external clock signals to the LEMO 2B connector or VME bus.

[[File:image23daq.png|509x348px]]

Figure 18 - IO Block Diagram

[[File:image24daq.png|299x412px]]

Figure 19 - ALPHA-16 and CDM board in front with the Trigger/Clock distribution cables

= Frontend Board Firmware =

The firmware (FW) refers to the embedded code running on the Field Programmable Gate Arrays (FPGAs) and microcontrollers (MCUs) located on the various modules within the experiment. These devices store, load, and run the programs required for operation of the different digital electronic components within the experiment.

Firmware code is essential to the operation of the detector as it provides the mechanism to configure the hardware for its particular purpose. Such as analog-to-digital conversion, data filtering, data trigger composition, transport of the data, and orchestration of all the different hardware modules to succeed in acquiring meaningful information across the overall system. Some of the firmware tasks are:

<ol style="list-style-type: upper-roman;">
<li>Low-level acquisition of the 3 different WFDigitizers (Anode wire, Cathode pad, Barrel Scintillator)</li>
<li>Links all the electronics boards to the DAQ system.</li>
<li>Collected in real-time information for trigger decision making.</li>
<li>Distribute synchronization signals and trigger to all the acquisition boards.</li>
<li>Provides to the user; configurable board and operation parameters settings.</li>
<li>Provides board monitoring and debugging tools.</li></ol>

Most of the FW code base has been based off of prior code developed for the currently running GRIFFIN experiment, with some exceptions, such as the Trigger Master Module which needed custom code specific to ALPHA-g, and the PADWING, which contained the AFTER SCA chip not present in GRIFFIN.



The firmware code is loaded onto the hardware board where an FPGA or MCU is present. Each firmware module has specific firmware capabilities, detailed as follows:

* Hit Detector firmware Module (ALPHA-16 carrier board)
** Anode Wire and Barrel Scint. signal waveform digitizers acquisition
** Local data filtering for Trigger purpose
** Transmission of summary data to Trigger Module for trigger decision
** Data compression/filtering and retention for transmission to backend on Trigger reception
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Pad Acquisition firmware Module (PADWING board)
** Cathode pad signal waveform digitizers acquisition
** Data compression/filtering and retention for transmission to backend on Trigger reception
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Master Trigger firmware Module (ALPHA-T board)
** Summary data reception of the multiple GRIF-16 boards
** Trigger decision algorithm
** Packaging of Trigger decision information and transmission to the backend.
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Clock and Trigger Distribution firmware Module (CDM board)
** Monitoring of hardware functions (U,I,T,Clock Frequency)
** Configuration of hardware mechanism for clock and trigger distribution
** Update of firmware code mechanism

== '''Hit Detector Module (ALPHA-16)''' ==

The Hit Detector firmware module handles the acquisition of the analog input signals from the anode wires and scintillators, the digital conversion of that data, and then the transfer of that data to both the DAQ and the Trigger Master. The first implementation of the hit detection is based on hit multiplicity. Later on, a more sophisticated algorithm will be implemented to determine in real time the timing and charge collected for each channel. This information will be transferred to the Trigger Master for more efficient trigger filtering.

The ADC data is acquired from both the FMC ADC32 ADCs and the onboard 16ch 14-bit ADCs using the FPGAs hardware SERDES modules. These modules de-serialize the data stream from the ADCs into a format suitable for internal analysis for hit detection, and for transfer to the MIDAS DAQ.

Once one or more hits are detected, the ALPHA-16 transmits the hit count to the ALPHA-T for a hit multiplicity test, and then waits for a trigger response to decide to discard or transmit the waveform data associated with the detected hit to the DAQ.

Currently, when a trigger is fired by the Trigger Decision module, all channels transmit their captured waveforms to the DAQ. In the future, only channels that have detected a hit will send waveforms on a trigger.

System monitoring and configuration of the Hit Detector module is handled by ESPER running on a NIOS-II soft-core processor instantiated within the FPGA. The OS used is Micrium µC/OS-II, a small real-time OS licensed by Altera for use with their NIOS-II processor. ESPER performs the remote upgrading of the Hit Detector, viewing of the captured waveforms, and diagnostic reading and writing of all firmware settings and counters via a simple JSON-based interface, or an HTML based webpage.

[[File:image25daq.png|517x318px]]

Figure 20 - Hit Detector for the Anode wire and scintillators in ALPHA-16

== '''Pad Acquisition Module (FEAM)''' ==

The pad acquisition firmware module handles the collection of the PAD analog signals captured by the four AFTER ASICs on the module. Capture occurs upon receiving a trigger signal from the Trigger Decision module. Once captured, the AFTER data is transmitted to the MIDAS DAQ over ethernet. No pad information is provided back to the Trigger Decision module.

Each of the AFTER ASICs transmits its captured analog data to a 12-bit ADC which in turn converts the analog signal into digital data and transmits that to the FPGA. The FPGA uses its internal SERDES hardware to de-serialize this data and process it. Once captured, channels that do not contain data of interest are suppressed, and the data is packaged up and sent out over UDP to the MIDAS DAQ.

In the event that the SFP module that provides ethernet connectivity fails, each PAD acquisition module is connected to one other PAD acquisition module via a secondary gigabit link. While currently unused, this link will be used in the future to support a backup link to the DAQ, in the event of a failure of the primary gigabit link.

System monitoring and configuration of the PAD acquisition module is handled by ESPER running on a NIOS-II soft-core processor instantiated within the FPGA. The OS used is Micrium µC/OS-II, a small real-time OS licensed by Altera for use with their NIOS-II processor. ESPER performs the remote upgrading of the Hit Detector, viewing of the captured waveforms, and diagnostic reading and writing of all firmware settings and counters via a simple JSON-based interface, or an HTML based webpage.

[[File:image26daq.png|490x299px]]

Figure 21 - AFTER chip WFD on the PADWINGS

== '''Trigger Master module (ALPHA-T)''' ==

The Trigger Master firmware module is to collect information from the anode wires and scintillators to make a real-time decision if the current physics event is to be recorded. That decision is fed to all the readout boards to trigger the storage of this particular event.

Initial trigger decision will be based on hit multiplicity of each of the ALPHA-16 boards. As the ALPHA-16 is acquiring the anode wire and the barrel scintillator signals, both of these 2 pieces of equipment will contribute to the trigger decision. Dedicated link from each of the ALPHA-16 (hit detector) to the Trigger module will be gathering the overall information for a final decision. Hardware trigger signal is then sent from the ALPHA-T to the CDM for distribution to all the acquisition modules to initiate the transmission of their data to the backend computer through UDP. The trigger board will compose a summary of the trigger information which will also be transferred to the backend.

The Trigger Master module contains two Mini-SAS FMCs, and one ‘communication’ FMC, that consists of a SATA, an SFP, and a Mini-SAS connector. This configuration of FMCs allows for up to twenty (20) 1G/2.5G/5G links via the Mini-SAS, in addition to a 1 Gbit/sec Ethernet connection via the SFP, and clock+trigger over the SATA.

[[File:image27daq.png|576x304px]]

Figure 22 - Trigger decision on ALPHA-T

== System Monitoring and debugging capability ==

The system monitoring is based on the ESPER protocol provided by the Electronics Development group at TRIUMF. Featuring a built-in web server, with real-time digitizer display, remote upgrade, and JSON-accessible parameters. ESPER allows for real-time diagnostics and testing to be performed on the various electronic modules using either JSON-based requests or a built-in webpage.

[[File:image28daq.png|800x400px]]

Figure 23 - ESPER Web Display. Test pulse recorded by the FEAM cards. Individual AFTER chip configuration is visible (gain change, delay).

= Safety and Hazard considerations =

There are no safety or hazard issues in FE system. All amplifiers are low-voltage and low-power circuits built with standard electronics components.

Detector Electronics

2017-11-19T21:06:23Z

Midas: /* System Monitoring and debugging capability */

Back to [[Documentation]]

= Table of Figures =

[[#_Toc493676266|Figure 1 - Overall Data Acquisition scheme 7]]

[[#_Toc493676267|Figure 2 - Anode wire pre-amplification block diagram 8]]

[[#_Toc493676268|Figure 3 - Anode Wire Board (AWB), 16 channels pre-amplifier 9]]

[[#_Toc493676269|Figure 4 - 4 consecutive anode wire signals 9]]

[[#_Toc493676270|Figure 5 - Anode wire pre-amp gain map for half the chamber circumference 10]]

[[#_Toc493676271|Figure 6 - Alpha16 Data Acquisition Board 12]]

[[#_Toc493676272|Figure 7 - Grif16 Acquisition Module Block Diagram on which the Alpha-16 is based 12]]

[[#_Toc493676273|Figure 8 - Model of the new 32channels 12bit @ 65Msps FMC produced in 2016. 13]]

[[#_Toc493676274|Figure 9 - FMC Alpha-ADC32 Block Diagram 13]]

[[#_Toc493676275|Figure 10 - Cathode Pad Board readout for 288 channels at 62.5Msps, visible 4 AFTER chips, 3 copper bars running under the central board for power distribution 15]]

[[#_Toc493676276|Figure 11 – Thermal image of the FEAM with hot spot temperature: without cooling plate (78°C), with cooling plate (45°C), with cooling plate & water cooling (36°C) 16]]

[[#_Toc493676277|Figure 12 - Block diagram of AFTER amplifier 17]]

[[#_Toc493676278|Figure 13 - 4 x 72 cathode pad signals, overall time width corresponds to the drift time 17]]

[[#_Toc493676279|Figure 14 - Block diagram of one channel of SiPM amplifier 18]]

[[#_Toc493676280|Figure 15 - Trigger Card Adapter and Trigger Card 19]]

[[#_Toc493676281|Figure 16 Trigger Card to FEAM 19]]

[[#_Toc493676282|Figure 17 - Clock Distribution Module 20]]

[[#_Toc493676283|Figure 18 - IO Block Diagram 21]]

[[#_Toc493676284|Figure 19 - ALPHA-16 and CDM board in front with the Trigger/Clock distribution cables 22]]

[[#_Toc493676285|Figure 20 - Hit Detector for the Anode wire and scintillators in ALPHA-16 24]]

[[#_Toc493676286|Figure 21 - AFTER chip WFD on the PADWINGS 25]]

[[#_Toc493676287|Figure 22 - Trigger decision on ALPHA-T 26]]

[[#_Toc493676288|Figure 23 - ESPER Web Display. Test pulse recorded by the FEAM cards. Individual AFTER chip configuration is visible (gain change, delay). 27]]

= Introduction =

This design note describes the electronics chain and components for the readout of the ALPHA-g TPC and barrel scintillator bars.

= Scope =

The Detector Electronics is composed of 3 independent signal sources:

# Anode Wire signals path
# Cathode Pad signals path
# Barrel Scintillator signals path.

All 3 sources provide a similar function such as signal amplification and conditioning (shaping).

= Definitions and Abbreviations =

General acronyms or terms used for the ALPHA-g experiment

{|
! TPC
! Radial Time projection Chamber
|-
| Pads
| PCB surface seeing the induced anode wire signal
|-
| SiPM
| Si photomultipliers used to detect scintillation light
|-
| ADC
| Analog to digital converter
|-
| ASIC
| Application specific integrated circuit
|-
| SCA
| Switch Capacitor Array ( A type of Waveform Digitizer)
|-
| TDC
| Time to digital converter
|-
| BSM
| Barrel Scintillator Module (64 bars sub-assembly)
|-
| FEAM, Padwing
| Cathode strip acquisition board
|-
| CDM
| Clock Distribution Module
|-
| BSB
| Barrel Scintillator Board
|-
| WFD
| Waveform Digitizer
|}

Table 1 – ALPHA-g Abbreviations

= References and related Document =

* AFTER manual
* SensL SPM data sheet
* Edev-group.triumf.ca: contains the FW information on all the Alpha-g custom cards ([https://edev-group.triumf.ca/fw/exp/alphag/feam/rev0/wikis/feam-test-packet-format https://edev-group.triumf.ca/fw/exp/alphag])

* ''' 
'''

= Overall Detector Signal Path =

The Alpha-g detector provides 3 analog signals that are collected for the track reconstruction to help on the annihilation location in the trap.

* The anode wire signal providing the drift time of the electron through the detector for an angular position.
* The cathode pad signal, which are in-time correlated to the anode wire signal, providing the amplitude of these signals from which the longitudinal position (Z) can be extracted.
* The Barrel Scintillator bar signals provide the time and amplitude of the particle crossing the detector. The Barrel Scintillator is mainly to reject cosmic events. For that purpose, the timing resolution is important. Therefore the BSM analog signal is split early in the chain to record the amplitude and time separately.

The anode wires and the barrel scintillator bars are read out from both ends to provide a coarse Z-position as well. The Data acquisition is therefore made for reading 2x256 anode wire channels, 2x64 barrel scintillator bars and 18432 channels of cathode pads covering the outer detector cylinder.

[[File:image2daq.png|576x379px]]

Figure 1 - Overall Data Acquisition scheme

= Anode wire signal path =

The design for the anode wires pre-amplifier is based on work done for several other projects used at TRIUMF and other labs.

Each of the 256 anode wires are read-out from two ends. The signals are used to (1) determine phi-position of ionization track; (2) reconstruct its z-position by weighting signals from two wire ends; (3) generate trigger signal. The pre-amplifiers convert the induced current to voltage that is digitized and processed in the readout system. The main requirements for the amplifier circuit are:

# Input impedance must be low enough so detected charge is sensitive to position of event along wire;
# The shape of signal is optimized for sampling frequency (16 ns) and for fast trigger timing (few ns accuracy);
# Linearity range adjusted for ADC used;
# Gain is adjusted for gas amplification of 105
# Amplifier noise is low enough to detect single-electron cluster.

[[File:image3daq.png|576x204px]]

Figure 2 - Anode wire pre-amplification block diagram

Anode wires are HV-decoupled before connected to the amplifier, but additional (not HV) decoupling is needed at amplifier input to accommodate non-zero potential of the input stage. Protection of the amplifier input is using a standard bi-diode configuration. The first stage is a current-sensitive loop with input impedance defined by resistor Rin and trans-impedance (gain) by feedback resistor Rf. The second stage is 2-pole shaper with shaping time constant defined by components Rs and Cs. The last stage is a cable driver.

Overall gain, transfer function and input impedance of the circuit can be adjusted by changing passive components. This adjustment will be done with studying the TPC prototypes.

Amplifiers are deployed on 16-channel cards, 16 boards serve each end of TPC. They are powered by standard +5V and -5V linear supplies. Each card has a test input that is used to measure amplifiers response and to check for malfunction.

[[File:image4daq.jpg|173x183px]] [[File:image5daq.png|169x184px]]

Figure 3 - Anode Wire Board (AWB), 16 channels pre-amplifier

The AWB schematic allows for bipolar signal input. This has the advantage to reproduce the full anode wire signal development including the inverted induced pulse from neighbouring wires as seen Figure 4.

[[File:image6daq.jpg|512x358px]]

Figure 4 - 4 consecutive anode wire signals

The anode pre-amps have an individual test pulse input to provide a quick functional test. It can also be used for calibration purpose. Several tests have been done in this regard, but the overall chain gain is dependent on many variables (chamber geometry, environmental condition (Gas mixture, T, P), pre-amp (layout, components)). Another more common test pulse injection is available by pulsing all the field wires at once (at the boundary of the drift and multiplication region). This technique has the advantage to produce an induced signal on all the anode wires and cathode pads together at the “same” time. Figure 5 shows the gain variation by wire seen when pulsed through the field wire. 2 interesting features are visible:

a) An overall negative slope, indicated by the linear fit. This slope is explained by the pulse attenuation through the field wires distribution.

b) A clear increase in gain for the wires near the anode wire card boundaries, indicated by the cyan lines is not yet well understood. A further test is planned.

[[File:image7daq.png|397x289px]]

Figure 5 - Anode wire pre-amp gain map for half the chamber circumference

== Anode Wire Waveform digitizer (Alpha-16) ==

The output of the AWB is presented to the Alpha-16 waveform digitizer sampling the analog signal at 62.5Msps.

'''''Note:''''' At the time of this report, the WFD 62.5Msps is not yet available. We use the WFD at 100Msps to perform the tests. The firmware is similar to the 62.5Msps and the final test will be reproduced later.

This module provides 16 channels 14bit ADC @100Msps for 50Ohms single-ended analog signal for the barrel scintillator. It also supports a dedicated mezzanine card (FMC) handling 32 channels 12bit ADC @ 65Msps for single-ended 50Ohms analog signals for the Anode wires.

The Alpha-16 board outputs (16ch.@100Msps and 32ch.@62.5Msps) are collected on the main carrier FPGA for transmission through Ethernet to the backend computer.

The board carries multiple I/O connections required for the module configuration, communication, data transfer, signal inputs, see Figure 7.

* Front panel SFP Gbit Ethernet (copper/fiber)
* Front panel eSATA: clock and sync inputs
* Front panel dual LEMO: Diagnostic DAC outputs (250Msps)
* Front panel MCX connector for 16 x ADC inputs
* Rear entry P2 connector for 16 x ADC inputs
* A24/D16 VME interface to MAXV configuration CPLD
** VME configuration flash updates
** VME bridge to FPGA
* FMC custom module connections.
** Dual MiniSAS for Acquisition setup
** 10 x5Gibt Link
** JESD204B Clocks
** Supports 32 Channel ADC LVDS interface
* Amplifier input switches: Front panel MCX connector, Rear Transition Card SMA connector
* Amplifier Gain x1 and x4
* Switch selectable LEMO NIM Input/ DAC outputs
* Micro SD Flash
* DDR3 DRAM – 667MHz – 128M x 23'''(MT41J128M16HA-15E)'''
* FPGA - Arria V '''(5AGXFB3H4F35C4N)'''
* MAXV CPLD controller '''(5M2210ZF256C5N)''' for USB JTAG and VME access

[[File:image8daq.jpg|218x380px]]

Figure 6. Alpha16 Data Acquisition Board

[[File:image9daq.png|264x383px]]

Figure 7. Grif16 Acquisition Module Block Diagram on which the Alpha-16 is based

== FMC – Alpha ADC32 ==

<blockquote>The FMC – ALPHA ADC32 provides single-stage amplification of up to 32 single-ended 50<math>\Omega</math> analog signals, from the Anode Wire Board Pre-Amplifier, to drive two 16 channel 14bit differential, analog to digital converters sampling at 65MSPS. Further, each ADC will provide a 0.9V common mode offset voltage to be fed into the differential driver

A 16 channel 12 bit digital-to-analog (DAC) converter is used to individually apply an appropriate offset voltage to each of the differential amplifier pairs. The Offset voltages span <math>\pm</math>2.5Vat 1.22mV increments and will output 0V upon power cycle. The DAC is configurable via an SPI interface via the FMC connector.

ADC32 board has the capability to receive and transmit an LVDS clock signal through the eSATA connector which is fed to the FMC connector
</blockquote>
[[File:image10daq.png|318x307px]]

Figure 8 - Model of the new 32channels 12bit @ 65Msps FMC produced in 2016.

[[File:image11daq.png|420x285px]]

Figure 9 - FMC Alpha-ADC32 Block Diagram

<blockquote>''These notes are for the current revision of the Alpha ADC32, a new revision is currently being talked about''
</blockquote>
The board is composed of the following elements:

* 400 Pin FMC connector
** Provides SPI interface
** ADC Synchronization
** Support for 32 LVDS analog signals
** Supply voltage of fused +12V, Switched 3.3V and 1.2-3.3V adjustable
* 32 channel Analog inputs via Hirose connector '''[FX2-40S-1.27DS(71)] 
'''
* 1V analog reference voltage '''[LTC6655BHMS8-3#PBF]'''
** ±2ppm
* Differential ADC Driver '''[ADA4950'''-'''2YCPZ]'''
** ±0.2mV Offset
** 9.2nHz / √Hz Output voltage Noise at Gain=1
** Adjustable output common-mode voltage
** Hardware programmable gain of 1x, 2x and 3x
* Dual 16 channel 14bit Analog to Digital converter '''[AD9249BBCZ-65]'''
** 2Vp-p input range
** 65MSPS
** ±0.6LSB
** Input Clock of 10-520MHz
* 16 channel 12bit Digital to Analog converter '''[ADA4950-2YCPZ]'''
** Programmable offset voltage
** SPI configurable outputs
** Output range ±2.5V, 0V upon reset
** 1.22mV/LSB
* 1 x eSATA Clk-In / Clk-out to and from FMC connector

= Cathode pad signal path =

The 18432 cathode pads covering the inner surface of the outer wall of the detector are individually connected to a signal acquisition chain. This collected signals will provide the position of the electron avalanche at the anode wire. Combining them in charge, permit the reconstruction of the track passing through the longitudinal direction the detector. While the cathode pads cover a large area (2.7m2), the actual footprint per channel is limited (3.8mmx37.1mm). Therefore a high-density waveform digitizer chain has been chosen based on our previous experience with the T2K experiment, we opted for the AFTER Switched Capacitor Array (SCA) ASIC. The analog signal path is short as the pads themselves are on the backside the physical outer cylinder of the detector and the input signal connectors to the AFTER chips are on the opposite side of the outer cylinder.

A custom frontend board (FEAM) see Figure 10 handling 288 individual cathode pads has been designed. It is composed of 4 ASIC AFTER (72 channels) with associated waveform digitizer for the individual signal on 512 cells at 20Msps. In addition, an FPGA manages the board services and the data collection and transmission through a 1 gigabit/sec optical link to the Ethernet using the UDP protocol.

While the power consumption per channel at the ASIC level is low, the power requirement is in the order of 15W per board for a total at the detector level approaching 1000W. This required proper cooling to maintain a reliable operation of the electronics. Figure 11 shows the board temperature with and without cooling plate. Thermal images have been taken to confirm the temperature reduction of the main heat source (Clock cleaner, FPGA, ADC, AFTER in that order). We can guarantee a chip temperature below 60°C to keep the default chip MTBF.

[[File:image12daq.jpg|558x246px]]

Figure 10 - Cathode Pad Board readout for 288 channels at 62.5Msps, visible 4 AFTER chips, 3 copper bars running under the central board for power distribution

[[File:image13daq.png|249x185px]]
[[File:image14daq.png|247x186px]]
[[File:image15daq.jpg|248x186px]]

Figure 11 – Thermal image of the FEAM with hot spot temperature: without cooling plate (78°C), with cooling plate (45°C), with cooling plate & water cooling (36°C)

== Cathode Pad Circuit ==

The cathode pads are read-out by AFTER ASIC which diagram is presented in Figure 12. Each channel consists of a charge-sensitive preamplifier, pole-zero cancellation of preamplifier decay time, RC2 shaper and 512-cell SCA to store the waveform. Amplifier gain, pole-zero time constant and shaping time are programmable.

{|
|
[[File:image16daq.png|361x171px]]

Figure 12 - Block diagram of AFTER amplifier
| [[File:image17daq.png|215x199px]]
|}

The acquisition of the FEAM cards is operational and initial waveforms can be displayed as seen in Figure 13. This visualization is for monitoring the individual channels only. The data acquisition is using a different path for fast data collection. Figure 13 shows cathode signal examples collected by the FEAM card. The signal shape is consistent with avalanches occurring from a cosmic track going through the detector. The initial pulse corresponds to the early avalanches when the track crosses the amplification region (near the anode wire). The remaining pulses show the later electron avalanches reaching the same anode wire from the drift region due to the track angle. The complex pulse shape from the drift region reflects the convolution in this time base of the arrival of the electron to the amplification region and the induced pulse from the resulting electron avalanche.

= Barrel Scintillator signal path =

'''''Note''''': While the Barrel Scintillator is part of the Alpha-g detector for cosmic rejection purpose, this section is still under development. The initial concept and implementation are therefore not final. The volume allocated for it in the other hand well defined due to external to the detector constraints.

Light at both ends of each bar of the barrel scintillator is collected for a rough position detection of the crossing particle and timing information. To improve the detection information (maximize photon collection), 6 individual SiPM light detector (SensL) are mounted on both ends of the individual scintillator bar for a coverage of 50% of the bar. This assembly is in a light-tight and gas-tight enclosure. A cold gas flows through the box to lower the SiPM temperature operation in order to reduce the dark noise of the device. A shaper/amplifier board (BSB) will be mounted on the outside of the enclosure. Each of the board will acquire the signals of 4 adjacent scintillator bars. In total 64 scintillator bars are read out by 16 boards at each end. A block diagram of one bar readout is shown in Figure 14. The signal gathering of the 6 sensors is based on an analog sum.

[[File:image18daq.png|480x296px]]

Figure 14 - Block diagram of one channel of SiPM amplifier

The 6 pre-amplifier outputs are combined to provide the sum of 6 signals. This resulting signal is further amplified and shaped (if necessary) on a second stage post-amplifier/discriminator. This signal sent to the readout system through a cable driver. Two signals will be acquired from each bar: (1) Analog sum fed to a waveform digitizer with proper digital processing to determine event position and timing; (2) LVDS signal fed to a TDC for off-line precise timing measurement purposes. For the LVDS signal, the post-amplifier will have a controlled threshold voltage to the signal comparator.

The BSB will be powered by standard +5V and -5V linear supplies. Each board has a test input to allow individual board measure of the amplifier response, malfunction test and to provide the necessary services to the light sensors device (Voltage bias, temperature sensor, etc).

The output of the analog output of the BSB will be shaped for the 100Msps WFD and in parallel will issue a digital signal for timing information to a TDC.

= Trigger Distribution =

On the full-length detector, the FEAM boards will receive trigger and clock signals from the CDM through the Trigger Card Adapter. The adapter receives signals from the CDM via a 7 pin SATA connector. The signals can be re-driven by repeaters on the adapter and are sent down a chain of 7 Trigger Cards with the adapter forming the first link.

While there are other elegant means of distributing the common clock and trigger to all the electronics boards, this method is the most simple and robust.

[[File:image19daq.png|195x575px|Adapter]]

[[File:image20daq.png|573x43px|Trigger_Board]]

Figure 15 - Trigger Card Adapter and Trigger Card

[[File:image21daq.jpg|216x294px|20170914_101103_resized]]

Figure 16 Trigger Card to FEAM

A Samtec SFM-110 connects each card to a FEAM board and also provides through holes pins where another card can be overlapped and soldered. In this manner the chain of Trigger Distribution Cards is formed, providing a shared clock and trigger signal to a column of 8 FEAM boards.

= Clock Distribution Module =

[[File:image22daq.png|231x356px]]

Figure 17 - Clock Distribution Module

* 6x LEMO Connectors [2 Output, 4 Input]
* 6x Mini-SAS providing up to 24 channels of clock and synchronization breakout
* 1x Combination eSATA/USB connector
** eSATA provides CLK and SYNC
** USB provides USB to Serial communication 115200 BAUD
* 1x 10/100 Base-TX Ethernet
* Optional Atomic Clock module support, 10MHz and 1PPS '''[CSAC - SA.45s]'''
** Short term Stability <1E-11
** over 1000 seconds (100μHz / 1000s)
** Aging rate of <9E-10 per month '''('''9mHz/month)
* Onboard 10MHz Crystal Oscillator '''[FOX924B-10.000]'''
** ±2.5ppm
** ±1ppm per year
* JTAG ARM Support
* SmartFusion2 SoC '''[MS2-FG484]'''
* Ultra-low noise clock jitter cleaner 3:15 input to output support '''[LMK04821] '''
** Min/Max VCO Frequency 2750/3072MHz
** 0.111RMS Jitter
* TTL and NIM signal compatibility for external CLK and SYNC
* VME - 6U - 3Row
* Approximate Current Draw 1.837A at 5V

The Clock Distribution Module ('''CDM)''' has the capability to distribute two externally sourced clock and synchronization signals to six mini-SAS connections for total 24 signal signals. The external signals are provided through the eSATA and LEMO 1A/B Connectors. The module also has the capability to add an Atomic clock that outputs a 10Mhz signal and a 1 Pulse Per Second (PPS), as well as user-defined synchronization signal. Lastly, the module can be configured to output the external clock signals to the LEMO 2B connector or VME bus.

[[File:image23daq.png|509x348px]]

Figure 18 - IO Block Diagram

[[File:image24daq.png|299x412px]]

Figure 19 - ALPHA-16 and CDM board in front with the Trigger/Clock distribution cables

= Frontend Board Firmware =

The firmware (FW) refers to the embedded code running on the Field Programmable Gate Arrays (FPGAs) and microcontrollers (MCUs) located on the various modules within the experiment. These devices store, load, and run the programs required for operation of the different digital electronic components within the experiment.

Firmware code is essential to the operation of the detector as it provides the mechanism to configure the hardware for its particular purpose. Such as analog-to-digital conversion, data filtering, data trigger composition, transport of the data, and orchestration of all the different hardware modules to succeed in acquiring meaningful information across the overall system. Some of the firmware tasks are:

<ol style="list-style-type: upper-roman;">
<li>Low-level acquisition of the 3 different WFDigitizers (Anode wire, Cathode pad, Barrel Scintillator)</li>
<li>Links all the electronics boards to the DAQ system.</li>
<li>Collected in real-time information for trigger decision making.</li>
<li>Distribute synchronization signals and trigger to all the acquisition boards.</li>
<li>Provides to the user; configurable board and operation parameters settings.</li>
<li>Provides board monitoring and debugging tools.</li></ol>

Most of the FW code base has been based off of prior code developed for the currently running GRIFFIN experiment, with some exceptions, such as the Trigger Master Module which needed custom code specific to ALPHA-g, and the PADWING, which contained the AFTER SCA chip not present in GRIFFIN.



The firmware code is loaded onto the hardware board where an FPGA or MCU is present. Each firmware module has specific firmware capabilities, detailed as follows:

* Hit Detector firmware Module (ALPHA-16 carrier board)
** Anode Wire and Barrel Scint. signal waveform digitizers acquisition
** Local data filtering for Trigger purpose
** Transmission of summary data to Trigger Module for trigger decision
** Data compression/filtering and retention for transmission to backend on Trigger reception
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Pad Acquisition firmware Module (PADWING board)
** Cathode pad signal waveform digitizers acquisition
** Data compression/filtering and retention for transmission to backend on Trigger reception
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Master Trigger firmware Module (ALPHA-T board)
** Summary data reception of the multiple GRIF-16 boards
** Trigger decision algorithm
** Packaging of Trigger decision information and transmission to the backend.
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Clock and Trigger Distribution firmware Module (CDM board)
** Monitoring of hardware functions (U,I,T,Clock Frequency)
** Configuration of hardware mechanism for clock and trigger distribution
** Update of firmware code mechanism

== '''Hit Detector Module (ALPHA-16)''' ==

The Hit Detector firmware module handles the acquisition of the analog input signals from the anode wires and scintillators, the digital conversion of that data, and then the transfer of that data to both the DAQ and the Trigger Master. The first implementation of the hit detection is based on hit multiplicity. Later on, a more sophisticated algorithm will be implemented to determine in real time the timing and charge collected for each channel. This information will be transferred to the Trigger Master for more efficient trigger filtering.

The ADC data is acquired from both the FMC ADC32 ADCs and the onboard 16ch 14-bit ADCs using the FPGAs hardware SERDES modules. These modules de-serialize the data stream from the ADCs into a format suitable for internal analysis for hit detection, and for transfer to the MIDAS DAQ.

Once one or more hits are detected, the ALPHA-16 transmits the hit count to the ALPHA-T for a hit multiplicity test, and then waits for a trigger response to decide to discard or transmit the waveform data associated with the detected hit to the DAQ.

Currently, when a trigger is fired by the Trigger Decision module, all channels transmit their captured waveforms to the DAQ. In the future, only channels that have detected a hit will send waveforms on a trigger.

System monitoring and configuration of the Hit Detector module is handled by ESPER running on a NIOS-II soft-core processor instantiated within the FPGA. The OS used is Micrium µC/OS-II, a small real-time OS licensed by Altera for use with their NIOS-II processor. ESPER performs the remote upgrading of the Hit Detector, viewing of the captured waveforms, and diagnostic reading and writing of all firmware settings and counters via a simple JSON-based interface, or an HTML based webpage.

[[File:image25daq.png|517x318px]]

Figure 20 - Hit Detector for the Anode wire and scintillators in ALPHA-16

== '''Pad Acquisition Module (FEAM)''' ==

The pad acquisition firmware module handles the collection of the PAD analog signals captured by the four AFTER ASICs on the module. Capture occurs upon receiving a trigger signal from the Trigger Decision module. Once captured, the AFTER data is transmitted to the MIDAS DAQ over ethernet. No pad information is provided back to the Trigger Decision module.

Each of the AFTER ASICs transmits its captured analog data to a 12-bit ADC which in turn converts the analog signal into digital data and transmits that to the FPGA. The FPGA uses its internal SERDES hardware to de-serialize this data and process it. Once captured, channels that do not contain data of interest are suppressed, and the data is packaged up and sent out over UDP to the MIDAS DAQ.

In the event that the SFP module that provides ethernet connectivity fails, each PAD acquisition module is connected to one other PAD acquisition module via a secondary gigabit link. While currently unused, this link will be used in the future to support a backup link to the DAQ, in the event of a failure of the primary gigabit link.

System monitoring and configuration of the PAD acquisition module is handled by ESPER running on a NIOS-II soft-core processor instantiated within the FPGA. The OS used is Micrium µC/OS-II, a small real-time OS licensed by Altera for use with their NIOS-II processor. ESPER performs the remote upgrading of the Hit Detector, viewing of the captured waveforms, and diagnostic reading and writing of all firmware settings and counters via a simple JSON-based interface, or an HTML based webpage.

[[File:image26daq.png|490x299px]]

Figure 21 - AFTER chip WFD on the PADWINGS

== '''Trigger Master module (ALPHA-T)''' ==

The Trigger Master firmware module is to collect information from the anode wires and scintillators to make a real-time decision if the current physics event is to be recorded. That decision is fed to all the readout boards to trigger the storage of this particular event.

Initial trigger decision will be based on hit multiplicity of each of the ALPHA-16 boards. As the ALPHA-16 is acquiring the anode wire and the barrel scintillator signals, both of these 2 pieces of equipment will contribute to the trigger decision. Dedicated link from each of the ALPHA-16 (hit detector) to the Trigger module will be gathering the overall information for a final decision. Hardware trigger signal is then sent from the ALPHA-T to the CDM for distribution to all the acquisition modules to initiate the transmission of their data to the backend computer through UDP. The trigger board will compose a summary of the trigger information which will also be transferred to the backend.

The Trigger Master module contains two Mini-SAS FMCs, and one ‘communication’ FMC, that consists of a SATA, an SFP, and a Mini-SAS connector. This configuration of FMCs allows for up to twenty (20) 1G/2.5G/5G links via the Mini-SAS, in addition to a 1 Gbit/sec Ethernet connection via the SFP, and clock+trigger over the SATA.

[[File:image27daq.png|576x304px]]

Figure 22 - Trigger decision on ALPHA-T

== System Monitoring and debugging capability ==

The system monitoring is based on the ESPER protocol provided by the Electronics Development group at TRIUMF. Featuring a built-in web server, with real-time digitizer display, remote upgrade, and JSON-accessible parameters. ESPER allows for real-time diagnostics and testing to be performed on the various electronic modules using either JSON-based requests or a built-in webpage.

[[File:image28daq.png|1000x500px]]

Figure 23 - ESPER Web Display. Test pulse recorded by the FEAM cards. Individual AFTER chip configuration is visible (gain change, delay).

= Safety and Hazard considerations =

There are no safety or hazard issues in FE system. All amplifiers are low-voltage and low-power circuits built with standard electronics components.

Detector Electronics

2017-11-19T20:58:01Z

Midas:

Back to [[Documentation]]

= Table of Figures =

[[#_Toc493676266|Figure 1 - Overall Data Acquisition scheme 7]]

[[#_Toc493676267|Figure 2 - Anode wire pre-amplification block diagram 8]]

[[#_Toc493676268|Figure 3 - Anode Wire Board (AWB), 16 channels pre-amplifier 9]]

[[#_Toc493676269|Figure 4 - 4 consecutive anode wire signals 9]]

[[#_Toc493676270|Figure 5 - Anode wire pre-amp gain map for half the chamber circumference 10]]

[[#_Toc493676271|Figure 6 - Alpha16 Data Acquisition Board 12]]

[[#_Toc493676272|Figure 7 - Grif16 Acquisition Module Block Diagram on which the Alpha-16 is based 12]]

[[#_Toc493676273|Figure 8 - Model of the new 32channels 12bit @ 65Msps FMC produced in 2016. 13]]

[[#_Toc493676274|Figure 9 - FMC Alpha-ADC32 Block Diagram 13]]

[[#_Toc493676275|Figure 10 - Cathode Pad Board readout for 288 channels at 62.5Msps, visible 4 AFTER chips, 3 copper bars running under the central board for power distribution 15]]

[[#_Toc493676276|Figure 11 – Thermal image of the FEAM with hot spot temperature: without cooling plate (78°C), with cooling plate (45°C), with cooling plate & water cooling (36°C) 16]]

[[#_Toc493676277|Figure 12 - Block diagram of AFTER amplifier 17]]

[[#_Toc493676278|Figure 13 - 4 x 72 cathode pad signals, overall time width corresponds to the drift time 17]]

[[#_Toc493676279|Figure 14 - Block diagram of one channel of SiPM amplifier 18]]

[[#_Toc493676280|Figure 15 - Trigger Card Adapter and Trigger Card 19]]

[[#_Toc493676281|Figure 16 Trigger Card to FEAM 19]]

[[#_Toc493676282|Figure 17 - Clock Distribution Module 20]]

[[#_Toc493676283|Figure 18 - IO Block Diagram 21]]

[[#_Toc493676284|Figure 19 - ALPHA-16 and CDM board in front with the Trigger/Clock distribution cables 22]]

[[#_Toc493676285|Figure 20 - Hit Detector for the Anode wire and scintillators in ALPHA-16 24]]

[[#_Toc493676286|Figure 21 - AFTER chip WFD on the PADWINGS 25]]

[[#_Toc493676287|Figure 22 - Trigger decision on ALPHA-T 26]]

[[#_Toc493676288|Figure 23 - ESPER Web Display. Test pulse recorded by the FEAM cards. Individual AFTER chip configuration is visible (gain change, delay). 27]]

= Introduction =

This design note describes the electronics chain and components for the readout of the ALPHA-g TPC and barrel scintillator bars.

= Scope =

The Detector Electronics is composed of 3 independent signal sources:

# Anode Wire signals path
# Cathode Pad signals path
# Barrel Scintillator signals path.

All 3 sources provide a similar function such as signal amplification and conditioning (shaping).

= Definitions and Abbreviations =

General acronyms or terms used for the ALPHA-g experiment

{|
! TPC
! Radial Time projection Chamber
|-
| Pads
| PCB surface seeing the induced anode wire signal
|-
| SiPM
| Si photomultipliers used to detect scintillation light
|-
| ADC
| Analog to digital converter
|-
| ASIC
| Application specific integrated circuit
|-
| SCA
| Switch Capacitor Array ( A type of Waveform Digitizer)
|-
| TDC
| Time to digital converter
|-
| BSM
| Barrel Scintillator Module (64 bars sub-assembly)
|-
| FEAM, Padwing
| Cathode strip acquisition board
|-
| CDM
| Clock Distribution Module
|-
| BSB
| Barrel Scintillator Board
|-
| WFD
| Waveform Digitizer
|}

Table 1 – ALPHA-g Abbreviations

= References and related Document =

* AFTER manual
* SensL SPM data sheet
* Edev-group.triumf.ca: contains the FW information on all the Alpha-g custom cards ([https://edev-group.triumf.ca/fw/exp/alphag/feam/rev0/wikis/feam-test-packet-format https://edev-group.triumf.ca/fw/exp/alphag])

* ''' 
'''

= Overall Detector Signal Path =

The Alpha-g detector provides 3 analog signals that are collected for the track reconstruction to help on the annihilation location in the trap.

* The anode wire signal providing the drift time of the electron through the detector for an angular position.
* The cathode pad signal, which are in-time correlated to the anode wire signal, providing the amplitude of these signals from which the longitudinal position (Z) can be extracted.
* The Barrel Scintillator bar signals provide the time and amplitude of the particle crossing the detector. The Barrel Scintillator is mainly to reject cosmic events. For that purpose, the timing resolution is important. Therefore the BSM analog signal is split early in the chain to record the amplitude and time separately.

The anode wires and the barrel scintillator bars are read out from both ends to provide a coarse Z-position as well. The Data acquisition is therefore made for reading 2x256 anode wire channels, 2x64 barrel scintillator bars and 18432 channels of cathode pads covering the outer detector cylinder.

[[File:image2daq.png|576x379px]]

Figure 1 - Overall Data Acquisition scheme

= Anode wire signal path =

The design for the anode wires pre-amplifier is based on work done for several other projects used at TRIUMF and other labs.

Each of the 256 anode wires are read-out from two ends. The signals are used to (1) determine phi-position of ionization track; (2) reconstruct its z-position by weighting signals from two wire ends; (3) generate trigger signal. The pre-amplifiers convert the induced current to voltage that is digitized and processed in the readout system. The main requirements for the amplifier circuit are:

# Input impedance must be low enough so detected charge is sensitive to position of event along wire;
# The shape of signal is optimized for sampling frequency (16 ns) and for fast trigger timing (few ns accuracy);
# Linearity range adjusted for ADC used;
# Gain is adjusted for gas amplification of 105
# Amplifier noise is low enough to detect single-electron cluster.

[[File:image3daq.png|576x204px]]

Figure 2 - Anode wire pre-amplification block diagram

Anode wires are HV-decoupled before connected to the amplifier, but additional (not HV) decoupling is needed at amplifier input to accommodate non-zero potential of the input stage. Protection of the amplifier input is using a standard bi-diode configuration. The first stage is a current-sensitive loop with input impedance defined by resistor Rin and trans-impedance (gain) by feedback resistor Rf. The second stage is 2-pole shaper with shaping time constant defined by components Rs and Cs. The last stage is a cable driver.

Overall gain, transfer function and input impedance of the circuit can be adjusted by changing passive components. This adjustment will be done with studying the TPC prototypes.

Amplifiers are deployed on 16-channel cards, 16 boards serve each end of TPC. They are powered by standard +5V and -5V linear supplies. Each card has a test input that is used to measure amplifiers response and to check for malfunction.

[[File:image4daq.jpg|173x183px]] [[File:image5daq.png|169x184px]]

Figure 3 - Anode Wire Board (AWB), 16 channels pre-amplifier

The AWB schematic allows for bipolar signal input. This has the advantage to reproduce the full anode wire signal development including the inverted induced pulse from neighbouring wires as seen Figure 4.

[[File:image6daq.jpg|512x358px]]

Figure 4 - 4 consecutive anode wire signals

The anode pre-amps have an individual test pulse input to provide a quick functional test. It can also be used for calibration purpose. Several tests have been done in this regard, but the overall chain gain is dependent on many variables (chamber geometry, environmental condition (Gas mixture, T, P), pre-amp (layout, components)). Another more common test pulse injection is available by pulsing all the field wires at once (at the boundary of the drift and multiplication region). This technique has the advantage to produce an induced signal on all the anode wires and cathode pads together at the “same” time. Figure 5 shows the gain variation by wire seen when pulsed through the field wire. 2 interesting features are visible:

a) An overall negative slope, indicated by the linear fit. This slope is explained by the pulse attenuation through the field wires distribution.

b) A clear increase in gain for the wires near the anode wire card boundaries, indicated by the cyan lines is not yet well understood. A further test is planned.

[[File:image7daq.png|397x289px]]

Figure 5 - Anode wire pre-amp gain map for half the chamber circumference

== Anode Wire Waveform digitizer (Alpha-16) ==

The output of the AWB is presented to the Alpha-16 waveform digitizer sampling the analog signal at 62.5Msps.

'''''Note:''''' At the time of this report, the WFD 62.5Msps is not yet available. We use the WFD at 100Msps to perform the tests. The firmware is similar to the 62.5Msps and the final test will be reproduced later.

This module provides 16 channels 14bit ADC @100Msps for 50Ohms single-ended analog signal for the barrel scintillator. It also supports a dedicated mezzanine card (FMC) handling 32 channels 12bit ADC @ 65Msps for single-ended 50Ohms analog signals for the Anode wires.

The Alpha-16 board outputs (16ch.@100Msps and 32ch.@62.5Msps) are collected on the main carrier FPGA for transmission through Ethernet to the backend computer.

The board carries multiple I/O connections required for the module configuration, communication, data transfer, signal inputs, see Figure 7.

* Front panel SFP Gbit Ethernet (copper/fiber)
* Front panel eSATA: clock and sync inputs
* Front panel dual LEMO: Diagnostic DAC outputs (250Msps)
* Front panel MCX connector for 16 x ADC inputs
* Rear entry P2 connector for 16 x ADC inputs
* A24/D16 VME interface to MAXV configuration CPLD
** VME configuration flash updates
** VME bridge to FPGA
* FMC custom module connections.
** Dual MiniSAS for Acquisition setup
** 10 x5Gibt Link
** JESD204B Clocks
** Supports 32 Channel ADC LVDS interface
* Amplifier input switches: Front panel MCX connector, Rear Transition Card SMA connector
* Amplifier Gain x1 and x4
* Switch selectable LEMO NIM Input/ DAC outputs
* Micro SD Flash
* DDR3 DRAM – 667MHz – 128M x 23'''(MT41J128M16HA-15E)'''
* FPGA - Arria V '''(5AGXFB3H4F35C4N)'''
* MAXV CPLD controller '''(5M2210ZF256C5N)''' for USB JTAG and VME access

[[File:image8daq.jpg|218x380px]]

Figure 6. Alpha16 Data Acquisition Board

[[File:image9daq.png|264x383px]]

Figure 7. Grif16 Acquisition Module Block Diagram on which the Alpha-16 is based

== FMC – Alpha ADC32 ==

<blockquote>The FMC – ALPHA ADC32 provides single-stage amplification of up to 32 single-ended 50<math>\Omega</math> analog signals, from the Anode Wire Board Pre-Amplifier, to drive two 16 channel 14bit differential, analog to digital converters sampling at 65MSPS. Further, each ADC will provide a 0.9V common mode offset voltage to be fed into the differential driver

A 16 channel 12 bit digital-to-analog (DAC) converter is used to individually apply an appropriate offset voltage to each of the differential amplifier pairs. The Offset voltages span <math>\pm</math>2.5Vat 1.22mV increments and will output 0V upon power cycle. The DAC is configurable via an SPI interface via the FMC connector.

ADC32 board has the capability to receive and transmit an LVDS clock signal through the eSATA connector which is fed to the FMC connector
</blockquote>
[[File:image10daq.png|318x307px]]

Figure 8 - Model of the new 32channels 12bit @ 65Msps FMC produced in 2016.

[[File:image11daq.png|420x285px]]

Figure 9 - FMC Alpha-ADC32 Block Diagram

<blockquote>''These notes are for the current revision of the Alpha ADC32, a new revision is currently being talked about''
</blockquote>
The board is composed of the following elements:

* 400 Pin FMC connector
** Provides SPI interface
** ADC Synchronization
** Support for 32 LVDS analog signals
** Supply voltage of fused +12V, Switched 3.3V and 1.2-3.3V adjustable
* 32 channel Analog inputs via Hirose connector '''[FX2-40S-1.27DS(71)] 
'''
* 1V analog reference voltage '''[LTC6655BHMS8-3#PBF]'''
** ±2ppm
* Differential ADC Driver '''[ADA4950'''-'''2YCPZ]'''
** ±0.2mV Offset
** 9.2nHz / √Hz Output voltage Noise at Gain=1
** Adjustable output common-mode voltage
** Hardware programmable gain of 1x, 2x and 3x
* Dual 16 channel 14bit Analog to Digital converter '''[AD9249BBCZ-65]'''
** 2Vp-p input range
** 65MSPS
** ±0.6LSB
** Input Clock of 10-520MHz
* 16 channel 12bit Digital to Analog converter '''[ADA4950-2YCPZ]'''
** Programmable offset voltage
** SPI configurable outputs
** Output range ±2.5V, 0V upon reset
** 1.22mV/LSB
* 1 x eSATA Clk-In / Clk-out to and from FMC connector

= Cathode pad signal path =

The 18432 cathode pads covering the inner surface of the outer wall of the detector are individually connected to a signal acquisition chain. This collected signals will provide the position of the electron avalanche at the anode wire. Combining them in charge, permit the reconstruction of the track passing through the longitudinal direction the detector. While the cathode pads cover a large area (2.7m2), the actual footprint per channel is limited (3.8mmx37.1mm). Therefore a high-density waveform digitizer chain has been chosen based on our previous experience with the T2K experiment, we opted for the AFTER Switched Capacitor Array (SCA) ASIC. The analog signal path is short as the pads themselves are on the backside the physical outer cylinder of the detector and the input signal connectors to the AFTER chips are on the opposite side of the outer cylinder.

A custom frontend board (FEAM) see Figure 10 handling 288 individual cathode pads has been designed. It is composed of 4 ASIC AFTER (72 channels) with associated waveform digitizer for the individual signal on 512 cells at 20Msps. In addition, an FPGA manages the board services and the data collection and transmission through a 1 gigabit/sec optical link to the Ethernet using the UDP protocol.

While the power consumption per channel at the ASIC level is low, the power requirement is in the order of 15W per board for a total at the detector level approaching 1000W. This required proper cooling to maintain a reliable operation of the electronics. Figure 11 shows the board temperature with and without cooling plate. Thermal images have been taken to confirm the temperature reduction of the main heat source (Clock cleaner, FPGA, ADC, AFTER in that order). We can guarantee a chip temperature below 60°C to keep the default chip MTBF.

[[File:image12daq.jpg|558x246px]]

Figure 10 - Cathode Pad Board readout for 288 channels at 62.5Msps, visible 4 AFTER chips, 3 copper bars running under the central board for power distribution

[[File:image13daq.png|249x185px]]
[[File:image14daq.png|247x186px]]
[[File:image15daq.jpg|248x186px]]

Figure 11 – Thermal image of the FEAM with hot spot temperature: without cooling plate (78°C), with cooling plate (45°C), with cooling plate & water cooling (36°C)

== Cathode Pad Circuit ==

The cathode pads are read-out by AFTER ASIC which diagram is presented in Figure 12. Each channel consists of a charge-sensitive preamplifier, pole-zero cancellation of preamplifier decay time, RC2 shaper and 512-cell SCA to store the waveform. Amplifier gain, pole-zero time constant and shaping time are programmable.

{|
|
[[File:image16daq.png|361x171px]]

Figure 12 - Block diagram of AFTER amplifier
| [[File:image17daq.png|215x199px]]
|}

The acquisition of the FEAM cards is operational and initial waveforms can be displayed as seen in Figure 13. This visualization is for monitoring the individual channels only. The data acquisition is using a different path for fast data collection. Figure 13 shows cathode signal examples collected by the FEAM card. The signal shape is consistent with avalanches occurring from a cosmic track going through the detector. The initial pulse corresponds to the early avalanches when the track crosses the amplification region (near the anode wire). The remaining pulses show the later electron avalanches reaching the same anode wire from the drift region due to the track angle. The complex pulse shape from the drift region reflects the convolution in this time base of the arrival of the electron to the amplification region and the induced pulse from the resulting electron avalanche.

= Barrel Scintillator signal path =

'''''Note''''': While the Barrel Scintillator is part of the Alpha-g detector for cosmic rejection purpose, this section is still under development. The initial concept and implementation are therefore not final. The volume allocated for it in the other hand well defined due to external to the detector constraints.

Light at both ends of each bar of the barrel scintillator is collected for a rough position detection of the crossing particle and timing information. To improve the detection information (maximize photon collection), 6 individual SiPM light detector (SensL) are mounted on both ends of the individual scintillator bar for a coverage of 50% of the bar. This assembly is in a light-tight and gas-tight enclosure. A cold gas flows through the box to lower the SiPM temperature operation in order to reduce the dark noise of the device. A shaper/amplifier board (BSB) will be mounted on the outside of the enclosure. Each of the board will acquire the signals of 4 adjacent scintillator bars. In total 64 scintillator bars are read out by 16 boards at each end. A block diagram of one bar readout is shown in Figure 14. The signal gathering of the 6 sensors is based on an analog sum.

[[File:image18daq.png|480x296px]]

Figure 14 - Block diagram of one channel of SiPM amplifier

The 6 pre-amplifier outputs are combined to provide the sum of 6 signals. This resulting signal is further amplified and shaped (if necessary) on a second stage post-amplifier/discriminator. This signal sent to the readout system through a cable driver. Two signals will be acquired from each bar: (1) Analog sum fed to a waveform digitizer with proper digital processing to determine event position and timing; (2) LVDS signal fed to a TDC for off-line precise timing measurement purposes. For the LVDS signal, the post-amplifier will have a controlled threshold voltage to the signal comparator.

The BSB will be powered by standard +5V and -5V linear supplies. Each board has a test input to allow individual board measure of the amplifier response, malfunction test and to provide the necessary services to the light sensors device (Voltage bias, temperature sensor, etc).

The output of the analog output of the BSB will be shaped for the 100Msps WFD and in parallel will issue a digital signal for timing information to a TDC.

= Trigger Distribution =

On the full-length detector, the FEAM boards will receive trigger and clock signals from the CDM through the Trigger Card Adapter. The adapter receives signals from the CDM via a 7 pin SATA connector. The signals can be re-driven by repeaters on the adapter and are sent down a chain of 7 Trigger Cards with the adapter forming the first link.

While there are other elegant means of distributing the common clock and trigger to all the electronics boards, this method is the most simple and robust.

[[File:image19daq.png|195x575px|Adapter]]

[[File:image20daq.png|573x43px|Trigger_Board]]

Figure 15 - Trigger Card Adapter and Trigger Card

[[File:image21daq.jpg|216x294px|20170914_101103_resized]]

Figure 16 Trigger Card to FEAM

A Samtec SFM-110 connects each card to a FEAM board and also provides through holes pins where another card can be overlapped and soldered. In this manner the chain of Trigger Distribution Cards is formed, providing a shared clock and trigger signal to a column of 8 FEAM boards.

= Clock Distribution Module =

[[File:image22daq.png|231x356px]]

Figure 17 - Clock Distribution Module

* 6x LEMO Connectors [2 Output, 4 Input]
* 6x Mini-SAS providing up to 24 channels of clock and synchronization breakout
* 1x Combination eSATA/USB connector
** eSATA provides CLK and SYNC
** USB provides USB to Serial communication 115200 BAUD
* 1x 10/100 Base-TX Ethernet
* Optional Atomic Clock module support, 10MHz and 1PPS '''[CSAC - SA.45s]'''
** Short term Stability <1E-11
** over 1000 seconds (100μHz / 1000s)
** Aging rate of <9E-10 per month '''('''9mHz/month)
* Onboard 10MHz Crystal Oscillator '''[FOX924B-10.000]'''
** ±2.5ppm
** ±1ppm per year
* JTAG ARM Support
* SmartFusion2 SoC '''[MS2-FG484]'''
* Ultra-low noise clock jitter cleaner 3:15 input to output support '''[LMK04821] '''
** Min/Max VCO Frequency 2750/3072MHz
** 0.111RMS Jitter
* TTL and NIM signal compatibility for external CLK and SYNC
* VME - 6U - 3Row
* Approximate Current Draw 1.837A at 5V

The Clock Distribution Module ('''CDM)''' has the capability to distribute two externally sourced clock and synchronization signals to six mini-SAS connections for total 24 signal signals. The external signals are provided through the eSATA and LEMO 1A/B Connectors. The module also has the capability to add an Atomic clock that outputs a 10Mhz signal and a 1 Pulse Per Second (PPS), as well as user-defined synchronization signal. Lastly, the module can be configured to output the external clock signals to the LEMO 2B connector or VME bus.

[[File:image23daq.png|509x348px]]

Figure 18 - IO Block Diagram

[[File:image24daq.png|299x412px]]

Figure 19 - ALPHA-16 and CDM board in front with the Trigger/Clock distribution cables

= Frontend Board Firmware =

The firmware (FW) refers to the embedded code running on the Field Programmable Gate Arrays (FPGAs) and microcontrollers (MCUs) located on the various modules within the experiment. These devices store, load, and run the programs required for operation of the different digital electronic components within the experiment.

Firmware code is essential to the operation of the detector as it provides the mechanism to configure the hardware for its particular purpose. Such as analog-to-digital conversion, data filtering, data trigger composition, transport of the data, and orchestration of all the different hardware modules to succeed in acquiring meaningful information across the overall system. Some of the firmware tasks are:

<ol style="list-style-type: upper-roman;">
<li>Low-level acquisition of the 3 different WFDigitizers (Anode wire, Cathode pad, Barrel Scintillator)</li>
<li>Links all the electronics boards to the DAQ system.</li>
<li>Collected in real-time information for trigger decision making.</li>
<li>Distribute synchronization signals and trigger to all the acquisition boards.</li>
<li>Provides to the user; configurable board and operation parameters settings.</li>
<li>Provides board monitoring and debugging tools.</li></ol>

Most of the FW code base has been based off of prior code developed for the currently running GRIFFIN experiment, with some exceptions, such as the Trigger Master Module which needed custom code specific to ALPHA-g, and the PADWING, which contained the AFTER SCA chip not present in GRIFFIN.



The firmware code is loaded onto the hardware board where an FPGA or MCU is present. Each firmware module has specific firmware capabilities, detailed as follows:

* Hit Detector firmware Module (ALPHA-16 carrier board)
** Anode Wire and Barrel Scint. signal waveform digitizers acquisition
** Local data filtering for Trigger purpose
** Transmission of summary data to Trigger Module for trigger decision
** Data compression/filtering and retention for transmission to backend on Trigger reception
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Pad Acquisition firmware Module (PADWING board)
** Cathode pad signal waveform digitizers acquisition
** Data compression/filtering and retention for transmission to backend on Trigger reception
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Master Trigger firmware Module (ALPHA-T board)
** Summary data reception of the multiple GRIF-16 boards
** Trigger decision algorithm
** Packaging of Trigger decision information and transmission to the backend.
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Clock and Trigger Distribution firmware Module (CDM board)
** Monitoring of hardware functions (U,I,T,Clock Frequency)
** Configuration of hardware mechanism for clock and trigger distribution
** Update of firmware code mechanism

== '''Hit Detector Module (ALPHA-16)''' ==

The Hit Detector firmware module handles the acquisition of the analog input signals from the anode wires and scintillators, the digital conversion of that data, and then the transfer of that data to both the DAQ and the Trigger Master. The first implementation of the hit detection is based on hit multiplicity. Later on, a more sophisticated algorithm will be implemented to determine in real time the timing and charge collected for each channel. This information will be transferred to the Trigger Master for more efficient trigger filtering.

The ADC data is acquired from both the FMC ADC32 ADCs and the onboard 16ch 14-bit ADCs using the FPGAs hardware SERDES modules. These modules de-serialize the data stream from the ADCs into a format suitable for internal analysis for hit detection, and for transfer to the MIDAS DAQ.

Once one or more hits are detected, the ALPHA-16 transmits the hit count to the ALPHA-T for a hit multiplicity test, and then waits for a trigger response to decide to discard or transmit the waveform data associated with the detected hit to the DAQ.

Currently, when a trigger is fired by the Trigger Decision module, all channels transmit their captured waveforms to the DAQ. In the future, only channels that have detected a hit will send waveforms on a trigger.

System monitoring and configuration of the Hit Detector module is handled by ESPER running on a NIOS-II soft-core processor instantiated within the FPGA. The OS used is Micrium µC/OS-II, a small real-time OS licensed by Altera for use with their NIOS-II processor. ESPER performs the remote upgrading of the Hit Detector, viewing of the captured waveforms, and diagnostic reading and writing of all firmware settings and counters via a simple JSON-based interface, or an HTML based webpage.

[[File:image25daq.png|517x318px]]

Figure 20 - Hit Detector for the Anode wire and scintillators in ALPHA-16

== '''Pad Acquisition Module (FEAM)''' ==

The pad acquisition firmware module handles the collection of the PAD analog signals captured by the four AFTER ASICs on the module. Capture occurs upon receiving a trigger signal from the Trigger Decision module. Once captured, the AFTER data is transmitted to the MIDAS DAQ over ethernet. No pad information is provided back to the Trigger Decision module.

Each of the AFTER ASICs transmits its captured analog data to a 12-bit ADC which in turn converts the analog signal into digital data and transmits that to the FPGA. The FPGA uses its internal SERDES hardware to de-serialize this data and process it. Once captured, channels that do not contain data of interest are suppressed, and the data is packaged up and sent out over UDP to the MIDAS DAQ.

In the event that the SFP module that provides ethernet connectivity fails, each PAD acquisition module is connected to one other PAD acquisition module via a secondary gigabit link. While currently unused, this link will be used in the future to support a backup link to the DAQ, in the event of a failure of the primary gigabit link.

System monitoring and configuration of the PAD acquisition module is handled by ESPER running on a NIOS-II soft-core processor instantiated within the FPGA. The OS used is Micrium µC/OS-II, a small real-time OS licensed by Altera for use with their NIOS-II processor. ESPER performs the remote upgrading of the Hit Detector, viewing of the captured waveforms, and diagnostic reading and writing of all firmware settings and counters via a simple JSON-based interface, or an HTML based webpage.

[[File:image26daq.png|490x299px]]

Figure 21 - AFTER chip WFD on the PADWINGS

== '''Trigger Master module (ALPHA-T)''' ==

The Trigger Master firmware module is to collect information from the anode wires and scintillators to make a real-time decision if the current physics event is to be recorded. That decision is fed to all the readout boards to trigger the storage of this particular event.

Initial trigger decision will be based on hit multiplicity of each of the ALPHA-16 boards. As the ALPHA-16 is acquiring the anode wire and the barrel scintillator signals, both of these 2 pieces of equipment will contribute to the trigger decision. Dedicated link from each of the ALPHA-16 (hit detector) to the Trigger module will be gathering the overall information for a final decision. Hardware trigger signal is then sent from the ALPHA-T to the CDM for distribution to all the acquisition modules to initiate the transmission of their data to the backend computer through UDP. The trigger board will compose a summary of the trigger information which will also be transferred to the backend.

The Trigger Master module contains two Mini-SAS FMCs, and one ‘communication’ FMC, that consists of a SATA, an SFP, and a Mini-SAS connector. This configuration of FMCs allows for up to twenty (20) 1G/2.5G/5G links via the Mini-SAS, in addition to a 1 Gbit/sec Ethernet connection via the SFP, and clock+trigger over the SATA.

[[File:image27daq.png|576x304px]]

Figure 22 - Trigger decision on ALPHA-T

== System Monitoring and debugging capability ==

The system monitoring is based on the ESPER protocol provided by the Electronics Development group at TRIUMF. Featuring a built-in web server, with real-time digitizer display, remote upgrade, and JSON-accessible parameters. ESPER allows for real-time diagnostics and testing to be performed on the various electronic modules using either JSON-based requests or a built-in webpage.

[[File:image28daq.png|576x67px]][[File:image29daq.png|576x286px]]

Figure 23 - ESPER Web Display. Test pulse recorded by the FEAM cards. Individual AFTER chip configuration is visible (gain change, delay).

= Safety and Hazard considerations =

There are no safety or hazard issues in FE system. All amplifiers are low-voltage and low-power circuits built with standard electronics components.

Detector Electronics

2017-11-19T20:50:55Z

Midas: /* Cathode pad signal path */

Back to [[Documentation]]

= Table of Figures =

[[#_Toc493676266|Figure 1 - Overall Data Acquisition scheme 7]]

[[#_Toc493676267|Figure 2 - Anode wire pre-amplification block diagram 8]]

[[#_Toc493676268|Figure 3 - Anode Wire Board (AWB), 16 channels pre-amplifier 9]]

[[#_Toc493676269|Figure 4 - 4 consecutive anode wire signals 9]]

[[#_Toc493676270|Figure 5 - Anode wire pre-amp gain map for half the chamber circumference 10]]

[[#_Toc493676271|Figure 6 - Alpha16 Data Acquisition Board 12]]

[[#_Toc493676272|Figure 7 - Grif16 Acquisition Module Block Diagram on which the Alpha-16 is based 12]]

[[#_Toc493676273|Figure 8 - Model of the new 32channels 12bit @ 65Msps FMC produced in 2016. 13]]

[[#_Toc493676274|Figure 9 - FMC Alpha-ADC32 Block Diagram 13]]

[[#_Toc493676275|Figure 10 - Cathode Pad Board readout for 288 channels at 62.5Msps, visible 4 AFTER chips, 3 copper bars running under the central board for power distribution 15]]

[[#_Toc493676276|Figure 11 – Thermal image of the FEAM with hot spot temperature: without cooling plate (78°C), with cooling plate (45°C), with cooling plate & water cooling (36°C) 16]]

[[#_Toc493676277|Figure 12 - Block diagram of AFTER amplifier 17]]

[[#_Toc493676278|Figure 13 - 4 x 72 cathode pad signals, overall time width corresponds to the drift time 17]]

[[#_Toc493676279|Figure 14 - Block diagram of one channel of SiPM amplifier 18]]

[[#_Toc493676280|Figure 15 - Trigger Card Adapter and Trigger Card 19]]

[[#_Toc493676281|Figure 16 Trigger Card to FEAM 19]]

[[#_Toc493676282|Figure 17 - Clock Distribution Module 20]]

[[#_Toc493676283|Figure 18 - IO Block Diagram 21]]

[[#_Toc493676284|Figure 19 - ALPHA-16 and CDM board in front with the Trigger/Clock distribution cables 22]]

[[#_Toc493676285|Figure 20 - Hit Detector for the Anode wire and scintillators in ALPHA-16 24]]

[[#_Toc493676286|Figure 21 - AFTER chip WFD on the PADWINGS 25]]

[[#_Toc493676287|Figure 22 - Trigger decision on ALPHA-T 26]]

[[#_Toc493676288|Figure 23 - ESPER Web Display. Test pulse recorded by the FEAM cards. Individual AFTER chip configuration is visible (gain change, delay). 27]]

= Introduction =

This design note describes the electronics chain and components for the readout of the ALPHA-g TPC and barrel scintillator bars.

= Scope =

The Detector Electronics is composed of 3 independent signal sources:

# Anode Wire signals path
# Cathode Pad signals path
# Barrel Scintillator signals path.

All 3 sources provide a similar function such as signal amplification and conditioning (shaping).

= Definitions and Abbreviations =

General acronyms or terms used for the ALPHA-g experiment

{|
! TPC
! Radial Time projection Chamber
|-
| Pads
| PCB surface seeing the induced anode wire signal
|-
| SiPM
| Si photomultipliers used to detect scintillation light
|-
| ADC
| Analog to digital converter
|-
| ASIC
| Application specific integrated circuit
|-
| SCA
| Switch Capacitor Array ( A type of Waveform Digitizer)
|-
| TDC
| Time to digital converter
|-
| BSM
| Barrel Scintillator Module (64 bars sub-assembly)
|-
| FEAM, Padwing
| Cathode strip acquisition board
|-
| CDM
| Clock Distribution Module
|-
| BSB
| Barrel Scintillator Board
|-
| WFD
| Waveform Digitizer
|}

Table 1 – ALPHA-g Abbreviations

= References and related Document =

* AFTER manual
* SensL SPM data sheet
* Edev-group.triumf.ca: contains the FW information on all the Alpha-g custom cards ([https://edev-group.triumf.ca/fw/exp/alphag/feam/rev0/wikis/feam-test-packet-format https://edev-group.triumf.ca/fw/exp/alphag])

* ''' 
'''

= Overall Detector Signal Path =

The Alpha-g detector provides 3 analog signals that are collected for the track reconstruction to help on the annihilation location in the trap.

* The anode wire signal providing the drift time of the electron through the detector for an angular position.
* The cathode pad signal, which are in-time correlated to the anode wire signal, providing the amplitude of these signals from which the longitudinal position (Z) can be extracted.
* The Barrel Scintillator bar signals provide the time and amplitude of the particle crossing the detector. The Barrel Scintillator is mainly to reject cosmic events. For that purpose, the timing resolution is important. Therefore the BSM analog signal is split early in the chain to record the amplitude and time separately.

The anode wires and the barrel scintillator bars are read out from both ends to provide a coarse Z-position as well. The Data acquisition is therefore made for reading 2x256 anode wire channels, 2x64 barrel scintillator bars and 18432 channels of cathode pads covering the outer detector cylinder.

[[File:image2daq.png|576x379px]]

Figure 1 - Overall Data Acquisition scheme

= Anode wire signal path =

The design for the anode wires pre-amplifier is based on work done for several other projects used at TRIUMF and other labs.

Each of the 256 anode wires are read-out from two ends. The signals are used to (1) determine phi-position of ionization track; (2) reconstruct its z-position by weighting signals from two wire ends; (3) generate trigger signal. The pre-amplifiers convert the induced current to voltage that is digitized and processed in the readout system. The main requirements for the amplifier circuit are:

# Input impedance must be low enough so detected charge is sensitive to position of event along wire;
# The shape of signal is optimized for sampling frequency (16 ns) and for fast trigger timing (few ns accuracy);
# Linearity range adjusted for ADC used;
# Gain is adjusted for gas amplification of 105
# Amplifier noise is low enough to detect single-electron cluster.

[[File:image3daq.png|576x204px]]

Figure 2 - Anode wire pre-amplification block diagram

Anode wires are HV-decoupled before connected to the amplifier, but additional (not HV) decoupling is needed at amplifier input to accommodate non-zero potential of the input stage. Protection of the amplifier input is using a standard bi-diode configuration. The first stage is a current-sensitive loop with input impedance defined by resistor Rin and trans-impedance (gain) by feedback resistor Rf. The second stage is 2-pole shaper with shaping time constant defined by components Rs and Cs. The last stage is a cable driver.

Overall gain, transfer function and input impedance of the circuit can be adjusted by changing passive components. This adjustment will be done with studying the TPC prototypes.

Amplifiers are deployed on 16-channel cards, 16 boards serve each end of TPC. They are powered by standard +5V and -5V linear supplies. Each card has a test input that is used to measure amplifiers response and to check for malfunction.

[[File:image4daq.jpg|173x183px]] [[File:image5daq.png|169x184px]]

Figure 3 - Anode Wire Board (AWB), 16 channels pre-amplifier

The AWB schematic allow for bi-polar signal input. This has the advantage to reproduce the full anode wire signal development including the inverted induced pulse from neighbouring wires as seen Figure 4.

[[File:image6daq.jpg|512x358px]]

Figure 4 - 4 consecutive anode wire signals

The anode pre-amps have an individual test pulse input to provide a quick functional test. It can also be used for calibration purpose. Several tests have been done in this regard, but the overall chain gain is dependent on many variables (chamber geometry, environmental condition (Gas mixture, T, P), pre-amp (layout, components)). Another more common test pulse injection is available by pulsing all the field wires at once (at the boundary of the drift and multiplication region). This technique has the advantage to produce an induced signal on all the anode wires and cathode pads together at the “same” time. Figure 5 shows the gain variation by wire seen when pulsed through the field wire. 2 interesting features are visible:

a) An overall negative slope, indicated by the linear fit. This slope is explained by the pulse attenuation through the field wires distribution.

b) A clear increase in gain for the wires near the anode wire card boundaries, indicated by the cyan lines is not yet well understood. A further test is planned.

[[File:image7daq.png|397x289px]]

Figure 5 - Anode wire pre-amp gain map for half the chamber circumference

== Anode Wire Waveform digitizer (Alpha-16) ==

The output of the AWB is presented to the Alpha-16 waveform digitizer sampling the analog signal at 62.5Msps.

'''''Note:''''' At the time of this report, the WFD 62.5Msps is not yet available. We use the WFD at 100Msps to perform the tests. The firmware is similar to the 62.5Msps and the final test will be reproduced later.

This module provides 16 channels 14bit ADC @100Msps for 50Ohms single-ended analog signal for the barrel scintillator. It also supports a dedicated mezzanine card (FMC) handling 32 channels 12bit ADC @ 65Msps for single-ended 50Ohms analog signals for the Anode wires.

The Alpha-16 board outputs (16ch.@100Msps and 32ch.@62.5Msps) are collected on the main carrier FPGA for transmission through Ethernet to the backend computer.

The board carries multiple I/O connections required for the module configuration, communication, data transfer, signal inputs, see Figure 7.

* Front panel SFP Gbit Ethernet (copper/fiber)
* Front panel eSATA: clock and sync inputs
* Front panel dual LEMO: Diagnostic DAC outputs (250Msps)
* Front panel MCX connector for 16 x ADC inputs
* Rear entry P2 connector for 16 x ADC inputs
* A24/D16 VME interface to MAXV configuration CPLD
** VME configuration flash updates
** VME bridge to FPGA
* FMC custom module connections.
** Dual MiniSAS for Acquisition setup
** 10 x5Gibt Link
** JESD204B Clocks
** Supports 32 Channel ADC LVDS interface
* Amplifier input switches: Front panel MCX connector, Rear Transition Card SMA connector
* Amplifier Gain x1 and x4
* Switch selectable LEMO NIM Input/ DAC outputs
* Micro SD Flash
* DDR3 DRAM – 667MHz – 128M x 23'''(MT41J128M16HA-15E)'''
* FPGA - Arria V '''(5AGXFB3H4F35C4N)'''
* MAXV CPLD controller '''(5M2210ZF256C5N)''' for USB JTAG and VME access

[[File:image8daq.jpg|218x380px]]

Figure 6. Alpha16 Data Acquisition Board

[[File:image9daq.png|264x383px]]

Figure 7. Grif16 Acquisition Module Block Diagram on which the Alpha-16 is based

== FMC – Alpha ADC32 ==

<blockquote>The FMC – ALPHA ADC32 provides single-stage amplification of up to 32 single-ended 50<math>\Omega</math> analog signals, from the Anode Wire Board Pre-Amplifier, to drive two 16 channel 14bit differential, analog to digital converters sampling at 65MSPS. Further, each ADC will provide a 0.9V common mode offset voltage to be fed into the differential driver

A 16 channel 12 bit digital-to-analog (DAC) converter is used to individually apply an appropriate offset voltage to each of the differential amplifier pairs. The Offset voltages span <math>\pm</math>2.5Vat 1.22mV increments and will output 0V upon power cycle. The DAC is configurable via an SPI interface via the FMC connector.

ADC32 board has the capability to receive and transmit an LVDS clock signal through the eSATA connector which is fed to the FMC connector
</blockquote>
[[File:imagedaq10.png|318x307px]]

Figure 8 - Model of the new 32channels 12bit @ 65Msps FMC produced in 2016.

[[File:imagedaq11.png|420x285px]]

Figure 9 - FMC Alpha-ADC32 Block Diagram

<blockquote>''These notes are for the current revision of the Alpha ADC32, a new revision is currently being talked about''
</blockquote>
The board is composed of the following elements:

* 400 Pin FMC connector
** Provides SPI interface
** ADC Synchronization
** Support for 32 LVDS analog signals
** Supply voltage of fused +12V, Switched 3.3V and 1.2-3.3V adjustable
* 32 channel Analog inputs via Hirose connector '''[FX2-40S-1.27DS(71)] 
'''
* 1V analog reference voltage '''[LTC6655BHMS8-3#PBF]'''
** ±2ppm
* Differential ADC Driver '''[ADA4950'''-'''2YCPZ]'''
** ±0.2mV Offset
** 9.2nHz / √Hz Output voltage Noise at Gain=1
** Adjustable output common-mode voltage
** Hardware programmable gain of 1x, 2x and 3x
* Dual 16 channel 14bit Analog to Digital converter '''[AD9249BBCZ-65]'''
** 2Vp-p input range
** 65MSPS
** ±0.6LSB
** Input Clock of 10-520MHz
* 16 channel 12bit Digital to Analog converter '''[ADA4950-2YCPZ]'''
** Programmable offset voltage
** SPI configurable outputs
** Output range ±2.5V, 0V upon reset
** 1.22mV/LSB
* 1 x eSATA Clk-In / Clk-out to and from FMC connector

= Cathode pad signal path =

The 18432 cathode pads covering the inner surface of the outer wall of the detector are individually connected to a signal acquisition chain. This collected signals will provide the position of the electron avalanche at the anode wire. Combining them in charge, permit the reconstruction of the track passing through the longitudinal direction the detector. While the cathode pads cover a large area (2.7m2), the actual footprint per channel is limited (3.8mmx37.1mm). Therefore a high-density waveform digitizer chain has been chosen based on our previous experience with the T2K experiment, we opted for the AFTER Switched Capacitor Array (SCA) ASIC. The analog signal path is short as the pads themselves are on the backside the physical outer cylinder of the detector and the input signal connectors to the AFTER chips are on the opposite side of the outer cylinder.

A custom frontend board (FEAM) see Figure 10 handling 288 individual cathode pads has been designed. It is composed of 4 ASIC AFTER (72 channels) with associated waveform digitizer for the individual signal on 512 cells at 20Msps. In addition, an FPGA manages the board services and the data collection and transmission through a 1 gigabit/sec optical link to the Ethernet using the UDP protocol.

While the power consumption per channel at the ASIC level is low, the power requirement is in the order of 15W per board for a total at the detector level approaching 1000W. This required proper cooling to maintain a reliable operation of the electronics. Figure 11 shows the board temperature with and without cooling plate. Thermal images have been taken to confirm the temperature reduction of the main heat source (Clock cleaner, FPGA, ADC, AFTER in that order). We can guarantee a chip temperature below 60°C to keep the default chip MTBF.

[[File:image12daq.jpg|558x246px]]

Figure 10 - Cathode Pad Board readout for 288 channels at 62.5Msps, visible 4 AFTER chips, 3 copper bars running under the central board for power distribution

[[File:imagedaq13.png|249x185px]]
[[File:imagedaq14.png|247x186px]]
[[File:imagedaq15.jpg|248x186px]]

Figure 11 – Thermal image of the FEAM with hot spot temperature: without cooling plate (78°C), with cooling plate (45°C), with cooling plate & water cooling (36°C)

== Cathode Pad Circuit ==

The cathode pads are read-out by AFTER ASIC which diagram is presented in Figure 12. Each channel consists of a charge-sensitive preamplifier, pole-zero cancellation of preamplifier decay time, RC2 shaper and 512-cell SCA to store the waveform. Amplifier gain, pole-zero time constant and shaping time are programmable.

{|
|
[[File:imagedaq16.png|361x171px]]

Figure 12 - Block diagram of AFTER amplifier
| [[File:imagedaq17.png|215x199px]]
|}

The acquisition of the FEAM cards is operational and initial waveforms can be displayed as seen in Figure 13. This visualization is for monitoring the individual channels only. The data acquisition is using a different path for fast data collection. Figure 13 shows cathode signal examples collected by the FEAM card. The signal shape is consistent with avalanches occurring from a cosmic track going through the detector. The initial pulse corresponds to the early avalanches when the track crosses the amplification region (near the anode wire). The remaining pulses show the later electron avalanches reaching the same anode wire from the drift region due to the track angle. The complex pulse shape from the drift region reflects the convolution in this time base of the arrival of the electron to the amplification region and the induced pulse from the resulting electron avalanche.

= Barrel Scintillator signal path =

'''''Note''''': While the Barrel Scintillator is part of the Alpha-g detector for cosmic rejection purpose, this section is still under development. The initial concept and implementation are therefore not final. The volume allocated for it in the other hand well defined due to external to the detector constraints.

Light at both ends of each bar of the barrel scintillator is collected for a rough position detection of the crossing particle and timing information. To improve the detection information (maximize photon collection), 6 individual SiPM light detector (SensL) are mounted on both ends of the individual scintillator bar for a coverage of 50% of the bar. This assembly is in a light-tight and gas-tight enclosure. A cold gas flows through the box to lower the SiPM temperature operation in order to reduce the dark noise of the device. A shaper/amplifier board (BSB) will be mounted on the outside of the enclosure. Each of the board will acquire the signals of 4 adjacent scintillator bars. In total 64 scintillator bars are read out by 16 boards at each end. A block diagram of one bar readout is shown in Figure 14. The signal gathering of the 6 sensors is based on an analog sum.

[[File:imagedaq18.png|480x296px]]

Figure 14 - Block diagram of one channel of SiPM amplifier

The 6 pre-amplifier outputs are combined to provide the sum of 6 signals. This resulting signal is further amplified and shaped (if necessary) on a second stage post-amplifier/discriminator. This signal sent to the readout system through a cable driver. Two signals will be acquired from each bar: (1) Analog sum fed to a waveform digitizer with proper digital processing to determine event position and timing; (2) LVDS signal fed to a TDC for off-line precise timing measurement purposes. For the LVDS signal, the post-amplifier will have a controlled threshold voltage to the signal comparator.

The BSB will be powered by standard +5V and -5V linear supplies. Each board has a test input to allow individual board measure of the amplifier response, malfunction test and to provide the necessary services to the light sensors device (Voltage bias, temperature sensor, etc).

The output of the analog output of the BSB will be shaped for the 100Msps WFD and in parallel will issue a digital signal for timing information to a TDC.

= Trigger Distribution =

On the full-length detector, the FEAM boards will receive trigger and clock signals from the CDM through the Trigger Card Adapter. The adapter receives signals from the CDM via a 7 pin SATA connector. The signals can be re-driven by repeaters on the adapter and are sent down a chain of 7 Trigger Cards with the adapter forming the first link.

While there are other elegant means of distributing the common clock and trigger to all the electronics boards, this method is the most simple and robust.

[[File:imagedaq19.png|195x575px|Adapter]]

[[File:imagedaq20.png|573x43px|Trigger_Board]]

Figure 15 - Trigger Card Adapter and Trigger Card

[[File:imagedaq21.jpg|216x294px|20170914_101103_resized]]

Figure 16 Trigger Card to FEAM

A Samtec SFM-110 connects each card to a FEAM board and also provides through holes pins where another card can be overlapped and soldered. In this manner the chain of Trigger Distribution Cards is formed, providing a shared clock and trigger signal to a column of 8 FEAM boards.

= Clock Distribution Module =

[[File:imagedaq22.png|231x356px]]

Figure 17 - Clock Distribution Module

* 6x LEMO Connectors [2 Output, 4 Input]
* 6x Mini-SAS providing up to 24 channels of clock and synchronization breakout
* 1x Combination eSATA/USB connector
** eSATA provides CLK and SYNC
** USB provides USB to Serial communication 115200 BAUD
* 1x 10/100 Base-TX Ethernet
* Optional Atomic Clock module support, 10MHz and 1PPS '''[CSAC - SA.45s]'''
** Short term Stability <1E-11
** over 1000 seconds (100μHz / 1000s)
** Aging rate of <9E-10 per month '''('''9mHz/month)
* Onboard 10MHz Crystal Oscillator '''[FOX924B-10.000]'''
** ±2.5ppm
** ±1ppm per year
* JTAG ARM Support
* SmartFusion2 SoC '''[MS2-FG484]'''
* Ultra-low noise clock jitter cleaner 3:15 input to output support '''[LMK04821] '''
** Min/Max VCO Frequency 2750/3072MHz
** 0.111RMS Jitter
* TTL and NIM signal compatibility for external CLK and SYNC
* VME - 6U - 3Row
* Approximate Current Draw 1.837A at 5V

The Clock Distribution Module ('''CDM)''' has the capability to distribute two externally sourced clock and synchronization signals to six mini-SAS connections for total 24 signal signals. The external signals are provided through the eSATA and LEMO 1A/B Connectors. The module also has the capability to add an Atomic clock that outputs a 10Mhz signal and a 1 Pulse Per Second (PPS), as well as user-defined synchronization signal. Lastly, the module can be configured to output the external clock signals to the LEMO 2B connector or VME bus.

[[File:imagedaq23.png|509x348px]]

Figure 18 - IO Block Diagram

[[File:imagedaq24.png|299x412px]]

Figure 19 - ALPHA-16 and CDM board in front with the Trigger/Clock distribution cables

= Frontend Board Firmware =

The firmware (FW) refers to the embedded code running on the Field Programmable Gate Arrays (FPGAs) and microcontrollers (MCUs) located on the various modules within the experiment. These devices store, load, and run the programs required for operation of the different digital electronic components within the experiment.

Firmware code is essential to the operation of the detector as it provides the mechanism to configure the hardware for its particular purpose. Such as analog-to-digital conversion, data filtering, data trigger composition, transport of the data, and orchestration of all the different hardware modules to succeed in acquiring meaningful information across the overall system. Some of the firmware tasks are:

<ol style="list-style-type: upper-roman;">
<li>Low-level acquisition of the 3 different WFDigitizers (Anode wire, Cathode pad, Barrel Scintillator)</li>
<li>Links all the electronics boards to the DAQ system.</li>
<li>Collected in real-time information for trigger decision making.</li>
<li>Distribute synchronization signals and trigger to all the acquisition boards.</li>
<li>Provides to the user; configurable board and operation parameters settings.</li>
<li>Provides board monitoring and debugging tools.</li></ol>

Most of the FW code base has been based off of prior code developed for the currently running GRIFFIN experiment, with some exceptions, such as the Trigger Master Module which needed custom code specific to ALPHA-g, and the PADWING, which contained the AFTER SCA chip not present in GRIFFIN.



The firmware code is loaded onto the hardware board where an FPGA or MCU is present. Each firmware module has specific firmware capabilities, detailed as follows:

* Hit Detector firmware Module (ALPHA-16 carrier board)
** Anode Wire and Barrel Scint. signal waveform digitizers acquisition
** Local data filtering for Trigger purpose
** Transmission of summary data to Trigger Module for trigger decision
** Data compression/filtering and retention for transmission to backend on Trigger reception
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Pad Acquisition firmware Module (PADWING board)
** Cathode pad signal waveform digitizers acquisition
** Data compression/filtering and retention for transmission to backend on Trigger reception
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Master Trigger firmware Module (ALPHA-T board)
** Summary data reception of the multiple GRIF-16 boards
** Trigger decision algorithm
** Packaging of Trigger decision information and transmission to the backend.
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Clock and Trigger Distribution firmware Module (CDM board)
** Monitoring of hardware functions (U,I,T,Clock Frequency)
** Configuration of hardware mechanism for clock and trigger distribution
** Update of firmware code mechanism

== '''Hit Detector Module (ALPHA-16)''' ==

The Hit Detector firmware module handles the acquisition of the analog input signals from the anode wires and scintillators, the digital conversion of that data, and then the transfer of that data to both the DAQ and the Trigger Master. The first implementation of the hit detection is based on hit multiplicity. Later on, a more sophisticated algorithm will be implemented to determine in real time the timing and charge collected for each channel. This information will be transferred to the Trigger Master for more efficient trigger filtering.

The ADC data is acquired from both the FMC ADC32 ADCs and the onboard 16ch 14-bit ADCs using the FPGAs hardware SERDES modules. These modules de-serialize the data stream from the ADCs into a format suitable for internal analysis for hit detection, and for transfer to the MIDAS DAQ.

Once one or more hits are detected, the ALPHA-16 transmits the hit count to the ALPHA-T for a hit multiplicity test, and then waits for a trigger response to decide to discard or transmit the waveform data associated with the detected hit to the DAQ.

Currently, when a trigger is fired by the Trigger Decision module, all channels transmit their captured waveforms to the DAQ. In the future, only channels that have detected a hit will send waveforms on a trigger.

System monitoring and configuration of the Hit Detector module is handled by ESPER running on a NIOS-II soft-core processor instantiated within the FPGA. The OS used is Micrium µC/OS-II, a small real-time OS licensed by Altera for use with their NIOS-II processor. ESPER performs the remote upgrading of the Hit Detector, viewing of the captured waveforms, and diagnostic reading and writing of all firmware settings and counters via a simple JSON-based interface, or an HTML based webpage.

[[File:imagedaq25.png|517x318px]]

Figure 20 - Hit Detector for the Anode wire and scintillators in ALPHA-16

== '''Pad Acquisition Module (FEAM)''' ==

The pad acquisition firmware module handles the collection of the PAD analog signals captured by the four AFTER ASICs on the module. Capture occurs upon receiving a trigger signal from the Trigger Decision module. Once captured, the AFTER data is transmitted to the MIDAS DAQ over ethernet. No pad information is provided back to the Trigger Decision module.

Each of the AFTER ASICs transmits its captured analog data to a 12-bit ADC which in turn converts the analog signal into digital data and transmits that to the FPGA. The FPGA uses its internal SERDES hardware to de-serialize this data and process it. Once captured, channels that do not contain data of interest are suppressed, and the data is packaged up and sent out over UDP to the MIDAS DAQ.

In the event that the SFP module that provides ethernet connectivity fails, each PAD acquisition module is connected to one other PAD acquisition module via a secondary gigabit link. While currently unused, this link will be used in the future to support a backup link to the DAQ, in the event of a failure of the primary gigabit link.

System monitoring and configuration of the PAD acquisition module is handled by ESPER running on a NIOS-II soft-core processor instantiated within the FPGA. The OS used is Micrium µC/OS-II, a small real-time OS licensed by Altera for use with their NIOS-II processor. ESPER performs the remote upgrading of the Hit Detector, viewing of the captured waveforms, and diagnostic reading and writing of all firmware settings and counters via a simple JSON-based interface, or an HTML based webpage.

[[File:imagedaq26.png|490x299px]]

Figure 21 - AFTER chip WFD on the PADWINGS

== '''Trigger Master module (ALPHA-T)''' ==

The Trigger Master firmware module is to collect information from the anode wires and scintillators to make a real-time decision if the current physics event is to be recorded. That decision is fed to all the readout boards to trigger the storage of this particular event.

Initial trigger decision will be based on hit multiplicity of each of the ALPHA-16 boards. As the ALPHA-16 is acquiring the anode wire and the barrel scintillator signals, both of these 2 pieces of equipment will contribute to the trigger decision. Dedicated link from each of the ALPHA-16 (hit detector) to the Trigger module will be gathering the overall information for a final decision. Hardware trigger signal is then sent from the ALPHA-T to the CDM for distribution to all the acquisition modules to initiate the transmission of their data to the backend computer through UDP. The trigger board will compose a summary of the trigger information which will also be transferred to the backend.

The Trigger Master module contains two Mini-SAS FMCs, and one ‘communication’ FMC, that consists of a SATA, an SFP, and a Mini-SAS connector. This configuration of FMCs allows for up to twenty (20) 1G/2.5G/5G links via the Mini-SAS, in addition to a 1 Gbit/sec Ethernet connection via the SFP, and clock+trigger over the SATA.

[[File:imagedaq27.png|576x304px]]

Figure 22 - Trigger decision on ALPHA-T

== System Monitoring and debugging capability ==

The system monitoring is based on the ESPER protocol provided by the Electronics Development group at TRIUMF. Featuring a built-in web server, with real-time digitizer display, remote upgrade, and JSON-accessible parameters. ESPER allows for real-time diagnostics and testing to be performed on the various electronic modules using either JSON-based requests or a built-in webpage.

[[File:imagedaq28.png|576x67px]][[File:image29.png|576x286px]]

Figure 23 - ESPER Web Display. Test pulse recorded by the FEAM cards. Individual AFTER chip configuration is visible (gain change, delay).

= Safety and Hazard considerations =

There are no safety or hazard issues in FE system. All amplifiers are low-voltage and low-power circuits built with standard electronics components.

Detector Electronics

2017-11-19T20:48:19Z

Midas:

Back to [[Documentation]]

= Table of Figures =

[[#_Toc493676266|Figure 1 - Overall Data Acquisition scheme 7]]

[[#_Toc493676267|Figure 2 - Anode wire pre-amplification block diagram 8]]

[[#_Toc493676268|Figure 3 - Anode Wire Board (AWB), 16 channels pre-amplifier 9]]

[[#_Toc493676269|Figure 4 - 4 consecutive anode wire signals 9]]

[[#_Toc493676270|Figure 5 - Anode wire pre-amp gain map for half the chamber circumference 10]]

[[#_Toc493676271|Figure 6 - Alpha16 Data Acquisition Board 12]]

[[#_Toc493676272|Figure 7 - Grif16 Acquisition Module Block Diagram on which the Alpha-16 is based 12]]

[[#_Toc493676273|Figure 8 - Model of the new 32channels 12bit @ 65Msps FMC produced in 2016. 13]]

[[#_Toc493676274|Figure 9 - FMC Alpha-ADC32 Block Diagram 13]]

[[#_Toc493676275|Figure 10 - Cathode Pad Board readout for 288 channels at 62.5Msps, visible 4 AFTER chips, 3 copper bars running under the central board for power distribution 15]]

[[#_Toc493676276|Figure 11 – Thermal image of the FEAM with hot spot temperature: without cooling plate (78°C), with cooling plate (45°C), with cooling plate & water cooling (36°C) 16]]

[[#_Toc493676277|Figure 12 - Block diagram of AFTER amplifier 17]]

[[#_Toc493676278|Figure 13 - 4 x 72 cathode pad signals, overall time width corresponds to the drift time 17]]

[[#_Toc493676279|Figure 14 - Block diagram of one channel of SiPM amplifier 18]]

[[#_Toc493676280|Figure 15 - Trigger Card Adapter and Trigger Card 19]]

[[#_Toc493676281|Figure 16 Trigger Card to FEAM 19]]

[[#_Toc493676282|Figure 17 - Clock Distribution Module 20]]

[[#_Toc493676283|Figure 18 - IO Block Diagram 21]]

[[#_Toc493676284|Figure 19 - ALPHA-16 and CDM board in front with the Trigger/Clock distribution cables 22]]

[[#_Toc493676285|Figure 20 - Hit Detector for the Anode wire and scintillators in ALPHA-16 24]]

[[#_Toc493676286|Figure 21 - AFTER chip WFD on the PADWINGS 25]]

[[#_Toc493676287|Figure 22 - Trigger decision on ALPHA-T 26]]

[[#_Toc493676288|Figure 23 - ESPER Web Display. Test pulse recorded by the FEAM cards. Individual AFTER chip configuration is visible (gain change, delay). 27]]

= Introduction =

This design note describes the electronics chain and components for the readout of the ALPHA-g TPC and barrel scintillator bars.

= Scope =

The Detector Electronics is composed of 3 independent signal sources:

# Anode Wire signals path
# Cathode Pad signals path
# Barrel Scintillator signals path.

All 3 sources provide a similar function such as signal amplification and conditioning (shaping).

= Definitions and Abbreviations =

General acronyms or terms used for the ALPHA-g experiment

{|
! TPC
! Radial Time projection Chamber
|-
| Pads
| PCB surface seeing the induced anode wire signal
|-
| SiPM
| Si photomultipliers used to detect scintillation light
|-
| ADC
| Analog to digital converter
|-
| ASIC
| Application specific integrated circuit
|-
| SCA
| Switch Capacitor Array ( A type of Waveform Digitizer)
|-
| TDC
| Time to digital converter
|-
| BSM
| Barrel Scintillator Module (64 bars sub-assembly)
|-
| FEAM, Padwing
| Cathode strip acquisition board
|-
| CDM
| Clock Distribution Module
|-
| BSB
| Barrel Scintillator Board
|-
| WFD
| Waveform Digitizer
|}

Table 1 – ALPHA-g Abbreviations

= References and related Document =

* AFTER manual
* SensL SPM data sheet
* Edev-group.triumf.ca: contains the FW information on all the Alpha-g custom cards ([https://edev-group.triumf.ca/fw/exp/alphag/feam/rev0/wikis/feam-test-packet-format https://edev-group.triumf.ca/fw/exp/alphag])

* ''' 
'''

= Overall Detector Signal Path =

The Alpha-g detector provides 3 analog signals that are collected for the track reconstruction to help on the annihilation location in the trap.

* The anode wire signal providing the drift time of the electron through the detector for an angular position.
* The cathode pad signal, which are in-time correlated to the anode wire signal, providing the amplitude of these signals from which the longitudinal position (Z) can be extracted.
* The Barrel Scintillator bar signals provide the time and amplitude of the particle crossing the detector. The Barrel Scintillator is mainly to reject cosmic events. For that purpose, the timing resolution is important. Therefore the BSM analog signal is split early in the chain to record the amplitude and time separately.

The anode wires and the barrel scintillator bars are read out from both ends to provide a coarse Z-position as well. The Data acquisition is therefore made for reading 2x256 anode wire channels, 2x64 barrel scintillator bars and 18432 channels of cathode pads covering the outer detector cylinder.

[[File:image2daq.png|576x379px]]

Figure 1 - Overall Data Acquisition scheme

= Anode wire signal path =

The design for the anode wires pre-amplifier is based on work done for several other projects used at TRIUMF and other labs.

Each of the 256 anode wires are read-out from two ends. The signals are used to (1) determine phi-position of ionization track; (2) reconstruct its z-position by weighting signals from two wire ends; (3) generate trigger signal. The pre-amplifiers convert the induced current to voltage that is digitized and processed in the readout system. The main requirements for the amplifier circuit are:

# Input impedance must be low enough so detected charge is sensitive to position of event along wire;
# The shape of signal is optimized for sampling frequency (16 ns) and for fast trigger timing (few ns accuracy);
# Linearity range adjusted for ADC used;
# Gain is adjusted for gas amplification of 105
# Amplifier noise is low enough to detect single-electron cluster.

[[File:image3daq.png|576x204px]]

Figure 2 - Anode wire pre-amplification block diagram

Anode wires are HV-decoupled before connected to the amplifier, but additional (not HV) decoupling is needed at amplifier input to accommodate non-zero potential of the input stage. Protection of the amplifier input is using a standard bi-diode configuration. The first stage is a current-sensitive loop with input impedance defined by resistor Rin and trans-impedance (gain) by feedback resistor Rf. The second stage is 2-pole shaper with shaping time constant defined by components Rs and Cs. The last stage is a cable driver.

Overall gain, transfer function and input impedance of the circuit can be adjusted by changing passive components. This adjustment will be done with studying the TPC prototypes.

Amplifiers are deployed on 16-channel cards, 16 boards serve each end of TPC. They are powered by standard +5V and -5V linear supplies. Each card has a test input that is used to measure amplifiers response and to check for malfunction.

[[File:image4daq.jpg|173x183px]] [[File:image5daq.png|169x184px]]

Figure 3 - Anode Wire Board (AWB), 16 channels pre-amplifier

The AWB schematic allow for bi-polar signal input. This has the advantage to reproduce the full anode wire signal development including the inverted induced pulse from neighbouring wires as seen Figure 4.

[[File:image6daq.jpg|512x358px]]

Figure 4 - 4 consecutive anode wire signals

The anode pre-amps have an individual test pulse input to provide a quick functional test. It can also be used for calibration purpose. Several tests have been done in this regard, but the overall chain gain is dependent on many variables (chamber geometry, environmental condition (Gas mixture, T, P), pre-amp (layout, components)). Another more common test pulse injection is available by pulsing all the field wires at once (at the boundary of the drift and multiplication region). This technique has the advantage to produce an induced signal on all the anode wires and cathode pads together at the “same” time. Figure 5 shows the gain variation by wire seen when pulsed through the field wire. 2 interesting features are visible:

a) An overall negative slope, indicated by the linear fit. This slope is explained by the pulse attenuation through the field wires distribution.

b) A clear increase in gain for the wires near the anode wire card boundaries, indicated by the cyan lines is not yet well understood. A further test is planned.

[[File:image7daq.png|397x289px]]

Figure 5 - Anode wire pre-amp gain map for half the chamber circumference

== Anode Wire Waveform digitizer (Alpha-16) ==

The output of the AWB is presented to the Alpha-16 waveform digitizer sampling the analog signal at 62.5Msps.

'''''Note:''''' At the time of this report, the WFD 62.5Msps is not yet available. We use the WFD at 100Msps to perform the tests. The firmware is similar to the 62.5Msps and the final test will be reproduced later.

This module provides 16 channels 14bit ADC @100Msps for 50Ohms single-ended analog signal for the barrel scintillator. It also supports a dedicated mezzanine card (FMC) handling 32 channels 12bit ADC @ 65Msps for single-ended 50Ohms analog signals for the Anode wires.

The Alpha-16 board outputs (16ch.@100Msps and 32ch.@62.5Msps) are collected on the main carrier FPGA for transmission through Ethernet to the backend computer.

The board carries multiple I/O connections required for the module configuration, communication, data transfer, signal inputs, see Figure 7.

* Front panel SFP Gbit Ethernet (copper/fiber)
* Front panel eSATA: clock and sync inputs
* Front panel dual LEMO: Diagnostic DAC outputs (250Msps)
* Front panel MCX connector for 16 x ADC inputs
* Rear entry P2 connector for 16 x ADC inputs
* A24/D16 VME interface to MAXV configuration CPLD
** VME configuration flash updates
** VME bridge to FPGA
* FMC custom module connections.
** Dual MiniSAS for Acquisition setup
** 10 x5Gibt Link
** JESD204B Clocks
** Supports 32 Channel ADC LVDS interface
* Amplifier input switches: Front panel MCX connector, Rear Transition Card SMA connector
* Amplifier Gain x1 and x4
* Switch selectable LEMO NIM Input/ DAC outputs
* Micro SD Flash
* DDR3 DRAM – 667MHz – 128M x 23'''(MT41J128M16HA-15E)'''
* FPGA - Arria V '''(5AGXFB3H4F35C4N)'''
* MAXV CPLD controller '''(5M2210ZF256C5N)''' for USB JTAG and VME access

[[File:image8daq.jpg|218x380px]]

Figure 6. Alpha16 Data Acquisition Board

[[File:image9daq.png|264x383px]]

Figure 7. Grif16 Acquisition Module Block Diagram on which the Alpha-16 is based

== FMC – Alpha ADC32 ==

<blockquote>The FMC – ALPHA ADC32 provides single-stage amplification of up to 32 single-ended 50<math>\Omega</math> analog signals, from the Anode Wire Board Pre-Amplifier, to drive two 16 channel 14bit differential, analog to digital converters sampling at 65MSPS. Further, each ADC will provide a 0.9V common mode offset voltage to be fed into the differential driver

A 16 channel 12 bit digital-to-analog (DAC) converter is used to individually apply an appropriate offset voltage to each of the differential amplifier pairs. The Offset voltages span <math>\pm</math>2.5Vat 1.22mV increments and will output 0V upon power cycle. The DAC is configurable via an SPI interface via the FMC connector.

ADC32 board has the capability to receive and transmit an LVDS clock signal through the eSATA connector which is fed to the FMC connector
</blockquote>
[[File:imagedaq10.png|318x307px]]

Figure 8 - Model of the new 32channels 12bit @ 65Msps FMC produced in 2016.

[[File:imagedaq11.png|420x285px]]

Figure 9 - FMC Alpha-ADC32 Block Diagram

<blockquote>''These notes are for the current revision of the Alpha ADC32, a new revision is currently being talked about''
</blockquote>
The board is composed of the following elements:

* 400 Pin FMC connector
** Provides SPI interface
** ADC Synchronization
** Support for 32 LVDS analog signals
** Supply voltage of fused +12V, Switched 3.3V and 1.2-3.3V adjustable
* 32 channel Analog inputs via Hirose connector '''[FX2-40S-1.27DS(71)] 
'''
* 1V analog reference voltage '''[LTC6655BHMS8-3#PBF]'''
** ±2ppm
* Differential ADC Driver '''[ADA4950'''-'''2YCPZ]'''
** ±0.2mV Offset
** 9.2nHz / √Hz Output voltage Noise at Gain=1
** Adjustable output common-mode voltage
** Hardware programmable gain of 1x, 2x and 3x
* Dual 16 channel 14bit Analog to Digital converter '''[AD9249BBCZ-65]'''
** 2Vp-p input range
** 65MSPS
** ±0.6LSB
** Input Clock of 10-520MHz
* 16 channel 12bit Digital to Analog converter '''[ADA4950-2YCPZ]'''
** Programmable offset voltage
** SPI configurable outputs
** Output range ±2.5V, 0V upon reset
** 1.22mV/LSB
* 1 x eSATA Clk-In / Clk-out to and from FMC connector

= Cathode pad signal path =

The 18432 cathode pads covering the inner surface of the outer wall of the detector are individually connected to a signal acquisition chain. This collected signals will provide the position of the electron avalanche at the anode wire. Combining them in charge, permit the reconstruction of the track passing through the longitudinal direction the detector. While the cathode pads cover a large area (2.7m2), the actual footprint per channel is limited (3.8mmx37.1mm). Therefore a high-density waveform digitizer chain has been chosen based on our previous experience with the T2K experiment, we opted for the AFTER Switched Capacitor Array (SCA) ASIC. The analog signal path is short as the pads themselves are on the backside the physical outer cylinder of the detector and the input signal connectors to the AFTER chips are on the opposite side of the outer cylinder.

A custom frontend board (FEAM) see Figure 10 handling 288 individual cathode pads has been designed. It is composed of 4 ASIC AFTER (72 channels) with associated waveform digitizer for the individual signal on 512 cells at 20Msps. In addition, an FPGA manages the board services and the data collection and transmission through a 1 gigabit/sec optical link to the Ethernet using the UDP protocol.

While the power consumption per channel at the ASIC level is low, the power requirement is in the order of 15W per board for a total at the detector level approaching 1000W. This required proper cooling to maintain a reliable operation of the electronics. Figure 11 shows the board temperature with and without cooling plate. Thermal images have been taken to confirm the temperature reduction of the main heat source (Clock cleaner, FPGA, ADC, AFTER in that order). We can guarantee a chip temperature below 60°C to keep the default chip MTBF.

[[File:image12daq.jpg|558x246px]]

Figure 10 - Cathode Pad Board readout for 288 channels at 62.5Msps, visible 4 AFTER chips, 3 copper bars running under the central board for power distribution

[[File:imagedaq13.png|249x185px]][[File:imagedaq14.png|247x186px]] [[File:imagedaq15.jpg|248x186px]]

Figure 11 – Thermal image of the FEAM with hot spot temperature: without cooling plate (78°C), with cooling plate (45°C), with cooling plate & water cooling (36°C)

== Cathode Pad Circuit ==

The cathode pads are read-out by AFTER ASIC which diagram is presented in Figure 12. Each channel consists of a charge-sensitive preamplifier, pole-zero cancellation of preamplifier decay time, RC2 shaper and 512-cell SCA to store the waveform. Amplifier gain, pole-zero time constant and shaping time are programmable.

{|
|
[[File:imagedaq16.png|361x171px]]

Figure 12 - Block diagram of AFTER amplifier
| [[File:imagedaq17.png|215x199px]]
|}

The acquisition of the FEAM cards is operational and initial waveforms can be displayed as seen in Figure 13. This visualization is for monitoring the individual channels only. The data acquisition is using a different path for fast data collection. Figure 13 shows cathode signal examples collected by the FEAM card. The signal shape is consistent with avalanches occurring from a cosmic track going through the detector. The initial pulse corresponds to the early avalanches when the track crosses the amplification region (near the anode wire). The remaining pulses show the later electron avalanches reaching the same anode wire from the drift region due to the track angle. The complex pulse shape from the drift region reflects the convolution in this time base of the arrival of the electron to the amplification region and the induced pulse from the resulting electron avalanche.

= Barrel Scintillator signal path =

'''''Note''''': While the Barrel Scintillator is part of the Alpha-g detector for cosmic rejection purpose, this section is still under development. The initial concept and implementation are therefore not final. The volume allocated for it in the other hand well defined due to external to the detector constraints.

Light at both ends of each bar of the barrel scintillator is collected for a rough position detection of the crossing particle and timing information. To improve the detection information (maximize photon collection), 6 individual SiPM light detector (SensL) are mounted on both ends of the individual scintillator bar for a coverage of 50% of the bar. This assembly is in a light-tight and gas-tight enclosure. A cold gas flows through the box to lower the SiPM temperature operation in order to reduce the dark noise of the device. A shaper/amplifier board (BSB) will be mounted on the outside of the enclosure. Each of the board will acquire the signals of 4 adjacent scintillator bars. In total 64 scintillator bars are read out by 16 boards at each end. A block diagram of one bar readout is shown in Figure 14. The signal gathering of the 6 sensors is based on an analog sum.

[[File:imagedaq18.png|480x296px]]

Figure 14 - Block diagram of one channel of SiPM amplifier

The 6 pre-amplifier outputs are combined to provide the sum of 6 signals. This resulting signal is further amplified and shaped (if necessary) on a second stage post-amplifier/discriminator. This signal sent to the readout system through a cable driver. Two signals will be acquired from each bar: (1) Analog sum fed to a waveform digitizer with proper digital processing to determine event position and timing; (2) LVDS signal fed to a TDC for off-line precise timing measurement purposes. For the LVDS signal, the post-amplifier will have a controlled threshold voltage to the signal comparator.

The BSB will be powered by standard +5V and -5V linear supplies. Each board has a test input to allow individual board measure of the amplifier response, malfunction test and to provide the necessary services to the light sensors device (Voltage bias, temperature sensor, etc).

The output of the analog output of the BSB will be shaped for the 100Msps WFD and in parallel will issue a digital signal for timing information to a TDC.

= Trigger Distribution =

On the full-length detector, the FEAM boards will receive trigger and clock signals from the CDM through the Trigger Card Adapter. The adapter receives signals from the CDM via a 7 pin SATA connector. The signals can be re-driven by repeaters on the adapter and are sent down a chain of 7 Trigger Cards with the adapter forming the first link.

While there are other elegant means of distributing the common clock and trigger to all the electronics boards, this method is the most simple and robust.

[[File:imagedaq19.png|195x575px|Adapter]]

[[File:imagedaq20.png|573x43px|Trigger_Board]]

Figure 15 - Trigger Card Adapter and Trigger Card

[[File:imagedaq21.jpg|216x294px|20170914_101103_resized]]

Figure 16 Trigger Card to FEAM

A Samtec SFM-110 connects each card to a FEAM board and also provides through holes pins where another card can be overlapped and soldered. In this manner the chain of Trigger Distribution Cards is formed, providing a shared clock and trigger signal to a column of 8 FEAM boards.

= Clock Distribution Module =

[[File:imagedaq22.png|231x356px]]

Figure 17 - Clock Distribution Module

* 6x LEMO Connectors [2 Output, 4 Input]
* 6x Mini-SAS providing up to 24 channels of clock and synchronization breakout
* 1x Combination eSATA/USB connector
** eSATA provides CLK and SYNC
** USB provides USB to Serial communication 115200 BAUD
* 1x 10/100 Base-TX Ethernet
* Optional Atomic Clock module support, 10MHz and 1PPS '''[CSAC - SA.45s]'''
** Short term Stability <1E-11
** over 1000 seconds (100μHz / 1000s)
** Aging rate of <9E-10 per month '''('''9mHz/month)
* Onboard 10MHz Crystal Oscillator '''[FOX924B-10.000]'''
** ±2.5ppm
** ±1ppm per year
* JTAG ARM Support
* SmartFusion2 SoC '''[MS2-FG484]'''
* Ultra-low noise clock jitter cleaner 3:15 input to output support '''[LMK04821] '''
** Min/Max VCO Frequency 2750/3072MHz
** 0.111RMS Jitter
* TTL and NIM signal compatibility for external CLK and SYNC
* VME - 6U - 3Row
* Approximate Current Draw 1.837A at 5V

The Clock Distribution Module ('''CDM)''' has the capability to distribute two externally sourced clock and synchronization signals to six mini-SAS connections for total 24 signal signals. The external signals are provided through the eSATA and LEMO 1A/B Connectors. The module also has the capability to add an Atomic clock that outputs a 10Mhz signal and a 1 Pulse Per Second (PPS), as well as user-defined synchronization signal. Lastly, the module can be configured to output the external clock signals to the LEMO 2B connector or VME bus.

[[File:imagedaq23.png|509x348px]]

Figure 18 - IO Block Diagram

[[File:imagedaq24.png|299x412px]]

Figure 19 - ALPHA-16 and CDM board in front with the Trigger/Clock distribution cables

= Frontend Board Firmware =

The firmware (FW) refers to the embedded code running on the Field Programmable Gate Arrays (FPGAs) and microcontrollers (MCUs) located on the various modules within the experiment. These devices store, load, and run the programs required for operation of the different digital electronic components within the experiment.

Firmware code is essential to the operation of the detector as it provides the mechanism to configure the hardware for its particular purpose. Such as analog-to-digital conversion, data filtering, data trigger composition, transport of the data, and orchestration of all the different hardware modules to succeed in acquiring meaningful information across the overall system. Some of the firmware tasks are:

<ol style="list-style-type: upper-roman;">
<li>Low-level acquisition of the 3 different WFDigitizers (Anode wire, Cathode pad, Barrel Scintillator)</li>
<li>Links all the electronics boards to the DAQ system.</li>
<li>Collected in real-time information for trigger decision making.</li>
<li>Distribute synchronization signals and trigger to all the acquisition boards.</li>
<li>Provides to the user; configurable board and operation parameters settings.</li>
<li>Provides board monitoring and debugging tools.</li></ol>

Most of the FW code base has been based off of prior code developed for the currently running GRIFFIN experiment, with some exceptions, such as the Trigger Master Module which needed custom code specific to ALPHA-g, and the PADWING, which contained the AFTER SCA chip not present in GRIFFIN.



The firmware code is loaded onto the hardware board where an FPGA or MCU is present. Each firmware module has specific firmware capabilities, detailed as follows:

* Hit Detector firmware Module (ALPHA-16 carrier board)
** Anode Wire and Barrel Scint. signal waveform digitizers acquisition
** Local data filtering for Trigger purpose
** Transmission of summary data to Trigger Module for trigger decision
** Data compression/filtering and retention for transmission to backend on Trigger reception
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Pad Acquisition firmware Module (PADWING board)
** Cathode pad signal waveform digitizers acquisition
** Data compression/filtering and retention for transmission to backend on Trigger reception
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Master Trigger firmware Module (ALPHA-T board)
** Summary data reception of the multiple GRIF-16 boards
** Trigger decision algorithm
** Packaging of Trigger decision information and transmission to the backend.
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Clock and Trigger Distribution firmware Module (CDM board)
** Monitoring of hardware functions (U,I,T,Clock Frequency)
** Configuration of hardware mechanism for clock and trigger distribution
** Update of firmware code mechanism

== '''Hit Detector Module (ALPHA-16)''' ==

The Hit Detector firmware module handles the acquisition of the analog input signals from the anode wires and scintillators, the digital conversion of that data, and then the transfer of that data to both the DAQ and the Trigger Master. The first implementation of the hit detection is based on hit multiplicity. Later on, a more sophisticated algorithm will be implemented to determine in real time the timing and charge collected for each channel. This information will be transferred to the Trigger Master for more efficient trigger filtering.

The ADC data is acquired from both the FMC ADC32 ADCs and the onboard 16ch 14-bit ADCs using the FPGAs hardware SERDES modules. These modules de-serialize the data stream from the ADCs into a format suitable for internal analysis for hit detection, and for transfer to the MIDAS DAQ.

Once one or more hits are detected, the ALPHA-16 transmits the hit count to the ALPHA-T for a hit multiplicity test, and then waits for a trigger response to decide to discard or transmit the waveform data associated with the detected hit to the DAQ.

Currently, when a trigger is fired by the Trigger Decision module, all channels transmit their captured waveforms to the DAQ. In the future, only channels that have detected a hit will send waveforms on a trigger.

System monitoring and configuration of the Hit Detector module is handled by ESPER running on a NIOS-II soft-core processor instantiated within the FPGA. The OS used is Micrium µC/OS-II, a small real-time OS licensed by Altera for use with their NIOS-II processor. ESPER performs the remote upgrading of the Hit Detector, viewing of the captured waveforms, and diagnostic reading and writing of all firmware settings and counters via a simple JSON-based interface, or an HTML based webpage.

[[File:imagedaq25.png|517x318px]]

Figure 20 - Hit Detector for the Anode wire and scintillators in ALPHA-16

== '''Pad Acquisition Module (FEAM)''' ==

The pad acquisition firmware module handles the collection of the PAD analog signals captured by the four AFTER ASICs on the module. Capture occurs upon receiving a trigger signal from the Trigger Decision module. Once captured, the AFTER data is transmitted to the MIDAS DAQ over ethernet. No pad information is provided back to the Trigger Decision module.

Each of the AFTER ASICs transmits its captured analog data to a 12-bit ADC which in turn converts the analog signal into digital data and transmits that to the FPGA. The FPGA uses its internal SERDES hardware to de-serialize this data and process it. Once captured, channels that do not contain data of interest are suppressed, and the data is packaged up and sent out over UDP to the MIDAS DAQ.

In the event that the SFP module that provides ethernet connectivity fails, each PAD acquisition module is connected to one other PAD acquisition module via a secondary gigabit link. While currently unused, this link will be used in the future to support a backup link to the DAQ, in the event of a failure of the primary gigabit link.

System monitoring and configuration of the PAD acquisition module is handled by ESPER running on a NIOS-II soft-core processor instantiated within the FPGA. The OS used is Micrium µC/OS-II, a small real-time OS licensed by Altera for use with their NIOS-II processor. ESPER performs the remote upgrading of the Hit Detector, viewing of the captured waveforms, and diagnostic reading and writing of all firmware settings and counters via a simple JSON-based interface, or an HTML based webpage.

[[File:imagedaq26.png|490x299px]]

Figure 21 - AFTER chip WFD on the PADWINGS

== '''Trigger Master module (ALPHA-T)''' ==

The Trigger Master firmware module is to collect information from the anode wires and scintillators to make a real-time decision if the current physics event is to be recorded. That decision is fed to all the readout boards to trigger the storage of this particular event.

Initial trigger decision will be based on hit multiplicity of each of the ALPHA-16 boards. As the ALPHA-16 is acquiring the anode wire and the barrel scintillator signals, both of these 2 pieces of equipment will contribute to the trigger decision. Dedicated link from each of the ALPHA-16 (hit detector) to the Trigger module will be gathering the overall information for a final decision. Hardware trigger signal is then sent from the ALPHA-T to the CDM for distribution to all the acquisition modules to initiate the transmission of their data to the backend computer through UDP. The trigger board will compose a summary of the trigger information which will also be transferred to the backend.

The Trigger Master module contains two Mini-SAS FMCs, and one ‘communication’ FMC, that consists of a SATA, an SFP, and a Mini-SAS connector. This configuration of FMCs allows for up to twenty (20) 1G/2.5G/5G links via the Mini-SAS, in addition to a 1 Gbit/sec Ethernet connection via the SFP, and clock+trigger over the SATA.

[[File:imagedaq27.png|576x304px]]

Figure 22 - Trigger decision on ALPHA-T

== System Monitoring and debugging capability ==

The system monitoring is based on the ESPER protocol provided by the Electronics Development group at TRIUMF. Featuring a built-in web server, with real-time digitizer display, remote upgrade, and JSON-accessible parameters. ESPER allows for real-time diagnostics and testing to be performed on the various electronic modules using either JSON-based requests or a built-in webpage.

[[File:imagedaq28.png|576x67px]][[File:image29.png|576x286px]]

Figure 23 - ESPER Web Display. Test pulse recorded by the FEAM cards. Individual AFTER chip configuration is visible (gain change, delay).

= Safety and Hazard considerations =

There are no safety or hazard issues in FE system. All amplifiers are low-voltage and low-power circuits built with standard electronics components.

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Detector Electronics

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Midas: /* Anode wire signal path */

Back to [[Documentation]]

= Table of Figures =

[[#_Toc493676266|Figure 1 - Overall Data Acquisition scheme 7]]

[[#_Toc493676267|Figure 2 - Anode wire pre-amplification block diagram 8]]

[[#_Toc493676268|Figure 3 - Anode Wire Board (AWB), 16 channels pre-amplifier 9]]

[[#_Toc493676269|Figure 4 - 4 consecutive anode wire signals 9]]

[[#_Toc493676270|Figure 5 - Anode wire pre-amp gain map for half the chamber circumference 10]]

[[#_Toc493676271|Figure 6 - Alpha16 Data Acquisition Board 12]]

[[#_Toc493676272|Figure 7 - Grif16 Acquisition Module Block Diagram on which the Alpha-16 is based 12]]

[[#_Toc493676273|Figure 8 - Model of the new 32channels 12bit @ 65Msps FMC produced in 2016. 13]]

[[#_Toc493676274|Figure 9 - FMC Alpha-ADC32 Block Diagram 13]]

[[#_Toc493676275|Figure 10 - Cathode Pad Board readout for 288 channels at 62.5Msps, visible 4 AFTER chips, 3 copper bars running under the central board for power distribution 15]]

[[#_Toc493676276|Figure 11 – Thermal image of the FEAM with hot spot temperature: without cooling plate (78°C), with cooling plate (45°C), with cooling plate & water cooling (36°C) 16]]

[[#_Toc493676277|Figure 12 - Block diagram of AFTER amplifier 17]]

[[#_Toc493676278|Figure 13 - 4 x 72 cathode pad signals, overall time width corresponds to the drift time 17]]

[[#_Toc493676279|Figure 14 - Block diagram of one channel of SiPM amplifier 18]]

[[#_Toc493676280|Figure 15 - Trigger Card Adapter and Trigger Card 19]]

[[#_Toc493676281|Figure 16 Trigger Card to FEAM 19]]

[[#_Toc493676282|Figure 17 - Clock Distribution Module 20]]

[[#_Toc493676283|Figure 18 - IO Block Diagram 21]]

[[#_Toc493676284|Figure 19 - ALPHA-16 and CDM board in front with the Trigger/Clock distribution cables 22]]

[[#_Toc493676285|Figure 20 - Hit Detector for the Anode wire and scintillators in ALPHA-16 24]]

[[#_Toc493676286|Figure 21 - AFTER chip WFD on the PADWINGS 25]]

[[#_Toc493676287|Figure 22 - Trigger decision on ALPHA-T 26]]

[[#_Toc493676288|Figure 23 - ESPER Web Display. Test pulse recorded by the FEAM cards. Individual AFTER chip configuration is visible (gain change, delay). 27]]

= Introduction =

This design note describes the electronics chain and components for the readout of the ALPHA-g TPC and barrel scintillator bars.

= Scope =

The Detector Electronics is composed of 3 independent signal sources:

# Anode Wire signals path
# Cathode Pad signals path
# Barrel Scintillator signals path.

All 3 sources provide a similar function such as signal amplification and conditioning (shaping).

= Definitions and Abbreviations =

General acronyms or terms used for the ALPHA-g experiment

{|
! TPC
! Radial Time projection Chamber
|-
| Pads
| PCB surface seeing the induced anode wire signal
|-
| SiPM
| Si photomultipliers used to detect scintillation light
|-
| ADC
| Analog to digital converter
|-
| ASIC
| Application specific integrated circuit
|-
| SCA
| Switch Capacitor Array ( A type of Waveform Digitizer)
|-
| TDC
| Time to digital converter
|-
| BSM
| Barrel Scintillator Module (64 bars sub-assembly)
|-
| FEAM, Padwing
| Cathode strip acquisition board
|-
| CDM
| Clock Distribution Module
|-
| BSB
| Barrel Scintillator Board
|-
| WFD
| Waveform Digitizer
|}

Table 1 – ALPHA-g Abbreviations

= References and related Document =

* AFTER manual
* SensL SPM data sheet
* Edev-group.triumf.ca: contains the FW information on all the Alpha-g custom cards ([https://edev-group.triumf.ca/fw/exp/alphag/feam/rev0/wikis/feam-test-packet-format https://edev-group.triumf.ca/fw/exp/alphag])

* ''' 
'''

= Overall Detector Signal Path =

The Alpha-g detector provides 3 analog signals that are collected for the track reconstruction to help on the annihilation location in the trap.

* The anode wire signal providing the drift time of the electron through the detector for an angular position.
* The cathode pad signal, which are in-time correlated to the anode wire signal, providing the amplitude of these signals from which the longitudinal position (Z) can be extracted.
* The Barrel Scintillator bar signals provide the time and amplitude of the particle crossing the detector. The Barrel Scintillator is mainly to reject cosmic events. For that purpose, the timing resolution is important. Therefore the BSM analog signal is split early in the chain to record the amplitude and time separately.

The anode wires and the barrel scintillator bars are read out from both ends to provide a coarse Z-position as well. The Data acquisition is therefore made for reading 2x256 anode wire channels, 2x64 barrel scintillator bars and 18432 channels of cathode pads covering the outer detector cylinder.

[[File:image2daq.png|576x379px]]

Figure 1 - Overall Data Acquisition scheme

= Anode wire signal path =

The design for the anode wires pre-amplifier is based on work done for several other projects used at TRIUMF and other labs.

Each of the 256 anode wires are read-out from two ends. The signals are used to (1) determine phi-position of ionization track; (2) reconstruct its z-position by weighting signals from two wire ends; (3) generate trigger signal. The pre-amplifiers convert the induced current to voltage that is digitized and processed in the readout system. The main requirements for the amplifier circuit are:

# Input impedance must be low enough so detected charge is sensitive to position of event along wire;
# The shape of signal is optimized for sampling frequency (16 ns) and for fast trigger timing (few ns accuracy);
# Linearity range adjusted for ADC used;
# Gain is adjusted for gas amplification of 105
# Amplifier noise is low enough to detect single-electron cluster.

[[File:image3daq.png|576x204px]]

Figure 2 - Anode wire pre-amplification block diagram

Anode wires are HV-decoupled before connected to the amplifier, but additional (not HV) decoupling is needed at amplifier input to accommodate non-zero potential of the input stage. Protection of the amplifier input is using a standard bi-diode configuration. The first stage is a current-sensitive loop with input impedance defined by resistor Rin and trans-impedance (gain) by feedback resistor Rf. The second stage is 2-pole shaper with shaping time constant defined by components Rs and Cs. The last stage is a cable driver.

Overall gain, transfer function and input impedance of the circuit can be adjusted by changing passive components. This adjustment will be done with studying the TPC prototypes.

Amplifiers are deployed on 16-channel cards, 16 boards serve each end of TPC. They are powered by standard +5V and -5V linear supplies. Each card has a test input that is used to measure amplifiers response and to check for malfunction.

[[File:image4daq.jpg|173x183px]] [[File:image5daq.png|169x184px]]

Figure 3 - Anode Wire Board (AWB), 16 channels pre-amplifier

The AWB schematic allow for bi-polar signal input. This has the advantage to reproduce the full anode wire signal development including the inverted induced pulse from neighbouring wires as seen Figure 4.

[[File:image6daq.jpg|512x358px]]

Figure 4 - 4 consecutive anode wire signals

The anode pre-amps have an individual test pulse input to provide a quick functional test. It can also be used for calibration purpose. Several tests have been done in this regard, but the overall chain gain is dependent on many variables (chamber geometry, environmental condition (Gas mixture, T, P), pre-amp (layout, components)). Another more common test pulse injection is available by pulsing all the field wires at once (at the boundary of the drift and multiplication region). This technique has the advantage to produce an induced signal on all the anode wires and cathode pads together at the “same” time. Figure 5 shows the gain variation by wire seen when pulsed through the field wire. 2 interesting features are visible:

a) An overall negative slope, indicated by the linear fit. This slope is explained by the pulse attenuation through the field wires distribution.

b) A clear increase in gain for the wires near the anode wire card boundaries, indicated by the cyan lines is not yet well understood. Further test is planned.

[[File:media/image7daq.png|397x289px]]

Figure 5 - Anode wire pre-amp gain map for half the chamber circumference

== Anode Wire Waveform digitizer (Alpha-16) ==

The output of the AWB is presented to the Alpha-16 waveform digitizer sampling the analog signal at 62.5Msps.

'''''Note:''''' At the time of this report, the WFD 62.5Msps is not yet available. We use the WFD at 100Msps to perform the tests. The firmware is similar to the 62.5Msps and the final test will be reproduced later.

This module provides 16 channels 14bit ADC @100Msps for 50Ohms single-ended analog signal for the barrel scintillator. It also supports a dedicated mezzanine card (FMC) handling 32 channels 12bit ADC @ 65Msps for single-ended 50Ohms analog signals for the Anode wires.

The Alpha-16 board outputs (16ch.@100Msps and 32ch.@62.5Msps) are collected on the main carrier FPGA for transmission through Ethernet to the backend computer.

The board carries multiple I/O connections required for the module configuration, communication, data transfer, signal inputs, see Figure 7.

* Front panel SFP Gbit Ethernet (copper/fiber)
* Front panel eSATA: clock and sync inputs
* Front panel dual LEMO: Diagnostic DAC outputs (250Msps)
* Front panel MCX connector for 16 x ADC inputs
* Rear entry P2 connector for 16 x ADC inputs
* A24/D16 VME interface to MAXV configuration CPLD
** VME configuration flash updates
** VME bridge to FPGA
* FMC custom module connections.
** Dual MiniSAS for Acquisition setup
** 10 x5Gibt Link
** JESD204B Clocks
** Supports 32 Channel ADC LVDS interface
* Amplifier input switches: Front panel MCX connector, Rear Transition Card SMA connector
* Amplifier Gain x1 and x4
* Switch selectable LEMO NIM Input/ DAC outputs
* Micro SD Flash
* DDR3 DRAM – 667MHz – 128M x 23'''(MT41J128M16HA-15E)'''
* FPGA - Arria V '''(5AGXFB3H4F35C4N)'''
* MAXV CPLD controller '''(5M2210ZF256C5N)''' for USB JTAG and VME access

[[File:media/image8daq.jpg|218x380px]]

Figure 6. Alpha16 Data Acquisition Board

[[File:media/image9daq.png|264x383px]]

Figure 7. Grif16 Acquisition Module Block Diagram on which the Alpha-16 is based

== FMC – Alpha ADC32 ==

<blockquote>The FMC – ALPHA ADC32 provides single-stage amplification of up to 32 single-ended 50<math>\Omega</math> analog signals, from the Anode Wire Board Pre-Amplifier, to drive two 16 channel 14bit differential, analog to digital converters sampling at 65MSPS. Further, each ADC will provide a 0.9V common mode offset voltage to be fed into the differential driver

A 16 channel 12 bit digital-to-analog (DAC) converter is used to individually apply an appropriate offset voltage to each of the differential amplifier pairs. The Offset voltages span <math>\pm</math>2.5Vat 1.22mV increments and will output 0V upon power cycle. The DAC is configurable via an SPI interface via the FMC connector.

ADC32 board has the capability to receive and transmit an LVDS clock signal through the eSATA connector which is fed to the FMC connector
</blockquote>
[[File:media/imagedaq10.png|318x307px]]

Figure 8 - Model of the new 32channels 12bit @ 65Msps FMC produced in 2016.

[[File:media/imagedaq11.png|420x285px]]

Figure 9 - FMC Alpha-ADC32 Block Diagram

<blockquote>''These notes are for the current revision of the Alpha ADC32, a new revision is currently being talked about''
</blockquote>
The board is composed of the following elements:

* 400 Pin FMC connector
** Provides SPI interface
** ADC Synchronization
** Support for 32 LVDS analog signals
** Supply voltage of fused +12V, Switched 3.3V and 1.2-3.3V adjustable
* 32 channel Analog inputs via Hirose connector '''[FX2-40S-1.27DS(71)] 
'''
* 1V analog reference voltage '''[LTC6655BHMS8-3#PBF]'''
** ±2ppm
* Differential ADC Driver '''[ADA4950'''-'''2YCPZ]'''
** ±0.2mV Offset
** 9.2nHz / √Hz Output voltage Noise at Gain=1
** Adjustable output common-mode voltage
** Hardware programmable gain of 1x, 2x and 3x
* Dual 16 channel 14bit Analog to Digital converter '''[AD9249BBCZ-65]'''
** 2Vp-p input range
** 65MSPS
** ±0.6LSB
** Input Clock of 10-520MHz
* 16 channel 12bit Digital to Analog converter '''[ADA4950-2YCPZ]'''
** Programmable offset voltage
** SPI configurable outputs
** Output range ±2.5V, 0V upon reset
** 1.22mV/LSB
* 1 x eSATA Clk-In / Clk-out to and from FMC connector

= Cathode pad signal path =

The 18432 cathode pads covering the inner surface of the outer wall of the detector are individually connected to a signal acquisition chain. This collected signals will provide the position of the electron avalanche at the anode wire. Combining them in charge, permit the reconstruction of the track passing through the longitudinal direction the detector. While the cathode pads cover a large area (2.7m2), the actual footprint per channel is limited (3.8mmx37.1mm). Therefore a high-density waveform digitizer chain has been chosen based on our previous experience with the T2K experiment, we opted for the AFTER Switched Capacitor Array (SCA) ASIC. The analog signal path is short as the pads themselves are on the backside the physical outer cylinder of the detector and the input signal connectors to the AFTER chips are on the opposite side of the outer cylinder.

A custom frontend board (FEAM) see Figure 10 handling 288 individual cathode pads has been designed. It is composed of 4 ASIC AFTER (72 channels) with associated waveform digitizer for the individual signal on 512 cells at 20Msps. In addition, an FPGA manages the board services and the data collection and transmission through a 1 gigabit/sec optical link to the Ethernet using the UDP protocol.

While the power consumption per channel at the ASIC level is low, the power requirement is in the order of 15W per board for a total at the detector level approaching 1000W. This required proper cooling to maintain a reliable operation of the electronics. Figure 11 shows the board temperature with and without cooling plate. Thermal images have been taken to confirm the temperature reduction of the main heat source (Clock cleaner, FPGA, ADC, AFTER in that order). We can guarantee a chip temperature below 60°C to keep the default chip MTBF.

[[File:media/image12daq.jpg|558x246px]]

Figure 10 - Cathode Pad Board readout for 288 channels at 62.5Msps, visible 4 AFTER chips, 3 copper bars running under the central board for power distribution

[[File:media/imagedaq13.png|249x185px]][[File:media/imagedaq14.png|247x186px]] [[File:media/imagedaq15.jpg|248x186px]]

Figure 11 – Thermal image of the FEAM with hot spot temperature: without cooling plate (78°C), with cooling plate (45°C), with cooling plate & water cooling (36°C)

== Cathode Pad Circuit ==

The cathode pads are read-out by AFTER ASIC which diagram is presented in Figure 12. Each channel consists of a charge-sensitive preamplifier, pole-zero cancellation of preamplifier decay time, RC2 shaper and 512-cell SCA to store the waveform. Amplifier gain, pole-zero time constant and shaping time are programmable.

{|
|
[[File:media/imagedaq16.png|361x171px]]

Figure 12 - Block diagram of AFTER amplifier
| [[File:media/imagedaq17.png|215x199px]]
|}

The acquisition of the FEAM cards is operational and initial waveforms can be displayed as seen in Figure 13. This visualization is for monitoring the individual channels only. The data acquisition is using a different path for fast data collection. Figure 13 shows cathode signal examples collected by the FEAM card. The signal shape is consistent with avalanches occurring from a cosmic track going through the detector. The initial pulse corresponds to the early avalanches when the track crosses the amplification region (near the anode wire). The remaining pulses show the later electron avalanches reaching the same anode wire from the drift region due to the track angle. The complex pulse shape from the drift region reflects the convolution in this time base of the arrival of the electron to the amplification region and the induced pulse from the resulting electron avalanche.

= Barrel Scintillator signal path =

'''''Note''''': While the Barrel Scintillator is part of the Alpha-g detector for cosmic rejection purpose, this section is still under development. The initial concept and implementation are therefore not final. The volume allocated for it in the other hand well defined due to external to the detector constraints.

Light at both ends of each bar of the barrel scintillator is collected for a rough position detection of the crossing particle and timing information. To improve the detection information (maximize photon collection), 6 individual SiPM light detector (SensL) are mounted on both ends of the individual scintillator bar for a coverage of 50% of the bar. This assembly is in a light-tight and gas-tight enclosure. A cold gas flows through the box to lower the SiPM temperature operation in order to reduce the dark noise of the device. A shaper/amplifier board (BSB) will be mounted on the outside of the enclosure. Each of the board will acquire the signals of 4 adjacent scintillator bars. In total 64 scintillator bars are read out by 16 boards at each end. A block diagram of one bar readout is shown in Figure 14. The signal gathering of the 6 sensors is based on an analog sum.

[[File:media/imagedaq18.png|480x296px]]

Figure 14 - Block diagram of one channel of SiPM amplifier

The 6 pre-amplifier outputs are combined to provide the sum of 6 signals. This resulting signal is further amplified and shaped (if necessary) on a second stage post-amplifier/discriminator. This signal sent to the readout system through a cable driver. Two signals will be acquired from each bar: (1) Analog sum fed to a waveform digitizer with proper digital processing to determine event position and timing; (2) LVDS signal fed to a TDC for off-line precise timing measurement purposes. . For the LVDS signal, the post-amplifier will have a controlled threshold voltage to the signal comparator.

The BSB will be powered by standard +5V and -5V linear supplies. Each board has a test input to allow individual board measure of the amplifier response, malfunction test and to provide the necessary services to the light sensors device (Voltage bias, temperature sensor, etc).

The output of the analog output of the BSB will be shaped for the 100Msps WFD and in parallel will issue a digital signal for timing information to a TDC.

= Trigger Distribution =

On the full-length detector, the FEAM boards will receive trigger and clock signals from the CDM through the Trigger Card Adapter. The adapter receives signals from the CDM via a 7 pin SATA connector. The signals can be re-driven by repeaters on the adapter and are sent down a chain of 7 Trigger Cards with the adapter forming the first link.

While there are other elegant means of distributing the common clock and trigger to all the electronics boards, this method is the most simple and robust.

[[File:media/imagedaq19.png|195x575px|Adapter]]

[[File:media/imagedaq20.png|573x43px|Trigger_Board]]

Figure 15 - Trigger Card Adapter and Trigger Card

[[File:media/imagedaq21.jpg|216x294px|20170914_101103_resized]]

Figure 16 Trigger Card to FEAM

A Samtec SFM-110 connects each card to a FEAM board and also provides through holes pins where another card can be overlapped and soldered. In this manner the chain of Trigger Distribution Cards is formed, providing a shared clock and trigger signal to a column of 8 FEAM boards.

= Clock Distribution Module =

[[File:media/imagedaq22.png|231x356px]]

Figure 17 - Clock Distribution Module

* 6x LEMO Connectors [2 Output, 4 Input]
* 6x Mini-SAS providing up to 24 channels of clock and synchronization breakout
* 1x Combination eSATA/USB connector
** eSATA provides CLK and SYNC
** USB provides USB to Serial communication 115200 BAUD
* 1x 10/100 Base-TX Ethernet
* Optional Atomic Clock module support, 10MHz and 1PPS '''[CSAC - SA.45s]'''
** Short term Stability <1E-11
** over 1000 seconds (100μHz / 1000s)
** Aging rate of <9E-10 per month '''('''9mHz/month)
* Onboard 10MHz Crystal Oscillator '''[FOX924B-10.000]'''
** ±2.5ppm
** ±1ppm per year
* JTAG ARM Support
* SmartFusion2 SoC '''[MS2-FG484]'''
* Ultra-low noise clock jitter cleaner 3:15 input to output support '''[LMK04821] '''
** Min/Max VCO Frequency 2750/3072MHz
** 0.111RMS Jitter
* TTL and NIM signal compatibility for external CLK and SYNC
* VME - 6U - 3Row
* Approximate Current Draw 1.837A at 5V

The Clock Distribution Module ('''CDM)''' has the capability to distribute two externally sourced clock and synchronization signals to six mini-SAS connections for total 24 signal signals. The external signals are provided through the eSATA and LEMO 1A/B Connectors. The module also has the capability to add an Atomic clock that outputs a 10Mhz signal and a 1 Pulse Per Second (PPS), as well as user-defined synchronization signal. Lastly, the module can be configured to output the external clock signals to the LEMO 2B connector or VME bus.

[[File:media/imagedaq23.png|509x348px]]

Figure 18 - IO Block Diagram

[[File:media/imagedaq24.png|299x412px]]

Figure 19 - ALPHA-16 and CDM board in front with the Trigger/Clock distribution cables

= Frontend Board Firmware =

The firmware (FW) refers to the embedded code running on the Field Programmable Gate Arrays (FPGAs) and microcontrollers (MCUs) located on the various modules within the experiment. These devices store, load, and run the programs required for operation of the different digital electronic components within the experiment.

Firmware code is essential to the operation of the detector as it provides the mechanism to configure the hardware for its particular purpose. Such as analog-to-digital conversion, data filtering, data trigger composition, transport of the data, and orchestration of all the different hardware modules to succeed in acquiring meaningful information across the overall system. Some of the firmware tasks are:

<ol style="list-style-type: upper-roman;">
<li>Low-level acquisition of the 3 different WFDigitizers (Anode wire, Cathode pad, Barrel Scintillator)</li>
<li>Links all the electronics boards to the DAQ system.</li>
<li>Collected in real-time information for trigger decision making.</li>
<li>Distribute synchronization signals and trigger to all the acquisition boards.</li>
<li>Provides to the user; configurable board and operation parameters settings.</li>
<li>Provides board monitoring and debugging tools.</li></ol>

Most of the FW code base has been based off of prior code developed for the currently running GRIFFIN experiment, with some exceptions, such as the Trigger Master Module which needed custom code specific to ALPHA-g, and the PADWING, which contained the AFTER SCA chip not present in GRIFFIN.



The firmware code is loaded onto the hardware board where an FPGA or MCU is present. Each firmware module has specific firmware capabilities, detailed as follows:

* Hit Detector firmware Module (ALPHA-16 carrier board)
** Anode Wire and Barrel Scint. signal waveform digitizers acquisition
** Local data filtering for Trigger purpose
** Transmission of summary data to Trigger Module for trigger decision
** Data compression/filtering and retention for transmission to backend on Trigger reception
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Pad Acquisition firmware Module (PADWING board)
** Cathode pad signal waveform digitizers acquisition
** Data compression/filtering and retention for transmission to backend on Trigger reception
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Master Trigger firmware Module (ALPHA-T board)
** Summary data reception of the multiple GRIF-16 boards
** Trigger decision algorithm
** Packaging of Trigger decision information and transmission to the backend.
** Monitoring of hardware functions (U,I,T)
** Configuration of hardware mechanism
** Update of firmware code mechanism
* Clock and Trigger Distribution firmware Module (CDM board)
** Monitoring of hardware functions (U,I,T,Clock Frequency)
** Configuration of hardware mechanism for clock and trigger distribution
** Update of firmware code mechanism

== '''Hit Detector Module (ALPHA-16)''' ==

The Hit Detector firmware module handles the acquisition of the analog input signals from the anode wires and scintillators, the digital conversion of that data, and then the transfer of that data to both the DAQ and the Trigger Master. The first implementation of the hit detection is based on hit multiplicity. Later on, a more sophisticated algorithm will be implemented to determine in real time the timing and charge collected for each channel. This information will be transferred to the Trigger Master for more efficient trigger filtering.

The ADC data is acquired from both the FMC ADC32 ADCs and the onboard 16ch 14-bit ADCs using the FPGAs hardware SERDES modules. These modules de-serialize the data stream from the ADCs into a format suitable for internal analysis for hit detection, and for transfer to the MIDAS DAQ.

Once one or more hits are detected, the ALPHA-16 transmits the hit count to the ALPHA-T for a hit multiplicity test, and then waits for a trigger response to decide to discard or transmit the waveform data associated with the detected hit to the DAQ.

Currently, when a trigger is fired by the Trigger Decision module, all channels transmit their captured waveforms to the DAQ. In the future, only channels that have detected a hit will send waveforms on a trigger.

System monitoring and configuration of the Hit Detector module is handled by ESPER running on a NIOS-II soft-core processor instantiated within the FPGA. The OS used is Micrium µC/OS-II, a small real-time OS licensed by Altera for use with their NIOS-II processor. ESPER performs the remote upgrading of the Hit Detector, viewing of the captured waveforms, and diagnostic reading and writing of all firmware settings and counters via a simple JSON-based interface, or an HTML based webpage.

[[File:media/imagedaq25.png|517x318px]]

Figure 20 - Hit Detector for the Anode wire and scintillators in ALPHA-16

== '''Pad Acquisition Module (FEAM)''' ==

The pad acquisition firmware module handles the collection of the PAD analog signals captured by the four AFTER ASICs on the module. Capture occurs upon receiving a trigger signal from the Trigger Decision module. Once captured, the AFTER data is transmitted to the MIDAS DAQ over ethernet. No pad information is provided back to the Trigger Decision module.

Each of the AFTER ASICs transmits its captured analog data to a 12-bit ADC which in turn converts the analog signal into digital data and transmits that to the FPGA. The FPGA uses its internal SERDES hardware to de-serialize this data and process it. Once captured, channels that do not contain data of interest are suppressed, and the data is packaged up and sent out over UDP to the MIDAS DAQ.

In the event that the SFP module that provides ethernet connectivity fails, each PAD acquisition module is connected to one other PAD acquisition module via a secondary gigabit link. While currently unused, this link will be used in the future to support a backup link to the DAQ, in the event of a failure of the primary gigabit link.

System monitoring and configuration of the PAD acquisition module is handled by ESPER running on a NIOS-II soft-core processor instantiated within the FPGA. The OS used is Micrium µC/OS-II, a small real-time OS licensed by Altera for use with their NIOS-II processor. ESPER performs the remote upgrading of the Hit Detector, viewing of the captured waveforms, and diagnostic reading and writing of all firmware settings and counters via a simple JSON-based interface, or an HTML based webpage.

[[File:media/imagedaq26.png|490x299px]]

Figure 21 - AFTER chip WFD on the PADWINGS

== '''Trigger Master module (ALPHA-T)''' ==

The Trigger Master firmware module is to collect information from the anode wires and scintillators to make a real-time decision if the current physics event is to be recorded. That decision is fed to all the readout boards to trigger the storage of this particular event.

Initial trigger decision will be based on hit multiplicity of each of the ALPHA-16 boards. As the ALPHA-16 is acquiring the anode wire and the barrel scintillator signals, both of these 2 pieces of equipment will contribute to the trigger decision. Dedicated link from each of the ALPHA-16 (hit detector) to the Trigger module will be gathering the overall information for a final decision. Hardware trigger signal is then sent from the ALPHA-T to the CDM for distribution to all the acquisition modules to initiate the transmission of their data to the backend computer through UDP. The trigger board will compose a summary of the trigger information which will also be transferred to the backend.

The Trigger Master module contains two Mini-SAS FMCs, and one ‘communication’ FMC, that consists of a SATA, an SFP, and a Mini-SAS connector. This configuration of FMCs allows for up to twenty (20) 1G/2.5G/5G links via the Mini-SAS, in addition to a 1 Gbit/sec Ethernet connection via the SFP, and clock+trigger over the SATA.

[[File:media/imagedaq27.png|576x304px]]

Figure 22 - Trigger decision on ALPHA-T

== System Monitoring and debugging capability ==

The system monitoring is based on the ESPER protocol provided by the Electronics Development group at TRIUMF. Featuring a built-in web server, with real-time digitizer display, remote upgrade, and JSON-accessible parameters. ESPER allows for real-time diagnostics and testing to be performed on the various electronic modules using either JSON-based requests or a built-in webpage.

[[File:media/imagedaq28.png|576x67px]][[File:media/image29.png|576x286px]]

Figure 23 - ESPER Web Display. Test pulse recorded by the FEAM cards. Individual AFTER chip configuration is visible (gain change, delay).

= Safety and Hazard considerations =

There are no safety or hazard issues in FE system. All amplifiers are low-voltage and low-power circuits built with standard electronics components.

File:Image6daq.jpg

2017-11-19T20:39:07Z

Midas: