VME-GRIF-ADC16-Rev1: Difference between revisions

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== ag.ctrl_d ==
== ag.ctrl_d ==


control of the adc16 and adc32 serializer, phase fifo and pattern alignement
control of the adc16 and adc32 serializer, phase matching fifo and pattern alignement


{| class="wikitable"
{| class="wikitable"
! bits !! Rev !! Quartus name !! Description
! bits !! Rev !! Quartus name !! Description
|-
|-
| 0 || 2020 || esata_clk invert || invert esata_clk going into sas_bits to the TRG
| 3..0 || 2020 || adc32_aligner_phff_sel || 1 clock delay for reading phase matching fifo, 1 bit per adc, for aligning together test patterns from all 4 adcs
|-
|-
| 1 || 2020 || esata_trig invert || invert esata_trig going into sas_bits to the TRG
| 11..4 || x || unused || should be set to zero
|-
|-
| 2 || 2020 || nim_clk invert || invert nim_clk going into sas_bits to the TRG
| 12 || 2020 || adc32_aligner_clk_sel || select inverted (0) or normal (1) clock for reading the phase matching fifo
|-
|-
| 3 || 2020 || nim_trig invert || invert nim_trig going into sas_bits to the TRG
| 13 || 2020 || adc32_aligner_sync || reset the phase matching fifo (does nothing useful)
|-
|-
| 31..4 || x || unused || should be set to zero
| 14 || 2020 || reset_serdes_adc32 || reset the serializer
|-
| 15 || 2020 || unused || should be set to zero, reserved for a reset signal
|-
| 31..16 || 2020 || adc16_xxx || same signals repeat for the adc16 section
|}
|}


Revision as of 10:20, 10 November 2020

VME-GRIF-ADC16-Rev1

Links

Front panel connectors

From top to bottom:

  • SFP connector - 1GigE fiber/copper/DAC
  • 4 LEDs
  • eSATA - clock+trigger input
  • FMC daughter card slot
  • 2 LEMO
  • 16 MCX analog inputs

Onboard switches and connectors

  • FP_SW1
  • FP_SW2
  • SEL1 rotary switch 0..F - MOD-SEL20..23
  • SEL2 rotary switch 0..F - MOD-SEL16..19
  • JTAG FPGA
  • JTAG MAXV
  • "reset" button
  • SD card slot
  • "Display" connector
  • 16x 3 position switches for gain and input (front/back) selection

LEMO connectors

|
|
|LEMO1A|LEMO1B|
|
|

LEMO connectors are controlled by two position switches FP_SW1 (LEMO1A) and FP_SW2 (LEMO1B): 

|
|      ---XX-
| left |..XX| right
|      ---XX-
|
  • right switch position (next to mark): DAC output
  • left switch position (opposite from mark): NIM input

Onboard LEDs

|
|
|0|1|2|3|
|
|
  • FP_LED0 - "clock_synched" (from qsys)
  • FP_LED1 - "led_trigger_input" (same as "trigger_input_adc")
  • FP_LED2 - "run active" (same as "force_run")
  • FP_LED3 - "led_link" (from qsys)

Onboard thermometers

  • Temperature readout chip: LTC2983CLX#PBF
  • Thermometers: 9x RTD1..RTD9 type PT100. The first 8 are on the back of the PCB next to the analog amps, the last one is on the front next to the FPGA.
RTD1 sensor_temp[0] opamp 1-3
RTD2 [1] amp 2-4
RTD3 [2] 5-7
RTD4 [3] 6-8
RTD5 [4] 9-11
RTD6 [5] 10-12
RTD7 [6] 13-15
RTD8 [7] 14-16
RTD9 [8] between the FPGA and U11-U15

Analog gain and input selector switches

The switches labeled SW1..SW16 (right side) are the input selector switches: default position (up; next to the dot) is "rear vme connector", reverse position (down) is "front panel MCX connector".

The switches without onboard label (left side; label on the schematics is "SW1") are the gain selection switches: default position (down; next to the dot) is "gain x4", reverse position (up) is "gain x1".

Onboard hardware

  • 2-output DAC: Maxim MAX5877EGK+D, output driver TI OPA 2690IDG4, range +/- 1V open, +/- 0.5V into 50 Ohm
  • I2C MAC chip: Microchip tech 24AA02E48T-I/OT, I2C addr 0xA0, MAC_SCL, MAC_SDA
  • FPGA Boot flash: Micron Serial NOR flash memory: N25Q00AA13GSF40G

Board schematics

File:GRIF-ADC16_Rev1.pdf

ALPHA-g board configuration

  • rotary switches SEL1, SEL2 - set to zero
  • FP_SW1 set left (NIM input)
  • FP_SW2 set right (DAC output)
  • analog input switches: default position (next to mark): from left to right: down, up, down, up, etc
  • FMC connector: FMC-ADC32 Rev1.1 module (rev0 can be used as a sata connector, rev1 has some adc channels miswired internally)
  • FMC connector: FMC-MiniSAS module cable plugs into the bottom connector

Firmware

ESPER variables

name RR Type Rev Description
ag.adc16_threshold RW INT16 x trigger discriminator threshold for the 100MHz ADCs
ag.adc32_threshold RW INT16 x trigger discriminator threshold for the 62.5MHz ADCs
ag.adc16_bits RO UINT16 x Output of the 16x 100MHz ADC trigger discriminators, goes into sas_bits (16 bits)
ag.adc32_bits RO UINT32 x Output of the 32x 62.5MHz ADC trigger discriminators, goes into sas_bits (32 bits)
ag.adc16_counter RO UINT32 2020 Counter for the 100MHz ADC trigger discriminators
ag.adc32_counter RO UINT32 2020 Counter for the 62.5MHz ADC trigger discriminators
ag.dac_data RW UINT32 x DAC data, read more #ag.dac_data
ag.dac_ctrl RW UINT32 x DAC control, read more #ag.dac_ctrl
ag.dac_ctrl_a RW UINT32 2020 DAC control, read more #ag.dac_ctrl_a
ag.dac_ctrl_b RW UINT32 2020 DAC control, read more #ag.dac_ctrl_b
ag.dac_ctrl_c RW UINT32 2020 DAC control, read more #ag.dac_ctrl_c
ag.dac_ctrl_d RW UINT32 2020 DAC control, read more #ag.dac_ctrl_d
ag.adc16_sthreshold RW INT16 2020 data suppression threshold for the 100MHz ADCs
ag.adc32_sthreshold RW INT16 2020 data suppression threshold for the 62.5MHz ADCs
ag.ctrl_a RW UINT32 2020 100MHz ADC sp control, read more #ag.ctrl_ab
ag.ctrl_b RW UINT32 2020 62.5MHz ADC sp control, read more #ag.ctrl_ab
ag.ctrl_c RW UINT32 2020 alphag block control, read more #ag.ctrl_c
ag.ctrl_d RW UINT32 2020 control, read more #ag.ctrl_d
ag.ctrl_e RW UINT32 2020 control, read more #ag.ctrl_e
ag.ctrl_f RW UINT32 2020 control, read more #ag.ctrl_f
ag.stat_a RO UINT32 2020 100MHz ADC sp status, read more #ag.stat_ab
ag.stat_b RO UINT32 2020 62.5MHz ADC sp status, read more #ag.stat_ab
ag.stat_c RO UINT32 2020 alphag block status, read more #ag.stat_c
ag.stat_d RO UINT32 2020 status, read more #ag.stat_d

ag.dac_data

bits Rev Description
15..0 x DAC output amplitude, +/-8000
31..16 x DAC pulse baseline

ag.dac_ctrl

bits Rev Quartus name Description
0 x ~DAC_PD inverted "DAC power down", 1=enable the DAC, 0=power down the DAC
1 x DAC_SELIQ select one of the DAC outputs, set to 0 to use the right hand LEMO output
2 x DAC_XOR invert the dac data, set to 0
3 x DAC_TORB select 1-complement data format, set to 1
4 x pulser_enable 0: dac_data drives the DAC directly, 1: dac_data is gated by the eSATA SYNC signal (DAQ trigger)
5 x ramp_enable DAC is ramped using linear ramp
7..6 x unused should be set to zero
15..8 x top_len time between ramp up and ramp down in DAC samples. time = 16ns*(top_len+2)
23..16 x d_down ramp down rate * 64, DAC counts per 1 DAC sample (16ns)
31..24 x d_up ramp up rate * 64, DAC counts per 1 DAC sample (16ns)

ag.ctrl_ab

ag.ctrl_a and ag.ctrl_b have the same function, except one controls the 100MHz ADCs, the other one controls the 62.5MHz ADCs.

bits Rev Quartus name Description
0 2020 ch_ctrl_supp_enable enable data suppression
1 2020 ch_ctrl_force_keep set data suppression keep_bit
15..2 x unused should be set to zero
27..16 2020 ch_ctrl_supp_keep_more additional ADC samples to keep at the end of the waveform
30..28 x unused should be set to zero
31 2020 ch_ctrl_reset reset the sp16 and sp32 blocks, if both reset bits are set, reset data path mux and fifos in the top-level block

ag.stat_ab

ag.stat_a and ag.stat_b have the same function, except one controls the 100MHz ADCs, the other one controls the 62.5MHz ADCs.

bits Rev Quartus name Description
31..0 x unused read zero

ag.ctrl_c

control of the alphag block

bits Rev Quartus name Description
0 2020 esata_clk invert invert esata_clk going into sas_bits to the TRG
1 2020 esata_trig invert invert esata_trig going into sas_bits to the TRG
2 2020 nim_clk invert invert nim_clk going into sas_bits to the TRG
3 2020 nim_trig invert invert nim_trig going into sas_bits to the TRG
31..4 x unused should be set to zero

ag.ctrl_d

control of the adc16 and adc32 serializer, phase matching fifo and pattern alignement

bits Rev Quartus name Description
3..0 2020 adc32_aligner_phff_sel 1 clock delay for reading phase matching fifo, 1 bit per adc, for aligning together test patterns from all 4 adcs
11..4 x unused should be set to zero
12 2020 adc32_aligner_clk_sel select inverted (0) or normal (1) clock for reading the phase matching fifo
13 2020 adc32_aligner_sync reset the phase matching fifo (does nothing useful)
14 2020 reset_serdes_adc32 reset the serializer
15 2020 unused should be set to zero, reserved for a reset signal
31..16 2020 adc16_xxx same signals repeat for the adc16 section

ag.stat_c

status of the alphag block

bits Rev Quartus name Description
31..0 x unused read zero

Data format

Version 1

  • note: the first two bytes of data (packet_cnt[15:0]) are removed from the UDP packet by the udp_payload_inserter block.
  • note: CRC16 is not implemented
  • PACKET_TYPE = 1
  • PACKET_VERSION = 1
  • stat_trig_accepted is the trigger counter
  • timestamp runs at 125 MHz
	   S1_HEADER0: begin
	      data	<= { 1'b1, 1'b0, 2'h0, packet_cnt[15:0], PACKET_TYPE[7:0], PACKET_VERSION[7:0] }; // determine total size (used by UDP offloader, does not appear in final packet!
	   S2_HEADER1: begin 
	      data	<= { 1'b0, 1'b0, 2'h0, stat_trig_accepted[15:0], hw_id[47:32] }; // MSB MAC Address
	   S3_HEADER2: begin 
	      data	<= { 1'b0, 1'b0, 2'h0, hw_id[31:0] };	// LSB MAC Address
	   S4_HEADER3: begin 
	      data	<= { 1'b0, 1'b0, 2'h0, fw_id[31:0] }; // build timestamp (acts as FW version)
	   S5_HEADER4: begin 
	      data	<= { 1'b0, 1'b0, 2'h0, {(32-(SZ_TIMESTAMP-32)){1'b0}},r_timestamp[(SZ_TIMESTAMP-1) : 32] }; // for now we'll reserve the remainder of this word until timestamp size is finalized
	   S6_HEADER5: begin 
	      data	<= { 1'b0, 1'b0, 2'h0, r_timestamp[31:0] };
	   S7_HEADER6: begin 
	      data	<= { 1'b0, 1'b0, 2'h0, trigger_offset[31:0] };
	   S8_HEADER7: begin 
	      data 	<= { 1'b0, 1'b0, 2'h0, module_id[7:0], ch_type, CH_ID[6:0], 4'h0 /* reserved for compression type*/, sample_cnt[11:0] };			
	   S8_HEADER7_RDY: begin 
	      data 	<= { 1'b0, 1'b0, 2'h0, module_id[7:0], ch_type, CH_ID[6:0], 4'h0 /* reserved for compression type*/, sample_cnt[11:0] };			
	   S11_DATA: begin // if last packet, pad and send out, otherwise put data in MSB, then send out next time
	      data	<= { 1'b0, 1'b0, 2'h0, wf_data[15:0], wf_data[31:16] };
	   S12_FOOTER0: begin 
	      data	<= { 1'b0, 1'b0, 2'h0, wf_data[15:0], wf_data[31:16] };
	   S13_FOOTER1: begin 
	      data	<= { 1'b0, 1'b1, 2'h0, wf_data[15:0], wf_data[31:16] };
	   //S14_CRC16: begin 
	   // data	<= { 1'b0, 1'b1, 2'h0, crc_value, 16'h0 };

Version 2

  • PACKET_TYPE = 1
  • PACKET_VERSION = 2
  • stat_trig_accepted is the trigger counter
  • timestamp runs at 125 MHz
	   S1_HEADER0: begin
              data	<= { 1'b1, 1'b0, 2'h0, PACKET_TYPE[7:0], PACKET_VERSION[7:0], PACKET_TYPE[7:0], PACKET_VERSION[7:0] };
	   S2_HEADER1: begin 
	      data	<= { 1'b0, 1'b0, 2'h0, stat_trig_accepted[15:0], hw_id[47:32] }; // MSB MAC Address
	   S3_HEADER2: begin 
	      data	<= { 1'b0, 1'b0, 2'h0, hw_id[31:0] };	// LSB MAC Address
	   S4_HEADER3: begin 
	      data	<= { 1'b0, 1'b0, 2'h0, fw_id[31:0] }; // build timestamp (acts as FW version)
	   S5_HEADER4: begin 
	      data	<= { 1'b0, 1'b0, 2'h0, {(32-(SZ_TIMESTAMP-32)){1'b0}},r_timestamp[(SZ_TIMESTAMP-1) : 32] }; // for now we'll reserve the remainder of this word until timestamp size is finalized
	   S6_HEADER5: begin 
	      data	<= { 1'b0, 1'b0, 2'h0, r_timestamp[31:0] };
	   S7_HEADER6: begin 
	      data	<= { 1'b0, 1'b0, 2'h0, trigger_offset[31:0] };
	   S8_HEADER7: begin 
	      data 	<= { 1'b0, 1'b0, 2'h0, module_id[7:0], ch_type, CH_ID[6:0], 4'h0 /* reserved for compression type*/, sample_cnt[11:0] };			
	   S8_HEADER7_RDY: begin 
	      data 	<= { 1'b0, 1'b0, 2'h0, module_id[7:0], ch_type, CH_ID[6:0], 4'h0 /* reserved for compression type*/, sample_cnt[11:0] };			
	   S11_DATA: begin // if last packet, pad and send out, otherwise put data in MSB, then send out next time
	      data	<= { 1'b0, 1'b0, 2'h0, wf_data[15:0], wf_data[31:16] };
	   S12_FOOTER0: begin 
	      data	<= { 1'b0, 1'b0, 2'h0, wf_data[15:0], wf_data[31:16] };
	   S13_FOOTER1: begin 
              data	<= { 1'b0, 1'b1, 2'h0, /* data */ 1'b1, 1'b1, ch_ctrl_supp_enable, keep_bit, keep_last[11:0], supp_baseline[15:0] };

Version 3

AAA

FMC modules

FMC-ADC32-Rev0

FMC-ADC32-Rev1

FMC-ADC32-Rev1.1

FMC-DualMiniSas-Rev1

FMC-SfpMiniSasEsata-Rev2

(note: not used on the GRIF16, this information is to be moved to the ALPHA-T page)

TODO

  • fix problem with adc16 channels not sending any data, fpga reboot does not fix this (needs power cycle to fix it?)
  • investigate counter for: Dropped Triggers Due to Full [cnt_trig_dfull] [0]
  • see this: all adc16 trigger counters stop after 63 events, except for one that keeps counting, I suspect the 16->1 packet mux is getting stuck?
  • (DONE) add esper block from pwb to show ethernet pause frames
  • update DAC control
  • implement waveform suppression
  • verify that trigger discriminator fires on both positive and negative pulses (positive and negative thresholds)
  • add provision for coded trigger signal
  • (DONE) add esper counters for adc16 and adc32 discriminator grand-or
  • (DONE) enable HTTP pipelining
  • update TRG link
  • (DONE) add more control and status registers in the "AG" module
  • verify that ADC SYNC works

ZZZ

ZZZ

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