VME-NEW-IO

Use cases of existing VME-NIMIO32 board

Specs of the existing board:

• full documentation is here: VME-NIMIO32
• 6U VME single width
• VME A32/D32, firmware implements A24/D32 single word and A24/BLT32 block transfers. There is no VME drivers on the A-lines so cannot do MBLT64, 2eVME, 2eSST.
• Altera Cyclone1 FPGA, 6k LE, 180 i/o pins, 100-200 MHz clock speeds.
• 16 NIM inputs (convertable to TTL), LEMO connectors
• 16 ECL/LVDS inputs, LeCroy 4616 compatible ECL ribbon cable connector
• 16 NIM outputs, LEMO connectors
• 32 LEDs (one for each LEMO connector)

Main uses of the IO32 board have been:

• trigger latch, trigger timestamp and busy logic daq synchronization (LXe, IRIS, M11 test beams, DRAGON, ALPHA, EMMA, TRINAT, TREK, PTF, S1249 muonium production test, etc)
• scalers (16 ch, up to 200 MHz, deadtimeless) (most users)
• timestamp counter (4 ch, 100 MHz) (TRINAT, etc)
• 40MHz V1190 and 20MHz VF48 clock generator and trigger synchronization (LXe, IRIS, TREK, S1249, etc)
• V792 ADC gate and delay generator (M11 test beams, DRAGON, TRINAT, S1249, etc)
• custom trigger logic (M11 test beams, DRAGON, ALPHA, TRINAT, S1249)
• clock and trigger synchronization between 2 VME crates (DRAGON), 2 IO32 modules (TRINAT), separate DAQs (M11 beam tests)
• in addition there is a 1ns-time-bin delay-line TDC (never used)

Number of I/Os used:

• T2K/M11 beam tests - 8 NIM in, 8 NIM out
• S1249 muonium production test (M15) - 4 NIM in, 8 NIM out, (FIXME: ECL scalers?)
• ALPHA2 Si detector DAQ (CERN) - 16 NIM in, 16 NIM out
• DRAGON - 4 NIM in, 8 NIM out
• TRINAT TTL - (FIXME: 4 TTL in?)
• TRINAT - 8 NIM in, 8 NIM out
• TRINAT 2014 - 10 NIM in, 16 NIM out
• IRIS - ???
• TITAN EC (orchid) - 8 TTL in
• TREK, IRIS - 4 NIM in, 4 NIM out (trigger, busy, 40 MHz V1190 clock, 20 MHz VF48 clock)
• BNMR/BNQR - ?
• PTF - ?

Note: existing IO32 has significant delay from LEMO connector to FPGA logic (NIM-to-LVTTL converter, FPGA input pin,etc) and from FPGA logic to NIM output pin (FPGA output pin delay, LVTTL-to-NIM converter, etc). If using ECL inputs, add delay in NIM-to-ECL converter and in the ECL ribbon cable. FIXME: what is this delay?

Conclusion: for most common cases, 8 NIM in, 8 NIM out is sufficient.

Business case for new IO32 module

The existing IO32 module is very successful. Out of all 3+10+5=18 modules built, all are in use (including the 3 rev0 modules), none have failed. This module is easy to program and easy to use.

The main problem with existing modules is the small size of the Cyclone 1 FPGA - only 6000 logic elements. This limits the generic firmware can only 16 (out of 32 possible) scaler channels, only 4 timestamp channels, only 1 or 2 (out of 5) experiment-specific functions (custom trigger logic) and no space for a high resolution TDC, no space for a high capacity timestamp or time-sliced scaler (like the Struck/SIS3820).

Secondary problem is lack of high-speed data interface - the existing VME interface is limited to single-word or 32-bit block transfers (no drivers on the A-lines to permit 2eVME or 2eSST transfers).

If this module had a bigger FPGA and a high capacity data interface, it could be used to implement a 32-channel non-deadtime scaler or timestamp counter or a delay line or wavelet medium resolution TDC (1 ns time bin or better).

We have existing experiments that could use the timestamp and wavelet/delay line TDC functions right away - as low precision and medium precision TDCs - 5-10 ns and 200-1000 ps time bins - respectively - and possibly release some high precision V1190 TDC module.

Wish list for the new IO module

• VME form factor for power and cooling
• possible standalone use (external power connector)
• high speed data interface, i.e. GigE ethernet
• VME slave interface at least A16/D16 for integrating into existing VME DAQ systems as trigger latch, trigger timestamp and busy logic modules.
• VME master interface A32/D32 with 2eVME/2eSST capability (drivers for all A and D lines + drivers for BERR and RETRY) for use as light-weight replacement for V7750/V7805/V7865 VME processors.
• 8 NIM input, 8 NIM output, LEMO connectors, switchable to TTL (like the PPG32).
• multicoloured LEDs for each LEMO input and output
• 16 ECL/LVDS LeCroy 4616 compatible ribbon cable interface (like the IO32)
• reduced time delay from LEMO connector to FPGA logic and back (compared to IO32 and PPG32)
• a few channels of medium speed DAC (like the PPG32)
• a few channels of medium speed ADC (60-100 MHz, 10-12 bits)
• industry standard daughter board connector (HSMC, FMC)

Note: implementing all wish-list items at once will run into limitations of FPGA pins and front panel connector space. It is certainly acceptable to produce several variations of the board - single-width minimum configuration and double-width maximum configuration.

Budget of FPGA I/O pins

• 8 LEMO in, 16 ECL in, 8 LEMO out: 24 lvds in, 8 lvds out = 32 lvds pairs = 64
• LEDs: 3 inout = 3
• VME slave interface:
  • D32 - 32 in/out + 1 OEn out - 33 inout
  • A24/A32 VME-NIMIO32 style - A[23..1],LWORD - 24 in
  • control in - AM[5..0], AS, DS0, DS1, WR - 10 in
  • control in/out - DTACK, BERR, RETRY - 3 inout
  • control interrupts - 2 in, 2 out
  • total control signals - 17
• VME slave interface (A16/D16): 16 A + 16 D + 1 OE + 10 control + 1 DTACK + 4 intr = 48
• VME slave interface (A24/D32): 24 A + 32 D + 1 OE + 10 control + 3 D/B/R + 4 intr = 74
• VME slave interface with MBLT64/2eSST/2eVME capability: 32 A (inout) + 32 D + 2 OE + 10 control + 3 D/B/R + 4 intr = 83
• VME note1: MBLT64/2eVME/2eSST do not require A[31..24] connected
• VME note2: MBLT64/2eVME/2eSST do not require that slave drives the address lines (obviously 64-bit path is reduced to 32-bit path)
• VME note3: 2eSST requires RETRY signal located on the P2 connector.
• VME full master interface: same as above = 83
• HSMC connector: 120 pins(?) (bank1: 40, bank2: 40, bank3: 40)
• FMC connector: 246 pins (68 LPC + 160 HPC)

Available pins using CriticalLink Cyclone5 MitySOM http://www.criticallink.com/wp-content/uploads/MitySOM-5CSx-Datasheet.pdf

• 133 FPGA pins (68 Bank4A + 32 Bank3B + 6 Bank8A + 1 Bank5A + 26 Bank3A/5A = 133)
• 44 CPU pins
• $500 https://www.arrow.com/en/products/5csx-h6-4ya-rc/critical-link

Available pins using bare Cyclone5 SOM FPGA

• 288 FPGA pins
• 188 CPU pins
• subtract pins required to connect RAM, boot flash, network, etc

Available pins Arria5GX FPGA (GRIF16)

• 544 FPGA pins

Proposal of minimum configuration board

This design is meant to: a) provide maximum similarity to the existing IO32 board in it's programming and it's use b) provides the least production cost

Features:

• VME 6U single width form factor
• 8 NIM/TTL inputs, 8 NIM/TTL, with corresponding LEDs (existing IO32 board, halved)
• 16 ECL/LVDS LeCroy 4616 compatible ribbon cable interface (like the IO32)
• GigE network interface
• HSMC/FMC site

Board connectors layout:

top front <---> back
-----------------------------------------------------------------
| block of LEDs (VME access, power, etc)
| RJ45 GigE
|/-----
|| space for
|| FMC/HSMC
|| daughter
|| board
|\-----
| same 6,7
| same 4,5
| same 2,3, nim/ttl switches
| dual lemo nim/ttl output 0,1
| same 6,7
| same 4,5
| same 2,3, nim/ttl switches      |................| ECL/LVDS
| dual lemo nim/ttl input 0,1     |................| inputs
-----------------------------------------------------------------
bottom front <---> back

It is easy to see how the front panel is very crowded. To save some space one can consider replacing dual-lemo connectors with higher-density connectors, but beware of additional costs (most experiments use LEMO cables, so adapters will have to be built/purchased) and board use difficulties (adapter cables of assorted lengths will have to be in stock ready to use at moment's notice - "the beam is on and we need one more signal connected right now at midnight on Sunday").

AAA

AAA