BNMR: Hardware Debugging: Difference between revisions

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Test3 runs a test using the external LNE and counter gate which can be provided by the PPG.  
Test3 runs a test using the external LNE and counter gate which can be provided by the PPG.  


=== Example ===
=== Examples ===
<pre>
<pre>
[bnqr@lxbnqr bnqr]$ ../../vmetest/sis3820
[bnqr@lxbnqr bnqr]$ ../../vmetest/sis3820
Line 224: Line 224:
R reset module              S status
R reset module              S status
X quit
X quit
 
</pre>
==== Read Control/Status Reg using command 'C' ====
<pre>
Enter command (A-Z) X to exit, P Print commands?  C
Enter command (A-Z) X to exit, P Print commands?  C
Control/Status Reg at Addr 0x000 : 0x40
Control/Status Reg at Addr 0x000 : 0x40
Line 235: Line 237:
Status of External Input bits 0
Status of External Input bits 0
Status of External Latch bits 0
Status of External Latch bits 0
 
</pre>
==== Read Operation Mode Reg using command 'B' ====
<pre>
Enter command (A-Z) X to exit, P Print commands?  B
Enter command (A-Z) X to exit, P Print commands?  B
Operation Mode Reg at Addr 0x100 : Read back  0x20230014 from reg 0x100
Operation Mode Reg at Addr 0x100 : Read back  0x20230014 from reg 0x100
Line 252: Line 256:
[bnqr@lxbnqr bnqr]$  
[bnqr@lxbnqr bnqr]$  
</pre>
</pre>
==== Run test3 (requires loaded PPG to supply signals) ====
<pre>
Enter command (A-Z) X to exit, P Print commands?  N
test3: Scaler Inputs are assumed to be NIM, starting at Ch 17
      All Scaler Input Channels will be disabled except channels 1 and 17-19
      Channel 1 Reference pulse is enabled
      PPG McsNext Output    should be connected to Scaler LNE Input
      PPG CounterGate Output should be connected to Scaler Inhibit LNE Input
      PPG should be loaded with a bnmr/bnqr loadfile so that it will run a cycle when started
      Continue (y/n) ?
Enter Number of bins ? 10
Number of bins=10
malloc SIS3820 readout buffer: pfifo ptr 0x978eb58
check_sis3820:  ModuleID and Firmware: 0x3820010c
ModuleID 0x3820
Setting up SIS3820 at base address 0x38000000
Writing 0xfff8fffe to reg 0x104
Read back  0xfff8fffe from reg 0x104
Writing nbins=10 to preset register
Writing 0xa to reg 0x10
Read back  0xa from reg 0x10
Writing 1 to LNE Prescale Register (no prescale)
Read back  0xa from reg 0x10
Preset register: 10
Read back  0xf from reg 0x14
Count register: 15
ARMing Scaler
SIS3820 at A32 0x38000000
Registers:
  ModuleID and Firmware Addr 0x004 : 0x3820010c
  CSR0                  Addr 0x000 : 0x1000040
  Operation mode        Addr 0x100 : 0x20230014
  Inhibit/Count disable Addr 0x200 : 0x0
  Counter Overflow      Addr 0x208 : 0x0
Control/Status Reg at Addr 0x000 : 0x1000040
Decoding Control/Status Reg at Addr 0x000 : 0x1000040
User LED off            25MHz Pulses disabled   
Cntr TestMode disabled  50MHz RefCh1 enabled   
Sclr enable NOT active  MCS enable NOT active   
SDRAM/FIFO test disabled Armed   
HISCAL disabled         
Status of External Input and Latch bits depend on Input Mode:
Status of External Input bits 0
Status of External Latch bits 0
Now start the PPG (e.g. with the program vppg)
Has PPG now run a cycle (y/n)?y
acquisition count = 10
MCS mode, bin 10 completed
Module contains 40 words
i=0 *pbuf=0x000f4209 h=00 ub=0 sdata=0x0f4209 gbl_bin=0  // Bin 0 Ch 1 test pulses enabled
i=1 *pbuf=0x10000000 h=01 ub=0 sdata=0x000000 gbl_bin=0  // Bin 0 Ch 17 no input
i=2 *pbuf=0x11000000 h=02 ub=0 sdata=0x000000 gbl_bin=0  // Bin 0 Ch 18 no input
i=3 *pbuf=0x12000000 h=03 ub=0 sdata=0x000000 gbl_bin=0  // Bin 0 Ch 19 no input
i=4 *pbuf=0x000f4208 h=00 ub=0 sdata=0x0f4208 gbl_bin=1  // Bin 1 Ch 1 test pulses enabled
i=5 *pbuf=0x10000000 h=01 ub=0 sdata=0x000000 gbl_bin=1
i=6 *pbuf=0x11000000 h=02 ub=0 sdata=0x000000 gbl_bin=1
i=7 *pbuf=0x12000000 h=03 ub=0 sdata=0x000000 gbl_bin=1
i=8 *pbuf=0x000f4209 h=00 ub=0 sdata=0x0f4209 gbl_bin=2
i=9 *pbuf=0x10000000 h=01 ub=0 sdata=0x000000 gbl_bin=2
i=10 *pbuf=0x11000000 h=02 ub=0 sdata=0x000000 gbl_bin=2
i=11 *pbuf=0x12000000 h=03 ub=0 sdata=0x000000 gbl_bin=2
i=12 *pbuf=0x000f4208 h=00 ub=0 sdata=0x0f4208 gbl_bin=3
i=13 *pbuf=0x10000000 h=01 ub=0 sdata=0x000000 gbl_bin=3
i=14 *pbuf=0x11000000 h=02 ub=0 sdata=0x000000 gbl_bin=3
i=15 *pbuf=0x12000000 h=03 ub=0 sdata=0x000000 gbl_bin=3
i=16 *pbuf=0x000f4208 h=00 ub=0 sdata=0x0f4208 gbl_bin=4
i=17 *pbuf=0x10000000 h=01 ub=0 sdata=0x000000 gbl_bin=4
i=18 *pbuf=0x11000000 h=02 ub=0 sdata=0x000000 gbl_bin=4
i=19 *pbuf=0x12000000 h=03 ub=0 sdata=0x000000 gbl_bin=4
i=20 *pbuf=0x000f4208 h=00 ub=0 sdata=0x0f4208 gbl_bin=5
i=21 *pbuf=0x10000000 h=01 ub=0 sdata=0x000000 gbl_bin=5
i=22 *pbuf=0x11000000 h=02 ub=0 sdata=0x000000 gbl_bin=5
i=23 *pbuf=0x12000000 h=03 ub=0 sdata=0x000000 gbl_bin=5
i=24 *pbuf=0x000f4208 h=00 ub=0 sdata=0x0f4208 gbl_bin=6
i=25 *pbuf=0x10000000 h=01 ub=0 sdata=0x000000 gbl_bin=6
i=26 *pbuf=0x11000000 h=02 ub=0 sdata=0x000000 gbl_bin=6
i=27 *pbuf=0x12000000 h=03 ub=0 sdata=0x000000 gbl_bin=6
i=28 *pbuf=0x000f4208 h=00 ub=0 sdata=0x0f4208 gbl_bin=7
i=29 *pbuf=0x10000000 h=01 ub=0 sdata=0x000000 gbl_bin=7
i=30 *pbuf=0x11000000 h=02 ub=0 sdata=0x000000 gbl_bin=7
i=31 *pbuf=0x12000000 h=03 ub=0 sdata=0x000000 gbl_bin=7
i=32 *pbuf=0x000f4208 h=00 ub=0 sdata=0x0f4208 gbl_bin=8
i=33 *pbuf=0x10000000 h=01 ub=0 sdata=0x000000 gbl_bin=8
i=34 *pbuf=0x11000000 h=02 ub=0 sdata=0x000000 gbl_bin=8
i=35 *pbuf=0x12000000 h=03 ub=0 sdata=0x000000 gbl_bin=8
i=36 *pbuf=0x000f4209 h=00 ub=0 sdata=0x0f4209 gbl_bin=9
i=37 *pbuf=0x10000000 h=01 ub=0 sdata=0x000000 gbl_bin=9
i=38 *pbuf=0x11000000 h=02 ub=0 sdata=0x000000 gbl_bin=9
i=39 *pbuf=0x12000000 h=03 ub=0 sdata=0x000000 gbl_bin=9
expect ub=2 on last bin for Type 2 (ub=0 gbl_bin=9 nbins=10  // NOTE: Userbit absent because
                                                              //  1. Userbits not plugged in       
Read back  0xa from reg 0x10                                  //  2. PPG cycle produces > 10 bins
Preset register: 10
Read back  0xa from reg 0x14
Count register: 10
Disabled and Cleared SIS3820 SCALER B
Enter command (A-Z) X to exit, P Print commands? 
</pre>
== Operation of sis3820 in the frontend ==
The operation of the sis3820 in the frontend is similar to test3 above.
The sis3820 scaler is reset in frontend_init() and begin_of_run() by calling init_sis3820(). This then sets up the
scaler for data acquisition, including disabling unused channels and writing the number of bins to the preset register.
After scaler_start()
<pre>
start_scalers: SIS3820_ACQUISITION_COUNT reg reads 300 bins
SIS3820 at A32 0x38000000
Registers:
  ModuleID and Firmware Addr 0x004 : 0x3820010c
  CSR0                  Addr 0x000 : 0x1000040
  Operation mode        Addr 0x100 : 0x20230014
  Inhibit/Count disable Addr 0x200 : 0x0
  Counter Overflow      Addr 0x208 : 0x0
Operation Mode register contents: 0x20230014  Prescaling register contents: 0x0
Clearing Mode: Y  Data Format  : 24 Bit
LNE Source  : Front Panel;  LNE can NOT be prescaled in this mode
Arm/enable source: LNE Front Panel
SDRAM mode  : FIFO Emulation
Input  Mode 1 selected  Control Inputs  are NOT inverted
Output Mode 0 selected  Control Outputs are NOT inverted
Operation Mode MULTI CHANNEL SCALER selected
Decoding Control/Status Reg at Addr 0x000 : 0x1000040
User LED off            25MHz Pulses disabled   
Cntr TestMode disabled  50MHz RefCh1 enabled   
Sclr enable NOT active  MCS enable NOT active   
SDRAM/FIFO test disabled Armed   
HISCAL disabled         
Status of External Input and Latch bits depend on Input Mode:
Status of External Input bits 0
Status of External Latch bits 0
</pre>
[[Category:BNMR]]
[[Category:BNMR]]

Revision as of 14:50, 14 September 2018

Introduction

Test programs have been created for some of the DAQ VME modules in use in the BNMR/BNQR experiments. The test programs can be found in the directory /home/bnm[qr]/vmetest.

Table 4: DAQ Test Software
Module ProgramName Purpose
PPG vppg test program for PulseBlaster PPG
PPG32 newppg test program for PPG32
SIS3801 sis3801 test program for SIS3801 scaler
SIS3820 sis3820 test program for SIS3820 scaler
PSM/PSMII psmII test program for PSM/PSMII RF module
PSMIII psm3 test program for PSMIII RF module
VMEIO heltest test program for setting helicity using VMEIO

All these programs must be run on the VMIC (not the host computer).

psm3

The test program psm3 tests the PSMIII module. The source code for psm3 is the PSMIII driver, i.e. files trPSM3.c and trPSM3.h. These are built with MAIN defined in the test area, using the command make psm3.

Copies of these files under /home/bn[mq]r/online/psm3/ are built into the frontend.

psm3 is a menu-driven program. It can be run (with caution) at the same time as the DAQ, as it does not automatically do any initialization. The module's registers can be dumped by using the 'Dump Registers' command.

example

[bnmr@lxbnmr ~/vmetest]$ psm3
calc_freq_conversion sets max freq = 199999999.953434 Hz and  finc=0.046566 
Current experiment is bnmr
vmic_mmap: Mapped VME AM 0x09 addr 0x00000000 size 0x00ffffff at address 0x20100000
mvme_open:
Bus handle              = 0x3
DMA handle              = 0x97413e8
DMA area size           = 1048576 bytes
DMA    physical address = 0xb667b000

Pol Synthesizer Module: base address  psm_base=0x820000
       TRIUMF PSM function support
A Read Control Reg         a Write Control Reg   
B Select BNMR/BNQR Mode    b Set BNQR PhaseShift 
C Select Channel(s)        c End Sweep Control
D Dump Registers           d Read/Write Freq Sweep Length
E Read Freq Memory         e Read IQ Memory 
F Write Freq Memory(Hz)    f Write IQ Memory
G Gate Control             g Pre/Gated Output Select
H help                     I Init module  
J Write Tuning Freq        j Read Tuning Freq
K Ancillary Control        k Ancillary I/O 
L Read/Write Channel Reg   l Read/Write Scale Factor   
M Load frequency file(hex) m Read/Write Buffer Factor 
P Print this list          p Freq Sweep Addr Preset  
R VME Reset                r Freq Sweep Addr Reset
S status                   s Freq Sweep Strobe
V RF Power Trip Threshold  v RF Power Trip Status/Reset 
d debug (toggles)

Test procedures:
1 Set freq, phase & turn channels on for a certain time
2 Load freq and iq memory from files, load idle, set length regs, preset addr, strobe

Enter command (A-Z a-z) X to exit?  D

               Frequency  
vmic_mmap: Mapped VME AM 0x3d addr 0x00000000 size 0x00ffffff at address 0x22100000
Idle Freq (offset 0x1ffc) = 40028000 Hz  (hex value= 0x333c6003) 
Frequency sweep address  =     0x7ff (2047)
Frequency sweep length  =     0x000 (0)
f1 tuning frequency = 0 Hz (hex value = 0x0)
fC0 tuning frequency = 0 Hz (hex value = 0x0)
fC1 tuning frequency = 0 Hz (hex value = 0x0)

      Control Registers   
Register Register #Valid|                 F0                        F1
Name     Offset   bits  |   Chan1 |   Chan2 |   Chan3 |   Chan4 |       
Phase Mod  0x00    16   |  0x0000 |  0x0000 |  0x0000 |  0x0000 |  0x0000  
Scale Fac  0x02    08   |    0x00 |    0x00 |    0x00 |    0x00 |    0x00  
Buff  Fac  0x04    10   |   0x001 |   0x001 |   0x001 |   0x001 |   0x001  
IQDM  Len  0x06    11   |   0x000 |   0x000 |   0x000 |   0x000 |   0x000  
IQDM Addr  0x08    11   |   0x7ff |   0x7ff |   0x7ff |   0x7ff |   0x7ff  
I,Q Idle 0x1ffc    10   |    512,0|    0,511|    512,0|    0,511|    0,511

Bit Pattern  registers
Reg      Reg    Reg
Name     Offset Value  Ch1  Ch2  Ch3  Ch4   F1  Freq 
EndSweep 0x004b  0x3f    1    1    1    1    1    1   0=stop at Nth 1=jump to idle
Gate     0x004c 0x000    0    0    0    0    0         0=disable 1=enable 2=invert 3=always on
AncCntrl 0x0050 0x000    0    0    0    0              0=NIM input 1=NIM output
AncIn    0x004e 0x000    0    0    0    0              0=Off 1=On
AncOut   0x004f 0x000    0    0    0    0              0=Off 1=On

Other registers
Reg         Reg     Reg
Name        Offset  Value
PreGatedOut 0x0051 0x000 RF  PreGated port: F0 ch1 selected
GatedOut    0x0052 0x000 RF     Gated port: F0 ch1 selected
RFtripThr   0x0053 0x0080 Voltage trip at 2.000000 Volts
RFtrip      0x0054 0x0000 1=tripped
Mode        0x0055 0x0000 0=BNMR 1=BNQR
FPGA Temp   0x0058 0x2040 Temperature 64 degrees C (approx) 

Enter command (A-Z a-z) X to exit?

vppg

The test program vppg tests the PulseBlaster PPG module. The source code for vppg is the ppg driver, i.e. files vppg.c and vppg.h. These are built with MAIN defined in the test area, using the command make ppg.

Copies of these files under /home/bn[mq]r/online/ppg/ are built into the frontend.

vppg is a menu-driven program. It can be run (with caution) for debugging at the same time as the DAQ, as it does not automatically do any initialization. For example, it can be used to check whether the PPG is running.

example

[bnmr@lxbnmr ~/vmetest]$ vppg
vmic_mmap: Mapped VME AM 0x09 addr 0x00000000 size 0x00ffffff at address 0x20100000
mvme_open:
Bus handle              = 0x3
DMA handle              = 0x870a3e8
DMA area size           = 1048576 bytes
DMA    physical address = 0xb6655000
vmic_mmap: Mapped VME AM 0x29 addr 0x00000000 size 0x0000ffff at address 0x27ff0000
Pulseblaster IS reset
Pulseblaster NOT running 
Pulseblaster is NOT stopped 
VME polarization source control bits = 0x0
VME Polarization control: OFF 
External clock IS present 
External  Polarization control: OFF 
External trigger is DISABLED
External trigger register = 0x1
       PPG function support
A Init               B Load
C StopSequencer      E StartSequencer
F EnableExtTrig      G DisableExtTrig
H ExtTrigRegRead     I StatusRead
J PolmskRead         K PolmskWrite
L RegWrite           M RegRead
N StartpatternWrite  O PolzSet
Q PolzRead           R PolzFlip
S PolzCtlPPG         T PolzCtlVME
U BeamOn             V BeamOff 
W BeamCtlPPG         Y BeamCtlRegRead
D debug (toggles)    P print this list
X exit 

Enter command (A-Y) X to exit?  I
Pulseblaster IS reset
Pulseblaster NOT running 
Pulseblaster is NOT stopped 
VME polarization source control bits = 0x0
VME Polarization control: OFF 
External clock IS present 
External  Polarization control: OFF 
Read back data =0x21

Enter command (A-Y) X to exit?  X

sis3820

Note
The sis3820 must be used in non-DMA mode. The DMA mode does not work

The test program sis3820 tests the SIS3820 scaler. The source code for sis3820 is the sis3820 driver, i.e. files sis3820.c and sis3820.h. For testing in /home/bn[mq]r/vmetest use 

$ cd /home/bnqr/vmetest
$ make sis3820
to build the test program. The makefile defines MAIN_ENABLE to build the main program for testing.

Copies of these files under /home/bn[mq]r/online/sis3820/ are built into the frontend with MAIN_ENABLE undefined.

sis3820 is a menu-driven program. It can be run (with caution) for debugging at the same time as the DAQ, as it does not automatically do any initialization. For example, it can be used to read the control/status and operation mode register.

Several test procedures are provided. For example, test1 runs a test using the internal 10MHz clock as the LNE source, then reads out the data from the FIFO. Test3 runs a test using the external LNE and counter gate which can be provided by the PPG.

Examples

[bnqr@lxbnqr bnqr]$ ../../vmetest/sis3820
vmic_mmap: Mapped VME AM 0x09 addr 0x00000000 size 0x00ffffff at address 0x28000000
mvme_open:
Bus handle              = 0x3
DMA handle              = 0x92c03e8
DMA area size           = 1048576 bytes
DMA    physical address = 0xb65f1000
Base Address is 0x38000000
To change Base Address, specify base address on command line
SIS3820 at A32 0x38000000
Registers:
vmic_mmap: Mapped VME AM 0x0d addr 0x38000000 size 0x00ffffff at address 0x21100000
   ModuleID and Firmware Addr 0x004 : 0x3820010c
   CSR0                  Addr 0x000 : 0x40
   Operation mode        Addr 0x100 : 0x20230014
   Inhibit/Count disable Addr 0x200 : 0x0
   Counter Overflow      Addr 0x208 : 0x0

sis3820 commands: 
B read Operation Mode reg    C read  Control/Status reg CSR0
D read copy disable reg      E write copy disable reg
F read reg                   G write reg
I read ACQ PRESET then ACQ COUNT reg 5 times (10ms intervals)
J issue LNE                  K enable operation/counting
L disable operation/counting M arm in MCS mode
N Test3 ext LNE with PPG     O Test1 internal 10 MHz clock as LNE
P print this list            Q Test2 
R reset module               S status
X quit

Read Control/Status Reg using command 'C'

Enter command (A-Z) X to exit, P Print commands?  C
Control/Status Reg at Addr 0x000 : 0x40
User LED off             25MHz Pulses disabled    
Cntr TestMode disabled   50MHz RefCh1 enabled     
Sclr enable NOT active   MCS enable NOT active    
SDRAM/FIFO test disabled NOT armed 
HISCAL disabled          
Status of External Input and Latch bits depend on Input Mode:
Status of External Input bits 0
Status of External Latch bits 0

Read Operation Mode Reg using command 'B'

Enter command (A-Z) X to exit, P Print commands?  B
Operation Mode Reg at Addr 0x100 : Read back  0x20230014 from reg 0x100
Prescaling Reg     at Addr 0x018 : Read back  0x0 from reg 0x18

Clearing Mode: Y   Data Format  : 24 Bit
LNE Source  : Front Panel;  LNE can NOT be prescaled in this mode
Arm/enable source: LNE Front Panel
SDRAM mode  : FIFO Emulation
Input  Mode 1 selected   Control Inputs  are NOT inverted
Output Mode 0 selected   Control Outputs are NOT inverted
Operation Mode MULTI CHANNEL SCALER selected


Enter command (A-Z) X to exit, P Print commands?  X
[bnqr@lxbnqr bnqr]$

Run test3 (requires loaded PPG to supply signals)

Enter command (A-Z) X to exit, P Print commands?  N

test3: Scaler Inputs are assumed to be NIM, starting at Ch 17
       All Scaler Input Channels will be disabled except channels 1 and 17-19
       Channel 1 Reference pulse is enabled

       PPG McsNext Output     should be connected to Scaler LNE Input
       PPG CounterGate Output should be connected to Scaler Inhibit LNE Input
       PPG should be loaded with a bnmr/bnqr loadfile so that it will run a cycle when started
       Continue (y/n) ?

Enter Number of bins ? 10
Number of bins=10
malloc SIS3820 readout buffer: pfifo ptr 0x978eb58
check_sis3820:   ModuleID and Firmware: 0x3820010c
ModuleID 0x3820 

Setting up SIS3820 at base address 0x38000000

Writing 0xfff8fffe to reg 0x104
Read back  0xfff8fffe from reg 0x104
Writing nbins=10 to preset register

Writing 0xa to reg 0x10
Read back  0xa from reg 0x10
Writing 1 to LNE Prescale Register (no prescale)
Read back  0xa from reg 0x10
Preset register: 10 
Read back  0xf from reg 0x14
Count register: 15 
ARMing Scaler
SIS3820 at A32 0x38000000
Registers:
   ModuleID and Firmware Addr 0x004 : 0x3820010c
   CSR0                  Addr 0x000 : 0x1000040
   Operation mode        Addr 0x100 : 0x20230014
   Inhibit/Count disable Addr 0x200 : 0x0
   Counter Overflow      Addr 0x208 : 0x0
Control/Status Reg at Addr 0x000 : 0x1000040
Decoding Control/Status Reg at Addr 0x000 : 0x1000040

User LED off             25MHz Pulses disabled    
Cntr TestMode disabled   50MHz RefCh1 enabled     
Sclr enable NOT active   MCS enable NOT active    
SDRAM/FIFO test disabled Armed     
HISCAL disabled          
Status of External Input and Latch bits depend on Input Mode:
Status of External Input bits 0
Status of External Latch bits 0

Now start the PPG (e.g. with the program vppg)
Has PPG now run a cycle (y/n)?y
acquisition count = 10

MCS mode, bin 10 completed
Module contains 40 words
i=0 *pbuf=0x000f4209 h=00 ub=0 sdata=0x0f4209 gbl_bin=0   // Bin 0 Ch 1 test pulses enabled
i=1 *pbuf=0x10000000 h=01 ub=0 sdata=0x000000 gbl_bin=0   // Bin 0 Ch 17 no input
i=2 *pbuf=0x11000000 h=02 ub=0 sdata=0x000000 gbl_bin=0   // Bin 0 Ch 18 no input 
i=3 *pbuf=0x12000000 h=03 ub=0 sdata=0x000000 gbl_bin=0   // Bin 0 Ch 19 no input
i=4 *pbuf=0x000f4208 h=00 ub=0 sdata=0x0f4208 gbl_bin=1   // Bin 1 Ch 1 test pulses enabled
i=5 *pbuf=0x10000000 h=01 ub=0 sdata=0x000000 gbl_bin=1
i=6 *pbuf=0x11000000 h=02 ub=0 sdata=0x000000 gbl_bin=1
i=7 *pbuf=0x12000000 h=03 ub=0 sdata=0x000000 gbl_bin=1
i=8 *pbuf=0x000f4209 h=00 ub=0 sdata=0x0f4209 gbl_bin=2
i=9 *pbuf=0x10000000 h=01 ub=0 sdata=0x000000 gbl_bin=2
i=10 *pbuf=0x11000000 h=02 ub=0 sdata=0x000000 gbl_bin=2
i=11 *pbuf=0x12000000 h=03 ub=0 sdata=0x000000 gbl_bin=2
i=12 *pbuf=0x000f4208 h=00 ub=0 sdata=0x0f4208 gbl_bin=3
i=13 *pbuf=0x10000000 h=01 ub=0 sdata=0x000000 gbl_bin=3
i=14 *pbuf=0x11000000 h=02 ub=0 sdata=0x000000 gbl_bin=3
i=15 *pbuf=0x12000000 h=03 ub=0 sdata=0x000000 gbl_bin=3
i=16 *pbuf=0x000f4208 h=00 ub=0 sdata=0x0f4208 gbl_bin=4
i=17 *pbuf=0x10000000 h=01 ub=0 sdata=0x000000 gbl_bin=4
i=18 *pbuf=0x11000000 h=02 ub=0 sdata=0x000000 gbl_bin=4
i=19 *pbuf=0x12000000 h=03 ub=0 sdata=0x000000 gbl_bin=4
i=20 *pbuf=0x000f4208 h=00 ub=0 sdata=0x0f4208 gbl_bin=5
i=21 *pbuf=0x10000000 h=01 ub=0 sdata=0x000000 gbl_bin=5
i=22 *pbuf=0x11000000 h=02 ub=0 sdata=0x000000 gbl_bin=5
i=23 *pbuf=0x12000000 h=03 ub=0 sdata=0x000000 gbl_bin=5
i=24 *pbuf=0x000f4208 h=00 ub=0 sdata=0x0f4208 gbl_bin=6
i=25 *pbuf=0x10000000 h=01 ub=0 sdata=0x000000 gbl_bin=6
i=26 *pbuf=0x11000000 h=02 ub=0 sdata=0x000000 gbl_bin=6
i=27 *pbuf=0x12000000 h=03 ub=0 sdata=0x000000 gbl_bin=6
i=28 *pbuf=0x000f4208 h=00 ub=0 sdata=0x0f4208 gbl_bin=7
i=29 *pbuf=0x10000000 h=01 ub=0 sdata=0x000000 gbl_bin=7
i=30 *pbuf=0x11000000 h=02 ub=0 sdata=0x000000 gbl_bin=7
i=31 *pbuf=0x12000000 h=03 ub=0 sdata=0x000000 gbl_bin=7
i=32 *pbuf=0x000f4208 h=00 ub=0 sdata=0x0f4208 gbl_bin=8
i=33 *pbuf=0x10000000 h=01 ub=0 sdata=0x000000 gbl_bin=8
i=34 *pbuf=0x11000000 h=02 ub=0 sdata=0x000000 gbl_bin=8
i=35 *pbuf=0x12000000 h=03 ub=0 sdata=0x000000 gbl_bin=8
i=36 *pbuf=0x000f4209 h=00 ub=0 sdata=0x0f4209 gbl_bin=9
i=37 *pbuf=0x10000000 h=01 ub=0 sdata=0x000000 gbl_bin=9
i=38 *pbuf=0x11000000 h=02 ub=0 sdata=0x000000 gbl_bin=9
i=39 *pbuf=0x12000000 h=03 ub=0 sdata=0x000000 gbl_bin=9

expect ub=2 on last bin for Type 2 (ub=0 gbl_bin=9 nbins=10   // NOTE: Userbit absent because 
                                                              //   1. Userbits not plugged in        
Read back  0xa from reg 0x10                                  //   2. PPG cycle produces > 10 bins
Preset register: 10 
Read back  0xa from reg 0x14
Count register: 10
Disabled and Cleared SIS3820 SCALER B 

Enter command (A-Z) X to exit, P Print commands?


Operation of sis3820 in the frontend

The operation of the sis3820 in the frontend is similar to test3 above.

The sis3820 scaler is reset in frontend_init() and begin_of_run() by calling init_sis3820(). This then sets up the scaler for data acquisition, including disabling unused channels and writing the number of bins to the preset register.

After scaler_start() 

start_scalers: SIS3820_ACQUISITION_COUNT reg reads 300 bins 
SIS3820 at A32 0x38000000
Registers:
   ModuleID and Firmware Addr 0x004 : 0x3820010c
   CSR0                  Addr 0x000 : 0x1000040
   Operation mode        Addr 0x100 : 0x20230014
   Inhibit/Count disable Addr 0x200 : 0x0
   Counter Overflow      Addr 0x208 : 0x0


Operation Mode register contents: 0x20230014   Prescaling register contents: 0x0

Clearing Mode: Y   Data Format  : 24 Bit
LNE Source  : Front Panel;  LNE can NOT be prescaled in this mode
Arm/enable source: LNE Front Panel
SDRAM mode  : FIFO Emulation
Input  Mode 1 selected   Control Inputs  are NOT inverted
Output Mode 0 selected   Control Outputs are NOT inverted
Operation Mode MULTI CHANNEL SCALER selected

Decoding Control/Status Reg at Addr 0x000 : 0x1000040

User LED off             25MHz Pulses disabled    
Cntr TestMode disabled   50MHz RefCh1 enabled     
Sclr enable NOT active   MCS enable NOT active    
SDRAM/FIFO test disabled Armed     
HISCAL disabled          
Status of External Input and Latch bits depend on Input Mode:
Status of External Input bits 0
Status of External Latch bits 0
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