BNMR: Hardware Debugging

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Introduction

Test programs have been created for some of the DAQ VME modules in use in the BNMR/BNQR experiments. The test programs are built alongside the main frontend and logger programs.

Table 4: DAQ Test Software

Module	ProgramName	Purpose
PulseBlaster PPG	vppg_interactive_32bit.exe	test program for PulseBlaster PPG
TRIUMF PPG (PPG32)	tppg_interactive_32bit.exe	test program for TRIUMF PPG32 (not used by bnmr / bnqr yet)
SIS3801	sis3801_interactive_32bit.exe	test program for SIS3801 scaler
SIS3820	sis3820_interactive_32bit.exe	test program for SIS3820 scaler
PSM	psm_interactive_32bit.exe	test program for PSM RF module
PSMII	psm2_interactive_32bit.exe	test program for PSMII RF module
PSMIII	psm3_interactive_32bit.exe	test program for PSMIII RF module
NIMIO	bnmrbeamsim_32bit.exe	test program for NIMIO32, inclusing simulating BNMR beam/helicity flipping

All the 32bit programs must be run on the VMIC (not the host computer). The non-32bit programs must be run on the host computer.

PSM

The test program psm3_interactive_32bit.exe tests the PSMIII module.

This is a menu-driven program. It can be run (with caution) at the same time as the DAQ, as it does not automatically do any initialization. The module's registers can be dumped by using the 'Dump Registers' command.

example

$ psm3_interactive_32bit.exe
calc_freq_conversion sets max freq = 199999999.953434 Hz and  finc=0.046566 
Current experiment is bnmr
vmic_mmap: Mapped VME AM 0x09 addr 0x00000000 size 0x00ffffff at address 0x20100000
mvme_open:
Bus handle              = 0x3
DMA handle              = 0x97413e8
DMA area size           = 1048576 bytes
DMA    physical address = 0xb667b000

Pol Synthesizer Module: base address  psm_base=0x820000
       TRIUMF PSM function support
A Read Control Reg         a Write Control Reg   
B Select BNMR/BNQR Mode    b Set BNQR PhaseShift 
C Select Channel(s)        c End Sweep Control
D Dump Registers           d Read/Write Freq Sweep Length
E Read Freq Memory         e Read IQ Memory 
F Write Freq Memory(Hz)    f Write IQ Memory
G Gate Control             g Pre/Gated Output Select
H help                     I Init module  
J Write Tuning Freq        j Read Tuning Freq
K Ancillary Control        k Ancillary I/O 
L Read/Write Channel Reg   l Read/Write Scale Factor   
M Load frequency file(hex) m Read/Write Buffer Factor 
P Print this list          p Freq Sweep Addr Preset  
R VME Reset                r Freq Sweep Addr Reset
S status                   s Freq Sweep Strobe
V RF Power Trip Threshold  v RF Power Trip Status/Reset 
d debug (toggles)

Test procedures:
1 Set freq, phase & turn channels on for a certain time
2 Load freq and iq memory from files, load idle, set length regs, preset addr, strobe

Enter command (A-Z a-z) X to exit?  D

               Frequency  
vmic_mmap: Mapped VME AM 0x3d addr 0x00000000 size 0x00ffffff at address 0x22100000
Idle Freq (offset 0x1ffc) = 40028000 Hz  (hex value= 0x333c6003) 
Frequency sweep address  =     0x7ff (2047)
Frequency sweep length  =     0x000 (0)
f1 tuning frequency = 0 Hz (hex value = 0x0)
fC0 tuning frequency = 0 Hz (hex value = 0x0)
fC1 tuning frequency = 0 Hz (hex value = 0x0)

      Control Registers   
Register Register #Valid|                 F0                        F1
Name     Offset   bits  |   Chan1 |   Chan2 |   Chan3 |   Chan4 |       
Phase Mod  0x00    16   |  0x0000 |  0x0000 |  0x0000 |  0x0000 |  0x0000  
Scale Fac  0x02    08   |    0x00 |    0x00 |    0x00 |    0x00 |    0x00  
Buff  Fac  0x04    10   |   0x001 |   0x001 |   0x001 |   0x001 |   0x001  
IQDM  Len  0x06    11   |   0x000 |   0x000 |   0x000 |   0x000 |   0x000  
IQDM Addr  0x08    11   |   0x7ff |   0x7ff |   0x7ff |   0x7ff |   0x7ff  
I,Q Idle 0x1ffc    10   |    512,0|    0,511|    512,0|    0,511|    0,511

Bit Pattern  registers
Reg      Reg    Reg
Name     Offset Value  Ch1  Ch2  Ch3  Ch4   F1  Freq 
EndSweep 0x004b  0x3f    1    1    1    1    1    1   0=stop at Nth 1=jump to idle
Gate     0x004c 0x000    0    0    0    0    0         0=disable 1=enable 2=invert 3=always on
AncCntrl 0x0050 0x000    0    0    0    0              0=NIM input 1=NIM output
AncIn    0x004e 0x000    0    0    0    0              0=Off 1=On
AncOut   0x004f 0x000    0    0    0    0              0=Off 1=On

Other registers
Reg         Reg     Reg
Name        Offset  Value
PreGatedOut 0x0051 0x000 RF  PreGated port: F0 ch1 selected
GatedOut    0x0052 0x000 RF     Gated port: F0 ch1 selected
RFtripThr   0x0053 0x0080 Voltage trip at 2.000000 Volts
RFtrip      0x0054 0x0000 1=tripped
Mode        0x0055 0x0000 0=BNMR 1=BNQR
FPGA Temp   0x0058 0x2040 Temperature 64 degrees C (approx) 

Enter command (A-Z a-z) X to exit?  

PPG

The test program vppg_interactive_32bit.exe tests the PulseBlaster PPG module.

This is a menu-driven program. It can be run (with caution) for debugging at the same time as the DAQ, as it does not automatically do any initialization. For example, it can be used to check whether the PPG is running.

example

$ vppg_interactive_32bit.exe
vmic_mmap: Mapped VME AM 0x09 addr 0x00000000 size 0x00ffffff at address 0x20100000
mvme_open:
Bus handle              = 0x3
DMA handle              = 0x870a3e8
DMA area size           = 1048576 bytes
DMA    physical address = 0xb6655000
vmic_mmap: Mapped VME AM 0x29 addr 0x00000000 size 0x0000ffff at address 0x27ff0000
Pulseblaster IS reset
Pulseblaster NOT running 
Pulseblaster is NOT stopped 
VME polarization source control bits = 0x0
VME Polarization control: OFF 
External clock IS present 
External  Polarization control: OFF 
External trigger is DISABLED
External trigger register = 0x1
       PPG function support
A Init               B Load
C StopSequencer      E StartSequencer
F EnableExtTrig      G DisableExtTrig
H ExtTrigRegRead     I StatusRead
J PolmskRead         K PolmskWrite
L RegWrite           M RegRead
N StartpatternWrite  O PolzSet
Q PolzRead           R PolzFlip
S PolzCtlPPG         T PolzCtlVME
U BeamOn             V BeamOff 
W BeamCtlPPG         Y BeamCtlRegRead
D debug (toggles)    P print this list
X exit 

Enter command (A-Y) X to exit?  I
Pulseblaster IS reset
Pulseblaster NOT running 
Pulseblaster is NOT stopped 
VME polarization source control bits = 0x0
VME Polarization control: OFF 
External clock IS present 
External  Polarization control: OFF 
Read back data =0x21

Enter command (A-Y) X to exit?  X

SIS3820

Note

The sis3820 must be used in non-DMA mode. The DMA mode does not work

The test program sis3820_interactive_32bit.exe tests the SIS3820 scaler.

This is a menu-driven program. It can be run (with caution) for debugging at the same time as the DAQ, as it does not automatically do any initialization. For example, it can be used to read the control/status and operation mode register.

Several test procedures are provided. For example, test1 runs a test using the internal 10MHz clock as the LNE source, then reads out the data from the FIFO.

NIMIO32 / beam simulator

The test program bnmrbeamsim_32bit.exe tests the NIMIO32 and provides a tool for testing when real beam/helicity inputs are not available.

This is a menu-driven program. It can be run (with caution) for debugging at the same time as the DAQ, as it does not automatically do any initialization. For example, it can be used to read the control/status and operation mode register.

The main menu provides a generic interface for the NIMIO32. Use the S command to enter a sub-menu of commands specific to bnmr and bnqr.

example

$ bnmrbeamsim_32bit.exe
vmic_mmap: Mapped VME AM 0x0d addr 0x00000000 size 0x00ffffff at address 0x20100000
mvme_open:
Bus handle              = 0x3
DMA handle              = 0x8df23f0
DMA area size           = 1048576 bytes
DMA    physical address = 0xb662b000

vmic_mmap: Mapped VME AM 0x3d addr 0x00000000 size 0x00ffffff at address 0x21100000
Firmware for Module 1: 0x1140317
Firmware for Module 2: 0xffffffff
Base[0]=0x100000

Enter command (A-Y) X to exit?  P
cmd=P
       NIMIO32 command list
A Read BNMR inputs       B Show BaseAddr
C Set One Output         D Set OutputBitPat
E Read OutputBitPat      F Read Firmware
G Read Input bits        H Reset Latch on Inputs
I Read OutputCntrlBits   J Read whole output word (32 bits)
K Write OutputCntrlBits  L Set Gate Delay values
M Read Gate Delay values N Pulse one output
O Read one input         Q Read one latched input
P print this list        R Reset
S bnmr simulator
X exit


Enter command (A-Y) X to exit?  S
cmd=S
BNMR Simulator - used when real signals are not available
Outputs 2,3,4 are used for the simulator.
Make sure output control bits are set so that Outputs 0-3 are regular outputs (see command 'K')
   Make the following connections:
   BEAM is controlled by output 2 (connected to input 0)
   Hel Down              output 3 (connected to input 1)
   Hel Up                output 4 (connected to input 2)

Enter simulator command (A-Y) X to exit?  P
cmd=P
 BNMR simulator command list
A Read BNMR inputs
B Beam On            C Beam Off
D Hel Up             E Hel Down
F Hel Up and Down    G Hel neither
H Read Outputs       I hel_read_io
S Simulate changing hel
P Print command list Q Quit