TACTIC

TACTIC

• computer: daq18.triumf.ca
• midas: https://daq18.triumf.ca
• elog: https://elog.triumf.ca/Tactic/General/
• digitizers: 2x V1740 via CAEN USB interface
• rebuild fetactic.exe

cd /home/tactic/newTACTIC/v1740mt
make
ls -l fetactic.exe

• rebuild analyzer

cd /home/tactic/newTACTIC/manalyzer
make
ls -l ./tacticana.exe

• trigger and v1740 connections:

- both v1740 trigger outputs go to logic OR. pulser goes into the same OR
- from this OR, they fan out to v1740 trigger inputs
- analog output of first v1740 provides the run gate (via polarity inverting kludge)
- analog output of second v1740 provides a "buffer-half-full" trigger veto (via polarity inverting kludge)

• trigger notes: (KO 7-oct-2024)

- trigger signal is not synched with the v1740 clock, actual "adc stop" time will have a jitter between the two v1740 of 1-2 clock periods
- actual event time jitter between the two v1740 is around 2 clock (from looking at event timestamps).
- because v1740 busy are not synched (and busy from first v1740 is missing), the second v1740 often has extra events. sometimes the first v1740 has an extra event. fetactic.exe has workaround against this, mostly by dropping mismatched data.