VME-PPG32

VME-PPG32 - pulse pattern generator VME FPGA board

References

• [1] VME-PPG32 (REA 198) project page on edev.triumf.ca
• [2] Rev0 board schematics
• [3] Svn repository for VME-PPG32 firmware

General characteristics

Available hardware

• Altera cyclone 3 FPGA: EP3C40Q240C8
• Serial flash for FPGA configuration: Altera EPCS16
• VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
• 32 NIM outputs
• 4 NIM inputs
• 32 "NIM output" LEDs
• 4 "NIM input" LEDs
• 1 "VME access" LED
• 2 output serial DAC: AD5439YRUZ

Firmware functions

TBW

Firmware revisions

To find out the current firmware revision, read VME register 0, i.e. run "test_VMENIMIO32_gef.exe --addr 0xN00000 --read 0".

To write Cyclone 1 FPGA firmware into the flash memory, use a JTAG programmer or a VME programmer: "srunner_vme_gef.exe -program -64 ~/daq/VME-NIMIO32/VME-NIMIO32/VME-NIMIO32/VME-NIMIO32.pof 0xN00020", where "N" is the A24 VME base address.

To reboot the Cyclone 1 FPGA into the new firmware, run "test_VMENIMIO32_gef.exe --addr 0xN00000 --read 0 --write 1 2 --read 0 --sleep 1 --read 0", where "N" is the A24 VME base address. This requires firmware 0x01100810 or newer and the "fpga-reset" hardware modification.

Firmware for the main FPGA:

• firmware sources [[4]]
• 0x4bcf5aef - [[5]]

Firmware for the VME address decoder (same as VME-NIMIO32):

• firmware sources [[6]]
• board Rev0 [[7]]
• board Rev1 [[8]]

Manual

VME interface

Firmware 0x01100810 implements VME A24/D32 access only. A24 addresses 0x00N0xxxx are decoded, where "N" is the A24 base address set by rotary switch SW3 "ADDRESS 20-23". Rotary switches SW1 and SW2 should be set to "0".

VME accessible registers are listed in the table below. VME address offsets are register numbers multiplied by 4, i.e. CSR register 1 is at address 0x00N00004. Flash programmer register 8 is at 0x00N00020 (use this address with srunner_vme flash programmer).

Registers

Number	Name	Access	FwRev	Description
0	FwRev	RO		Firmware revision
1	CSR	RW	TBW	TBW

SOFTWARE

test_VMENIMIO32.exe

Command line switches:

• --addr 0x00N00000 - module A24 base address, N is the setting of rotary switch SW3 "ADDRESS 20-23"
• --read MMM - read register MMM, i.e. "--read 0" reads the firmware revision
• --write MMM VVV - write value VVV into register MMM, i.e. "--write 1 0" writes 0 to the CSR
• --readscalers - read the 32 input scalers, print scaler value, counting rate using the 20 MHz timestamp clock and counting rate using the computer clock.
• --pulsenim - pulse all NIM outputs
• --sleep SSS - sleep SSS seconds, i.e. "--sleep 1" sleeps for 1 second.
• --readtsc - example reading TSC register
• --readtsc4 - example reading and decoding the TSC4 data, programming TSC4 routing

Board modifications

Rev0 modifications

• none

Rev1 modifications

• none

K.O.