VME-NEW-IO: Difference between revisions
		
		
		
		
		
		Jump to navigation
		Jump to search
		
				
		
		
	
| m (New page: = Use cases of existing VME-NIMIO32 board =  aaa  = AAA =) | |||
| Line 1: | Line 1: | ||
| = Use cases of existing VME-NIMIO32 board = | = Use cases of existing VME-NIMIO32 board = | ||
| Specs of the existing board: | |||
| * 6U VME single width | |||
| * VME A32/D32, firmware implements A24/D32 single word and A24/BLT32 block transfers. There is no VME drivers on the A-lines so cannot do MBLT64, 2eVME, 2eSST. | |||
| * Altera Cyclone1 FPGA, 6k LE, 180 i/o pins, 100-200 MHz clock speeds. | |||
| * 16 NIM inputs (convertable to TTL), LEMO connectors | |||
| * 16 ECL/LVDS inputs, LeCroy 4616 compatible ECL ribbon cable connector | |||
| * 16 NIM outputs, LEMO connectors | |||
| * 32 LEDs (one for each LEMO connector) | |||
| Main uses of the IO32 board have been: | |||
| * trigger latch, trigger timestamp and busy logic daq synchronization (LXe, IRIS, M11 test beams, DRAGON, ALPHA, EMMA, TRINAT, TREK, PTF, S1249 muonium production test, etc) | |||
| * scalers (16 ch, up to 200 MHz, deadtimeless) (most users) | |||
| * timestamp counter (4 ch, 100 MHz) (TRINAT, etc) | |||
| * 40MHz V1190 and 20MHz VF48 clock generator and trigger synchronization (LXe, IRIS, TREK, S1249, etc) | |||
| * V792 ADC gate and delay generator (M11 test beams, DRAGON, TRINAT, S1249, etc) | |||
| * custom trigger logic (M11 test beams, DRAGON, ALPHA, TRINAT, S1249) | |||
| * clock and trigger synchronization between 2 VME crates (DRAGON) and 2 IO32 modules (TRINAT) | |||
| * in addition there is a 1ns-time-bin delay-line TDC (never used) | |||
| Number of I/Os used: | |||
| * ALPHA2 Si detector DAQ (CERN) - 16 NIM in, 16 NIM out | |||
| = AAA = | = AAA = | ||
Revision as of 00:46, 10 March 2016
Use cases of existing VME-NIMIO32 board
Specs of the existing board:
- 6U VME single width
- VME A32/D32, firmware implements A24/D32 single word and A24/BLT32 block transfers. There is no VME drivers on the A-lines so cannot do MBLT64, 2eVME, 2eSST.
- Altera Cyclone1 FPGA, 6k LE, 180 i/o pins, 100-200 MHz clock speeds.
- 16 NIM inputs (convertable to TTL), LEMO connectors
- 16 ECL/LVDS inputs, LeCroy 4616 compatible ECL ribbon cable connector
- 16 NIM outputs, LEMO connectors
- 32 LEDs (one for each LEMO connector)
Main uses of the IO32 board have been:
- trigger latch, trigger timestamp and busy logic daq synchronization (LXe, IRIS, M11 test beams, DRAGON, ALPHA, EMMA, TRINAT, TREK, PTF, S1249 muonium production test, etc)
- scalers (16 ch, up to 200 MHz, deadtimeless) (most users)
- timestamp counter (4 ch, 100 MHz) (TRINAT, etc)
- 40MHz V1190 and 20MHz VF48 clock generator and trigger synchronization (LXe, IRIS, TREK, S1249, etc)
- V792 ADC gate and delay generator (M11 test beams, DRAGON, TRINAT, S1249, etc)
- custom trigger logic (M11 test beams, DRAGON, ALPHA, TRINAT, S1249)
- clock and trigger synchronization between 2 VME crates (DRAGON) and 2 IO32 modules (TRINAT)
- in addition there is a 1ns-time-bin delay-line TDC (never used)
Number of I/Os used:
- ALPHA2 Si detector DAQ (CERN) - 16 NIM in, 16 NIM out