DS-DM: Difference between revisions
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* jtag chain: arm_dap_0 0x5BA00477, xczu4_1 0x04721093 | * jtag chain: arm_dap_0 0x5BA00477, xczu4_1 0x04721093 | ||
* Xilinx® Zynq Ultrascale+™ MPSoC | * Mercury+ XU8 module: ME-XU8-4CG-1E-D11E-R2.1 | ||
** Xilinx® Zynq Ultrascale+™ MPSoC XCZU4CG-1FBVB900E | |||
** DDR4 ECC SDRAM (PS) 2 GB | |||
** DDR4 SDRAM (PL) 1GB | |||
= Board schematics = | = Board schematics = | ||
Revision as of 16:15, 1 September 2022
DS-DM
DarkSide-20k Global and Crate Data Manager board (GDM and CDM).
Global Data Manager (GDM):
- clock distribution to CDM boards (including GPS/atomic clock source)
- collection of trigger data from CDM boards, processing and distribution of trigger decision to CDM boards
- run control
Crate Data Manager (CDM):
- clock distribution from GDM to CAEN digitizers
- receive trigger data from CAEN digitizers
- send trigger data to GDM
- run control and dead time control
Links
edev links:
- https://edev-group.triumf.ca/fw/exp/darkside/gcdm
- https://edev-group.triumf.ca/hw/vme/dark-side-20k-data-manager-card/rev0
- https://edev-group.triumf.ca/hw/vme/dark-side-20k-data-manager-card/rev0/-/blob/master/Altium/Project%20Outputs%20for%20DS-DM-Rev0/SCH-DS-xDM-Rev0.PDF
- https://edev-group.triumf.ca/hw/vme/dark-side-20k-data-manager-card/rev0/-/blob/master/Testing/Clk3_XO_125_to_fpgaIN_recoveredMGTclk_to_IN2_Si5394-RevA-Project.slabtimeproj
Xilinx links:
- Platform Cable USB II: https://docs.xilinx.com/v/u/en-US/ds593
Enclustra links:
Onboard hardware
- jtag chain: arm_dap_0 0x5BA00477, xczu4_1 0x04721093
- Mercury+ XU8 module: ME-XU8-4CG-1E-D11E-R2.1
- Xilinx® Zynq Ultrascale+™ MPSoC XCZU4CG-1FBVB900E
- DDR4 ECC SDRAM (PS) 2 GB
- DDR4 SDRAM (PL) 1GB
Board schematics
Install Xilinx tools
- install Vivado 2020.2
login at https://www.xilinx.com/myprofile.html go to "Downloads" go to archive, find 2020.2 download Xilinx_Unified_2020.2_1118_1232_Lin64.bin sh ./Xilinx_Unified_2020.2_1118_1232_Lin64.bin banner window should open with spinner "downloading installation data" "a newer version is available" -> say "continue" next "select install type" window: provide email and password, select "download image" select directory /home/olchansk/Xilinx/Downloads/2020.2\ select "linux" and "full image" next download summary: space required 38.52 Gbytes download installation progress downloading spinner, 16 M/s 47 minutes... "download image has been created successfully". Ok. check contents of /home/olchansk/Xilinx/Downloads/2020.2 ls -l /home/olchansk/Xilinx/Downloads/2020.2 total 67 drwxr-xr-x 2 olchansk users 9 Sep 1 16:22 bin drwxr-xr-x 3 olchansk users 15 Sep 1 16:23 data drwxr-xr-x 4 olchansk users 4 Sep 1 16:22 lib drwxr-xr-x 2 olchansk users 644 Sep 1 16:22 payload drwxr-xr-x 2 olchansk users 7 Sep 1 16:22 scripts drwxr-xr-x 4 olchansk users 4 Sep 1 16:22 tps -rwxr-xr-x 1 olchansk users 3256 Nov 18 2020 xsetup daq13:2020.2$ ./xsetup spinned loading installation data xilinx design tools 2022.1 now available -> say continue "welcome" -> next "select product" -> vivado -> next -> vivado hl system edition -> next select devices: only zynq ultrascale+ mpsoc -> next select destination: /opt/Xilinx (as root, mkdir /opt/Xilinx, chmod olchansk.users /opt/Xilinx) install ...
JTAG server
localhost:3121
Build firmware
- git clone git@edev-group.triumf.ca:fw/exp/darkside/gcdm.git
- Makefile change VIVADO_SETTINGS_SCRIPT := /opt/Xilinx/Vivado/2022.1/settings64.sh
- . /opt/Xilinx/Vivado/2022.1/settings64.sh
- make clean
- make all_from_scratch
ZZZ
ZZZ