Revision as of 14:49, 6 December 2016

CriticalLink MityARM

Getting Started

For general information on the Critical Link ARM SOM, start here MityARM
Follow instruction at MityARM to login into Linux
Build and install GPMC-CAMAC drivers
Load the FPGA firmware
Run CAMAC tests

BOOTCONFIG

BOOTCONFIG settings:

CL eval board:
- BOOTCONFIG[0..11] are SYSBOOT[0..11]
- boot from SD: all open, [3] closed
- boot from on-SoM NAND: all open, close [2], [3], [8], [9], [10], [11] (6 jumpers)

CAMAC board Rev1:
- top-to-bottom: B0..4,G0..5,R0 correspond to LCD_DATA[0..11] are SYSBOOT[0..11]
- boot from SD: all open, B3 closed
- boot from on-SoM NAND: all open, close B2, B3, G3, G4, G5, R0 (6 jumpers)

NOTES:

boot from EMAC1 requires PHY connection to RGMII1, CLeval and CAMAC boards connected PHY to RGMII2.

SYSBOOT modes: http://ladd00.triumf.ca/~olchansk/MityARM/Docs/spruh73g.pdf table 26-7

SYSBOOT[4..0]
00000 - reserved
00001 - UART0
00010 - UART0
00011 - UART0
00100 - UART0
00101 - UART0
00110 - EMAC1, SYSBOOT[7..6]: 00=MII, 01=RMII, 10=reserved, 11=RGMII
00111 - EMAC1
01000 - EMAC1
01001 - EMAC1
01010 - EMAC1
01011 - USB0
01100 - USB0
01101 - USB0
01110 - reserved
01111 - fast external boot
10000 - XIP
10001 - XIP
10010 - NAND
10011 - NAND
10100 - NAND
10101 - NAND-I2C
10110 - SPI0
10111 - MMC0 <---- default (boot from SD flash) - other bits - don't care
11000 - SPI0
11001 - SPI0
11010 - XIP
11011 - XIP
11100 - MMC1
11101 - reserved
11110 - reserved
11111 - fast external boot

GPMC interface

0x8 = CS0 - on-SoM NAND flash (boot loader)
0x9 = CS1 - not used
0xa = CS2 - not used
0xb = CS3 - CAMAC interface

./gpmc 0x0a000000 0x12ff5678

CAMAC interface

General information:

CAMAC interface responds to GPMC CS3
the host CPU should always issue 32-bit read and write cycles on even addresses (last 2 bits of address set to 0)
address bits 15..12 address the FPGA GPMC registers (4 bits, 16 registers)
remaining address bits are used for encoding CAMAC operations
all GPMC registers are 32-bit wide

LEDs (Rev1)

                       ----
gpmc            0x0008 |OO| 0x0040 ACB RQ (lemo output "request")
busy            0x0010 |OO| 0x0080 grant_in (lemo input)
ACB RQ          0x0020 |OO| 0x0100 ACB RI
-----------------------------------------------------

Front Panel LEMO connectors (Rev1)

top
|
| busy out
| inhibit in
| grant in
| grant out
| request out
|
bottom

Install the software

Get and build the software tools

ssh daquser@armdaq02
mkdir packages
cd packages
git clone https://bitbucket.org/ttriumfdaq/gpmc-camac.git
cd gpmc-camac
make CROSS_COMPILE=
ls -l gpmc camac srunner_gpmc

-bash-4.2$ ls -l gpmc camac srunner_gpmc
-rwxrwxr-x 1 daquser users 668337 Dec  6 22:43 camac
-rwxrwxr-x 1 daquser users 654454 Dec  6 22:43 gpmc
-rwxrwxr-x 1 daquser users 692961 Dec  6 22:43 srunner_gpmc
-bash-4.2$

build kernel driver

cd gpmc-camac/kernel-module
make CROSS_COMPILE=
ls -l gpmc_camac_module.ko

-bash-4.2$ ls -l gpmc_camac_module.ko
-rw-rw-r-- 1 daquser users 93154 Dec  6 22:48 gpmc_camac_module.ko
-bash-4.2$

ssh ladd00 cd /home/olchansk/daq/CAMAC-Crate-Controller/edevel00195/CAMAC-Crate-Controller/LINUX/kernel-module make make install

install kernel driver

(follow instructions printed by "make install")

add this to /etc/rc.local:

# enable GPMC pins

echo 30 >> /sys/kernel/debug/omap_mux/gpmc_ad8     ### AD pin
echo 30 >> /sys/kernel/debug/omap_mux/gpmc_ad9     ### AD pin
echo 30 >> /sys/kernel/debug/omap_mux/gpmc_ad10     ### AD pin
echo 30 >> /sys/kernel/debug/omap_mux/gpmc_ad11     ### AD pin
echo 30 >> /sys/kernel/debug/omap_mux/gpmc_ad12     ### AD pin
echo 30 >> /sys/kernel/debug/omap_mux/gpmc_ad13     ### AD pin
echo 30 >> /sys/kernel/debug/omap_mux/gpmc_ad14     ### AD pin
echo 30 >> /sys/kernel/debug/omap_mux/gpmc_ad15     ### AD pin

echo 8 >> /sys/kernel/debug/omap_mux/gpmc_csn1     ### CS pin
echo 8 >> /sys/kernel/debug/omap_mux/gpmc_csn2     ### CS pin
echo 8 >> /sys/kernel/debug/omap_mux/gpmc_csn3     ### CS pin

echo 8 >> /sys/kernel/debug/omap_mux/gpmc_ben1     ### output pin
echo 30 >> /sys/kernel/debug/omap_mux/gpmc_clk     ### CLK has to be configured as in "input" pin

Firmware update

test the active serial flash programmer interface

$ ./srunner_gpmc -id -16 /dev/null

Operation: Identify EPCS Device
bb_open!
Info: Found GPMC 0xABCD FlashProgrammer interface.

Info: Silicon ID - 0x14 
Info: Serial Configuration Device - EPCS16

Operation Completed!!!

write pof file to flash memory

$ ./srunner_gpmc -program -16 CAMAC_Crat_Controller.pof

Operation: Programming EPCS
Info: Programming file: "CAMAC_Crat_Controller.pof" opened.
Info: File size: 2097359 bytes.
Skipping POF file header: start of data at 154, file size 2097359, remain 2097205, modulo 1024 = 53
Final file size 2097152
bb_open!
Info: Found GPMC 0xABCD FlashProgrammer interface.

Info: Silicon ID - 0x14 
Info: Serial Configuration Device - EPCS16
Info: Erasing...
....................Info: Erase Done
Info: Start programming process.

Info: Programming 8192 pages...
Info: Programming successful
bb_close!

Operation Completed!!!

reboot the FPGA

lxdaq30:LINUX$ ./camac --reboot
CAMAC firmware: 0x14120407
rebooting FPGA...
CAMAC firmware: 0x14120711
lxdaq30:LINUX$

Register 1 - command

Write-only 32 bit register:

command 1: CMD_reset: 0x
command 2: CMD_reconfigure
command 3: CMD_TestMode
command 4: CMD_Zero
command 5: CMD_Clear
command 6: CMD_Inhibit
command 7: CMD_WriteLED: 0xXXXX0007 -> write 0xXXXX to the LED bus

Register 2 - test read/write register

32-bit read/write register for testing GPMC bus communications

Register 3 - FPGA flash programmer

active-serial flash programmer interface (see srunner, srunner_vme and srunner_gpmc).

Register 4 and 5 - CAMAC command, write data and read data

A write cycle to the GPMC bus carries 16 bits of address and 32 bits of data:

Address 16 bits (Quartus cmd_A[15..0])
----
15..12 - GPMC register address 
--
11 - not used
10 - not used
9 - not used
8..4 - CAMAC N[4..0]
--
3 - CAMAC F[4]
2 - CAMAC_start - set this bit to 1 to trigger a CAMAC operation. Value 0 is for testing the communications without running the CAMAC sequencer.
1 - not accessible
0 - not accessible
----

Data 32 bits: (Quartus cmd_D[31..0])
----
31..28 - CAMAC F[3..0]. (CAMAC F[4] is cmd_A[3])
27..24 - CAMAC A[3..0]
--
23..0 - CAMAC write lines W[24..1]
----

To verify correct data transmission on the GPMC bus and correct latching of the data in the CAMAC part of the FPGA, the 32 bits of data can be read back through register 4 and the 16 bits of address can be read through the low 16 bits of register 5. Reading from these registers is not necessary for operating CAMAC cycles.

Register 6 - CAMAC status and read data

Read-only 32 bit register:

31 - not used
30 - not used
29 - not used
28 - BUSY_OUT
--
27 - BUSY
26 - set to 1 when CAMAC cycle is finished and new data is ready
25 - CMD_ACCPT
24 - RESPONSE
--
23..0 - CAMAC read data[24..1]

Register 7 - CAMAC LAM and interface status

Read-only 32-bit register:

31 - EXT_BUSY
30 - EXT_INHIBIT
29 - EXT_GRANT_IN
28 - EXT_GRANT_OUT
--
27 - ACB ACL
26 - ACB RI
25 - ACB RQ
24 - not used
--
23..0 - CAMAC LAM from slots 24..1

Software commands

./gpmc # initialize the GPMC interface
./gpmc 0x0b000000 # read firmware revision
./gpmc 0x0b001000 2 # reconfigure the fpga
./srunner_gpmc -id -64 /dev/null # use the flash programmer to read the flash chip identity
./srunner_gpmc -program -16 ../QUARTUS/output_files/CAMAC_Crat_Controller.pof # write POF file into the flash (remember to do an FPGA reconfigure to reboot into the new firmware)
./gpmc 0x0b001000 0x01f80007 # write to the LEDs
./gpmc 0x0b0040ac 0x00123456 # run some camac cycle
./gpmc 0x0b001000 0x80000003 # enable test mode
./gpmc 0x0b004174 0x00123456 # read from slot 23 - "manual input register"
./gpmc 0x0b00416c 0x00000000 # write to slot 22 - dataway display
./gpmc 0x0b00416c 0x00ffffff # write to slot 22 - dataway display
./gpmc 0x0b006000 # read CAMAC read data and status
./gpmc 0x0a00012c # reconfigure FPGA thorugh the CS2 line

./gpmc # initialize the GPMC interface
./camac # read firmware revision, etc
./camac --reboot # reboot the FPGA
./camac --scan # scan CAMAC crate
./camac --gpmctest1 # test GPMC bus integrity - read/write test
./camac --gpmctest2 # test GPMC bus integrity - both data and address read/write test
./camac --testleds # test front panel LEDs - they should blink at 1Hz
./camac --testlemo # test front panel LEMOs - the voltages should alternate between 0V and ???V at 1Hz
./camac r # read CAMAC register r, e.g. \"./camac 0\" to read register 0 - firmware revision
./camac w v # write CAMAC register w with value v, e.g. \"./camac 2 0xabcd\" to write 0xabcd to test register 2
./camac n f a w # run a CAMAC cycle with given N, F, A, write data W

List of on-board hardware

on SoM: http://www.mitydsp.com/products-services/cpu-engines/mityarm-3359 http://ladd00.triumf.ca/~olchansk/MityARM/Docs/MityARM-335x_Datasheet.pdf
- TI 3354/3359 CPU: http://ladd00.triumf.ca/~olchansk/MityARM/Docs/spruh73g.pdf
- 256MB or 512MB NAND flash: GPMC CS#0, 8-bit wide
- 8MB serial NOR flash: SPI1 interface
- configuration EPROM: I2C1 interface (module serial number, ethernet MAC, etc)
- 256MB DDR2 or 512MB DDR3 RAM, 16-bit interface, 300 or 400MHz
- power management chip tps65910: I2C1, I2C2 interface, http://ladd00.triumf.ca/~olchansk/MityARM/Docs/tps65910.pdf
on CAMAC board:
- Micrel KSZ9021RL GigE ethernet PHY: Davinci_MDIO interface http://ladd00.triumf.ca/~olchansk/MityARM/Docs/ksz9021rl-rn_ds.pdf
- Altera Cyclone4 FPGA EP4CE30F23: GPMC bus

End

AAA

MityCAMAC: Difference between revisions

Revision as of 14:49, 6 December 2016

Contents

CriticalLink MityARM

Getting Started

BOOTCONFIG

GPMC interface

CAMAC interface

LEDs (Rev1)

Front Panel LEMO connectors (Rev1)

Install the software

Firmware update

Register 1 - command

Register 2 - test read/write register

Register 3 - FPGA flash programmer

Register 4 and 5 - CAMAC command, write data and read data

Register 6 - CAMAC status and read data

Register 7 - CAMAC LAM and interface status

Software commands

List of on-board hardware

End

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MityCAMAC: Difference between revisions

Revision as of 14:49, 6 December 2016

CriticalLink MityARM

Getting Started

BOOTCONFIG

GPMC interface

CAMAC interface

LEDs (Rev1)

Front Panel LEMO connectors (Rev1)

Install the software

Firmware update

Register 1 - command

Register 2 - test read/write register

Register 3 - FPGA flash programmer

Register 4 and 5 - CAMAC command, write data and read data

Register 6 - CAMAC status and read data

Register 7 - CAMAC LAM and interface status

Software commands

List of on-board hardware

End

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