DL-TDC: Difference between revisions

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6.009 GPIO_0_9 dl|WideOr1|combout add 6 -> 6 = 10.189 sub 2
6.009 GPIO_0_9 dl|WideOr1|combout add 6 -> 6 = 10.189 sub 2
5.917 GPIO_0_0 dl|WideOr1|combout add 6
5.917 GPIO_0_0 dl|WideOr1|combout add 6
</pre>
= Cyclone-1 =
<pre>
report_path -to [get_keepers {TDC6:tdc|TDC2ef:a|TDC2e:tdc|TDC1:le|TDClcell40:phase|TDClcell10:d|latch[9]}] -npaths 1 -panel_name {Report Path}
</pre>
<pre>
with set_max_delay -to {TDC6:tdc|TDC2ef:*|TDC2e:tdc|TDC1:*|TDClcell40:phase|TDClcell10:d|latch[9]} 10.0
13.237 ns
13.237 13.237 data path 1
0.000   0.000 1 LC_X3_Y17_N0 TS_DFF[0] 1
0.000   0.000 RR CELL 10 LC_X3_Y17_N0 TS_DFF[0]|regout 2
1.285   1.285 RR IC 2 LC_X8_Y13_N0 tdc|a|tdc|le|phase|a|latch[0]|datad 3
1.373   0.088 RR CELL 1 LC_X8_Y13_N0 tdc|a|tdc|le|phase|a|latch[0]|combout 4
1.513   0.140 RR IC 2 LC_X8_Y13_N1 tdc|a|tdc|le|phase|a|latch[1]|datad 5
1.601   0.088 RR CELL 1 LC_X8_Y13_N1 tdc|a|tdc|le|phase|a|latch[1]|combout 6
1.741   0.140 RR IC 2 LC_X8_Y13_N2 tdc|a|tdc|le|phase|a|latch[2]|datad 7
1.829   0.088 RR CELL 1 LC_X8_Y13_N2 tdc|a|tdc|le|phase|a|latch[2]|combout 8
1.969   0.140 RR IC 2 LC_X8_Y13_N3 tdc|a|tdc|le|phase|a|latch[3]|datad 9
2.057   0.088 RR CELL 1 LC_X8_Y13_N3 tdc|a|tdc|le|phase|a|latch[3]|combout 10
2.197   0.140 RR IC 2 LC_X8_Y13_N4 tdc|a|tdc|le|phase|a|latch[4]|datad 11
2.285   0.088 RR CELL 1 LC_X8_Y13_N4 tdc|a|tdc|le|phase|a|latch[4]|combout 12
2.547   0.262 RR IC 2 LC_X8_Y13_N5 tdc|a|tdc|le|phase|a|latch[5]|datad 13
2.635   0.088 RR CELL 1 LC_X8_Y13_N5 tdc|a|tdc|le|phase|a|latch[5]|combout 14
2.775   0.140 RR IC 2 LC_X8_Y13_N6 tdc|a|tdc|le|phase|a|latch[6]|datad 15
2.863   0.088 RR CELL 1 LC_X8_Y13_N6 tdc|a|tdc|le|phase|a|latch[6]|combout 16
3.003   0.140 RR IC 2 LC_X8_Y13_N7 tdc|a|tdc|le|phase|a|latch[7]|datad 17
3.091   0.088 RR CELL 1 LC_X8_Y13_N7 tdc|a|tdc|le|phase|a|latch[7]|combout 18
3.231   0.140 RR IC 2 LC_X8_Y13_N8 tdc|a|tdc|le|phase|a|latch[8]|datad 19
3.319   0.088 RR CELL 1 LC_X8_Y13_N8 tdc|a|tdc|le|phase|a|latch[8]|combout 20
3.459   0.140 RR IC 2 LC_X8_Y13_N9 tdc|a|tdc|le|phase|a|latch[9]|datad 21
3.547   0.088 RR CELL 1 LC_X8_Y13_N9 tdc|a|tdc|le|phase|a|latch[9]|combout 22
4.074   0.527 RR IC 2 LC_X9_Y13_N1 tdc|a|tdc|le|phase|b|latch[0]|datad 23
4.162   0.088 RR CELL 1 LC_X9_Y13_N1 tdc|a|tdc|le|phase|b|latch[0]|combout 24
4.302   0.140 RR IC 2 LC_X9_Y13_N2 tdc|a|tdc|le|phase|b|latch[1]|datad 25
4.390   0.088 RR CELL 1 LC_X9_Y13_N2 tdc|a|tdc|le|phase|b|latch[1]|combout 26
4.530   0.140 RR IC 2 LC_X9_Y13_N3 tdc|a|tdc|le|phase|b|latch[2]|datad 27
4.618   0.088 RR CELL 1 LC_X9_Y13_N3 tdc|a|tdc|le|phase|b|latch[2]|combout 28
4.758   0.140 RR IC 2 LC_X9_Y13_N4 tdc|a|tdc|le|phase|b|latch[3]|datad 29
4.846   0.088 RR CELL 1 LC_X9_Y13_N4 tdc|a|tdc|le|phase|b|latch[3]|combout 30
5.108   0.262 RR IC 2 LC_X9_Y13_N5 tdc|a|tdc|le|phase|b|latch[4]|datad 31
5.196   0.088 RR CELL 1 LC_X9_Y13_N5 tdc|a|tdc|le|phase|b|latch[4]|combout 32
5.336   0.140 RR IC 2 LC_X9_Y13_N6 tdc|a|tdc|le|phase|b|latch[5]|datad 33
5.424   0.088 RR CELL 1 LC_X9_Y13_N6 tdc|a|tdc|le|phase|b|latch[5]|combout 34
5.564   0.140 RR IC 2 LC_X9_Y13_N7 tdc|a|tdc|le|phase|b|latch[6]|datad 35
5.652   0.088 RR CELL 1 LC_X9_Y13_N7 tdc|a|tdc|le|phase|b|latch[6]|combout 36
5.792   0.140 RR IC 2 LC_X9_Y13_N8 tdc|a|tdc|le|phase|b|latch[7]|datad 37
5.880   0.088 RR CELL 1 LC_X9_Y13_N8 tdc|a|tdc|le|phase|b|latch[7]|combout 38
6.218   0.338 RR IC 2 LC_X9_Y13_N0 tdc|a|tdc|le|phase|b|latch[8]|datac 39
6.443   0.225 RR CELL 1 LC_X9_Y13_N0 tdc|a|tdc|le|phase|b|latch[8]|combout 40
6.762   0.319 RR IC 2 LC_X9_Y13_N9 tdc|a|tdc|le|phase|b|latch[9]|datad 41
6.850   0.088 RR CELL 1 LC_X9_Y13_N9 tdc|a|tdc|le|phase|b|latch[9]|combout 42
7.767   0.917 RR IC 2 LC_X8_Y14_N0 tdc|a|tdc|le|phase|c|latch[0]|datad 43
7.855   0.088 RR CELL 1 LC_X8_Y14_N0 tdc|a|tdc|le|phase|c|latch[0]|combout 44
7.995   0.140 RR IC 2 LC_X8_Y14_N1 tdc|a|tdc|le|phase|c|latch[1]|datad 45
8.083   0.088 RR CELL 1 LC_X8_Y14_N1 tdc|a|tdc|le|phase|c|latch[1]|combout 46
8.223   0.140 RR IC 2 LC_X8_Y14_N2 tdc|a|tdc|le|phase|c|latch[2]|datad 47
8.311   0.088 RR CELL 1 LC_X8_Y14_N2 tdc|a|tdc|le|phase|c|latch[2]|combout 48
8.451   0.140 RR IC 2 LC_X8_Y14_N3 tdc|a|tdc|le|phase|c|latch[3]|datad 49
8.539   0.088 RR CELL 1 LC_X8_Y14_N3 tdc|a|tdc|le|phase|c|latch[3]|combout 50
8.679   0.140 RR IC 2 LC_X8_Y14_N4 tdc|a|tdc|le|phase|c|latch[4]|datad 51
8.767   0.088 RR CELL 1 LC_X8_Y14_N4 tdc|a|tdc|le|phase|c|latch[4]|combout 52
9.029   0.262 RR IC 2 LC_X8_Y14_N5 tdc|a|tdc|le|phase|c|latch[5]|datad 53
9.117   0.088 RR CELL 1 LC_X8_Y14_N5 tdc|a|tdc|le|phase|c|latch[5]|combout 54
9.257   0.140 RR IC 2 LC_X8_Y14_N6 tdc|a|tdc|le|phase|c|latch[6]|datad 55
9.345   0.088 RR CELL 1 LC_X8_Y14_N6 tdc|a|tdc|le|phase|c|latch[6]|combout 56
9.485   0.140 RR IC 2 LC_X8_Y14_N7 tdc|a|tdc|le|phase|c|latch[7]|datad 57
9.573   0.088 RR CELL 1 LC_X8_Y14_N7 tdc|a|tdc|le|phase|c|latch[7]|combout 58
9.713   0.140 RR IC 2 LC_X8_Y14_N8 tdc|a|tdc|le|phase|c|latch[8]|datad 59
9.801   0.088 RR CELL 1 LC_X8_Y14_N8 tdc|a|tdc|le|phase|c|latch[8]|combout 60
9.941   0.140 RR IC 2 LC_X8_Y14_N9 tdc|a|tdc|le|phase|c|latch[9]|datad 61
10.029   0.088 RR CELL 1 LC_X8_Y14_N9 tdc|a|tdc|le|phase|c|latch[9]|combout 62
10.551   0.522 RR IC 2 LC_X9_Y14_N0 tdc|a|tdc|le|phase|d|latch[0]|datad 63
10.639   0.088 RR CELL 1 LC_X9_Y14_N0 tdc|a|tdc|le|phase|d|latch[0]|combout 64
10.779   0.140 RR IC 2 LC_X9_Y14_N1 tdc|a|tdc|le|phase|d|latch[1]|datad 65
10.867   0.088 RR CELL 1 LC_X9_Y14_N1 tdc|a|tdc|le|phase|d|latch[1]|combout 66
11.007   0.140 RR IC 2 LC_X9_Y14_N2 tdc|a|tdc|le|phase|d|latch[2]|datad 67
11.095   0.088 RR CELL 1 LC_X9_Y14_N2 tdc|a|tdc|le|phase|d|latch[2]|combout 68
11.235   0.140 RR IC 2 LC_X9_Y14_N3 tdc|a|tdc|le|phase|d|latch[3]|datad 69
11.323   0.088 RR CELL 1 LC_X9_Y14_N3 tdc|a|tdc|le|phase|d|latch[3]|combout 70
11.463   0.140 RR IC 2 LC_X9_Y14_N4 tdc|a|tdc|le|phase|d|latch[4]|datad 71
11.551   0.088 RR CELL 1 LC_X9_Y14_N4 tdc|a|tdc|le|phase|d|latch[4]|combout 72
11.813   0.262 RR IC 2 LC_X9_Y14_N5 tdc|a|tdc|le|phase|d|latch[5]|datad 73
11.901   0.088 RR CELL 1 LC_X9_Y14_N5 tdc|a|tdc|le|phase|d|latch[5]|combout 74
12.041   0.140 RR IC 2 LC_X9_Y14_N6 tdc|a|tdc|le|phase|d|latch[6]|datad 75
12.129   0.088 RR CELL 1 LC_X9_Y14_N6 tdc|a|tdc|le|phase|d|latch[6]|combout 76
12.269   0.140 RR IC 2 LC_X9_Y14_N7 tdc|a|tdc|le|phase|d|latch[7]|datad 77
12.357   0.088 RR CELL 1 LC_X9_Y14_N7 tdc|a|tdc|le|phase|d|latch[7]|combout 78
12.497   0.140 RR IC 2 LC_X9_Y14_N8 tdc|a|tdc|le|phase|d|latch[8]|datad 79
12.585   0.088 RR CELL 1 LC_X9_Y14_N8 tdc|a|tdc|le|phase|d|latch[8]|combout 80
12.725   0.140 RR IC 1 LC_X9_Y14_N9 tdc|a|tdc|le|phase|d|latch[9]|datad 81
12.813   0.088 RR CELL 1 LC_X9_Y14_N9 tdc|a|tdc|le|phase|d|latch[9]|combout 82
13.148   0.335 RR IC 1 LC_X9_Y14_N9 tdc|a|tdc|le|phase|d|latch[9]|datac 83
13.237   0.089 RR CELL 1 LC_X9_Y14_N9 TDC6:tdc|TDC2ef:a|TDC2e:tdc|TDC1:le|TDClcell40:phase|TDClcell10:d|latch[9] 84
minimal time bin: 140+88 = 228 ps
10.0 ns period / 0.228 ps = 43.9 bins
tdc6i.pdf
min bin: 0.065 0.038 0.062 0.040 ns, max bin: 1.000 0.840 0.681 0.913 ns, max phase 39 39 39 39
min bin: 0.062 0.035 0.075 0.029 ns, max bin: 0.895 1.042 0.800 0.997 ns, max phase 39 39 39 39
min bin: 0.063 0.036 0.027 0.033 ns, max bin: 0.918 0.985 0.596 0.933 ns, max phase 39 39 39 39
</pre>
<pre>
without set_max_delay
20.718 20.718 data path
0.000   0.000 1 LC_X5_Y7_N8 TS_DFF[0]
0.000   0.000 RR CELL 10 LC_X5_Y7_N8 TS_DFF[0]|regout
3.168   3.168 RR IC 2 LC_X27_Y12_N1 tdc|a|tdc|le|phase|a|latch[0]|datad
3.256   0.088 RR CELL 1 LC_X27_Y12_N1 tdc|a|tdc|le|phase|a|latch[0]|combout
3.581   0.325 RR IC 2 LC_X27_Y12_N7 tdc|a|tdc|le|phase|a|latch[1]|datad
3.669   0.088 RR CELL 1 LC_X27_Y12_N7 tdc|a|tdc|le|phase|a|latch[1]|combout
3.809   0.140 RR IC 2 LC_X27_Y12_N8 tdc|a|tdc|le|phase|a|latch[2]|datad
3.897   0.088 RR CELL 1 LC_X27_Y12_N8 tdc|a|tdc|le|phase|a|latch[2]|combout
4.037   0.140 RR IC 2 LC_X27_Y12_N9 tdc|a|tdc|le|phase|a|latch[3]|datad
4.125   0.088 RR CELL 1 LC_X27_Y12_N9 tdc|a|tdc|le|phase|a|latch[3]|combout
4.460   0.335 RR IC 2 LC_X27_Y12_N4 tdc|a|tdc|le|phase|a|latch[4]|datac
4.685   0.225 RR CELL 1 LC_X27_Y12_N4 tdc|a|tdc|le|phase|a|latch[4]|combout
4.947   0.262 RR IC 2 LC_X27_Y12_N5 tdc|a|tdc|le|phase|a|latch[5]|datad
5.035   0.088 RR CELL 1 LC_X27_Y12_N5 tdc|a|tdc|le|phase|a|latch[5]|combout
5.175   0.140 RR IC 2 LC_X27_Y12_N6 tdc|a|tdc|le|phase|a|latch[6]|datad
5.263   0.088 RR CELL 1 LC_X27_Y12_N6 tdc|a|tdc|le|phase|a|latch[6]|combout
5.588   0.325 RR IC 2 LC_X27_Y12_N3 tdc|a|tdc|le|phase|a|latch[7]|datad
5.676   0.088 RR CELL 1 LC_X27_Y12_N3 tdc|a|tdc|le|phase|a|latch[7]|combout
5.999   0.323 RR IC 2 LC_X27_Y12_N0 tdc|a|tdc|le|phase|a|latch[8]|datad
6.087   0.088 RR CELL 1 LC_X27_Y12_N0 tdc|a|tdc|le|phase|a|latch[8]|combout
6.409   0.322 RR IC 2 LC_X27_Y12_N2 tdc|a|tdc|le|phase|a|latch[9]|datad
6.497   0.088 RR CELL 1 LC_X27_Y12_N2 tdc|a|tdc|le|phase|a|latch[9]|combout
7.445   0.948 RR IC 2 LC_X27_Y11_N6 tdc|a|tdc|le|phase|b|latch[0]|datad  <------------
7.533   0.088 RR CELL 1 LC_X27_Y11_N6 tdc|a|tdc|le|phase|b|latch[0]|combout
7.860   0.327 RR IC 2 LC_X27_Y11_N5 tdc|a|tdc|le|phase|b|latch[1]|datad
7.948   0.088 RR CELL 1 LC_X27_Y11_N5 tdc|a|tdc|le|phase|b|latch[1]|combout
8.278   0.330 RR IC 2 LC_X27_Y11_N0 tdc|a|tdc|le|phase|b|latch[2]|datad
8.366   0.088 RR CELL 1 LC_X27_Y11_N0 tdc|a|tdc|le|phase|b|latch[2]|combout
8.694   0.328 RR IC 2 LC_X27_Y11_N4 tdc|a|tdc|le|phase|b|latch[3]|datad
8.782   0.088 RR CELL 1 LC_X27_Y11_N4 tdc|a|tdc|le|phase|b|latch[3]|combout
9.118   0.336 RR IC 2 LC_X27_Y11_N2 tdc|a|tdc|le|phase|b|latch[4]|datac
9.343   0.225 RR CELL 1 LC_X27_Y11_N2 tdc|a|tdc|le|phase|b|latch[4]|combout
9.483   0.140 RR IC 2 LC_X27_Y11_N3 tdc|a|tdc|le|phase|b|latch[5]|datad
9.571   0.088 RR CELL 1 LC_X27_Y11_N3 tdc|a|tdc|le|phase|b|latch[5]|combout
9.897   0.326 RR IC 2 LC_X27_Y11_N1 tdc|a|tdc|le|phase|b|latch[6]|datad
9.985   0.088 RR CELL 1 LC_X27_Y11_N1 tdc|a|tdc|le|phase|b|latch[6]|combout
10.314   0.329 RR IC 2 LC_X27_Y11_N7 tdc|a|tdc|le|phase|b|latch[7]|datad
10.402   0.088 RR CELL 1 LC_X27_Y11_N7 tdc|a|tdc|le|phase|b|latch[7]|combout
10.542   0.140 RR IC 2 LC_X27_Y11_N8 tdc|a|tdc|le|phase|b|latch[8]|datad
10.630   0.088 RR CELL 1 LC_X27_Y11_N8 tdc|a|tdc|le|phase|b|latch[8]|combout
10.770   0.140 RR IC 2 LC_X27_Y11_N9 tdc|a|tdc|le|phase|b|latch[9]|datad
10.858   0.088 RR CELL 1 LC_X27_Y11_N9 tdc|a|tdc|le|phase|b|latch[9]|combout
11.385   0.527 RR IC 2 LC_X26_Y11_N0 tdc|a|tdc|le|phase|c|latch[0]|datad <--------------
11.473   0.088 RR CELL 1 LC_X26_Y11_N0 tdc|a|tdc|le|phase|c|latch[0]|combout
11.801   0.328 RR IC 2 LC_X26_Y11_N4 tdc|a|tdc|le|phase|c|latch[1]|datad
11.889   0.088 RR CELL 1 LC_X26_Y11_N4 tdc|a|tdc|le|phase|c|latch[1]|combout
12.225   0.336 RR IC 2 LC_X26_Y11_N3 tdc|a|tdc|le|phase|c|latch[2]|datac
12.450   0.225 RR CELL 1 LC_X26_Y11_N3 tdc|a|tdc|le|phase|c|latch[2]|combout
12.776   0.326 RR IC 2 LC_X26_Y11_N1 tdc|a|tdc|le|phase|c|latch[3]|datad
12.864   0.088 RR CELL 1 LC_X26_Y11_N1 tdc|a|tdc|le|phase|c|latch[3]|combout
13.184   0.320 RR IC 2 LC_X26_Y11_N6 tdc|a|tdc|le|phase|c|latch[4]|datad
13.272   0.088 RR CELL 1 LC_X26_Y11_N6 tdc|a|tdc|le|phase|c|latch[4]|combout
13.412   0.140 RR IC 2 LC_X26_Y11_N7 tdc|a|tdc|le|phase|c|latch[5]|datad
13.500   0.088 RR CELL 1 LC_X26_Y11_N7 tdc|a|tdc|le|phase|c|latch[5]|combout
13.640   0.140 RR IC 2 LC_X26_Y11_N8 tdc|a|tdc|le|phase|c|latch[6]|datad
13.728   0.088 RR CELL 1 LC_X26_Y11_N8 tdc|a|tdc|le|phase|c|latch[6]|combout
13.868   0.140 RR IC 2 LC_X26_Y11_N9 tdc|a|tdc|le|phase|c|latch[7]|datad
13.956   0.088 RR CELL 1 LC_X26_Y11_N9 tdc|a|tdc|le|phase|c|latch[7]|combout
14.292   0.336 RR IC 2 LC_X26_Y11_N5 tdc|a|tdc|le|phase|c|latch[8]|datac
14.517   0.225 RR CELL 1 LC_X26_Y11_N5 tdc|a|tdc|le|phase|c|latch[8]|combout
14.846   0.329 RR IC 2 LC_X26_Y11_N2 tdc|a|tdc|le|phase|c|latch[9]|datad
14.934   0.088 RR CELL 1 LC_X26_Y11_N2 tdc|a|tdc|le|phase|c|latch[9]|combout
15.857   0.923 RR IC 2 LC_X26_Y12_N3 tdc|a|tdc|le|phase|d|latch[0]|datad <--------------
15.945   0.088 RR CELL 1 LC_X26_Y12_N3 tdc|a|tdc|le|phase|d|latch[0]|combout
16.273   0.328 RR IC 2 LC_X26_Y12_N8 tdc|a|tdc|le|phase|d|latch[1]|datad
16.361   0.088 RR CELL 1 LC_X26_Y12_N8 tdc|a|tdc|le|phase|d|latch[1]|combout
16.701   0.340 RR IC 2 LC_X26_Y12_N4 tdc|a|tdc|le|phase|d|latch[2]|datac
16.926   0.225 RR CELL 1 LC_X26_Y12_N4 tdc|a|tdc|le|phase|d|latch[2]|combout
17.266   0.340 RR IC 2 LC_X26_Y12_N1 tdc|a|tdc|le|phase|d|latch[3]|datac
17.491   0.225 RR CELL 1 LC_X26_Y12_N1 tdc|a|tdc|le|phase|d|latch[3]|combout
17.817   0.326 RR IC 2 LC_X26_Y12_N7 tdc|a|tdc|le|phase|d|latch[4]|datad
17.905   0.088 RR CELL 1 LC_X26_Y12_N7 tdc|a|tdc|le|phase|d|latch[4]|combout
18.248   0.343 RR IC 2 LC_X26_Y12_N9 tdc|a|tdc|le|phase|d|latch[5]|datac
18.473   0.225 RR CELL 1 LC_X26_Y12_N9 tdc|a|tdc|le|phase|d|latch[5]|combout
18.818   0.345 RR IC 2 LC_X26_Y12_N0 tdc|a|tdc|le|phase|d|latch[6]|datac
19.043   0.225 RR CELL 1 LC_X26_Y12_N0 tdc|a|tdc|le|phase|d|latch[6]|combout
19.372   0.329 RR IC 2 LC_X26_Y12_N6 tdc|a|tdc|le|phase|d|latch[7]|datad
19.460   0.088 RR CELL 1 LC_X26_Y12_N6 tdc|a|tdc|le|phase|d|latch[7]|combout
19.783   0.323 RR IC 2 LC_X26_Y12_N5 tdc|a|tdc|le|phase|d|latch[8]|datad
19.871   0.088 RR CELL 1 LC_X26_Y12_N5 tdc|a|tdc|le|phase|d|latch[8]|combout
20.199   0.328 RR IC 1 LC_X26_Y12_N2 tdc|a|tdc|le|phase|d|latch[9]|datad
20.287   0.088 RR CELL 1 LC_X26_Y12_N2 tdc|a|tdc|le|phase|d|latch[9]|combout
20.629   0.342 RR IC 1 LC_X26_Y12_N2 tdc|a|tdc|le|phase|d|latch[9]|datac
20.718   0.089 RR CELL 1 LC_X26_Y12_N2 TDC6:tdc|TDC2ef:a|TDC2e:tdc|TDC1:le|TDClcell40:phase|TDClcell10:d|latch[9]
tdc6k.pdf
min bin: 0.156 0.008 0.158 0.127 ns, max bin: 0.808 0.807 0.765 0.783 ns, max phase 33 33 30 29
min bin: 0.064 0.122 0.043 0.079 ns, max bin: 0.826 0.900 0.838 0.893 ns, max phase 33 32 34 32
min bin: 0.074 0.122 0.009 0.085 ns, max bin: 0.851 0.930 0.766 0.814 ns, max phase 31 29 35 34
</pre>
</pre>



Revision as of 15:41, 7 September 2024

DL-TDC DarkLight FPGA TDC

ODB settings

  • dl_enable - yes/no - enable or disable TDC readout in the midas frontend
  • dl_ctrl - 32 bits of general control
bit - quartus - description
  0 - dl_ctrl_gate   - jam TDC gate open, enable un-triggered free-running mode
  1 - dl_ctrl_gate_A - gate TDC from A-side trigger
  2 - dl_ctrl_gate_B - gate TDC from B-side trigger
  3 - dl_ctrl_gate_AB - gate TDC from A*B
  4 - dl_ctrl_gate_T - gate TDC from T trigger (T = A*B)
  5 - dl_ctrl_ena_A - enable TDC channel 32 (A)
  6 - dl_ctrl_ena_B - enable TDC channel 33 (B)
  7 - dl_ctrl_ena_T - enable TDC channel 34 (T)
15..8 - dl_ctrl_gate_w - TDC gate width in units of 8 ns
31..16 - not used
  • dl_trg_mask - 16 bits of trigger mask
bit - description
  0 - enable A pair 1-9
  1 - enable A pair 2-10
  2 - enable A pair 3-11
  3 - enable A pair 4-12
  4
  5
  6
  7
  8 - enable B pair 5-13
  9 - enable B pair 6-14
 10 - enable B pair 7-15
 11 - enable B pair 8-16
  • dl_tdc_mask - 32 bits to enable 32 TDC channels, in sequence

Channel map

// map TDC cable to SiPM channels
   
   assign ch[1]  = tdc[0];
   assign ch[2]  = tdc[1];
   assign ch[3]  = tdc[10];
   assign ch[4]  = tdc[11];
   assign ch[5]  = tdc[2];
   assign ch[6]  = tdc[3];
   assign ch[7]  = tdc[8];
   assign ch[8]  = tdc[9];

   assign ch[9]  = tdc[15];
   assign ch[10] = tdc[14];
   assign ch[11] = tdc[7];
   assign ch[12] = tdc[6];
   assign ch[13] = tdc[13];
   assign ch[14] = tdc[12];
   assign ch[15] = tdc[5];
   assign ch[16] = tdc[4];

   assign ch[16+1]  = tdc[16+0];  // 16
   assign ch[16+2]  = tdc[16+1];  // 17
   assign ch[16+3]  = tdc[16+10]; // 26
   assign ch[16+4]  = tdc[16+11]; // 27
   assign ch[16+5]  = tdc[16+2];  // 18
   assign ch[16+6]  = tdc[16+3];  // 19
   assign ch[16+7]  = tdc[16+8];  // 24
   assign ch[16+8]  = tdc[16+9];  // 25

   assign ch[16+9]  = tdc[16+15]; // 31
   assign ch[16+10] = tdc[16+14]; // 30
   assign ch[16+11] = tdc[16+7];  // 23
   assign ch[16+12] = tdc[16+6];  // 22
   assign ch[16+13] = tdc[16+13]; // 29
   assign ch[16+14] = tdc[16+12]; // 28
   assign ch[16+15] = tdc[16+5];  // 21
   assign ch[16+16] = tdc[16+4];  // 20

   // compute SiPM pair concindences
   
   assign A[0] = ch[1] & ch[9]  & enable_input[0]; //  0 * 15 -> pair1
   assign A[1] = ch[2] & ch[10] & enable_input[1]; //  1 * 14 -> pair2
   assign A[2] = ch[3] & ch[11] & enable_input[2]; // 10 *  7 -> pair3
   assign A[3] = ch[4] & ch[12] & enable_input[3]; // 11 *  6 -> pair4
   assign A[4] = ch[5] & ch[13] & enable_input[4];
   assign A[5] = ch[6] & ch[14] & enable_input[5];
   assign A[6] = ch[7] & ch[15] & enable_input[6];
   assign A[7] = ch[8] & ch[16] & enable_input[7];

   assign B[0] = ch[16+1] & ch[16+9]  & enable_input[8];  // 16 * 31
   assign B[1] = ch[16+2] & ch[16+10] & enable_input[9];  // 17 * 30
   assign B[2] = ch[16+3] & ch[16+11] & enable_input[10]; // 26 * 23
   assign B[3] = ch[16+4] & ch[16+12] & enable_input[11]; // 27 * 22
   assign B[4] = ch[16+5] & ch[16+13] & enable_input[12]; // 18 * 29 -> pair5
   assign B[5] = ch[16+6] & ch[16+14] & enable_input[13]; // 19 * 28 -> pair6
   assign B[6] = ch[16+7] & ch[16+15] & enable_input[14]; // 24 * 21 -> pair7
   assign B[7] = ch[16+8] & ch[16+16] & enable_input[15]; // 25 * 20 -> pair8

   wire        A_or = |A;
   wire        B_or = |B;

   //wire        A_or = A[0] | A{1] | A{2] | A[3] | A[4] | A{5] | A{6] | A[7];
   //wire        B_or = B[0] | B{1] | B{2] | B[3] | B[4] | B{5] | B{6] | B[7];

   wire        AB_and = A_or & B_or;

D3 delay tuning

9.109	GPIO_1_20	dl|WideOr0|combout -> 1
9.025	GPIO_1_33	dl|WideOr0|combout -> 1
9.022	GPIO_1_26	dl|WideOr0|combout -> 0
8.966	GPIO_1_28	dl|WideOr0|combout -> 5            = 8.494 add 1
8.787	GPIO_1_22	dl|WideOr0|combout -> 0
8.714	GPIO_1_21	dl|WideOr0|combout -> 5
8.711	GPIO_1_34	dl|WideOr0|combout -> 0
8.597	GPIO_1_30	dl|WideOr0|combout -> 0            = 8.240 add 1 -> 1 = 9.733 sub 1
8.590	GPIO_1_29	dl|WideOr0|combout -> 1 add 1 -> 2 = 9.588 sub 1
8.506	GPIO_1_27	dl|WideOr0|combout -> 4 add 1 --------------------> 5 = 10.097 sub 1
8.453	GPIO_1_24	dl|WideOr0|combout -> 2 add 1 -> 3 = 9.588 sub 1
8.412	GPIO_1_35	dl|WideOr0|combout add 1
8.380	GPIO_1_31	dl|WideOr0|combout -> 4 add 1 -> 5 = 9.208 sub 1
8.312	GPIO_1_25	dl|WideOr0|combout -> 1 add 1 -> 2 = 8.555 add 1 -> 3 = 9.379
7.992	GPIO_1_32	dl|WideOr0|combout add 2
7.248	GPIO_1_23	dl|WideOr0|combout -> 2 add 3 -> 5 = 9.425 sub 1
9.339	GPIO_0_14	dl|WideOr1|combout -> 6 sub 1 -> 5 = 8.587
9.207	GPIO_0_2	dl|WideOr1|combout -> 7 sub 1 -> 6 = 8.360 add 1
9.174	GPIO_0_10	dl|WideOr1|combout -> 6
9.161	GPIO_0_6	dl|WideOr1|combout -> 7
9.105	GPIO_0_11	dl|WideOr1|combout -> 7
9.019	GPIO_0_7	dl|WideOr1|combout -> 7
8.731	GPIO_0_15	dl|WideOr1|combout add 0 -> 0 = 8.540 add 1
8.462	GPIO_0_12	dl|WideOr1|combout add 1 -> 1 = 9.189
8.256	GPIO_0_4	dl|WideOr1|combout add 2 -> 2 = 9.750 sub 1
8.214	GPIO_0_5	dl|WideOr1|combout add 2
8.182	GPIO_0_1	dl|WideOr1|combout add 2
7.328	GPIO_0_3	dl|WideOr1|combout add 3
6.584	GPIO_0_8	dl|WideOr1|combout add 5
6.409	GPIO_0_13	dl|WideOr1|combout add 5 -> 5 =  9.943 sub 2
6.009	GPIO_0_9	dl|WideOr1|combout add 6 -> 6 = 10.189 sub 2
5.917	GPIO_0_0	dl|WideOr1|combout add 6

Cyclone-5

report_path -multi_corner -panel_name {Report Path} -to [get_keepers {TDC6:TDC6_inst|TDC2ef:a|TDC2e:tdc|TDC1:le|TDClcell40:phase|TDClcell10:d|latch[9]}] -npaths 1
2 TDCs, 40 LCELLs, region lock 3x3

21.108	21.108					data path	1
0.000	  0.000			1	FF_X85_Y18_N2	tdc_ts[0]	1
0.000	  0.000	RR	CELL	9	FF_X85_Y18_N2	tdc_ts[0]|q	2
1.530	  1.530	RR	IC	1	MLABCELL_X87_Y10_N15	TDC6_inst|a|tdc|le|phase|a|inst0|dataf	3
1.617	  0.087	RR	CELL	2	MLABCELL_X87_Y10_N15	TDC6_inst|a|tdc|le|phase|a|inst0|combout	4
1.860	  0.243	RR	IC	1	MLABCELL_X87_Y10_N6	TDC6_inst|a|tdc|le|phase|a|inst1|dataf	5
1.946	  0.086	RR	CELL	2	MLABCELL_X87_Y10_N6	TDC6_inst|a|tdc|le|phase|a|inst1|combout	6
2.714	  0.768	RR	IC	1	LABCELL_X85_Y11_N51	TDC6_inst|a|tdc|le|phase|a|inst2|dataf	7
2.800	  0.086	RR	CELL	2	LABCELL_X85_Y11_N51	TDC6_inst|a|tdc|le|phase|a|inst2|combout	8
3.323	  0.523	RR	IC	1	LABCELL_X85_Y11_N48	TDC6_inst|a|tdc|le|phase|a|inst3|datad	9
3.576	  0.253	RR	CELL	2	LABCELL_X85_Y11_N48	TDC6_inst|a|tdc|le|phase|a|inst3|combout	10
3.827	  0.251	RR	IC	1	LABCELL_X85_Y11_N15	TDC6_inst|a|tdc|le|phase|a|inst4|dataf	11
3.914	  0.087	RR	CELL	2	LABCELL_X85_Y11_N15	TDC6_inst|a|tdc|le|phase|a|inst4|combout	12
4.146	  0.232	RR	IC	1	LABCELL_X85_Y11_N12	TDC6_inst|a|tdc|le|phase|a|inst5|dataf	13
4.233	  0.087	RR	CELL	2	LABCELL_X85_Y11_N12	TDC6_inst|a|tdc|le|phase|a|inst5|combout	14
4.484	  0.251	RR	IC	1	LABCELL_X85_Y11_N9	TDC6_inst|a|tdc|le|phase|a|inst6|dataf	15
4.571	  0.087	RR	CELL	2	LABCELL_X85_Y11_N9	TDC6_inst|a|tdc|le|phase|a|inst6|combout	16
4.800	  0.229	RR	IC	1	LABCELL_X85_Y11_N6	TDC6_inst|a|tdc|le|phase|a|inst7|dataf	17
4.887	  0.087	RR	CELL	2	LABCELL_X85_Y11_N6	TDC6_inst|a|tdc|le|phase|a|inst7|combout	18
5.124	  0.237	RR	IC	1	LABCELL_X85_Y11_N3	TDC6_inst|a|tdc|le|phase|a|inst8|dataf	19
5.211	  0.087	RR	CELL	2	LABCELL_X85_Y11_N3	TDC6_inst|a|tdc|le|phase|a|inst8|combout	20
5.459	  0.248	RR	IC	1	LABCELL_X85_Y11_N0	TDC6_inst|a|tdc|le|phase|a|inst9|datac	21
5.864	  0.405	RR	CELL	2	LABCELL_X85_Y11_N0	TDC6_inst|a|tdc|le|phase|a|inst9|combout	22
6.075	  0.211	RR	IC	1	LABCELL_X85_Y11_N27	TDC6_inst|a|tdc|le|phase|b|inst0|dataa	23
6.656	  0.581	RR	CELL	2	LABCELL_X85_Y11_N27	TDC6_inst|a|tdc|le|phase|b|inst0|combout	24
6.901	  0.245	RR	IC	1	LABCELL_X85_Y11_N24	TDC6_inst|a|tdc|le|phase|b|inst1|datac	25
7.306	  0.405	RR	CELL	2	LABCELL_X85_Y11_N24	TDC6_inst|a|tdc|le|phase|b|inst1|combout	26
7.552	  0.246	RR	IC	1	LABCELL_X85_Y11_N21	TDC6_inst|a|tdc|le|phase|b|inst2|dataf	27
7.639	  0.087	RR	CELL	2	LABCELL_X85_Y11_N21	TDC6_inst|a|tdc|le|phase|b|inst2|combout	28
7.886	  0.247	RR	IC	1	LABCELL_X85_Y11_N18	TDC6_inst|a|tdc|le|phase|b|inst3|datac	29
8.291	  0.405	RR	CELL	2	LABCELL_X85_Y11_N18	TDC6_inst|a|tdc|le|phase|b|inst3|combout	30
8.548	  0.257	RR	IC	1	LABCELL_X85_Y11_N45	TDC6_inst|a|tdc|le|phase|b|inst4|dataf	31
8.635	  0.087	RR	CELL	2	LABCELL_X85_Y11_N45	TDC6_inst|a|tdc|le|phase|b|inst4|combout	32
8.839	  0.204	RR	IC	1	LABCELL_X85_Y11_N42	TDC6_inst|a|tdc|le|phase|b|inst5|datab	33
9.394	  0.555	RR	CELL	2	LABCELL_X85_Y11_N42	TDC6_inst|a|tdc|le|phase|b|inst5|combout	34
9.638	  0.244	RR	IC	1	LABCELL_X85_Y11_N39	TDC6_inst|a|tdc|le|phase|b|inst6|dataf	35
9.725	  0.087	RR	CELL	2	LABCELL_X85_Y11_N39	TDC6_inst|a|tdc|le|phase|b|inst6|combout	36
9.959	  0.234	RR	IC	1	LABCELL_X85_Y11_N36	TDC6_inst|a|tdc|le|phase|b|inst7|dataf	37
10.046	  0.087	RR	CELL	2	LABCELL_X85_Y11_N36	TDC6_inst|a|tdc|le|phase|b|inst7|combout	38
10.250	  0.204	RR	IC	1	LABCELL_X85_Y11_N33	TDC6_inst|a|tdc|le|phase|b|inst8|dataa	39
10.831	  0.581	RR	CELL	2	LABCELL_X85_Y11_N33	TDC6_inst|a|tdc|le|phase|b|inst8|combout	40
11.059	  0.228	RR	IC	1	LABCELL_X85_Y11_N30	TDC6_inst|a|tdc|le|phase|b|inst9|dataf	41
11.145	  0.086	RR	CELL	2	LABCELL_X85_Y11_N30	TDC6_inst|a|tdc|le|phase|b|inst9|combout	42
11.724	  0.579	RR	IC	1	LABCELL_X88_Y11_N57	TDC6_inst|a|tdc|le|phase|c|inst0|dataf	43
11.811	  0.087	RR	CELL	2	LABCELL_X88_Y11_N57	TDC6_inst|a|tdc|le|phase|c|inst0|combout	44
12.018	  0.207	RR	IC	1	LABCELL_X88_Y11_N54	TDC6_inst|a|tdc|le|phase|c|inst1|datab	45
12.573	  0.555	RR	CELL	2	LABCELL_X88_Y11_N54	TDC6_inst|a|tdc|le|phase|c|inst1|combout	46
12.780	  0.207	RR	IC	1	LABCELL_X88_Y11_N51	TDC6_inst|a|tdc|le|phase|c|inst2|dataa	47
13.361	  0.581	RR	CELL	2	LABCELL_X88_Y11_N51	TDC6_inst|a|tdc|le|phase|c|inst2|combout	48
13.591	  0.230	RR	IC	1	LABCELL_X88_Y11_N48	TDC6_inst|a|tdc|le|phase|c|inst3|dataf	49
13.678	  0.087	RR	CELL	2	LABCELL_X88_Y11_N48	TDC6_inst|a|tdc|le|phase|c|inst3|combout	50
13.935	  0.257	RR	IC	1	LABCELL_X88_Y11_N15	TDC6_inst|a|tdc|le|phase|c|inst4|dataf	51
14.022	  0.087	RR	CELL	2	LABCELL_X88_Y11_N15	TDC6_inst|a|tdc|le|phase|c|inst4|combout	52
14.254	  0.232	RR	IC	1	LABCELL_X88_Y11_N12	TDC6_inst|a|tdc|le|phase|c|inst5|dataf	53
14.341	  0.087	RR	CELL	2	LABCELL_X88_Y11_N12	TDC6_inst|a|tdc|le|phase|c|inst5|combout	54
14.592	  0.251	RR	IC	1	LABCELL_X88_Y11_N9	TDC6_inst|a|tdc|le|phase|c|inst6|dataf	55
14.679	  0.087	RR	CELL	2	LABCELL_X88_Y11_N9	TDC6_inst|a|tdc|le|phase|c|inst6|combout	56
14.908	  0.229	RR	IC	1	LABCELL_X88_Y11_N6	TDC6_inst|a|tdc|le|phase|c|inst7|dataf	57
14.995	  0.087	RR	CELL	2	LABCELL_X88_Y11_N6	TDC6_inst|a|tdc|le|phase|c|inst7|combout	58
15.247	  0.252	RR	IC	1	LABCELL_X88_Y11_N33	TDC6_inst|a|tdc|le|phase|c|inst8|dataf	59
15.334	  0.087	RR	CELL	2	LABCELL_X88_Y11_N33	TDC6_inst|a|tdc|le|phase|c|inst8|combout	60
15.568	  0.234	RR	IC	1	LABCELL_X88_Y11_N30	TDC6_inst|a|tdc|le|phase|c|inst9|dataf	61
15.655	  0.087	RR	CELL	2	LABCELL_X88_Y11_N30	TDC6_inst|a|tdc|le|phase|c|inst9|combout	62
15.909	  0.254	RR	IC	1	LABCELL_X88_Y11_N27	TDC6_inst|a|tdc|le|phase|d|inst0|dataf	63
15.996	  0.087	RR	CELL	2	LABCELL_X88_Y11_N27	TDC6_inst|a|tdc|le|phase|d|inst0|combout	64
16.241	  0.245	RR	IC	1	LABCELL_X88_Y11_N24	TDC6_inst|a|tdc|le|phase|d|inst1|datac	65
16.646	  0.405	RR	CELL	2	LABCELL_X88_Y11_N24	TDC6_inst|a|tdc|le|phase|d|inst1|combout	66
16.892	  0.246	RR	IC	1	LABCELL_X88_Y11_N21	TDC6_inst|a|tdc|le|phase|d|inst2|dataf	67
16.979	  0.087	RR	CELL	2	LABCELL_X88_Y11_N21	TDC6_inst|a|tdc|le|phase|d|inst2|combout	68
17.226	  0.247	RR	IC	1	LABCELL_X88_Y11_N18	TDC6_inst|a|tdc|le|phase|d|inst3|datac	69
17.631	  0.405	RR	CELL	2	LABCELL_X88_Y11_N18	TDC6_inst|a|tdc|le|phase|d|inst3|combout	70
17.888	  0.257	RR	IC	1	LABCELL_X88_Y11_N45	TDC6_inst|a|tdc|le|phase|d|inst4|dataf	71
17.975	  0.087	RR	CELL	2	LABCELL_X88_Y11_N45	TDC6_inst|a|tdc|le|phase|d|inst4|combout	72
18.185	  0.210	RR	IC	1	LABCELL_X88_Y11_N42	TDC6_inst|a|tdc|le|phase|d|inst5|datab	73
18.740	  0.555	RR	CELL	2	LABCELL_X88_Y11_N42	TDC6_inst|a|tdc|le|phase|d|inst5|combout	74
18.984	  0.244	RR	IC	1	LABCELL_X88_Y11_N39	TDC6_inst|a|tdc|le|phase|d|inst6|dataf	75
19.071	  0.087	RR	CELL	2	LABCELL_X88_Y11_N39	TDC6_inst|a|tdc|le|phase|d|inst6|combout	76
19.305	  0.234	RR	IC	1	LABCELL_X88_Y11_N36	TDC6_inst|a|tdc|le|phase|d|inst7|dataf	77
19.392	  0.087	RR	CELL	2	LABCELL_X88_Y11_N36	TDC6_inst|a|tdc|le|phase|d|inst7|combout	78
19.618	  0.226	RR	IC	1	LABCELL_X88_Y11_N3	TDC6_inst|a|tdc|le|phase|d|inst8|dataa	79
20.199	  0.581	RR	CELL	2	LABCELL_X88_Y11_N3	TDC6_inst|a|tdc|le|phase|d|inst8|combout	80
20.447	  0.248	RR	IC	1	LABCELL_X88_Y11_N0	TDC6_inst|a|tdc|le|phase|d|inst9|datac	81
20.847	  0.000	RR	IC	1	FF_X88_Y11_N2	TDC6_inst|a|tdc|le|phase|d|latch[9]|d	82
20.847	  0.400	RR	CELL	1	LABCELL_X88_Y11_N0	TDC6_inst|a|tdc|le|phase|d|inst9|combout	83
21.108	  0.261	RR	CELL	1	FF_X88_Y11_N2	TDC6:TDC6_inst|TDC2ef:a|TDC2e:tdc|TDC1:le|TDClcell40:phase|TDClcell10:d|latch[9]	84

tdc6g.pdf

min bin: 0.021 0.016 0.031 0.030 ns, max bin: 0.484 0.612 0.872 1.171 ns, max phase 38 36 33 33
min bin: 0.016 0.074 0.009 0.130 ns, max bin: 0.857 0.727 0.622 0.782 ns, max phase 33 30 38 35
6 TDCs, 40 LCELLs, region lock floating

21.415	21.415					data path	1
0.000	  0.000			1	FF_X72_Y13_N2	tdc_ts[0]	1
0.000	  0.000	RR	CELL	25	FF_X72_Y13_N2	tdc_ts[0]|q	2
1.788	  1.788	RR	IC	1	MLABCELL_X84_Y1_N9	TDC6_inst|a|tdc|le|phase|a|inst0|dataf	3
1.874	  0.086	RR	CELL	2	MLABCELL_X84_Y1_N9	TDC6_inst|a|tdc|le|phase|a|inst0|combout	4
2.436	  0.562	RR	IC	1	MLABCELL_X87_Y1_N9	TDC6_inst|a|tdc|le|phase|a|inst1|datac	5
2.865	  0.429	RR	CELL	2	MLABCELL_X87_Y1_N9	TDC6_inst|a|tdc|le|phase|a|inst1|combout	6
3.142	  0.277	RR	IC	1	MLABCELL_X87_Y1_N33	TDC6_inst|a|tdc|le|phase|a|inst2|dataf	7
3.229	  0.087	RR	CELL	2	MLABCELL_X87_Y1_N33	TDC6_inst|a|tdc|le|phase|a|inst2|combout	8
3.458	  0.229	RR	IC	1	MLABCELL_X87_Y1_N30	TDC6_inst|a|tdc|le|phase|a|inst3|dataf	9
3.545	  0.087	RR	CELL	2	MLABCELL_X87_Y1_N30	TDC6_inst|a|tdc|le|phase|a|inst3|combout	10
3.795	  0.250	RR	IC	1	MLABCELL_X87_Y1_N57	TDC6_inst|a|tdc|le|phase|a|inst4|dataf	11
3.882	  0.087	RR	CELL	2	MLABCELL_X87_Y1_N57	TDC6_inst|a|tdc|le|phase|a|inst4|combout	12
4.084	  0.202	RR	IC	1	MLABCELL_X87_Y1_N54	TDC6_inst|a|tdc|le|phase|a|inst5|datab	13
4.639	  0.555	RR	CELL	2	MLABCELL_X87_Y1_N54	TDC6_inst|a|tdc|le|phase|a|inst5|combout	14
4.848	  0.209	RR	IC	1	MLABCELL_X87_Y1_N51	TDC6_inst|a|tdc|le|phase|a|inst6|dataa	15
5.429	  0.581	RR	CELL	2	MLABCELL_X87_Y1_N51	TDC6_inst|a|tdc|le|phase|a|inst6|combout	16
5.662	  0.233	RR	IC	1	MLABCELL_X87_Y1_N48	TDC6_inst|a|tdc|le|phase|a|inst7|dataf	17
5.749	  0.087	RR	CELL	2	MLABCELL_X87_Y1_N48	TDC6_inst|a|tdc|le|phase|a|inst7|combout	18
6.008	  0.259	RR	IC	1	MLABCELL_X87_Y1_N15	TDC6_inst|a|tdc|le|phase|a|inst8|dataf	19
6.095	  0.087	RR	CELL	2	MLABCELL_X87_Y1_N15	TDC6_inst|a|tdc|le|phase|a|inst8|combout	20
6.328	  0.233	RR	IC	1	MLABCELL_X87_Y1_N12	TDC6_inst|a|tdc|le|phase|a|inst9|dataf	21
6.415	  0.087	RR	CELL	2	MLABCELL_X87_Y1_N12	TDC6_inst|a|tdc|le|phase|a|inst9|combout	22
6.678	  0.263	RR	IC	1	MLABCELL_X87_Y1_N39	TDC6_inst|a|tdc|le|phase|b|inst0|dataf	23
6.765	  0.087	RR	CELL	2	MLABCELL_X87_Y1_N39	TDC6_inst|a|tdc|le|phase|b|inst0|combout	24
6.995	  0.230	RR	IC	1	MLABCELL_X87_Y1_N36	TDC6_inst|a|tdc|le|phase|b|inst1|dataf	25
7.082	  0.087	RR	CELL	2	MLABCELL_X87_Y1_N36	TDC6_inst|a|tdc|le|phase|b|inst1|combout	26
7.328	  0.246	RR	IC	1	MLABCELL_X87_Y1_N3	TDC6_inst|a|tdc|le|phase|b|inst2|datae	27
7.535	  0.207	RR	CELL	2	MLABCELL_X87_Y1_N3	TDC6_inst|a|tdc|le|phase|b|inst2|combout	28
8.070	  0.535	RR	IC	1	LABCELL_X85_Y1_N12	TDC6_inst|a|tdc|le|phase|b|inst3|dataf	29
8.157	  0.087	RR	CELL	2	LABCELL_X85_Y1_N12	TDC6_inst|a|tdc|le|phase|b|inst3|combout	30
8.412	  0.255	RR	IC	1	LABCELL_X85_Y1_N39	TDC6_inst|a|tdc|le|phase|b|inst4|dataf	31
8.499	  0.087	RR	CELL	2	LABCELL_X85_Y1_N39	TDC6_inst|a|tdc|le|phase|b|inst4|combout	32
8.745	  0.246	RR	IC	1	LABCELL_X85_Y1_N51	TDC6_inst|a|tdc|le|phase|b|inst5|dataf	33
8.832	  0.087	RR	CELL	2	LABCELL_X85_Y1_N51	TDC6_inst|a|tdc|le|phase|b|inst5|combout	34
9.083	  0.251	RR	IC	1	LABCELL_X85_Y1_N9	TDC6_inst|a|tdc|le|phase|b|inst6|dataf	35
9.170	  0.087	RR	CELL	2	LABCELL_X85_Y1_N9	TDC6_inst|a|tdc|le|phase|b|inst6|combout	36
9.405	  0.235	RR	IC	1	LABCELL_X85_Y1_N6	TDC6_inst|a|tdc|le|phase|b|inst7|dataf	37
9.491	  0.086	RR	CELL	2	LABCELL_X85_Y1_N6	TDC6_inst|a|tdc|le|phase|b|inst7|combout	38
9.840	  0.349	RR	IC	1	LABCELL_X85_Y1_N33	TDC6_inst|a|tdc|le|phase|b|inst8|dataa	39
10.421	  0.581	RR	CELL	2	LABCELL_X85_Y1_N33	TDC6_inst|a|tdc|le|phase|b|inst8|combout	40
10.655	  0.234	RR	IC	1	LABCELL_X85_Y1_N30	TDC6_inst|a|tdc|le|phase|b|inst9|dataf	41
10.742	  0.087	RR	CELL	2	LABCELL_X85_Y1_N30	TDC6_inst|a|tdc|le|phase|b|inst9|combout	42
10.993	  0.251	RR	IC	1	LABCELL_X85_Y1_N57	TDC6_inst|a|tdc|le|phase|c|inst0|dataf	43
11.080	  0.087	RR	CELL	2	LABCELL_X85_Y1_N57	TDC6_inst|a|tdc|le|phase|c|inst0|combout	44
11.294	  0.214	RR	IC	1	LABCELL_X85_Y1_N48	TDC6_inst|a|tdc|le|phase|c|inst1|datab	45
11.849	  0.555	RR	CELL	2	LABCELL_X85_Y1_N48	TDC6_inst|a|tdc|le|phase|c|inst1|combout	46
12.087	  0.238	RR	IC	1	LABCELL_X85_Y1_N42	TDC6_inst|a|tdc|le|phase|c|inst2|dataf	47
12.173	  0.086	RR	CELL	2	LABCELL_X85_Y1_N42	TDC6_inst|a|tdc|le|phase|c|inst2|combout	48
12.504	  0.331	RR	IC	1	MLABCELL_X84_Y1_N57	TDC6_inst|a|tdc|le|phase|c|inst3|datae	49
12.713	  0.209	RR	CELL	2	MLABCELL_X84_Y1_N57	TDC6_inst|a|tdc|le|phase|c|inst3|combout	50
12.949	  0.236	RR	IC	1	MLABCELL_X84_Y1_N51	TDC6_inst|a|tdc|le|phase|c|inst4|datac	51
13.361	  0.412	RR	CELL	2	MLABCELL_X84_Y1_N51	TDC6_inst|a|tdc|le|phase|c|inst4|combout	52
13.595	  0.234	RR	IC	1	MLABCELL_X84_Y1_N48	TDC6_inst|a|tdc|le|phase|c|inst5|dataf	53
13.682	  0.087	RR	CELL	2	MLABCELL_X84_Y1_N48	TDC6_inst|a|tdc|le|phase|c|inst5|combout	54
13.935	  0.253	RR	IC	1	MLABCELL_X84_Y1_N45	TDC6_inst|a|tdc|le|phase|c|inst6|dataf	55
14.021	  0.086	RR	CELL	2	MLABCELL_X84_Y1_N45	TDC6_inst|a|tdc|le|phase|c|inst6|combout	56
14.329	  0.308	RR	IC	1	LABCELL_X85_Y1_N36	TDC6_inst|a|tdc|le|phase|c|inst7|dataf	57
14.416	  0.087	RR	CELL	2	LABCELL_X85_Y1_N36	TDC6_inst|a|tdc|le|phase|c|inst7|combout	58
14.635	  0.219	RR	IC	1	LABCELL_X85_Y1_N3	TDC6_inst|a|tdc|le|phase|c|inst8|dataa	59
15.219	  0.584	RR	CELL	2	LABCELL_X85_Y1_N3	TDC6_inst|a|tdc|le|phase|c|inst8|combout	60
15.461	  0.242	RR	IC	1	LABCELL_X85_Y1_N0	TDC6_inst|a|tdc|le|phase|c|inst9|datac	61
15.864	  0.403	RR	CELL	2	LABCELL_X85_Y1_N0	TDC6_inst|a|tdc|le|phase|c|inst9|combout	62
16.180	  0.316	RR	IC	1	MLABCELL_X84_Y1_N39	TDC6_inst|a|tdc|le|phase|d|inst0|dataa	63
16.761	  0.581	RR	CELL	2	MLABCELL_X84_Y1_N39	TDC6_inst|a|tdc|le|phase|d|inst0|combout	64
16.996	  0.235	RR	IC	1	MLABCELL_X84_Y1_N36	TDC6_inst|a|tdc|le|phase|d|inst1|dataf	65
17.083	  0.087	RR	CELL	2	MLABCELL_X84_Y1_N36	TDC6_inst|a|tdc|le|phase|d|inst1|combout	66
17.302	  0.219	RR	IC	1	MLABCELL_X84_Y1_N3	TDC6_inst|a|tdc|le|phase|d|inst2|dataa	67
17.883	  0.581	RR	CELL	2	MLABCELL_X84_Y1_N3	TDC6_inst|a|tdc|le|phase|d|inst2|combout	68
18.125	  0.242	RR	IC	1	MLABCELL_X84_Y1_N33	TDC6_inst|a|tdc|le|phase|d|inst3|datae	69
18.334	  0.209	RR	CELL	2	MLABCELL_X84_Y1_N33	TDC6_inst|a|tdc|le|phase|d|inst3|combout	70
18.594	  0.260	RR	IC	1	MLABCELL_X84_Y1_N12	TDC6_inst|a|tdc|le|phase|d|inst4|datac	71
19.022	  0.428	RR	CELL	2	MLABCELL_X84_Y1_N12	TDC6_inst|a|tdc|le|phase|d|inst4|combout	72
19.264	  0.242	RR	IC	1	MLABCELL_X84_Y1_N27	TDC6_inst|a|tdc|le|phase|d|inst5|datac	73
19.676	  0.412	RR	CELL	2	MLABCELL_X84_Y1_N27	TDC6_inst|a|tdc|le|phase|d|inst5|combout	74
19.924	  0.248	RR	IC	1	MLABCELL_X84_Y1_N18	TDC6_inst|a|tdc|le|phase|d|inst6|datae	75
20.175	  0.251	RR	CELL	2	MLABCELL_X84_Y1_N18	TDC6_inst|a|tdc|le|phase|d|inst6|combout	76
20.421	  0.246	RR	IC	1	MLABCELL_X84_Y1_N24	TDC6_inst|a|tdc|le|phase|d|inst7|dataf	77
20.508	  0.087	RR	CELL	2	MLABCELL_X84_Y1_N24	TDC6_inst|a|tdc|le|phase|d|inst7|combout	78
20.757	  0.249	RR	IC	1	MLABCELL_X84_Y1_N6	TDC6_inst|a|tdc|le|phase|d|inst8|dataf	79
20.844	  0.087	RR	CELL	2	MLABCELL_X84_Y1_N6	TDC6_inst|a|tdc|le|phase|d|inst8|combout	80
21.070	  0.226	RR	IC	1	MLABCELL_X84_Y1_N0	TDC6_inst|a|tdc|le|phase|d|inst9|dataf	81
21.153	  0.000	RR	IC	1	FF_X84_Y1_N2	TDC6_inst|a|tdc|le|phase|d|latch[9]|d	82
21.153	  0.083	RR	CELL	1	MLABCELL_X84_Y1_N0	TDC6_inst|a|tdc|le|phase|d|inst9|combout	83
21.415	  0.262	RR	CELL	1	FF_X84_Y1_N2	TDC6:TDC6_inst|TDC2ef:a|TDC2e:tdc|TDC1:le|TDClcell40:phase|TDClcell10:d|latch[9]	84

tdc6h.pdf

min bin: 0.060 0.064 0.061 0.063 ns, max bin: 0.783 0.962 0.736 0.755 ns, max phase 36 34 35 34
min bin: 0.058 0.067 0.061 0.063 ns, max bin: 0.872 0.800 0.671 0.759 ns, max phase 35 31 36 34
min bin: 0.062 0.062 0.062 0.062 ns, max bin: 0.617 0.625 0.741 0.688 ns, max phase 36 33 39 35
min bin: 0.061 0.064 0.061 0.064 ns, max bin: 0.727 1.083 0.727 0.764 ns, max phase 38 35 38 35
min bin: 0.058 0.067 0.062 0.062 ns, max bin: 0.698 0.800 0.741 0.750 ns, max phase 38 35 38 36
min bin: 0.059 0.065 0.062 0.062 ns, max bin: 0.888 0.980 0.617 0.750 ns, max phase 39 36 39 36
interim 80 LCELL
22.127	22.127					data path
0.000	  0.000			1	FF_X72_Y17_N2	tdc_ts[0]
0.000	  0.000	FF	CELL	71	FF_X72_Y17_N2	tdc_ts[0]|q
1.955	  1.955	FF	IC	1	LABCELL_X48_Y13_N27	tdcs|tdc[0].tdc|tdc|le|phase|a|inst0|dataf
2.038	  0.083	FF	CELL	2	LABCELL_X48_Y13_N27	tdcs|tdc[0].tdc|tdc|le|phase|a|inst0|combout
2.257	  0.219	FF	IC	1	LABCELL_X48_Y13_N24	tdcs|tdc[0].tdc|tdc|le|phase|a|inst1|datad
2.613	  0.356	FF	CELL	2	LABCELL_X48_Y13_N24	tdcs|tdc[0].tdc|tdc|le|phase|a|inst1|combout
2.833	  0.220	FF	IC	1	LABCELL_X48_Y13_N21	tdcs|tdc[0].tdc|tdc|le|phase|a|inst2|dataf
2.912	  0.079	FF	CELL	2	LABCELL_X48_Y13_N21	tdcs|tdc[0].tdc|tdc|le|phase|a|inst2|combout
3.248	  0.336	FF	IC	1	LABCELL_X48_Y13_N18	tdcs|tdc[0].tdc|tdc|le|phase|a|inst3|dataf
3.330	  0.082	FF	CELL	2	LABCELL_X48_Y13_N18	tdcs|tdc[0].tdc|tdc|le|phase|a|inst3|combout
3.554	  0.224	FF	IC	1	LABCELL_X48_Y13_N15	tdcs|tdc[0].tdc|tdc|le|phase|a|inst4|dataf
3.633	  0.079	FF	CELL	2	LABCELL_X48_Y13_N15	tdcs|tdc[0].tdc|tdc|le|phase|a|inst4|combout
3.958	  0.325	FF	IC	1	LABCELL_X48_Y13_N12	tdcs|tdc[0].tdc|tdc|le|phase|a|inst5|dataf
4.040	  0.082	FF	CELL	2	LABCELL_X48_Y13_N12	tdcs|tdc[0].tdc|tdc|le|phase|a|inst5|combout
4.257	  0.217	FF	IC	1	LABCELL_X48_Y13_N9	tdcs|tdc[0].tdc|tdc|le|phase|a|inst6|dataf
4.337	  0.080	FF	CELL	2	LABCELL_X48_Y13_N9	tdcs|tdc[0].tdc|tdc|le|phase|a|inst6|combout
4.546	  0.209	FF	IC	1	LABCELL_X48_Y13_N6	tdcs|tdc[0].tdc|tdc|le|phase|a|inst7|dataf
4.628	  0.082	FF	CELL	2	LABCELL_X48_Y13_N6	tdcs|tdc[0].tdc|tdc|le|phase|a|inst7|combout
4.857	  0.229	FF	IC	1	LABCELL_X48_Y13_N33	tdcs|tdc[0].tdc|tdc|le|phase|a|inst8|dataf
4.937	  0.080	FF	CELL	2	LABCELL_X48_Y13_N33	tdcs|tdc[0].tdc|tdc|le|phase|a|inst8|combout
5.142	  0.205	FF	IC	1	LABCELL_X48_Y13_N30	tdcs|tdc[0].tdc|tdc|le|phase|a|inst9|dataf
5.224	  0.082	FF	CELL	2	LABCELL_X48_Y13_N30	tdcs|tdc[0].tdc|tdc|le|phase|a|inst9|combout
5.463	  0.239	FF	IC	1	LABCELL_X48_Y13_N57	tdcs|tdc[0].tdc|tdc|le|phase|b|inst0|dataf
5.542	  0.079	FF	CELL	2	LABCELL_X48_Y13_N57	tdcs|tdc[0].tdc|tdc|le|phase|b|inst0|combout
5.842	  0.300	FF	IC	1	LABCELL_X48_Y13_N54	tdcs|tdc[0].tdc|tdc|le|phase|b|inst1|dataf
5.926	  0.084	FF	CELL	2	LABCELL_X48_Y13_N54	tdcs|tdc[0].tdc|tdc|le|phase|b|inst1|combout
6.141	  0.215	FF	IC	1	LABCELL_X48_Y13_N51	tdcs|tdc[0].tdc|tdc|le|phase|b|inst2|datad
6.523	  0.382	FF	CELL	2	LABCELL_X48_Y13_N51	tdcs|tdc[0].tdc|tdc|le|phase|b|inst2|combout
6.729	  0.206	FF	IC	1	LABCELL_X48_Y13_N48	tdcs|tdc[0].tdc|tdc|le|phase|b|inst3|dataf
6.811	  0.082	FF	CELL	2	LABCELL_X48_Y13_N48	tdcs|tdc[0].tdc|tdc|le|phase|b|inst3|combout
7.036	  0.225	FF	IC	1	LABCELL_X48_Y13_N45	tdcs|tdc[0].tdc|tdc|le|phase|b|inst4|dataf
7.116	  0.080	FF	CELL	2	LABCELL_X48_Y13_N45	tdcs|tdc[0].tdc|tdc|le|phase|b|inst4|combout
7.329	  0.213	FF	IC	1	LABCELL_X48_Y13_N42	tdcs|tdc[0].tdc|tdc|le|phase|b|inst5|datad
7.682	  0.353	FF	CELL	2	LABCELL_X48_Y13_N42	tdcs|tdc[0].tdc|tdc|le|phase|b|inst5|combout
7.907	  0.225	FF	IC	1	LABCELL_X48_Y13_N39	tdcs|tdc[0].tdc|tdc|le|phase|b|inst6|dataf
7.987	  0.080	FF	CELL	2	LABCELL_X48_Y13_N39	tdcs|tdc[0].tdc|tdc|le|phase|b|inst6|combout
8.203	  0.216	FF	IC	1	LABCELL_X48_Y13_N36	tdcs|tdc[0].tdc|tdc|le|phase|b|inst7|dataf
8.285	  0.082	FF	CELL	2	LABCELL_X48_Y13_N36	tdcs|tdc[0].tdc|tdc|le|phase|b|inst7|combout
8.524	  0.239	FF	IC	1	LABCELL_X48_Y13_N3	tdcs|tdc[0].tdc|tdc|le|phase|b|inst8|datad
8.906	  0.382	FF	CELL	2	LABCELL_X48_Y13_N3	tdcs|tdc[0].tdc|tdc|le|phase|b|inst8|combout
9.117	  0.211	FF	IC	1	LABCELL_X48_Y13_N0	tdcs|tdc[0].tdc|tdc|le|phase|b|inst9|datad
9.468	  0.351	FF	CELL	2	LABCELL_X48_Y13_N0	tdcs|tdc[0].tdc|tdc|le|phase|b|inst9|combout
10.043	  0.575	FF	IC	1	LABCELL_X48_Y11_N57	tdcs|tdc[0].tdc|tdc|le|phase|c|inst0|dataf
10.122	  0.079	FF	CELL	2	LABCELL_X48_Y11_N57	tdcs|tdc[0].tdc|tdc|le|phase|c|inst0|combout
10.417	  0.295	FF	IC	1	LABCELL_X48_Y11_N54	tdcs|tdc[0].tdc|tdc|le|phase|c|inst1|dataf
10.499	  0.082	FF	CELL	2	LABCELL_X48_Y11_N54	tdcs|tdc[0].tdc|tdc|le|phase|c|inst1|combout
10.718	  0.219	FF	IC	1	LABCELL_X48_Y11_N21	tdcs|tdc[0].tdc|tdc|le|phase|c|inst2|datad
11.098	  0.380	FF	CELL	2	LABCELL_X48_Y11_N21	tdcs|tdc[0].tdc|tdc|le|phase|c|inst2|combout
11.434	  0.336	FF	IC	1	LABCELL_X48_Y11_N18	tdcs|tdc[0].tdc|tdc|le|phase|c|inst3|dataf
11.515	  0.081	FF	CELL	2	LABCELL_X48_Y11_N18	tdcs|tdc[0].tdc|tdc|le|phase|c|inst3|combout
12.094	  0.579	FF	IC	1	LABCELL_X48_Y11_N45	tdcs|tdc[0].tdc|tdc|le|phase|c|inst4|dataf
12.174	  0.080	FF	CELL	2	LABCELL_X48_Y11_N45	tdcs|tdc[0].tdc|tdc|le|phase|c|inst4|combout
12.387	  0.213	FF	IC	1	LABCELL_X48_Y11_N42	tdcs|tdc[0].tdc|tdc|le|phase|c|inst5|datad
12.740	  0.353	FF	CELL	2	LABCELL_X48_Y11_N42	tdcs|tdc[0].tdc|tdc|le|phase|c|inst5|combout
12.965	  0.225	FF	IC	1	LABCELL_X48_Y11_N39	tdcs|tdc[0].tdc|tdc|le|phase|c|inst6|dataf
13.045	  0.080	FF	CELL	2	LABCELL_X48_Y11_N39	tdcs|tdc[0].tdc|tdc|le|phase|c|inst6|combout
13.261	  0.216	FF	IC	1	LABCELL_X48_Y11_N36	tdcs|tdc[0].tdc|tdc|le|phase|c|inst7|dataf
13.343	  0.082	FF	CELL	2	LABCELL_X48_Y11_N36	tdcs|tdc[0].tdc|tdc|le|phase|c|inst7|combout
13.561	  0.218	FF	IC	1	LABCELL_X48_Y11_N33	tdcs|tdc[0].tdc|tdc|le|phase|c|inst8|datad
13.943	  0.382	FF	CELL	2	LABCELL_X48_Y11_N33	tdcs|tdc[0].tdc|tdc|le|phase|c|inst8|combout
14.148	  0.205	FF	IC	1	LABCELL_X48_Y11_N30	tdcs|tdc[0].tdc|tdc|le|phase|c|inst9|dataf
14.230	  0.082	FF	CELL	2	LABCELL_X48_Y11_N30	tdcs|tdc[0].tdc|tdc|le|phase|c|inst9|combout
14.465	  0.235	FF	IC	1	LABCELL_X48_Y11_N27	tdcs|tdc[0].tdc|tdc|le|phase|d|inst0|dataf
14.544	  0.079	FF	CELL	2	LABCELL_X48_Y11_N27	tdcs|tdc[0].tdc|tdc|le|phase|d|inst0|combout
14.848	  0.304	FF	IC	1	LABCELL_X48_Y11_N24	tdcs|tdc[0].tdc|tdc|le|phase|d|inst1|dataf
14.930	  0.082	FF	CELL	2	LABCELL_X48_Y11_N24	tdcs|tdc[0].tdc|tdc|le|phase|d|inst1|combout
15.146	  0.216	FF	IC	1	LABCELL_X48_Y11_N51	tdcs|tdc[0].tdc|tdc|le|phase|d|inst2|dataf
15.226	  0.080	FF	CELL	2	LABCELL_X48_Y11_N51	tdcs|tdc[0].tdc|tdc|le|phase|d|inst2|combout
15.431	  0.205	FF	IC	1	LABCELL_X48_Y11_N48	tdcs|tdc[0].tdc|tdc|le|phase|d|inst3|dataf
15.513	  0.082	FF	CELL	2	LABCELL_X48_Y11_N48	tdcs|tdc[0].tdc|tdc|le|phase|d|inst3|combout
15.750	  0.237	FF	IC	1	LABCELL_X48_Y11_N15	tdcs|tdc[0].tdc|tdc|le|phase|d|inst4|dataf
15.830	  0.080	FF	CELL	2	LABCELL_X48_Y11_N15	tdcs|tdc[0].tdc|tdc|le|phase|d|inst4|combout
16.036	  0.206	FF	IC	1	LABCELL_X48_Y11_N12	tdcs|tdc[0].tdc|tdc|le|phase|d|inst5|dataf
16.118	  0.082	FF	CELL	2	LABCELL_X48_Y11_N12	tdcs|tdc[0].tdc|tdc|le|phase|d|inst5|combout
16.342	  0.224	FF	IC	1	LABCELL_X48_Y11_N9	tdcs|tdc[0].tdc|tdc|le|phase|d|inst6|dataf
16.422	  0.080	FF	CELL	2	LABCELL_X48_Y11_N9	tdcs|tdc[0].tdc|tdc|le|phase|d|inst6|combout
16.626	  0.204	FF	IC	1	LABCELL_X48_Y11_N6	tdcs|tdc[0].tdc|tdc|le|phase|d|inst7|dataf
16.708	  0.082	FF	CELL	2	LABCELL_X48_Y11_N6	tdcs|tdc[0].tdc|tdc|le|phase|d|inst7|combout
16.926	  0.218	FF	IC	1	LABCELL_X48_Y11_N3	tdcs|tdc[0].tdc|tdc|le|phase|d|inst8|dataf
17.006	  0.080	FF	CELL	2	LABCELL_X48_Y11_N3	tdcs|tdc[0].tdc|tdc|le|phase|d|inst8|combout
17.217	  0.211	FF	IC	1	LABCELL_X48_Y11_N0	tdcs|tdc[0].tdc|tdc|le|phase|d|inst9|datad
17.568	  0.351	FF	CELL	2	LABCELL_X48_Y11_N0	tdcs|tdc[0].tdc|tdc|le|phase|d|inst9|combout
18.294	  0.726	FF	IC	1	LABCELL_X48_Y10_N57	tdcs|tdc[0].tdc|tdc|le|phase|e|inst0|dataf
18.373	  0.079	FF	CELL	2	LABCELL_X48_Y10_N57	tdcs|tdc[0].tdc|tdc|le|phase|e|inst0|combout
18.668	  0.295	FF	IC	1	LABCELL_X48_Y10_N54	tdcs|tdc[0].tdc|tdc|le|phase|e|inst1|dataf
18.750	  0.082	FF	CELL	2	LABCELL_X48_Y10_N54	tdcs|tdc[0].tdc|tdc|le|phase|e|inst1|combout
18.970	  0.220	FF	IC	1	LABCELL_X48_Y10_N21	tdcs|tdc[0].tdc|tdc|le|phase|e|inst2|datad
19.350	  0.380	FF	CELL	2	LABCELL_X48_Y10_N21	tdcs|tdc[0].tdc|tdc|le|phase|e|inst2|combout
19.687	  0.337	FF	IC	1	LABCELL_X48_Y10_N18	tdcs|tdc[0].tdc|tdc|le|phase|e|inst3|dataf
19.769	  0.082	FF	CELL	2	LABCELL_X48_Y10_N18	tdcs|tdc[0].tdc|tdc|le|phase|e|inst3|combout
20.007	  0.238	FF	IC	1	LABCELL_X48_Y10_N45	tdcs|tdc[0].tdc|tdc|le|phase|e|inst4|dataf
20.087	  0.080	FF	CELL	2	LABCELL_X48_Y10_N45	tdcs|tdc[0].tdc|tdc|le|phase|e|inst4|combout
20.300	  0.213	FF	IC	1	LABCELL_X48_Y10_N42	tdcs|tdc[0].tdc|tdc|le|phase|e|inst5|datad
20.653	  0.353	FF	CELL	2	LABCELL_X48_Y10_N42	tdcs|tdc[0].tdc|tdc|le|phase|e|inst5|combout
20.895	  0.242	FF	IC	1	LABCELL_X48_Y10_N9	tdcs|tdc[0].tdc|tdc|le|phase|e|inst6|dataf
20.975	  0.080	FF	CELL	2	LABCELL_X48_Y10_N9	tdcs|tdc[0].tdc|tdc|le|phase|e|inst6|combout
21.179	  0.204	FF	IC	1	LABCELL_X48_Y10_N6	tdcs|tdc[0].tdc|tdc|le|phase|e|inst7|dataf
21.261	  0.082	FF	CELL	2	LABCELL_X48_Y10_N6	tdcs|tdc[0].tdc|tdc|le|phase|e|inst7|combout
21.498	  0.237	FF	IC	1	LABCELL_X48_Y10_N33	tdcs|tdc[0].tdc|tdc|le|phase|e|inst8|dataf
21.578	  0.080	FF	CELL	2	LABCELL_X48_Y10_N33	tdcs|tdc[0].tdc|tdc|le|phase|e|inst8|combout
21.783	  0.205	FF	IC	1	LABCELL_X48_Y10_N30	tdcs|tdc[0].tdc|tdc|le|phase|e|inst9|dataf
21.865	  0.082	FF	CELL	2	LABCELL_X48_Y10_N30	tdcs|tdc[0].tdc|tdc|le|phase|e|inst9|combout
21.865	  0.000	FF	IC	1	FF_X48_Y10_N31	tdcs|tdc[0].tdc|tdc|le|phase|e|latch[9]|d
22.127	  0.262	FF	CELL	1	FF_X48_Y10_N31	TDCn:tdcs|TDC2ef:tdc[0].tdc|TDC2e:tdc|TDC1:le|TDClcell80:phase|TDClcell10:e|latch[9]