VME-GRIF-ADC16-Rev1: Difference between revisions

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! bits !! Rev !! Quartus name !! Description
! bits !! Rev !! Quartus name !! Description
|-
|-
| 2 || x || DAC_PD || "DAC power down", set to 0
| 0 || x || ~DAC_PD || inverted "DAC power down", 1=enable the DAC, 0=power down the DAC
|-
|-
| 3 || x || DAC_SELIQ || select one of the DAC outputs, set to 0 to use the right hand LEMO output
| 1 || x || DAC_SELIQ || select one of the DAC outputs, set to 0 to use the right hand LEMO output
|-
|-
| 0 || x || DAC_XOR || set to 0
| 2 || x || DAC_XOR || invert the dac data, set to 0
|-
|-
| 1 || x || DAC_TORB || set to 1
| 3 || x || DAC_TORB || select 1-complement data format, set to 1
|-
| 2 || x || DAC_PD || "DAC power down", set to 0
|-
| 3 || x || DAC_SELIQ || select one of the DAC outputs, set to 0 to use the right hand LEMO output
|-
|-
| 4 || x || pulser_enable || 0: dac_data drives the DAC directly, 1: dac_data is gated by the eSATA SYNC signal (DAQ trigger)
| 4 || x || pulser_enable || 0: dac_data drives the DAC directly, 1: dac_data is gated by the eSATA SYNC signal (DAQ trigger)
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| 7..6 || x || unused || should be set to zero
| 7..6 || x || unused || should be set to zero
|-
|-
| 15..8 || x || top_len || delay from ramp up to ramp down
| 15..8 || x || top_len || time between ramp up and ramp down in DAC samples (16ns)
|-
|-
| 23..16 || x || d_down || ramp down rate
| 23..16 || x || d_down || ramp down rate, DAC counts per 1 DAC sample (16ns)
|-
|-
| 31..24 || x || d_up || ramp up rate
| 31..24 || x || d_up || ramp up rate, DAC counts per 1 DAC sample (16ns)
|}
|}


Revision as of 13:10, 8 May 2018

VME-GRIF-ADC16-Rev1

Links

Front panel connectors

From top to bottom:

  • SFP connector - 1GigE fiber/copper/DAC
  • 4 LEDs
  • eSATA - clock+trigger input
  • FMC daughter card slot
  • 2 LEMO
  • 16 MCX analog inputs

Onboard switches and connectors

  • FP_SW1
  • FP_SW2
  • JTAG FPGA
  • JTAG MAXV
  • 2x VME address rotary switches
  • "reset" button
  • SD card slot
  • "Display" connector
  • 16x 3 position switches for gain and input (front/back) selection

Onboard LEDs

|
|
|0|1|2|3|
|
|
  • FP_LED0 - "clock_synched" (from qsys)
  • FP_LED1 - "led_trigger_input" (same as "trigger_input_adc")
  • FP_LED2 - "run active" (same as "force_run")
  • FP_LED3 - "led_link" (from qsys)

Onboard thermometers

  • Temperature readout chip: LTC2983CLX#PBF
  • Thermometers: 9x RTD1..RTD9 type PT100. The first 8 are on the back of the PCB next to the analog amps, the last one is on the front next to the FPGA.
RTD1 sensor_temp[0] opamp 1-3
RTD2 [1] amp 2-4
RTD3 [2] 5-7
RTD4 [3] 6-8
RTD5 [4] 9-11
RTD6 [5] 10-12
RTD7 [6] 13-15
RTD8 [7] 14-16
RTD9 [8] between the FPGA and U11-U15

Onboard hardware

  • 2-output DAC: Maxim MAX5877EGK+D, output driver TI OPA 2690IDG4, range +/- 5V
  • I2C MAC chip: Microchip tech 24AA02E48T-I/OT, I2C addr 0xA0, MAC_SCL, MAC_SDA
  • FPGA Boot flash: Micron Serial NOR flash memory: N25Q00AA13GSF40G

Board schematics

File:GRIF-ADC16_Rev1.pdf

Firmware

https://bitbucket.org/teamalphag/adc_firmware/overview

ESPER variables

name RR Type Rev Description
ag.adc16_threshold RW INT16 x ADC threshold for the 100MHz ADC discriminators
ag.adc32_threshold RW INT16 x ADC threshold for the 62.5MHz ADC discriminators
ag.adc16_bits RO UINT16 x Output of the 16x 100MHz ADC discriminators, goes into sas_bits (16 bits)
ag.adc32_bits RO UINT32 x Output of the 32x 62.5MHz ADC discriminators, goes into sas_bits (32 bits)
ag.dac_data RW UINT32 x DAC data, read more #ag.dac_data
ag.dac_ctrl RW UINT32 x DAC control, read more #ag.dac_ctrl

ag.dac_data

bits Rev Description
15..0 x DAC output amplitude, +/-8000
31..16 x DAC pulse baseline

ag.dac_ctrl

bits Rev Quartus name Description
0 x ~DAC_PD inverted "DAC power down", 1=enable the DAC, 0=power down the DAC
1 x DAC_SELIQ select one of the DAC outputs, set to 0 to use the right hand LEMO output
2 x DAC_XOR invert the dac data, set to 0
3 x DAC_TORB select 1-complement data format, set to 1
4 x pulser_enable 0: dac_data drives the DAC directly, 1: dac_data is gated by the eSATA SYNC signal (DAQ trigger)
5 x ramp_enable DAC is ramped using linear ramp
7..6 x unused should be set to zero
15..8 x top_len time between ramp up and ramp down in DAC samples (16ns)
23..16 x d_down ramp down rate, DAC counts per 1 DAC sample (16ns)
31..24 x d_up ramp up rate, DAC counts per 1 DAC sample (16ns)

FMC modules

FMC-ADC32-Rev0

FMC-ADC32-Rev1

FMC-DualMiniSas-Rev1

FMC-SfpMiniSasEsata-Rev2

(note: not used on the GRIF16, this information is to be moved to the ALPHA-T page)

ZZZ

ZZZ

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