VME-NEW-IO: Difference between revisions

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* V792 ADC gate and delay generator (M11 test beams, DRAGON, TRINAT, S1249, etc)
* V792 ADC gate and delay generator (M11 test beams, DRAGON, TRINAT, S1249, etc)
* custom trigger logic (M11 test beams, DRAGON, ALPHA, TRINAT, S1249)
* custom trigger logic (M11 test beams, DRAGON, ALPHA, TRINAT, S1249)
* clock and trigger synchronization between 2 VME crates (DRAGON) and 2 IO32 modules (TRINAT)
* clock and trigger synchronization between 2 VME crates (DRAGON), 2 IO32 modules (TRINAT), separate DAQs (M11 beam tests)
* in addition there is a 1ns-time-bin delay-line TDC (never used)
* in addition there is a 1ns-time-bin delay-line TDC (never used)


Number of I/Os used:
Number of I/Os used:
* T2K/M11 beam tests - 8 NIM in, 8 NIM out
* S1249 muonium production test (M15) - 4 NIM in, 8 NIM out, (FIXME: ECL scalers?)
* ALPHA2 Si detector DAQ (CERN) - 16 NIM in, 16 NIM out
* ALPHA2 Si detector DAQ (CERN) - 16 NIM in, 16 NIM out
* DRAGON - 4 NIM in, 8 NIM out
* TRINAT TTL - (FIXME: 4 TTL in?)
* TRINAT - 8 NIM in, 8 NIM out
* TRINAT 2014 - 10 NIM in, 16 NIM out
* IRIS - ???
* TITAN EC (orchid) - 8 TTL in
* TREK, IRIS - 4 NIM in, 4 NIM out (trigger, busy, 40 MHz V1190 clock, 20 MHz VF48 clock)
* BNMR/BNQR - ?
* PTF - ?
Note: existing IO32 has significant delay from LEMO connector to FPGA logic (NIM-to-LVTTL converter, FPGA input pin,etc) and from FPGA logic to NIM output pin (FPGA output pin delay, LVTTL-to-NIM converter, etc). If using ECL inputs, add delay in NIM-to-ECL converter and in the ECL ribbon cable. FIXME: what is this delay?
Conclusion: for most common cases, 8 NIM in, 8 NIM out is sufficient.


= AAA =
= AAA =

Revision as of 16:59, 9 March 2016

Use cases of existing VME-NIMIO32 board

Specs of the existing board:

  • 6U VME single width
  • VME A32/D32, firmware implements A24/D32 single word and A24/BLT32 block transfers. There is no VME drivers on the A-lines so cannot do MBLT64, 2eVME, 2eSST.
  • Altera Cyclone1 FPGA, 6k LE, 180 i/o pins, 100-200 MHz clock speeds.
  • 16 NIM inputs (convertable to TTL), LEMO connectors
  • 16 ECL/LVDS inputs, LeCroy 4616 compatible ECL ribbon cable connector
  • 16 NIM outputs, LEMO connectors
  • 32 LEDs (one for each LEMO connector)

Main uses of the IO32 board have been:

  • trigger latch, trigger timestamp and busy logic daq synchronization (LXe, IRIS, M11 test beams, DRAGON, ALPHA, EMMA, TRINAT, TREK, PTF, S1249 muonium production test, etc)
  • scalers (16 ch, up to 200 MHz, deadtimeless) (most users)
  • timestamp counter (4 ch, 100 MHz) (TRINAT, etc)
  • 40MHz V1190 and 20MHz VF48 clock generator and trigger synchronization (LXe, IRIS, TREK, S1249, etc)
  • V792 ADC gate and delay generator (M11 test beams, DRAGON, TRINAT, S1249, etc)
  • custom trigger logic (M11 test beams, DRAGON, ALPHA, TRINAT, S1249)
  • clock and trigger synchronization between 2 VME crates (DRAGON), 2 IO32 modules (TRINAT), separate DAQs (M11 beam tests)
  • in addition there is a 1ns-time-bin delay-line TDC (never used)

Number of I/Os used:

  • T2K/M11 beam tests - 8 NIM in, 8 NIM out
  • S1249 muonium production test (M15) - 4 NIM in, 8 NIM out, (FIXME: ECL scalers?)
  • ALPHA2 Si detector DAQ (CERN) - 16 NIM in, 16 NIM out
  • DRAGON - 4 NIM in, 8 NIM out
  • TRINAT TTL - (FIXME: 4 TTL in?)
  • TRINAT - 8 NIM in, 8 NIM out
  • TRINAT 2014 - 10 NIM in, 16 NIM out
  • IRIS - ???
  • TITAN EC (orchid) - 8 TTL in
  • TREK, IRIS - 4 NIM in, 4 NIM out (trigger, busy, 40 MHz V1190 clock, 20 MHz VF48 clock)
  • BNMR/BNQR - ?
  • PTF - ?

Note: existing IO32 has significant delay from LEMO connector to FPGA logic (NIM-to-LVTTL converter, FPGA input pin,etc) and from FPGA logic to NIM output pin (FPGA output pin delay, LVTTL-to-NIM converter, etc). If using ECL inputs, add delay in NIM-to-ECL converter and in the ECL ribbon cable. FIXME: what is this delay?

Conclusion: for most common cases, 8 NIM in, 8 NIM out is sufficient.

AAA