DL-TDC

DL-TDC DarkLight FPGA TDC

ODB settings

• dl_enable - yes/no - enable or disable TDC readout in the midas frontend
• dl_ctrl - 32 bits of general control

bit - quartus - description
  0 - dl_ctrl_gate   - jam TDC gate open, enable un-triggered free-running mode
  1 - dl_ctrl_gate_A - gate TDC from A-side trigger
  2 - dl_ctrl_gate_B - gate TDC from B-side trigger
  3 - dl_ctrl_gate_AB - gate TDC from A*B
  4 - dl_ctrl_gate_T - gate TDC from T trigger (T = A*B)
  5 - dl_ctrl_ena_A - enable TDC channel 32 (A)
  6 - dl_ctrl_ena_B - enable TDC channel 33 (B)
  7 - dl_ctrl_ena_T - enable TDC channel 34 (T)
15..8 - dl_ctrl_gate_w - TDC gate width in units of 8 ns
31..16 - not used

• dl_trg_mask - 16 bits of trigger mask

bit - description
  0 - enable A pair 1-9
  1 - enable A pair 2-10
  2 - enable A pair 3-11
  3 - enable A pair 4-12
  4
  5
  6
  7
  8 - enable B pair 5-13
  9 - enable B pair 6-14
 10 - enable B pair 7-15
 11 - enable B pair 8-16

• dl_tdc_mask - 32 bits to enable 32 TDC channels, in sequence

Channel map

// map TDC cable to SiPM channels
   
   assign ch[1]  = tdc[0];
   assign ch[2]  = tdc[1];
   assign ch[3]  = tdc[10];
   assign ch[4]  = tdc[11];
   assign ch[5]  = tdc[2];
   assign ch[6]  = tdc[3];
   assign ch[7]  = tdc[8];
   assign ch[8]  = tdc[9];

   assign ch[9]  = tdc[15];
   assign ch[10] = tdc[14];
   assign ch[11] = tdc[7];
   assign ch[12] = tdc[6];
   assign ch[13] = tdc[13];
   assign ch[14] = tdc[12];
   assign ch[15] = tdc[5];
   assign ch[16] = tdc[4];

   assign ch[16+1]  = tdc[16+0];  // 16
   assign ch[16+2]  = tdc[16+1];  // 17
   assign ch[16+3]  = tdc[16+10]; // 26
   assign ch[16+4]  = tdc[16+11]; // 27
   assign ch[16+5]  = tdc[16+2];  // 18
   assign ch[16+6]  = tdc[16+3];  // 19
   assign ch[16+7]  = tdc[16+8];  // 24
   assign ch[16+8]  = tdc[16+9];  // 25

   assign ch[16+9]  = tdc[16+15]; // 31
   assign ch[16+10] = tdc[16+14]; // 30
   assign ch[16+11] = tdc[16+7];  // 23
   assign ch[16+12] = tdc[16+6];  // 22
   assign ch[16+13] = tdc[16+13]; // 29
   assign ch[16+14] = tdc[16+12]; // 28
   assign ch[16+15] = tdc[16+5];  // 21
   assign ch[16+16] = tdc[16+4];  // 20

   // compute SiPM pair concindences
   
   assign A[0] = ch[1] & ch[9]  & enable_input[0]; //  0 * 15 -> pair1
   assign A[1] = ch[2] & ch[10] & enable_input[1]; //  1 * 14 -> pair2
   assign A[2] = ch[3] & ch[11] & enable_input[2]; // 10 *  7 -> pair3
   assign A[3] = ch[4] & ch[12] & enable_input[3]; // 11 *  6 -> pair4
   assign A[4] = ch[5] & ch[13] & enable_input[4];
   assign A[5] = ch[6] & ch[14] & enable_input[5];
   assign A[6] = ch[7] & ch[15] & enable_input[6];
   assign A[7] = ch[8] & ch[16] & enable_input[7];

   assign B[0] = ch[16+1] & ch[16+9]  & enable_input[8];  // 16 * 31
   assign B[1] = ch[16+2] & ch[16+10] & enable_input[9];  // 17 * 30
   assign B[2] = ch[16+3] & ch[16+11] & enable_input[10]; // 26 * 23
   assign B[3] = ch[16+4] & ch[16+12] & enable_input[11]; // 27 * 22
   assign B[4] = ch[16+5] & ch[16+13] & enable_input[12]; // 18 * 29 -> pair5
   assign B[5] = ch[16+6] & ch[16+14] & enable_input[13]; // 19 * 28 -> pair6
   assign B[6] = ch[16+7] & ch[16+15] & enable_input[14]; // 24 * 21 -> pair7
   assign B[7] = ch[16+8] & ch[16+16] & enable_input[15]; // 25 * 20 -> pair8

   wire        A_or = |A;
   wire        B_or = |B;

   //wire        A_or = A[0] | A{1] | A{2] | A[3] | A[4] | A{5] | A{6] | A[7];
   //wire        B_or = B[0] | B{1] | B{2] | B[3] | B[4] | B{5] | B{6] | B[7];

   wire        AB_and = A_or & B_or;

D3 delay tuning

9.109	GPIO_1_20	dl|WideOr0|combout -> 1
9.025	GPIO_1_33	dl|WideOr0|combout -> 1
9.022	GPIO_1_26	dl|WideOr0|combout -> 0
8.966	GPIO_1_28	dl|WideOr0|combout -> 5            = 8.494 add 1
8.787	GPIO_1_22	dl|WideOr0|combout -> 0
8.714	GPIO_1_21	dl|WideOr0|combout -> 5
8.711	GPIO_1_34	dl|WideOr0|combout -> 0
8.597	GPIO_1_30	dl|WideOr0|combout -> 0            = 8.240 add 1 -> 1 = 9.733 sub 1
8.590	GPIO_1_29	dl|WideOr0|combout -> 1 add 1 -> 2 = 9.588 sub 1
8.506	GPIO_1_27	dl|WideOr0|combout -> 4 add 1 --------------------> 5 = 10.097 sub 1
8.453	GPIO_1_24	dl|WideOr0|combout -> 2 add 1 -> 3 = 9.588 sub 1
8.412	GPIO_1_35	dl|WideOr0|combout add 1
8.380	GPIO_1_31	dl|WideOr0|combout -> 4 add 1 -> 5 = 9.208 sub 1
8.312	GPIO_1_25	dl|WideOr0|combout -> 1 add 1 -> 2 = 8.555 add 1 -> 3 = 9.379
7.992	GPIO_1_32	dl|WideOr0|combout add 2
7.248	GPIO_1_23	dl|WideOr0|combout -> 2 add 3 -> 5 = 9.425 sub 1

9.339	GPIO_0_14	dl|WideOr1|combout -> 6 sub 1 -> 5 = 8.587
9.207	GPIO_0_2	dl|WideOr1|combout -> 7 sub 1 -> 6 = 8.360 add 1
9.174	GPIO_0_10	dl|WideOr1|combout -> 6
9.161	GPIO_0_6	dl|WideOr1|combout -> 7
9.105	GPIO_0_11	dl|WideOr1|combout -> 7
9.019	GPIO_0_7	dl|WideOr1|combout -> 7
8.731	GPIO_0_15	dl|WideOr1|combout add 0 -> 0 = 8.540 add 1
8.462	GPIO_0_12	dl|WideOr1|combout add 1 -> 1 = 9.189
8.256	GPIO_0_4	dl|WideOr1|combout add 2 -> 2 = 9.750 sub 1
8.214	GPIO_0_5	dl|WideOr1|combout add 2
8.182	GPIO_0_1	dl|WideOr1|combout add 2
7.328	GPIO_0_3	dl|WideOr1|combout add 3
6.584	GPIO_0_8	dl|WideOr1|combout add 5
6.409	GPIO_0_13	dl|WideOr1|combout add 5 -> 5 =  9.943 sub 2
6.009	GPIO_0_9	dl|WideOr1|combout add 6 -> 6 = 10.189 sub 2
5.917	GPIO_0_0	dl|WideOr1|combout add 6