VME-CDM: Difference between revisions
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== VME-CDM - GRIFFIN Clock Distribution Module == | |||
=== References === | |||
* edev login: no public access, sorry! | |||
* edev-pps login: no public access, sorry! | |||
* ladd00 svn login: username: svn, password: svn | |||
* [http://edev.triumf.ca/projects/edevel00163] VME-CDM project page on edev.triumf.ca | |||
* [https://edev.triumf.ca/projects/edevel00163/repository/entry/tags/Rev2/Altium/VME%20-%20Clock%20Distribution%20Module.pdf] Rev2 board schematics (link to edev) | |||
* [https://edev-group.triumf.ca/hw/vme/cdm] VME-CDM project page on edev gitlab | |||
=== General characteristics === | |||
==== Photos ==== | |||
[[Image:VME-xxx.jpg|150px|Rev2 boards]] | |||
==== Available hardware ==== | |||
* Altera cyclone 1 FPGA: EP1C6Q240C6N | |||
* Serial flash for FPGA configuration: Altera EPCS16 | |||
* External SDRAM memory | |||
* VME interface: VME-D[31..0] bidirectional, VME-A[19..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible. | |||
* 16 NIM outputs | |||
* 16 NIM inputs | |||
* 16 ECL/LVDS inputs compatible with LeCroy 4616 ECL/NIM/ECL converter. (Except: Rev0 boards have an incompatible ECL connector) | |||
* 16 "red" and 16 "green" LEDs | |||
* 1 "VME access" LED | |||
* 1 RJ-45 high speed serial I/O interface | |||
==== Firmware functions ==== | |||
Revision as of 18:04, 8 September 2017
VME-CDM - GRIFFIN Clock Distribution Module
References
- edev login: no public access, sorry!
- edev-pps login: no public access, sorry!
- ladd00 svn login: username: svn, password: svn
- [1] VME-CDM project page on edev.triumf.ca
- [2] Rev2 board schematics (link to edev)
- [3] VME-CDM project page on edev gitlab
General characteristics
Photos
Available hardware
- Altera cyclone 1 FPGA: EP1C6Q240C6N
- Serial flash for FPGA configuration: Altera EPCS16
- External SDRAM memory
- VME interface: VME-D[31..0] bidirectional, VME-A[19..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
- 16 NIM outputs
- 16 NIM inputs
- 16 ECL/LVDS inputs compatible with LeCroy 4616 ECL/NIM/ECL converter. (Except: Rev0 boards have an incompatible ECL connector)
- 16 "red" and 16 "green" LEDs
- 1 "VME access" LED
- 1 RJ-45 high speed serial I/O interface