VME-NIMIO32-Rev3

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VME-NIMIO32-Rev3

Links

General information

Hardware

  • FPGA: Cyclone5 5CGXFC7D7F27C8N
  • boot flash: EPCQ256
  • clock cleaner: IDT 8T49N241-009NLG1, I2C addr 1111'100b
  • mac address: Microchip 24AA02E48T-I/OT, I2C address 0xA0, bus MAC_SCL, MAC_SDA
  • eeprom: Microchip 24AA04T-I/OT, I2C address 0xA0, bus SCLK, SDATA
  • clocks: OSC1, OSC2: 125 MHz, OSC3: 10 MHz
  • front panel double SATA connector: 1 serial communication, 1 clock (in our out) and trigger (in or out)
  • on board 3 double SATA connectors: 7 serial communication.
  • front panel SFP, (1/2.5/5 Gige ethernet?)
  • 16 double LEMO connectors: switchable between input and output. input: NIM or TTL. output: NIM
  • 16 ECL or LVDS inputs: onboard 34-pin header connector, LeCroy 4616 compatible.

Front panel connectors

(CHRONOBOX)
|
| LEMO - CLK_IN - jumpers: SINE<->CLK<->NIM/TTL and NIM<->CLK<->TTL
|
| ECL P1
| 32
| |
| 1
|
| ECL P2
| 32
| |
| 1
|
| PLED - power-on LED
|
| jumper: bank A direction IN<->X<->OUT
| LEMO 0-1
| LED 0-1
| LEMO 2-3
| LED 2-3
|
| jumper: bank B direction IN<->X<->OUT
| LEMO 4-5
| LED 4-5
| LEMO 6-7
| LED 6-7
|

Input channel mapping

  • 0+16 : LVDS/ECL connector
  • 16+32 : LEMO inputs
  • 48+2: ESATA CLK, ESATA TRIG
  • 50+2: CLN_CLKOUT1, CLN_CLKOUT2 from clock cleaner
  • 52+1 : LVDS_OSC1 (125 MHz oscillator)

Firmware

for building firmware use: /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh 

git clone git@bitbucket.org:ttriumfdaq/vmeio.git
cd vmeio
/opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
make
make jic
make load_jic

for jtag access, use /daq/quartus/13.1.3.178/quartus/bin/quartus 

daq01:intelFPGA$ /daq/quartus/13.1.3.178/quartus/bin/jtagconfig 
1) USB-Blaster [1-8]
  02B030DD   5CGTFD7(B5|C5|D5)/5CGXBC7B6/..

Firmware registers

vmeio register set is a mix of IO32 registers and chronobox registers. 

reg | rw/ro | quartus name | firmware | description
0 | ro | sof_revision_in | all | firmware revision timestamp code
#0 | wo | latch_scalers_out, zero_scalers_out | all | see [[#reg_0_write_bits]]
1 | rw | command | all | see [[#reg_1_command]]
2 | rw | reg2_led_ctrl | all | LED control, see [[#reg_2_led_control_bits]]
3 | rw | reg3_fp_led_out | all | FP LED output
4 | rw | reg4_test | all | 32-bit read-write test register
#5 | rw | flash_programmer_in, reg5_flash_programmer_out | 0x5b6de806 | 0xABCD srunner flash programmer
6 | ro | ecl_in_async | all | read state of ECL inputs
#7 | ro | reg7_test_in | all | ???
8 | rw | flash_programmer_in, reg8_flash_programmer_out | all | 0xABCD srunner_vme flash programmer
#8 | rw | scaler_addr_out, reg8_scaler_data_in | all | top 16 bits of address becomes scaler bus address, 32 bit read is the corresponding scaler data
9 | ro | lemo_in_async | all | read state of LEMO inputs
#A | ro | gpio_in | all | read state of GPIO inputs
11 | rw | reg11_lemo_out | all | LEMO output data
#C | rw | regC_gpio_out | all | GPIO output data
#D | rw | regD_out_enable_out | all | enable output tristates: [31:24] - LEMO_OUT, [17:0] - GPIO_OUT
#E | rw | regE, reconfig_out | 0x5b6de806 | FPGA reboot: write inverted firmware revision (reg0) to reboot the FPGA
#F | ro | regF_input_num_in | 0x5b89e4b4 | number of chronobox inputs (to read scalers, add 1 for the clock counter)
#10 | ro | reg10_fifo_status | 0x5b8de2b0 | data fifo status, see below
#11 | ro | reg11_fifo_data | 0x5b8de2b0 | data fifo data, see below
#12 | rw | cb_invert_a | 0x5bf7557e | invert inputs 31..0
#13 | rw | cb_invert_b | 0x5bf7557e | invert inputs 63..32
#14 | rw | cb_enable_le_a | 0x5bf7557e | enable TSC leading edge
#15 | rw | cb_enable_le_b | 0x5bf7557e | enable TSC leading edge
#16 | rw | cb_enable_te_a | 0x5bf7557e | enable TSC trailing edge
#17 | rw | cb_enable_te_b | 0x5bf7557e | enable TSC trailing edge
#18 | ro | fc_ext_clk_100_counter | 0x5bf7557e | external clock frequency counter 100MHz reference
#19 | ro | fc_ext_clk_ext_counter | 0x5bf7557e | external clock frequency counter
#1A | ro | fc_ts_clk_100_counter | 0x5bf7557e | timestamp clock frequency counter 100MHz reference
#1B | ro | fc_ts_clk_ts_counter | 0x5bf7557e | timestamp clock frequency counter
#1C | ro | ts_clk_pll_status | 0x5bf7557e | timestamp clock PLL status
#1D | rw | cb_lemo_out_mux_ctrl | 0x5bfdc798 | 8*4 bits to control 8 LEMO output multiplexers (4 bits/16 options each mux)
#1E | rw | cb_sync_mask[31:0] | NEXT | source of chronobox sync signal, low bits
#1F | rw | cb_sync_mask[63:32] | NEXT | source of chronobox sync signal, high bits

reg 0 write bits

    2. 

  2. bit | fw revision | quartus signal | description
    3. 

  3. 0 | all | | latch scalers
    4. 

  4. 1 | all | | zero scalers
    5. 

  5. 2 | ... | fifo_rdreq_out | fifo_rdreq_out
    6. 

  6. 3 | ... | ts_clk_pll_extswitch_out | clear ts_clk_pll_extswitch_out
    7. 

  7. 4 | ... | ts_clk_pll_extswitch_out | set ts_clk_pll_extswitch_out
    8. 

  8. 5 | NEXT | sync_arm | arm the synchronization sequence
    9. 

  9. 6 | NEXT | cb_sync | activate the synchronization
    10. 



reg 1 command


  • command 0: nothing
    • 

  • command 1: IO32_CMD_RESET: issue reset signal
    • 

  • command 2: IO32_CMD_FPGA_RECONFIGURE: reboot the FPGA


reg 2 led control bits


bits:



  • 0+4: select FP LED bus mux:

    • 0: default bus
      • 

    • 1: fp_led_out
      • 

    • 2: LEMO outputs
      • 

    • 3: LEMO inputs
      • 

    • 4: LVDS/ECL inputs
      • 

    • 5: OR of LEMO outputs, LEMO inputs and LVDS/ECL inputs
    • 

  • 4+: unconnected







reg N


Data FIFO status bits:



31: fifo_full
30: fifo_empty
29: 0
28: 0
24+4: 0
0+24: fifo_usedw



reg 0x1C


Timestamp clock PLL status bits:



31 : PLL locked
30 : PLL active clock (0=internal, 1=external
29 : external clock bad
28 : internal clock bad
27 : ts_clk_pll_extswitch
0..26 : not used



Required board mods


  • VME_LWORD jumper to VME_SERB
    • 

  • VME_A29 jumper to ???
    • 

  • RGB_LED_SDI jumper to ???
    • 

  • -3V external power supply


Test status


  • power up ok
    • 

  • fpga jtag ok
    • 

  • flash load ok
    • 

  • fpga boot from flash ok
    • 

  • VME slave interface: A32/D32 single word cycle ok (minus VME_A29), 32-bit and 64-bit transfer untested (should work), 2eVME and 2eSST untested (should work).
    • 

  • VME interface: D lines: read ok, drive ok, A lines read ok (minus VME_A29), A lines drive untested. AS/DS read ok, drive untested. DTACK read ok, drive ok.
    • 

  • JTAG JIC flash programmer ok ("serial flash loader" block)
    • 

  • VME flash programmer (srunner_vme): connected, can read silicon ID, but problem with pof and jic data format, not usable.
    • 

  • FPGA reboot ok ("remote update" block)
    • 

  • front panel I/O LEDs: partially tested (generally alive. mapping and individual leds untested)
    • 

  • front panel RGB LED: untested (no RGB_LED_SDI)
    • 

  • LVDS/ECL input: untested
    • 

  • NIM/TTL input/output: untested
    • 

  • SATA connectors: untested
    • 

  • clock cleaner: untested
    • 

  • ethernet interface: RX/TX untested, SPI untested, ethernet MAC address flash memory untested


Mysteries:



  • set_location_assignment PIN_AC7 -to RGB_LED_SDI -disable -comment "vrefb3an0 PIN_AC7"
    • 

  • set_location_assignment PIN_L26 -to VME_A[29] -disable -comment "vrefb6an0 PIN_L26"
    • 

  • D8 - DIFFIO_TX_T56 - "VME-DIG-3.3V"
    • 

  • quartus messages pin eSATA_TRIG:


Critical Warning (12888): Cross talk of LVDS Pin eSATA_TRIG from SE IO is too high. Reassign or move one or more of the following SE I/Os pins location and re-run the analysis again.  Please refer to the guideline from the Knowledge Base solution ID: rd10102013_979 and ensure the total % of crosstalk for the following SE I/O pins does not exceed 100%.
    Info (12899): SE I/O from the bank contributed to 99.18% of the margin due to SSN
    Info (12900): SE I/O MAC_SDA contributed to 9.19% of margin due to crosstalk
    Info (12900): SE I/O MAC_SCL contributed to 7.02% of margin due to crosstalk
    Info (12900): SE I/O VME_BR_out[0] contributed to 0.46% of margin due to crosstalk
    Info (12900): SE I/O VME_D[27] contributed to 2.75% of margin due to crosstalk
    Info (12900): SE I/O FP_LED_LATCH contributed to 10.17% of margin due to crosstalk



  • quartus messages about pins eSATA_CLKmon, LVDS_OSC1:


Critical Warning (12887): Too many 2.5-V SE IO in bank 7A with LVDS RX pin LVDS_OSC1. Reduce the number of 2.5-V I/Os used and re-run the analysis again.  Please refer to th
e guideline from the Knowledge Base solution ID: rd10102013_979 and ensure the total % of SSN for the following SE I/O pins does not exceed 100%.
    Info (12899): SE I/O VME_AM[3] contributed to 4.96% of the margin due to SSN
    Info (12899): SE I/O VME_AM[1] contributed to 4.96% of the margin due to SSN
    Info (12899): SE I/O VME_AM[0] contributed to 4.96% of the margin due to SSN
    Info (12899): SE I/O VME_BGOUTn[3] contributed to 4.96% of the margin due to SSN
    Info (12899): SE I/O VME_BGOUTn[2] contributed to 4.96% of the margin due to SSN
    Info (12899): SE I/O VME_BGOUTn[0] contributed to 4.96% of the margin due to SSN
    Info (12899): SE I/O VME_IACKOUTn contributed to 4.96% of the margin due to SSN
    Info (12899): SE I/O SFP_SDA contributed to 4.96% of the margin due to SSN
    Info (12899): SE I/O VME_SYSCTRL contributed to 4.96% of the margin due to SSN
    Info (12899): SE I/O VME_ARBITER contributed to 4.96% of the margin due to SSN
...



ZZZ








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