BNMR: Hardware Debugging
Introduction
Test programs have been created for some of the DAQ VME modules in use in the BNMR/BNQR experiments. The test programs can be found in the directory /home/bnm[qr]/vmetest.
| Module | ProgramName | Purpose |
|---|---|---|
| PPG | vppg | test program for PulseBlaster PPG |
| PPG32 | newppg | test program for PPG32 |
| SIS3801 | sis3801 | test program for SIS3801 scaler |
| SIS3820 | sis3820 | test program for SIS3820 scaler |
| PSM/PSMII | psmII | test program for PSM/PSMII RF module |
| PSMIII | psm3 | test program for PSMIII RF module |
| VMEIO | heltest | test program for setting helicity using VMEIO |
All these programs must be run on the VMIC (not the host computer).
psm3
The test program psm3 tests the PSMIII module. The source code for psm3 is the PSMIII driver, i.e. files trPSM3.c and trPSM3.h. These are built with MAIN defined in the test area, using the command make psm3.
Copies of these files under /home/bn[mq]r/online/psm3/ are built into the frontend.
psm3 is a menu-driven program. It can be run (with caution) at the same time as the DAQ, as it does not automatically do any initialization. The module's registers can be dumped by using the 'Dump Registers' command.
example
[bnmr@lxbnmr ~/vmetest]$ psm3
calc_freq_conversion sets max freq = 199999999.953434 Hz and finc=0.046566
Current experiment is bnmr
vmic_mmap: Mapped VME AM 0x09 addr 0x00000000 size 0x00ffffff at address 0x20100000
mvme_open:
Bus handle = 0x3
DMA handle = 0x97413e8
DMA area size = 1048576 bytes
DMA physical address = 0xb667b000
Pol Synthesizer Module: base address psm_base=0x820000
TRIUMF PSM function support
A Read Control Reg a Write Control Reg
B Select BNMR/BNQR Mode b Set BNQR PhaseShift
C Select Channel(s) c End Sweep Control
D Dump Registers d Read/Write Freq Sweep Length
E Read Freq Memory e Read IQ Memory
F Write Freq Memory(Hz) f Write IQ Memory
G Gate Control g Pre/Gated Output Select
H help I Init module
J Write Tuning Freq j Read Tuning Freq
K Ancillary Control k Ancillary I/O
L Read/Write Channel Reg l Read/Write Scale Factor
M Load frequency file(hex) m Read/Write Buffer Factor
P Print this list p Freq Sweep Addr Preset
R VME Reset r Freq Sweep Addr Reset
S status s Freq Sweep Strobe
V RF Power Trip Threshold v RF Power Trip Status/Reset
d debug (toggles)
Test procedures:
1 Set freq, phase & turn channels on for a certain time
2 Load freq and iq memory from files, load idle, set length regs, preset addr, strobe
Enter command (A-Z a-z) X to exit? D
Frequency
vmic_mmap: Mapped VME AM 0x3d addr 0x00000000 size 0x00ffffff at address 0x22100000
Idle Freq (offset 0x1ffc) = 40028000 Hz (hex value= 0x333c6003)
Frequency sweep address = 0x7ff (2047)
Frequency sweep length = 0x000 (0)
f1 tuning frequency = 0 Hz (hex value = 0x0)
fC0 tuning frequency = 0 Hz (hex value = 0x0)
fC1 tuning frequency = 0 Hz (hex value = 0x0)
Control Registers
Register Register #Valid| F0 F1
Name Offset bits | Chan1 | Chan2 | Chan3 | Chan4 |
Phase Mod 0x00 16 | 0x0000 | 0x0000 | 0x0000 | 0x0000 | 0x0000
Scale Fac 0x02 08 | 0x00 | 0x00 | 0x00 | 0x00 | 0x00
Buff Fac 0x04 10 | 0x001 | 0x001 | 0x001 | 0x001 | 0x001
IQDM Len 0x06 11 | 0x000 | 0x000 | 0x000 | 0x000 | 0x000
IQDM Addr 0x08 11 | 0x7ff | 0x7ff | 0x7ff | 0x7ff | 0x7ff
I,Q Idle 0x1ffc 10 | 512,0| 0,511| 512,0| 0,511| 0,511
Bit Pattern registers
Reg Reg Reg
Name Offset Value Ch1 Ch2 Ch3 Ch4 F1 Freq
EndSweep 0x004b 0x3f 1 1 1 1 1 1 0=stop at Nth 1=jump to idle
Gate 0x004c 0x000 0 0 0 0 0 0=disable 1=enable 2=invert 3=always on
AncCntrl 0x0050 0x000 0 0 0 0 0=NIM input 1=NIM output
AncIn 0x004e 0x000 0 0 0 0 0=Off 1=On
AncOut 0x004f 0x000 0 0 0 0 0=Off 1=On
Other registers
Reg Reg Reg
Name Offset Value
PreGatedOut 0x0051 0x000 RF PreGated port: F0 ch1 selected
GatedOut 0x0052 0x000 RF Gated port: F0 ch1 selected
RFtripThr 0x0053 0x0080 Voltage trip at 2.000000 Volts
RFtrip 0x0054 0x0000 1=tripped
Mode 0x0055 0x0000 0=BNMR 1=BNQR
FPGA Temp 0x0058 0x2040 Temperature 64 degrees C (approx)
Enter command (A-Z a-z) X to exit?
vppg
The test program vppg tests the PulseBlaster PPG module. The source code for vppg is the ppg driver, i.e. files vppg.c and vppg.h. These are built with MAIN defined in the test area, using the command make ppg.
Copies of these files under /home/bn[mq]r/online/ppg/ are built into the frontend.
vppg is a menu-driven program. It can be run (with caution) for debugging at the same time as the DAQ, as it does not automatically do any initialization. For example, it can be used to check whether the PPG is running.
example
[bnmr@lxbnmr ~/vmetest]$ vppg
vmic_mmap: Mapped VME AM 0x09 addr 0x00000000 size 0x00ffffff at address 0x20100000
mvme_open:
Bus handle = 0x3
DMA handle = 0x870a3e8
DMA area size = 1048576 bytes
DMA physical address = 0xb6655000
vmic_mmap: Mapped VME AM 0x29 addr 0x00000000 size 0x0000ffff at address 0x27ff0000
Pulseblaster IS reset
Pulseblaster NOT running
Pulseblaster is NOT stopped
VME polarization source control bits = 0x0
VME Polarization control: OFF
External clock IS present
External Polarization control: OFF
External trigger is DISABLED
External trigger register = 0x1
PPG function support
A Init B Load
C StopSequencer E StartSequencer
F EnableExtTrig G DisableExtTrig
H ExtTrigRegRead I StatusRead
J PolmskRead K PolmskWrite
L RegWrite M RegRead
N StartpatternWrite O PolzSet
Q PolzRead R PolzFlip
S PolzCtlPPG T PolzCtlVME
U BeamOn V BeamOff
W BeamCtlPPG Y BeamCtlRegRead
D debug (toggles) P print this list
X exit
Enter command (A-Y) X to exit? I
Pulseblaster IS reset
Pulseblaster NOT running
Pulseblaster is NOT stopped
VME polarization source control bits = 0x0
VME Polarization control: OFF
External clock IS present
External Polarization control: OFF
Read back data =0x21
Enter command (A-Y) X to exit? X