VME-NIMIO32-Rev3

Links

• https://edev-group.triumf.ca/hw/vme/vme_nimio/rev3
• https://bitbucket.org/ttriumfdaq/vmeio/src/master/

General information

Hardware

• FPGA: Cyclone5 5CGXFC7D7F27C8N
• boot flash: EPCQ256
• clock cleaner: IDT 8T49N241-009NLG1, I2C addr 1111'100b
• mac address: Microchip 24AA02E48T-I/OT, I2C address 0xA0, bus MAC_SCL, MAC_SDA
• eeprom: Microchip 24AA04T-I/OT, I2C address 0xA0, bus SCLK, SDATA
• clocks: OSC1, OSC2: 125 MHz, OSC3: 10 MHz
• front panel double SATA connector: 1 serial communication, 1 clock (in our out) and trigger (in or out)
• on board 3 double SATA connectors: 7 serial communication.
• front panel SFP, (1/2.5/5 Gige ethernet?)
• 16 double LEMO connectors: switchable between input and output. input: NIM or TTL. output: NIM
• 16 ECL or LVDS inputs: onboard 34-pin header connector, LeCroy 4616 compatible.

Front panel connectors

(CHRONOBOX)
|
| LEMO - CLK_IN - jumpers: SINE<->CLK<->NIM/TTL and NIM<->CLK<->TTL
|
| ECL P1
| 32
| |
| 1
|
| ECL P2
| 32
| |
| 1
|
| PLED - power-on LED
|
| jumper: bank A direction IN<->X<->OUT
| LEMO 0-1
| LED 0-1
| LEMO 2-3
| LED 2-3
|
| jumper: bank B direction IN<->X<->OUT
| LEMO 4-5
| LED 4-5
| LEMO 6-7
| LED 6-7
|

Input channel mapping

• 0+16 : LVDS/ECL connector
• 16+32 : LEMO inputs
• 48+2: ESATA CLK, ESATA TRIG
• 50+2: FPGA_CLKIN1, FPGA_CLKIN2 from clock cleaner
• 52+1 : LVDS_OSC1 (125 MHz)

Firmware

for building firmware use: /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh

git clone git@bitbucket.org:ttriumfdaq/vmeio.git
cd vmeio
/opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
make
make jic
make load_jic

for jtag access, use /daq/quartus/13.1.3.178/quartus/bin/quartus

daq01:intelFPGA$ /daq/quartus/13.1.3.178/quartus/bin/jtagconfig 
1) USB-Blaster [1-8]
  02B030DD   5CGTFD7(B5|C5|D5)/5CGXBC7B6/..

Required board mods

• VME_LWORD jumper to VME_SERB
• VME_A29 jumper to ???
• RGB_LED_SDI jumper to ???
• -3V external power supply

Test status

• power up ok
• fpga jtag ok
• flash load ok
• fpga boot from flash ok
• VME slave interface: A32/D32 single word cycle ok (minus VME_A29), 32-bit and 64-bit transfer untested (should work), 2eVME and 2eSST untested (should work).
• VME interface: D lines: read ok, drive ok, A lines read ok (minus VME_A29), A lines drive untested. AS/DS read ok, drive untested. DTACK read ok, drive ok.
• JTAG JIC flash programmer ok ("serial flash loader" block)
• VME flash programmer (srunner_vme): connected, can read silicon ID, but problem with pof and jic data format, not usable.
• FPGA reboot ok ("remote update" block)
• front panel I/O LEDs: partially tested (generally alive. mapping and individual leds untested)
• front panel RGB LED: untested (no RGB_LED_SDI)
• LVDS/ECL input: untested
• NIM/TTL input/output: untested
• SATA connectors: untested
• clock cleaner: untested
• ethernet interface: RX/TX untested, SPI untested, ethernet MAC address flash memory untested

Mysteries:

• set_location_assignment PIN_AC7 -to RGB_LED_SDI -disable -comment "vrefb3an0 PIN_AC7"
• set_location_assignment PIN_L26 -to VME_A[29] -disable -comment "vrefb6an0 PIN_L26"
• D8 - DIFFIO_TX_T56 - "VME-DIG-3.3V"
• quartus messages about many pins:

Critical Warning (12888): Cross talk of LVDS Pin eSATA_TRIG from SE IO is too high. Reassign or move one or more of the following SE I/Os pins location and re-run the analysis again.  Please refer to the guideline from the Knowledge Base solution ID: rd10102013_979 and ensure the total % of crosstalk for the following SE I/O pins does not exceed 100%.
    Info (12899): SE I/O from the bank contributed to 99.18% of the margin due to SSN
    Info (12900): SE I/O MAC_SDA contributed to 9.19% of margin due to crosstalk
    Info (12900): SE I/O MAC_SCL contributed to 7.02% of margin due to crosstalk
    Info (12900): SE I/O VME_BR_out[0] contributed to 0.46% of margin due to crosstalk
    Info (12900): SE I/O VME_D[27] contributed to 2.75% of margin due to crosstalk
    Info (12900): SE I/O FP_LED_LATCH contributed to 10.17% of margin due to crosstalk

and

Critical Warning (12887): Too many 2.5-V SE IO in bank 7A with LVDS RX pin LVDS_OSC1. Reduce the number of 2.5-V I/Os used and re-run the analysis again.  Please refer to th
e guideline from the Knowledge Base solution ID: rd10102013_979 and ensure the total % of SSN for the following SE I/O pins does not exceed 100%.
    Info (12899): SE I/O VME_AM[3] contributed to 4.96% of the margin due to SSN
    Info (12899): SE I/O VME_AM[1] contributed to 4.96% of the margin due to SSN
    Info (12899): SE I/O VME_AM[0] contributed to 4.96% of the margin due to SSN
    Info (12899): SE I/O VME_BGOUTn[3] contributed to 4.96% of the margin due to SSN
    Info (12899): SE I/O VME_BGOUTn[2] contributed to 4.96% of the margin due to SSN
    Info (12899): SE I/O VME_BGOUTn[0] contributed to 4.96% of the margin due to SSN
    Info (12899): SE I/O VME_IACKOUTn contributed to 4.96% of the margin due to SSN
    Info (12899): SE I/O SFP_SDA contributed to 4.96% of the margin due to SSN
    Info (12899): SE I/O VME_SYSCTRL contributed to 4.96% of the margin due to SSN
    Info (12899): SE I/O VME_ARBITER contributed to 4.96% of the margin due to SSN
...