VME-PPG32
VME-PPG32 - pulse pattern generator VME FPGA board
References
- [1] VME-PPG32 Rev0 (REA 198) project page on edev.triumf.ca
- [2] VME-PPG32 Rev1 (REA 198) project page on edev.triumf.ca
- [3] VME-PPG32 Rev2 (REA 198) project page on edev.triumf.ca
- [4] Rev0 board schematics on edev site
- [5] Rev1 board schematics on edev site
- [6] Rev2 board schematics on edev site
- File:VME-PPG32 Rev1.pdf Rev1 board schematics, local copy
- File:VME-PPG32 Rev2.pdf Rev2 board schematics, local copy
VME-PPG32-IO32 firmware: (IO32 functions, no PPG functions)
- [7] Svn repository for VME-PPG32-Rev0 initial test firmware (IO32 function only, no PPG function)
- [8] Svn repository for VME-PPG32-Rev1 firmware (IO32 function only, no PPG function)
VME-PPG32 VME CPLD firmware: (VME address decoder)
- [9] Svn repository for VME-PPG32 Rev0 and Rev1 VME address decoder CPLD (Altera EPM3032)
VME-PPG32 firmware: (PPG function)
- [10] Current PPG firmware Source/binary
General characteristics
Available hardware
- Altera cyclone 3 FPGA: EP3C40Q240C8
- Serial flash for FPGA configuration: Altera EPCS16
- VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
- 32 NIM outputs
- 4 NIM inputs
- 32 "NIM output" LEDs
- 4 "NIM input" LEDs
- 1 "VME access" LED
- 2 output serial DAC: AD5439YRUZ
- Rev1 and Rev2 boards: inputs are switchable between NIM and TTL (JMP3)
- Rev2 boards: outputs are switchable between NIM and TTL (micro switches)
PPG characteristics
4k words (128bit words) of program memory. 256 entry stack. Halt/Continue/Loop/Subroutine/Branch instructions 100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input - see note 1) fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction
FPGA resource Usage : 1044 LE, 500 kbits Memory
Note 1 : Some modules allow an external clock frequency of 20-100MHz . Divide-downs must be programmed where external clock frequency is not 20MHz. Examples of divide-down programming is shown at end of this document.
Onboard jumper settings
- JMP1 - set to "INP" for input with 50 Ohm termination, set to "DAC" for DAC output
- JMP2 - set to "INP" same as JMP1
- JMP3 - set to "NIM" (pins 1-2) for NIM inputs or "TTL" (pins 2-3) for TTL inputs
- JMP4 - "MSEL1" jumper set to "ACT" for use with the active-serial flash
- IrqSel - leave open
- JTAG - leave open (not a jumper block!)
- SW1..3 - VME base address selectors (see below)
VME interface
VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address. VME registers are listed in the table below.
Registers
| Number | Address | Name | Access | Description |
|---|---|---|---|---|
| 0 | 0x00000 | CSR | RW | Control/Status Register |
| 1 | 0x00004 | Test | RW | Test Register |
| 2 | 0x00008 | Addr | RW | Program Address Register |
| 3 | 0x0000C | Inst_Lo | RW | Instruction Register Part 1/4 |
| 4 | 0x00010 | Inst_Med | RW | Instruction Register Part 2/4 |
| 5 | 0x00014 | Inst_Hi | RW | Instruction Register Part 3/4 |
| 6 | 0x00018 | Inst_Top | RW | Instruction Register Part 4/4 |
| 7 | 0x0001C | Inv_Mask | RW | Output Inversion Mask |
| 8 | 0x00020 | Version | R | Firmware Version Register |
| 9 | 0x00024 | Flash | RW | Serial Flash Control Register |
| 10 | 0x00028 | Serial | R | Serial Number Register |
| 11 | 0x0002C | Hardware | R | hardware Identification Register |
Test Register (0x00000)
Simple Test Register - Value Written is preserved and can be read back.
CSR Register (0x00004)
The first 5 bits control the ppg, the remaining 26 bits provide read-only status information. (writes to the 26 bits of status information are ignored, and overwritten on the next status update)
| Bit | Name | Access | description |
|---|---|---|---|
| 0 | Run | R/W | Run Control/Status |
| 1 | Ext-Clk-Toggle | W | Toggles between PPG external and internal Clk |
| 2 | Ext-Start | R/W | 1=Ext-PPG Start 0=Int-PPG Start |
| 3 | PPG-Reset | R/W | 1=Reset 0=Normal operation |
| 4 | Test-Mode | R/W | 1=Test Mode 0=Normal operation |
| 16 | Ext-Clk-Sel | R | 1= External clock is selected 0 = Internal clock selected |
| 17 | Ext-Clk good | R | 1= External clock is connected and is "good" 0= external clock not connected or is "bad" |
| ?-31 | Status | R | Readback of PC,SP,Current Delay Counter |
RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.
Ext_Clk bit: Writing an edge here toggles the ppg logic between the internal and external CLK (connected to Nim_Input[3]). The VME interface always uses the internal clock. Note that the correct divide-down must be programmed unless external clock is the same frequency (i.e. 10MHz) as internal clock.
Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start. (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[4])
Reset bit: Set bit to Reset PPG. Stops PPG pgm even if executing a long delay. Does NOT do a full reset to power-up condition. Bit must be cleared after Reset or module will not operate.
Test-Mode bit: Set bit to enable Test Mode. When Test Mode is enabled, inputs 1 and 2 become output the internal PPG clock and actual clock PPG is using, respectively. If internal clock is set, inputs 1 and 2 output identical clocks. If external clock is set, and the external clock is "good", input 1 will not change, but input 2 will show the external clock frequency. If Test-Mode bit is cleared, Normal Mode is enabled, where inputs 1 and 2 act as regular inputs.
Ext-Clk-Sel: If bit is set, external clock is selected and LED 4 will be lit. If clear, internal clock is selected
Ext-Clk Good: If bit is set, external clock is connected to Nim_Input[3] and is "good". LED 2 will be lit. If clear, external clock is either not connected or is "bad".
Address Register (0x00008)
Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address. Also in test-Mode, the NIM/LED outputs follow the state of this register.
Instruction Registers (0x0000C - 0x00018)
Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.
The instructions format is as follows ...
| Bits 0-31 | Bits 32-63 | Bits 64-95 | Bits 96-115 | Bits 116-117 | Bits 118-127 |
|---|---|---|---|---|---|
| 32 Output Set Bits | 32 Output Clear Bits | 32bit Delay Count | 20bit Data | 4bit instruction type | Ignored |
The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.
The instruction types are ... 0 - Halt 1 - Continue 2 - new Loop ( 20 bit data used for count - i.e. maximum 1 million ) 3 - End Loop 4 - Call Subroutine ( 20 bit data used for address ) 5 - Return from subroutine 6 - Branch ( 20 bit data used for address )
Output Inversion Mask (0x0001C)
32 individual inversion bits (1 per output) a 1 inverts the state of that output.
Firmware Version (0x00020)
Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.
Serial Flash Control (0x00024)
Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)
Serial Number (0x00028)
Returns the module serial number, and Board revision (if set) or 0xdead
hardware Type (0x0002C)
Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32
Front Panel
NIM Inputs
The Input assignments are (as labelled on front panel) ... 4 - External Start (Not fully tested yet) Needs to stay high (low => stop!) 3 - External Clock (20Mhz, internally scaled - 100Mhz) 2 - Unassigned 1 - Unassigned
Input LEDs
The Input LED assignments are (as labelled on front panel) ... 4 - Clock setting (Lit => External Clk) 3 - NimIn[2] status 2 - External Clock Good indicator (Lit => Clock is good) 1 - Program Running
Test Software
c-shell script to run 2 nested loops
set dec_hex=( 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 \
0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf \
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 \
0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f \
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 )
# dly4,loop4,dly3,loop6,dly2,end,end
set inst=( \
0xff 0x00 0x4 0x100000 0x0 0x0 0x0 0x200004 \
0x1 0x1 0x3 0x100000 0x0 0x0 0x0 0x200006 \
0x2 0x2 0x2 0x100000 0x0 0x0 0x0 0x300000 \
0x0 0x0 0x0 0x300000 0x0 0x0 0x0 0x000000 )
set i=0
set j=0
while( $i < $#inst )
@ j++; vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 $dec_hex[$j]
@ i++; vme_poke -a VME_A32UD -A 0x0010000c -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100010 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100014 -d VME_D32 $inst[$i]
@ i++; vme_poke -a VME_A32UD -A 0x00100018 -d VME_D32 $inst[$i]
end
# start program (from addr 0)...
vme_poke -a VME_A32UD -A 0x00100008 -d VME_D32 0x0
vme_poke -a VME_A32UD -A 0x00100000 -d VME_D32 0x1
c-shell script to set divide-downs for 100MHz frequency
This would be used with an external frequency input of 100MHz
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x00000305 # set hi counter to 3 vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x01000205 # set lo counter to 2 vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x05000105 # set mode counter to odd vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000005 # set counter bypass to 0 vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3 vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0
c-shell script to set divide-downs for 10MHz frequency
This would be used when returning to the internal frequency of 10MHz :
vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x04000105 # set counter bypass to 1 vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x3 # reconfig clock vme_poke -a VME_A32UD -A 0x00100030 -d VME_D32 0x0 # prepare for next cmd
IO32 firmware
The VME-PPG32 board can run the IO32 firmware (subproject "PPG32-Rev1" of the VME-NIMIO32 firmware). For instructions, please refer to the IO32 documentation.