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DarkSide-20k Global and Crate Data Manager board (GDM and CDM).

Global Data Manager (GDM):

  • clock distribution to CDM boards (including GPS/atomic clock source)
  • collection of trigger data from CDM boards, processing and distribution of trigger decision to CDM boards
  • run control

Crate Data Manager (CDM):

  • clock distribution from GDM to CAEN digitizers
  • receive trigger data from CAEN digitizers
  • send trigger data to GDM
  • run control and dead time control


edev links:

Xilinx links:

Enclustra links:

Onboard hardware

  • jtag chain: arm_dap_0 0x5BA00477, xczu4_1 0x04721093
  • Eclustra Mercury+ XU8 module: ME-XU8-4CG-1E-D11E-R2.1
    • Xilinx® Zynq Ultrascale+™ MPSoC XCZU4CG-1FBVB900E
    • DDR4 ECC SDRAM (PS) 2 GB
    • DDR4 SDRAM (PL) 1GB
  • USB UART for Enclustra serial console, micro-USB, 115200n8
  • LEDs:
    • LED_FP A/B/C/D 0/1/2/3
    • led1 - 3V3_SW_ON, SOM_POWER_GOOD - Enclustra FPGA module 3.3V power is good
    • led2 - LTM4624 PGOOD
    • led3 - FPGA_DONE - FPGA has booted
    • led4 - TP-S-1, PCLK_P
    • led5 - TP-S-2, PCLK_N
  • LEMO connectors (top to bottom)
    • J4 - input (NIM/TTL)
    • J5 - input (NIM/TTL)
    • J6 - external clock (GPS 10MHz and PPS)
    • J7 - output (NIM/TTL)
  • ethernet connector
  • SFP connector
  • 4 QSFP connectors (GDM)
  • 6 VX connectors (CDM)

Jumpers and switches

  • PB1 - HRST - reboot FPGA
  • PB2 - SRST - ???
  • SW1 - boot mode BM0, BM1 [-->]
  • SW2 - LEMO output NIM<->TTL
  • SW3 - LEMO input 1 and 2 NIM/TTL
  • SW4 - LEMO input 2 and 4 NIM/TTL
  • SW5 - ???
  • SW6 - serial console select. [PS<--PL] PS is ARM CPU, PL is FPGA.

Board schematics

Board test plan

To test:

  • Enclustra FPGA board
  • SFP port
  • CDM VX ports 2x(CLK, 3 tx, 4 rx)
  • GDM QSFP ports (lanes 0,1,2. lane 3 n/c)
  • J4A, J4B, J5A, J5B external inputs (NIM/TTL) EXT_IN1..4_LV. TTL threshold 1.7V, NIM threshold -0.3V. 50 Ohm termination.
  • J6A, J6B external clock CLK_EXT1, CLK_EXT0 (sw5 is missing how is this supposed to work?). 50 ohm termination.
  • ethernet MAC i2c chip
  • BOOT_MODE 0 and 1


  • LED_FP1A..D: tested ok. K.O. 15 sep 2022
  • USB UART: tested ok. K.O. 15 sep 2022
  • J7A, J7B external outputs EXT_OUT1, EXT_OUT2 (NIM/TTL)
    • TTL out tested ok, 0=0V, 1=5V, rise time 2 ns, K.O. 15 sep 2022


  • ethernet: does not connect to alliedtelesys switch. connects to my USB-eth adapter at 100 Mbit speed. uboot mii status reports connection speed oscillating between 1000, 100 and 10. K.O. 16-sep-2022
  • J7A, J7B external outputs EXT_OUT1, EXT_OUT2 (NIM/TTL)
    • NIM problematic, 0=0V, without 50 ohm termination: 1=-5V, rise time 50 and 150 ns (the two outputs are not the same), drop time 100 ns. with 50 ohm termination, 1=-1V, rise time 20 ns, drop time 10-20ns, the two channels are not the same.

Checklist for newly build boards


Serial console

Install Xilinx tools

  • install Vivado 2020.2
login at https://www.xilinx.com/myprofile.html
go to "Downloads"
go to archive,
find 2020.2
download Xilinx_Unified_2020.2_1118_1232_Lin64.bin
sh ./Xilinx_Unified_2020.2_1118_1232_Lin64.bin
banner window should open with spinner "downloading installation data"
"a newer version is available" -> say "continue"
"select install type" window:
provide email and password,
select "download image"
select directory /home/olchansk/Xilinx/Downloads/2020.2\
select "linux" and "full image"
download summary: space required 38.52 Gbytes
installation progress
downloading spinner, 16 M/s 47 minutes...
"download image has been created successfully". Ok.
check contents of /home/olchansk/Xilinx/Downloads/2020.2
ls -l /home/olchansk/Xilinx/Downloads/2020.2
total 67
drwxr-xr-x 2 olchansk users    9 Sep  1 16:22 bin
drwxr-xr-x 3 olchansk users   15 Sep  1 16:23 data
drwxr-xr-x 4 olchansk users    4 Sep  1 16:22 lib
drwxr-xr-x 2 olchansk users  644 Sep  1 16:22 payload
drwxr-xr-x 2 olchansk users    7 Sep  1 16:22 scripts
drwxr-xr-x 4 olchansk users    4 Sep  1 16:22 tps
-rwxr-xr-x 1 olchansk users 3256 Nov 18  2020 xsetup
spinned loading installation data
xilinx design tools 2022.1 now available -> say continue
"welcome" -> next
"select product" -> vivado -> next -> vivado hl system edition -> next
select devices: only zynq ultrascale+ mpsoc -> next
select destination: /opt/Xilinx (as root, mkdir /opt/Xilinx, chmod olchansk.users /opt/Xilinx)
install ...
move /home/olchansk/Xilinx/Downloads/2020.2 to /daq/daqstore/olchansk/Xilinx/Downloads/
  • install petalinux 2020.2
"a newer version is available" -> say "continue"
"select product to install" -> select Petalinux (Linux only) -> next
"select destination directory" -> select "/opt/Xilinx" (disk space required 2.64 GB) -> next
"summary" -> install ...
error about missing /tmp/tmp-something files
"installation completed successfully" (hard to dismiss, "ok" button is partially cut-off)
I think it failed, /opt/Xilinx/PetaLinux/2020.2/bin is empty except for petalinux-v2020.2-final-installer.run
try to run it by hand, same error about /tmp/tmp-something files. strange...
notice it complains about "truncate", which truncate finds ~/bin/truncate, get rid of it,
try again
now complains about missing texinfo and zlib1g:i386
apt install texinfo -> ok
apt install zlib1g:i386 -> installs bunch of gcc stuff -> ok
try again
reports "already installed" -> delete /opt/Xilinx/.xinstall/PetaLinux_2020.2/, delete entries in ~/.Xilinx/registry/installedSW.xml
try again
  • install vivado 2022.1 and petalinux 2022.1 - everything is pretty much the same

JTAG server


Build firmware

Build from git clone

  • git clone git@edev-group.triumf.ca:fw/exp/darkside/gcdm.git
  • #Makefile change VIVADO_SETTINGS_SCRIPT := /opt/Xilinx/Vivado/2022.1/settings64.sh
  • #. /opt/Xilinx/Vivado/2022.1/settings64.sh
  • . /opt/Xilinx/Vivado/2020.2/settings64.sh
  • make clean
  • make all_from_scratch
  • . /opt/Xilinx/PetaLinux/2020.2/tool/settings.sh
  • make petalinux_create
  • make petalinux_rebuild_new_hw_des
  • bomb out: The TMPDIR: /home/olchansk/git/ds-dm-gcdm/PetaLinux_GDM_CDM/build/tmp can't be located on nfs.
  • mkdir /tmp/build_tmp
  • rm -rf /home/olchansk/git/ds-dm-gcdm/PetaLinux_GDM_CDM/build/tmp/
  • ln -s /tmp/build_tmp /home/olchansk/git/ds-dm-gcdm/PetaLinux_GDM_CDM/build/tmp
  • try again
  • grinds, loads a whole bunch of packages...
  • finishes with desire to copy things to /tftpboot
  • make sdcard_cp_to wants to copy files from PetaLinux_GDM_CDM/images/linux/ to SD card


. /opt/Xilinx/Vivado/2020.2/settings64.sh
. /opt/Xilinx/PetaLinux/2020.2/tool/settings.sh
/usr/bin/time make vivado_rebuild_fw_hw_des
# to see errors:
more Vivado_GDM_XU8/GDM_XU8.runs/synth_1/runme.log
# if successful, updates GDM_XU8_top.bit
ls -ltr Vivado_GDM_XU8/GDM_XU8.runs/impl_1/GDM_XU8_top.bit
#-rw-r--r-- 1 olchansk users 7797807 Sep 15 13:30 Vivado_GDM_XU8/GDM_XU8.runs/impl_1/GDM_XU8_top.bit
# update sdcard files
/usr/bin/time make petalinux_repackage
# updates BOOT.BIN
ls -l PetaLinux_GDM_CDM/images/linux/BOOT.BIN 
#-rw-r--r-- 1 olchansk users 9228720 Sep 15 13:34 PetaLinux_GDM_CDM/images/linux/BOOT.BIN

prepare bootable sd card

format the sd card

this only needs to be done once

  • become root
  • cd ~olchansk/git/ds-dm-gcdm
  • use "lsblk" to identify the SD card (should show as 8/16/32 GB block device)/ /dev/sdd in this case
  • make sdcard_format SDCARD_DEVICE=/dev/sdd
  • disconnect sd card, reconnect the sd card (to detect new partition tables, etc)

copy boot files to the sd card

  • as root: identify partition labels, run "blkid", should say "BOOT", "rootfs" and "data"
  • mount
mkdir /media/olchansk/BOOT
mkdir /media/olchansk/rootfs
mkdir /media/olchansk/data
mount -L BOOT /media/olchansk/BOOT
mount -L rootfs /media/olchansk/rootfs
mount -L data /media/olchansk/data
cp PetaLinux_GDM_CDM/images/linux/BOOT.BIN /media/olchansk/BOOT/
cp PetaLinux_GDM_CDM/images/linux/boot.scr /media/olchansk/BOOT/
cp PetaLinux_GDM_CDM/images/linux/image.ub /media/olchansk/BOOT/
umount /media/olchansk/BOOT
umount /media/olchansk/rootfs
umount /media/olchansk/data
eject /dev/sdd



DS-DM, GDM and CDM are key parts of the DS-20K DAQ system:

  • common clock distribution from external clock (atomic clock, GPS) to GDM to per-quadrant CDMs to VX digitizers
  • common trigger distribution from GDM internal algorithm or external input to all VX digitizers
  • run control: GDM, CDM, VX all start recording data at the same time (clock and timestamp reset)
  • collection of trigger data from VX digitizers to per-quadrant CDMs to GDM


  • hardware and firmware for GDM to CDM clock distribution
  • hardware and firmware for CDM to VX clock distribution
  • hardware and firmware for GDM external clock input (atomic clock or GPS)
  • hardware and firmware for CDM and VX serial communications (VX LVDS I/O connector)
  • firmware for run control (timestamp reset and sync): GDM to CDM to VX
  • firmware for common trigger distribution: GDM to CDM to VX
  • firmware for trigger data flow: VX to CDM to GDM
  • GDM MIDAS frontend: clock selector and monitoring, trigger and run control, GDM housekeeping
  • CDM MIDAS frontend: clock monitoring, CDM housekeeping

specific performance:

  • GDM external clock: 10 MHz GPS clock
  • GDM to CDM fiber link:
    • clock XXX MHz
    • link data rate: XXX Gbit/sec
    • CDM recovered clock: XXX MHz
    • CDM recovered clock jitter: XXX ns
    • phase alignment between CDMs: XXX ns
    • phase alignment between CDMs persists across reboots, power cycles, firmware updates
    • phase alignment between CDMs should be easy to measure
    • phase alignment between CDMs should be easy to recalibrate if hardware parts are replaced (DS-DM boards, fiber transceivers, fiber cables, etc)
    • data packet bandwidth: XXX Mbytes/sec
    • data packet latency: XXX clocks
    • data packet skew between CDMs: XXX clocks
  • CDM to VX clock:
    • clock: XXX MHz
    • jitter, all CDM clock outputs: XXX MHz
    • phase alignment between all CDM clock outputs: XXX ns
  • CDM to VX trigger:
    • TBD (use the VX "sync" input or VX LVDS I/O line or VX serial link packet)
  • CDM to VX serial link:
    • clock: XXX MHz (TBD: VX external clock, or LVDS I/O line or link recovered clock)
    • bit rate: XXX bits/sec
    • latency: XXX link clocks
    • maximum skew between VXes: XXX ns
  • VX to CDM serial link:
    • clock: XXX MHz (TBD: VX external clock, or LVDS I/O line or link recovered clock)
    • bit rate: XXX bits/sec
    • latency: XXX link clocks
    • maximum skew between VXes: XXX ns
  • timestamp reset:
    • maximum skew between VXes: XXX ns

Technical risk items

this refers to unexpected behaviour and performance of system components, causes big difficulty in implementing the system, prevents delivery of deliverables, and prevents or negatively affects operation of the DS-20K DAQ or of the whole experiment.

(14-sep-2022, list is not sorted by any criterial: severity, probability, ease of investigation)

(stability of course is long term stability, across hours, days, weeks, months, years)

  • stability of Enclustra FPGA modules (crashes/year, failures to boot/year, flash corruption/year)
  • stability of GDM external clock PLL (lock loss/year)
  • stability of CDM recovered clock (lock loss/year, unexpected phase drifts, etc)
  • unexpected failures or bit error rates in GDM-CDM fiber links
  • stability of CDM VX clock outputs (stability of clock cleaner chip)
  • stability of VX internal clock distribution (VX PLL lock loss events)
  • stability of VX CAEN base firmware (different versions of CAEN base firmware have different clock distribution behaviour)
  • strange things in CAEN base firmware (unexpected clocking of LVDS I/O, unexpected phase shifts between clocks, etc)
  • DS-DM and VX hardware problems (incompatible LVSD I/O, incompatible clock signals, etc)


(14-sep-2022: at this stage of the project, priority must be given to identifying and retiring (so called) technical risk factors. it is not good to build the complete system only to discover that (for example) some Enclustra FPGA modules require 5 attempts to boot and erase their flash memory contents once a month. Both example are real-life actual problems that caused big difficulties in GRIFFIN/TIGRESS and ALPHA-g experiments).

Development and testing milestones in time reversed order:

  • full DAQ data challenge: all VXes, CDM, GDM, network, FEP, TSP, MIDAS operate as designed
  • one quadrant data challenge: 1 VME crate of VX, CDM, GDM, network, FEP, TSP, MIDAS operate as designed
  • vertical slice data challenge: 1 VME crate, 2 VX, 2 CDM (1 VX per CDM), GDM, etc operate as designed
  • GDM-CDM link finalized (data rate frozen, data packet format frozen, data content permitted to change)
  • CDM-VX serial link finalized (data rate frozen, data packet format frozen, data content permitted to change)
  • run control (timestamp reset) and trigger distribution design agreed upon, frozen (list of possible triggers permitted to change)
  • VX to CDM to GDM data flow design agreed upon, frozen (data contents permitted to change)
  • major technical risk items retired (all hardware and firmware is working as expecred without mysteries and surprises, all problems are identified, investigated, resolved, solutions tested)
  • stable operation of CDM-VX serial links in vertical slice system
  • stable operation of GDM to CDM clock in vertical slice system
  • stable operation of CDM to VX clock in vertical slice system
  • vertical slice system assembled (1 VME crate, 2 VX, 2 CDM, 1 GDM, network, FEP, TSP, MIDAS)