TRB3 Centos-7 instructions

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Introduction

See main TRB3 document for introductory material.

Centos-7 Software Setup

The TRB3 software and associated analysis packages are developed on newer operating systems than Centos-7 (namely Opensuse). So a certain amount of work is needed to get the software to work on Centos-7.

1) I started by copying over the software in trbsoft from an existing installation.

scp trbsoft_backup.tar.gz trb3@ladd00:/data0/trb3/.

2) The main problem is with the TRB3 code requiring a newer version of perl. I used perlbrew to setup a newer version of perl than Centos-7 supports:

Following the instructions on website:

https://perlbrew.pl/

source ~/perl5/perlbrew/etc/bashrc
perlbrew init
perlbrew install perl-5.24.0

and then add this line to login script

rm -f /home/trb3/.perlbrew/init
source ~/perl5/perlbrew/etc/bashrc
perlbrew switch perl-5.24.0 

3) Rebuild libtrbnet with different perl

cd ~/trbsoft/trbnettools/libtrbnet_perl
perl Makefile.PL
cd /home/trb3/trbsoft/trbnettools
make TRB3=1 clean
make TRB3=1
make TRB3=1 install
<pre>

4) Modify 

<pre>
~/trbsoft/daqtools/merge_serial_address.pl

to use the perlbrew version of perl, rather than the system default.


5) Rebuild DABC

Make sure you have ROOT (ie ROOTSYS) setup properly

 svn co https://subversion.gsi.de/dabc/trb3 trb3
cd trb3
make

This seems to build dabc and stream successfully. go4 doesn't compile cleanly, but this doesn't matter for the MIDAS frontend readout.

TRB3 MIDAS implementation

We have a working MIDAS readout of the TRB3 TDC data. Currently this readout uses a lot of the original GSI tools for setting up the TRB3 before the readout can start. At this time you need to do steps 1 and 2 described in "Start up instructions" in order to setup the TRB3 before starting the MIDAS frontend. Eventually we will try to remove as many as possible of the original GSI tools.

MIDAS frontend code is available here:

https://bitbucket.org/ttriumfdaq/trb3_frontend

The MIDAS frontend is setup to read events directly from the UDP buffer. You can see a running MIDAS TRB3 frontend here:

https://daq11.triumf.ca:8443

(midas/midas).

Setting up for MIDAS data taking

We are using the account trb3@daq11.triumf.ca for running this DAQ. If you need to restart the DAQ system, do the following

  • Run the setup program that will initialize the TRB3 and set the 10kHz software trigger
 
cd /home/trb3/trbsoft/daqtools/users/triumf_trb171
source startup.sh
  • (Optional) We can also start a webgui that allows us to check/configure the TRB3 separate from MIDAS; this is sometimes useful for monitoring. To do this, do
cd /home/trb3/trbsoft/daqtools/web
./cts_gui --noopenxterm --port=1234 --endpoint=0xc001
  • Start the MIDAS TRB3 readout frontend, if not running:
/home/trb3/online/trb3_frontend/fetrb3UDP.exe -D

As noted, we currently (April 9) we have the TRB3 setup with a 10kHz software trigger.

Running the online analyzer

I added simple decoder and histograming classes to rootana. Currently I have only implemented the crude TDC calibration into the TRB3 bank decoders. In the long run we may want to integrate the fine TDC calibration directly into the frontend.

To look at the analyzer display, run the following

/home/trb3/online/trb3_frontend/analyzer/anaDisplay.exe

The display shows different histograms, arranged by FPGA and channel number. Histograms are

  1. The TDC times for each channel, with crude calibration applied
  2. The TDC raw fine times; ie, the raw counts for the sub-5ns part of the TDCs
  3. TDC time difference histograms; for this canvas you can set the reference FPGA and channel

Analyzer notes:

  • On the physical TRB3 board the FPGAs are numbered as being 1-4, but the analyzer converts these to the more normal 0-3 indexing.
  • Channel 0 is also the TDC associated with the actual trigger; in our case, the time of the software trigger
  • For FPGA 0 and 1 the firmware is configured so we are reading both leading and falling TDC edges; so for these FPGAs channel 1 is the leading edge of the first input and channel 2 is the trailing edge of the first input, and so on. For FPGAs 2 and 3 we are only reading the leading edge of the TDCs.