VME-NIMIO32: Difference between revisions

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* Altera cyclone 1 FPGA: EP1C6Q240C6N
* Altera cyclone 1 FPGA: EP1C6Q240C6N
* external SDRAM memory
* VME interface: VME-D[31..0] bidirectional, VME-A[19..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* VME interface: VME-D[31..0] bidirectional, VME-A[19..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
* 16 NIM outputs
* 16 NIM outputs

Revision as of 16:28, 12 August 2010

VME-NIMIO32 - general purpose VME FPGA board

References

  • [1] VME-NIMIO32 (REA 131) project page on edev.triumf.ca
  • [2] Rev0 board schematics
  • [3] Rev1 board schematics

General characteristics

Available hardware

  • Altera cyclone 1 FPGA: EP1C6Q240C6N
  • external SDRAM memory
  • VME interface: VME-D[31..0] bidirectional, VME-A[19..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
  • 16 NIM outputs
  • 16 NIM inputs
  • 16 ECL/LVDS inputs compatible with LeCroy 4616 ECL/NIM/ECL converter. (Except: Rev0 boards have an incompatible ECL connector)
  • 16 "red" and 16 "green" LEDs
  • 1 "VME access" LED
  • 1 RJ-45 high speed serial I/O interface

Firmware functions

Generic IO32 firmware can include a number of functions. Not all functions are available all at the same time due to resource limitations on the FPGA. Refer to VME Registers for detailed information.

  • 20 MHz 32-bit timestamp clock register
  • 16 bits of NIM output register (first 4 NIM outputs are multi-function)
  • 16 bits of NIM and 16 bits of ECL/LVDS input register with latch function.
  • 32 scalers 32 bit, up to 300 MHz counting rate
  • 4 timestamp registers using the 20 MHz timestamp clock. Any of the 32 inputs can be routed into any of the 4 timestamp registers.
  • experimental 4-channel TDC. 10 ns base clock with 0.3 ns interpolation ladder (1 ns RMS).

Firmware revisions

To find out the current firmware revision, read VME register 0, i.e. run "test_VMENIMIO32_gef.exe --addr 0xN00000 --read 0".

To write Cyclone 1 FPGA firmware into the flash memory, use a JTAG programmer or a VME programmer: "srunner_vme_gef.exe -program -64 ~/daq/VME-NIMIO32/VME-NIMIO32/VME-NIMIO32/VME-NIMIO32.pof 0xN00020", where "N" is the A24 VME base address.

To reboot the Cyclone 1 FPGA into the new firmware, run "test_VMENIMIO32_gef.exe --addr 0xN00000 --read 0 --write 1 2 --read 0 --sleep 1 --read 0", where "N" is the A24 VME base address. This requires firmware 0x01100810 or newer and the "fpga-reset" hardware modification.

  • 0x01100810 - first revision of generic firmware

VME Interface

ccc

Board modifications

Rev0 modifications

  • none

Rev1 modifications

  • fpga-reset-mod

K.O.