VME-NIMIO32-Rev3: Difference between revisions

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* VME interface: D lines: read ok, drive ok, A lines read ok (minus VME_A29), A lines drive untested. AS/DS read ok, drive untested. DTACK read ok, drive ok.
* VME interface: D lines: read ok, drive ok, A lines read ok (minus VME_A29), A lines drive untested. AS/DS read ok, drive untested. DTACK read ok, drive ok.
* VME flash programmer (srunner_vme): connected, can read silicon ID, but problem with pof and jic data format, not usable.
* VME flash programmer (srunner_vme): connected, can read silicon ID, but problem with pof and jic data format, not usable.
* FPGA reboot ok ("remote update" block)
* front panel I/O LEDs: partially tested (generally alive. mapping and individual leds untested)
* front panel I/O LEDs: partially tested (generally alive. mapping and individual leds untested)
* front panel RGB LED: untested (no RGB_LED_SDI)
* front panel RGB LED: untested (no RGB_LED_SDI)

Revision as of 10:36, 8 April 2021

VME-NIMIO32-Rev3

Links

General information

Hardware

  • FPGA: Cyclone5 5CGXFC7D7F27C8N
  • boot flash: EPCQ256
  • clock cleaner: IDT 8T49N241-009NLG1, I2C addr 1111'100b
  • mac address: Microchip 24AA02E48T-I/OT, I2C address 0xA0, bus MAC_SCL, MAC_SDA
  • eeprom: Microchip 24AA04T-I/OT, I2C address 0xA0, bus SCLK, SDATA
  • clocks: OSC1, OSC2: 125 MHz, OSC3: 10 MHz
  • SATA connectors: 2 on front panel
  • SFP on front panel

Front panel connectors

(CHRONOBOX)
|
| LEMO - CLK_IN - jumpers: SINE<->CLK<->NIM/TTL and NIM<->CLK<->TTL
|
| ECL P1
| 32
| |
| 1
|
| ECL P2
| 32
| |
| 1
|
| PLED - power-on LED
|
| jumper: bank A direction IN<->X<->OUT
| LEMO 0-1
| LED 0-1
| LEMO 2-3
| LED 2-3
|
| jumper: bank B direction IN<->X<->OUT
| LEMO 4-5
| LED 4-5
| LEMO 6-7
| LED 6-7
|

Input channel mapping

  • 0+16 : LVDS/ECL connector
  • 16+32 : LEMO inputs
  • 48+2: ESATA CLK, ESATA TRIG
  • 50+2: FPGA_CLKIN1, FPGA_CLKIN2 from clock cleaner
  • 52+1 : LVDS_OSC1 (125 MHz)

Firmware

for building firmware use: /opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh

git clone git@bitbucket.org:ttriumfdaq/vmeio.git
cd vmeio
/opt/intelFPGA/20.1/nios2eds/nios2_command_shell.sh
make
make jic
make load_jic

for jtag access, use /daq/quartus/13.1.3.178/quartus/bin/quartus

daq01:intelFPGA$ /daq/quartus/13.1.3.178/quartus/bin/jtagconfig 
1) USB-Blaster [1-8]
  02B030DD   5CGTFD7(B5|C5|D5)/5CGXBC7B6/..

Required board mods

  • VME_LWORD jumper to VME_SERB
  • VME_A29 jumper to ???
  • RGB_LED_SDI jumper to ???
  • -3V external power supply

Test status

  • power up ok
  • fpga jtag ok
  • flash load ok
  • fpga boot from flash ok
  • VME slave interface: A32/D32 single word cycle ok (minus VME_A29), 32-bit and 64-bit transfer untested (should work), 2eVME and 2eSST untested (should work).
  • VME interface: D lines: read ok, drive ok, A lines read ok (minus VME_A29), A lines drive untested. AS/DS read ok, drive untested. DTACK read ok, drive ok.
  • VME flash programmer (srunner_vme): connected, can read silicon ID, but problem with pof and jic data format, not usable.
  • FPGA reboot ok ("remote update" block)
  • front panel I/O LEDs: partially tested (generally alive. mapping and individual leds untested)
  • front panel RGB LED: untested (no RGB_LED_SDI)
  • LVDS/ECL input: untested
  • NIM/TTL input/output: untested
  • SATA connectors: untested
  • clock cleaner: untested
  • ethernet interface: RX/TX untested, SPI untested, ethernet MAC address flash memory untested

ZZZ