Cdms workshop: Difference between revisions
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== MIDAS slow controls paths == | == MIDAS slow controls paths == | ||
[[Image:web_paths_svg.svg]] | |||
[[Image:web_paths.png]] | |||
== MIDAS history paths == | == MIDAS history paths == | ||
TBW | TBW | ||
Revision as of 07:48, 10 March 2014
Notes for the CDMS workshop March 2014
MIDAS general picture
MIDAS main data path
hardware -> mfe user thread -> ring buffer -> (compression thread -> ring buffer ->) mfe main thread -> TCP socket -> mserver -> event buffer -> event builder thread -> SYSTEM buffer -> mlogger -> (ring buffer -> compression thread -> ) data file -> lazylogger -> dcache/castor/hadoop/cloud storage
Needs to scale from 0.5GB/0.3GHz/1core PPC on FPGA to 1GB/1GHz/1core 32-bit ARM to 64GB/4GHz/12core 64-bit x86!
MIDAS web security
MIDAS slow controls paths
MIDAS history paths
TBW