| Date |
User |
Note |
| 2019-05-14 00:00:00 |
|
labeled "dead, overheated". K.O. |
| 2019-09-25 00:00:00 |
|
jtag ok, sof load ok, boot ok, cannot access EPCQ device. quartus flash programmer cannot identify EPCQ device. K.O. |
| 2019-09-25 00:00:00 |
|
Error (209025): Can't recognize silicon ID for device 1. A device's silicon ID is different from its JTAG ID. Verify that all cables are securely connected, select a different device, or check the power on the target system. Make sure the device pins are connected and configured correctly.
|
| 2020-10-04 00:00:00 |
|
the vcxo drive from clock cleaner is erratic, from long zero, goes to (3.3/2)V, as it should in holdover mode, but quickly has exp decay back to zero. then the cycle repeats. on the fpga side this is seen as a series of pll-lock-loss events that trigger nios restart. on the nios-console all this looks like a series of erratic nios reboots/resets. K.O. |
| 2020-10-04 00:00:00 |
|
the clock cleaner powers up in "pin select" mode, the fpga code drives these pins to "holdover mode", which should keep the vcxo dac constant (hopefully at half-scale, (3.3/2)V). right now nios reboots before reprogramming the clock cleaner, so all clock cleaner registers are in power-on state. K.O. |
| 2020-10-04 00:00:00 |
|
signaltap can see the clock cleaner "HOLDOVER" signal drop out. this should not happen as we continuously drive the pin select mode to "holdover mode". K.O. |
| 2020-10-06 00:00:00 |
|
epcq: see activity on nCS, DCL and DQ0. K.O.
|