| Date |
User |
Note |
| 2023-02-15 00:00:00 |
|
firmware was already loaded
no problems |
| 2023-02-15 00:00:00 |
|
missing LVDS3/4 |
| 2023-02-17 00:00:00 |
|
ethernet OK, esper OK |
| 2023-03-27 00:00:00 |
|
testing temp_spi: at U4, 2.5V FPGA side: SCK ok, CSn ok, RSTn ok, SDI from FPGA is strange. at U4 3.3V side: SCK ok, CSn ok, RSTn ok, SDI is stuck at zero. at TEMP, SDO is stuck at ~1V. K.O. |
| 2023-03-27 00:00:00 |
|
testing ext_spi: CS, clock, SDO present, but CF5,6,7,8 must be removed. K.O. |
| 2023-03-29 00:00:00 |
|
EXT_SPI capacitors removed. K.O. |
| 2023-03-29 00:00:00 |
|
output 12.5 MHz clock to Temp_SPI, see it on SCK and RSTn, see nothing on SDI and CSn. |
| 2023-03-29 00:00:00 |
|
LVDS3/4 clock fanouts installed by Peter M. |
| 2023-03-29 00:00:00 |
|
tested off TPC, all waveforms look ok. K.O. |
| 2023-04-05 00:00:00 |
|
Ext SPI caps removed |
| 2023-04-17 00:00:00 |
|
baseline offset resistors are correct. K.O. & L.M. |