The PowerPC MMU introduces a distinction between instruction and data MMU and allows them to be separately enabled or disabled. Two parameters, USER_I_MMU_ENABLE and USER_D_MMU_ENABLE, are enabled by default in the Params tab of the Properties window under SELECT_MMU. To enable/disable one or both MMUs, select the corresponding parameter and remove the TRUE.

The PowerPC 603 and 604 MMU supports two models for memory mapping. The first, the BAT model, allows mapping of a memory block ranging in size from 128KB to 256MB into a BAT register. The second, the segment model, gives the ability to map the memory in pages of 4KB. Tornado for PowerPC supports both memory models.

The size of a BAT register is two words of 32 bits. For the PowerPC 603 and PowerPC 604, eight BAT registers are implemented: four for the instruction MMU and four for the data MMU.

The data structure sysBatDesc[], defined in sysLib.c, handles the BAT register configuration. The registers will be set by the initialization software in the MMU library. By default these registers are cleared and set to zero.

All the configuration constants used to fill the sysBatDesc[] are defined in installDir/target/h/arch/ppc/mmu603Lib.h for both the PowerPC 603 and the PowerPC 604.

This model specifies the configuration for each memory page. The entire physical memory is described by the data structure sysPhysMemDesc[], defined in sysLib.c. This data structure is made up of configuration constants for each page or group of pages. All the configuration constants defined in Table 7-1 of 7. Virtual Memory Interface are available for PowerPC virtual memory pages.

Use of the VM_STATE_CACHEABLE constant listed in Table 7-1 for each page or group of pages, sets the cache to copy-back mode.

In addition to VM_STATE_CACHEABLE, the following additional constants are supported:

The first constant sets the page descriptor cache mode field in cacheable write-through mode. Cache coherency and guarded modes are controlled by the other constants.

For more information regarding cache modes, refer to PowerPC Microprocessor Family: The Programming Environments.

For more information on memory page states, state flags, and state masks, see 7. Virtual Memory Interface.

The page table size depends on the total memory to be mapped. The larger the memory to be mapped, the bigger the page table will be. The VxWorks implementation of the segment model follows the recommendations given in PowerPC Microprocessor Family: The Programming Environments. During MMU library initialization, the total size of the memory to be mapped is computed, allowing dynamic determination of the page table size. The following table shows the correspondence between the total amount of memory to map and the page table size.

Table 9-4:  Page table size