vf48.h

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00001 /*********************************************************************
00002 
00003   Name:         vf48.h
00004   Created by:   Pierre-Andre Amaudruz / Jean-Pierre Martin
00005 
00006   Contents:     48 ch Flash ADC / 20-64 Msps from J.-P. Martin
00007   $Id: vf48.h 4463 2009-04-04 01:31:28Z olchanski $
00008 
00009 *********************************************************************/
00010  
00011 #ifndef  VF48_INCLUDE_H
00012 #define  VF48_INCLUDE_H
00013 
00014 #include <stdio.h>
00015 #include <string.h>
00016 
00017 #include "mvmestd.h"
00018 
00019 /* Definitions */
00020 #define VF48_IDXMAX 4096
00021  
00022 /* Registers */
00023 #define  VF48_MAX_CHANNELS         (DWORD) 48
00024 #define  VF48_SUCCESS              (1)
00025 #define  VF48_ERROR                (-1)
00026 #define  VF48_ERR_PARM             (-1)
00027 #define  VF48_ERR_NODATA           (503)
00028 #define  VF48_ERR_HW               (603)
00029 #define  VF48_CSR_REG_RW           (DWORD) (0)          /**< -RW-D16/32 */
00030 #define  VF48_SELECTIVE_SET_W      (DWORD) (0x0010)
00031 #define  VF48_SELECTIVE_CLR_W      (DWORD) (0x0014)
00032 #define  VF48_TEST_REG_RW          (DWORD) (0x0020)
00033 #define  VF48_FIRMWARE_R           (DWORD) (0x0030)  /**< -R-D16/32 */
00034 #define  VF48_SOFTWARE_RESET_W     (DWORD) (0x0040)  /**< -W */
00035 #define  VF48_PARAM_DATA_RW        (DWORD) (0x0050)  /**< -RW-D16/32 */
00036 #define  VF48_PARAM_ID_W           (DWORD) (0x0060)  /**< -W-D16/32 */
00037 #define  VF48_SOFT_TRIG_W          (DWORD) (0x0070)
00038 #define  VF48_LVDSSR_W             (DWORD) (0x0080)
00039 #define  VF48_GRP_REG_RW           (DWORD) (0x0090)
00040 #define  VF48_NFRAME_R             (DWORD) (0x00A0)  /**< -R-D16/32 */
00041 #define  VF48_GLOBAL_RESET_W       (DWORD) (0x00B0)  /**< -W */
00042 #define  VF48_DATA_FIFO_R          (DWORD) (0x1000)  /**< -R-D32 */
00043 /*
00044 Parameter frame
00045 15 ...    ...
00046 CCCCDDDD RVPP PPPP
00047 C: Destination Card/Port N/A
00048 R: Read bit (0:Write, 1:Read)
00049 D: Destination channels (0..5)
00050    bit 11..8
00051           0: channel 1..8
00052           1: channel 9..16
00053           2: channel 17..24
00054           3: channel 25..32
00055           4: channel 33..40
00056           5: channel 41..48
00057           6: channel N/C
00058       7..15: channel N/C
00059 V: Version 0 for now (0:D16, 1:D32(extended))
00060 P: Parameter ID
00061   Default values for the different PIDs
00062 ID#   Def Value
00063 1     0x0000 Pedestal
00064 2     0x000A Hit Det Threshold
00065 3     0x0028 Clip Delay
00066 4     0x0020 Pre-Trigger
00067 5     0x0100 Segment size
00068 6     0x0190 K-coeff
00069 7     0x0200 L-coeff
00070 8     0x1000 M-coeff
00071 9     0x0005 Feature Delay A
00072 10    0x0000 Mbit1
00073           0x1: Data simulation
00074           0x2: Supress Raw Data
00075           0x8: Inverse Signal
00076 11    0x0001 Feature Delay B
00077 12    0x0005 Latency
00078 13    0x0100 Firmware ID
00079 14    0x0190 Attenuator
00080 15    0x0050 Trigger threshold
00081 16    0x00FF Active Channel Mask
00082 17    0x0000 Mbit2
00083           0x1: Enable Channel Suppress
00084        0xff00: sampling divisor         // Temporary
00085 */
00086 
00087 /* Parameters ID for Frontend */
00088 #define  VF48_GRP_OFFSET           (DWORD) (12)
00089 #define  VF48_PARMA_BIT_RD         (DWORD) (0x80)
00090 #define  VF48_PEDESTAL             (DWORD) (1)    //** 0x0000
00091 #define  VF48_HIT_THRESHOLD        (DWORD) (2)    //** 0x000A
00092 #define  VF48_CLIP_DELAY           (DWORD) (3)    //** 0x0028
00093 #define  VF48_PRE_TRIGGER          (DWORD) (4)    //** 0x0020
00094 #define  VF48_SEGMENT_SIZE         (DWORD) (5)    //** 0x0100
00095 #define  VF48_K_COEF               (DWORD) (6)    //** 0x0190
00096 #define  VF48_L_COEF               (DWORD) (7)    //** 0x0200
00097 #define  VF48_M_COEF               (DWORD) (8)    //** 0x1000
00098 #define  VF48_DELAY_A              (DWORD) (9)    //** 0x0005
00099 #define  VF48_MBIT1                (DWORD) (10)   //** 0x0000
00100 #define  VF48_DELAY_B              (DWORD) (11)   //** 0x0001
00101 #define  VF48_LATENCY              (DWORD) (12)   //** 0x0005
00102 #define  VF48_FIRMWARE_ID          (DWORD) (13)   //** 0x0100
00103 #define  VF48_ATTENUATOR           (DWORD) (14)   //** 0x0190
00104 #define  VF48_TRIG_THRESHOLD       (DWORD) (15)   //** 0x0050
00105 // #define  VF48_ACTIVE_CH_MASK       (DWORD) (16)   //** 0x00FF
00106 // #define  VF48_MBIT2                (DWORD) (17)   //** 0x0000
00107 
00108 #define  VF48_ACTIVE_CH_MASK       (DWORD) (9)   //** 0x00FF << Temporary
00109 #define  VF48_MBIT2                (DWORD) (11)   //** 0x0000 << Temporary
00110 
00111 /* CSR bit assignment */
00112 /*
00113   CSR setting:
00114     0: Run  0:stop, 1:start
00115     1: Parameter ID ready
00116     2: Parameter Data ready
00117     3: Event Fifo Not empty
00118 */
00119 #define  VF48_CSR_START_ACQ        (DWORD) (0x00000001)
00120 #define  VF48_CSR_PARM_ID_RDY      (DWORD) (0x00000002)
00121 #define  VF48_CSR_PARM_DATA_RDY    (DWORD) (0x00000004)
00122 #define  VF48_CSR_FE_NOTEMPTY      (DWORD) (0x00000008)
00123 #define  VF48_CSR_CRC_ERROR        (DWORD) (0x00000020)
00124 #define  VF48_CSR_EXT_TRIGGER      (DWORD) (0x00000080)
00125 #define  VF48_CSR_FE_FULL          (DWORD) (0x00008000)
00126 #define  VF48_RAW_DISABLE           0x2
00127 #define  VF48_CH_SUPPRESS_ENABLE    0x1
00128 #define  VF48_INVERSE_SIGNAL        0x8
00129 #define  VF48_ALL_CHANNELS_ACTIVE   0xFF
00130 /* Header definition */
00131 #define  VF48_HEADER               (DWORD) (0x80000000)
00132 #define  VF48_TIME_STAMP           (DWORD) (0xA0000000)
00133 #define  VF48_CHANNEL              (DWORD) (0xC0000000)
00134 #define  VF48_DATA                 (DWORD) (0x00000000)
00135 #define  VF48_CFD_FEATURE          (DWORD) (0x40000000)
00136 #define  VF48_Q_FEATURE            (DWORD) (0x50000000)
00137 #define  VF48_TRAILER              (DWORD) (0xE0000000)
00138 
00139 //#define  VF48_OUT_OF_SYNC          (DWORD) (0x88000000)
00140 //#define  VF48_TIMEOUT              (DWORD) (0x10000000)
00141 
00142 int  vf48_isPresent(MVME_INTERFACE *mvme, DWORD base);
00143 int  vf48_Setup(MVME_INTERFACE *mvme, DWORD base, int mode);
00144 int  vf48_EventRead(MVME_INTERFACE *myvme, DWORD base, DWORD *event, int *elements);
00145 int  vf48_EventRead64(MVME_INTERFACE *myvme, DWORD base, DWORD *event, int *elements);
00146 int  vf48_GroupRead(MVME_INTERFACE *myvme, DWORD base, DWORD *event, int grp, int *elements);
00147 int  vf48_DataRead(MVME_INTERFACE *myvme, DWORD base, DWORD *event, int *elements);
00148 int  vf48_ExtTrgSet(MVME_INTERFACE *myvme, DWORD base);
00149 int  vf48_ExtTrgClr(MVME_INTERFACE *myvme, DWORD base);
00150 int  vf48_Reset(MVME_INTERFACE *myvme, DWORD base);
00151 int  vf48_ResetCollector(MVME_INTERFACE *myvme, DWORD base);
00152 int  vf48_ResetFrontends(MVME_INTERFACE *myvme, DWORD base, int groupMask);
00153 int  vf48_AcqStart(MVME_INTERFACE *myvme, DWORD base);
00154 int  vf48_AcqStop(MVME_INTERFACE *myvme, DWORD base);
00155 int  vf48_NFrameRead(MVME_INTERFACE *myvme, DWORD base);
00156 int  vf48_CsrRead(MVME_INTERFACE *myvme, DWORD base);
00157 int  vf48_GrpRead(MVME_INTERFACE *myvme, DWORD base);
00158 int  vf48_FeFull(MVME_INTERFACE *myvme, DWORD base);
00159 int  vf48_EvtEmpty(MVME_INTERFACE *myvme, DWORD base);
00160 int  vf48_GrpEnable(MVME_INTERFACE *myvme, DWORD base, int grpbit);
00161 int  vf48_GrpRead(MVME_INTERFACE *myvme, DWORD base);
00162 int  vf48_GrpOperationMode(MVME_INTERFACE *myvme, DWORD base, int grp, int opmode);
00163 int  vf48_ParameterRead(MVME_INTERFACE *myvme, DWORD base, int grp, int param);
00164 int  vf48_ParameterWrite(MVME_INTERFACE *myvme, DWORD base, int grp, int param, int value);
00165 int  vf48_ParameterCheck(MVME_INTERFACE *myvme, DWORD base, int what);
00166 int  vf48_SegmentSizeSet(MVME_INTERFACE *mvme, DWORD base, DWORD size);
00167 int  vf48_SegmentSizeRead(MVME_INTERFACE *mvme, DWORD base, int grp);
00168 int  vf48_TrgThresholdSet(MVME_INTERFACE *mvme, DWORD base, int grp, DWORD size);
00169 int  vf48_TrgThresholdRead(MVME_INTERFACE *mvme, DWORD base, int grp);
00170 int  vf48_HitThresholdSet(MVME_INTERFACE *mvme, DWORD base, int grp, DWORD size);
00171 int  vf48_HitThresholdRead(MVME_INTERFACE *mvme, DWORD base, int grp);
00172 int  vf48_ActiveChMaskSet(MVME_INTERFACE *mvme, DWORD base, int grp, DWORD size);
00173 int  vf48_ActiveChMaskRead(MVME_INTERFACE *mvme, DWORD base, int grp);
00174 int  vf48_RawDataSuppSet(MVME_INTERFACE *mvme, DWORD base, int grp, DWORD size);
00175 int  vf48_RawDataSuppRead(MVME_INTERFACE *mvme, DWORD base, int grp);
00176 int  vf48_ChSuppSet(MVME_INTERFACE *mvme, DWORD base, int grp, DWORD size);
00177 int  vf48_ChSuppRead(MVME_INTERFACE *mvme, DWORD base, int grp);
00178 int  vf48_DivisorWrite(MVME_INTERFACE *mvme, DWORD base, DWORD size);
00179 int  vf48_DivisorRead(MVME_INTERFACE *mvme, DWORD base, int grp);
00180 int  vf48_Trigger(MVME_INTERFACE *mvme, DWORD base);
00181 int  vf48_Status(MVME_INTERFACE *mvme, DWORD base);
00182 #endif
00183 

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Contributions: Pierre-Andre Amaudruz - Sergio Ballestrero - Suzannah Daviel - Doxygen - Peter Green - Qing Gu - Greg Hackman - Gertjan Hofman - Paul Knowles - Exaos Lee - Rudi Meier - Glenn Moloney - Dave Morris - John M O'Donnell - Konstantin Olchanski - Renee Poutissou - Tamsen Schurman - Andreas Suter - Jan M.Wouters - Piotr Adam Zolnierczuk