caenv488.c

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00001 /*-----------------------------------------------------------------------------
00002  *  Copyright (c) 1996      TRIUMF Data Acquistion Group
00003  *  Please leave this header in any reproduction of that distribution
00004  *
00005  *  TRIUMF Data Acquisition Group, 4004 Wesbrook Mall, Vancouver, B.C. V6T 2A3
00006  *  Email: online@triumf.ca           Tel: (604) 222-1047  Fax: (604) 222-1074
00007  *         amaudruz@triumf.ca
00008  * -----------------------------------------------------------------------------
00009  *
00010  *  Description : function library for the CAEN V488 *TDC chan.
00011  *                no interrupt support yet
00012  *  Requires    :
00013  *  Author:  Pierre-Andre Amaudruz Data Acquisition Group
00014  *  Revision History:
00015  *  Revision 1.0  1998/Jun02 Pierre      Initial revision
00016  *
00017  *---------------------------------------------------------------------------*/
00018 
00019 #ifdef OS_VXWORKS
00020 #include "vxWorks.h"
00021 #include "vme.h"
00022 #endif
00023 
00024 #define A24D16_V488  0xf0000000 /* A24D16 access */
00025 
00026 #if defined( _MSC_VER )
00027 #define INLINE __inline
00028 #elif defined(__GNUC__)
00029 #define INLINE __inline__
00030 #else
00031 #define INLINE
00032 #endif
00033 
00034 #define EXTERNAL extern
00035 
00036 #ifndef MIDAS_TYPE_DEFINED
00037 #define MIDAS_TYPE_DEFINED
00038 
00039 typedef unsigned short int WORD;
00040 
00041 #ifdef __alpha
00042 typedef unsigned int DWORD;
00043 #else
00044 typedef unsigned long int DWORD;
00045 #endif
00046 
00047 #endif                          /* MIDAS_TYPE_DEFINED */
00048 
00049 #define VER_SER     0xFE        /* version _ serial# */
00050 #define MAN_MOD     0xFC        /* manufactor ID _ mode type */
00051 #define FIXED_CODE  0xFA        /* fix code ID */
00052 #define HF_REG      0x1E        /* Half full reg */
00053 #define RESET_REG   0x1C        /* reset reg */
00054 #define CTL_REG     0x1A        /* control reg */
00055 #define OUTB_REG    0x18        /* Output buffer reg */
00056 #define FF_REG      0x16        /* Fifo full reg */
00057 #define RR_REG      0x14        /* Range reg */
00058 #define THRH_REG    0x12        /* High threshold reg */
00059 #define THRL_REG    0x10        /* Low threshold reg */
00060 #define INT_REG     0x00        /* interrupt reg */
00061 #define V488_CSTART 0x8000      /* Common start */
00062 #define V488_IE1    0x1
00063 #define V488_IE2    0x2
00064 #define V488_IE3    0x4
00065 #define V488_IE4    0x8
00066 #define V488_IE5    0x10
00067 #define V488_IE6    0x20
00068 #define V488_IE7    0x40
00069 #define V488_IE8    0x80
00070 #define V488_IE14   0xf
00071 #define V488_IE58   0xf0
00072 #define V488_IE18   0xff
00073 
00074 INLINE caenv488_HF_set(const DWORD base, const WORD mode)
00075 {
00076    volatile WORD *spec_adr;
00077 
00078    spec_adr = (WORD *) (A24D16_V488 | base | HF_REG);
00079    if (mode)
00080       *spec_adr = 0x1 << 12;
00081    else
00082       *spec_adr = 0x0;
00083 }
00084 
00085 INLINE caenv488_HF_get(const DWORD base, WORD * mode)
00086 {
00087    volatile WORD *spec_adr;
00088 
00089    spec_adr = (WORD *) (A24D16_V488 | base | HF_REG);
00090    *mode = *spec_adr;
00091    *mode = (*mode >> 12) & 0x1;
00092 }
00093 
00094 INLINE caenv488_reset(const DWORD base)
00095 {
00096    volatile WORD *spec_adr;
00097 
00098    spec_adr = (WORD *) (A24D16_V488 | base | RESET_REG);
00099    *spec_adr = 0x0;
00100 }
00101 
00102 INLINE caenv488_CTL_write(const DWORD base, const WORD mode)
00103 {
00104    volatile WORD *spec_adr;
00105    volatile WORD ctl;
00106 
00107    spec_adr = (WORD *) (A24D16_V488 | base | CTL_REG);
00108    ctl = *spec_adr;
00109    ctl |= mode & 0x80ff;
00110    *spec_adr = ctl & 0x80ff;
00111 }
00112 
00113 INLINE caenv488_CTL_read(const DWORD base, WORD * mode)
00114 {
00115    volatile WORD *spec_adr;
00116 
00117    spec_adr = (WORD *) (A24D16_V488 | base | CTL_REG);
00118    *mode = *spec_adr;
00119 }
00120 
00121 INLINE caenv488_RR_write(const DWORD base, const WORD mode)
00122 {
00123    volatile WORD *spec_adr;
00124 
00125    spec_adr = (WORD *) (A24D16_V488 | base | RR_REG);
00126    *spec_adr = mode & 0x11ff;
00127 }
00128 
00129 INLINE caenv488_THRH_write(const DWORD base, const WORD mode)
00130 {
00131    volatile WORD *spec_adr;
00132 
00133    spec_adr = (WORD *) (A24D16_V488 | base | THRH_REG);
00134    *spec_adr = mode & 0xff;
00135 }
00136 
00137 INLINE caenv488_THRL_write(const DWORD base, const WORD mode)
00138 {
00139    volatile WORD *spec_adr;
00140 
00141    spec_adr = (WORD *) (A24D16_V488 | base | THRL_REG);
00142    *spec_adr = mode & 0xff;
00143 }
00144 
00145 INLINE caenv488_FF_set(const DWORD base)
00146 {
00147    volatile WORD *spec_adr;
00148 
00149    spec_adr = (WORD *) (A24D16_V488 | base | FF_REG);
00150    *spec_adr = 0x0;
00151 }
00152 
00153 INLINE caenv488_read(const DWORD base, WORD ** data)
00154 {
00155    volatile WORD *spec_adr;
00156    int header, mult;
00157 
00158    spec_adr = (WORD *) (A24D16_V488 | base | OUTB_REG);
00159    header = *spec_adr;
00160    if (header & 0x8000) {
00161       if ((header & 0xfff) != 1)
00162          logMsg("Event counter in V488 base:0x%x = %d", base, (header & 0xfff), 0, 0, 0,
00163                 0);
00164       else {
00165          mult = (header >> 12) & 0x7;
00166          while (mult > 0) {
00167             *((*data)++) = *spec_adr;
00168          }
00169       }
00170    } else
00171       logMsg("Event out of sequence in V488 base 0x%x", base, 0, 0, 0, 0, 0);
00172 }
00173 
00174 /*-Tests---------------------------------------------------------*/
00175 void caenv488(void)
00176 {
00177    printf("\n CAEN V488 8ch. TDC Tool Box\n");
00178    printf("Inline : caenv488_HF_set(DWORD vmeBase);\n");
00179    printf("Inline : caenv488_HF_get(DWORD vmeBase, INT * mode);\n");
00180    printf("Inline : caenv488_reset(DWORD vmeBase);\n");
00181    printf("Inline : caenv488_CTL_write(DWORD vmeBase, WORD mode);\n");
00182    printf("Inline : caenv488_CTL_read(DWORD vmeBase, WORD * mode);\n");
00183    printf("Inline : caenv488_RR_write(DWORD vmeBase, WORD mode);\n");
00184    printf("Inline : caenv488_THRH_write(DWORD vmeBase, WORD value);\n");
00185    printf("Inline : caenv488_FF_set(DWORD vmeBase, WORD value);\n");
00186    printf("Inline : caenv488_read(DWORD vmeBase, WORD ** data);\n");
00187    printf("Test   : caenv488_MIW(DWORDS base)\n");
00188    printf("Test   : caenv488_status(DWORD base)\n");
00189    printf("Test   : caenv488_cstop_set(DWORDS base)\n");
00190    printf("Test   : caenv488_cstart_set(DWORDS base)\n");
00191    printf("Test   : caenv488_all_enable(DWORDS base)\n");
00192    printf("Test   : caenv488_all_disable(DWORDS base)\n");
00193    printf("Test   : caenv488_std_init(DWORDS base)\n");
00194    printf("Test   : caenv488_outb_read(DWORDS base)\n");
00195 }
00196 
00197 INLINE void caenv488_MIW(DWORD base)
00198 {
00199    volatile WORD *spec_adr;
00200    volatile WORD data;
00201 
00202    /* module */
00203    spec_adr = (WORD *) (A24D16_V488 | base | VER_SER);
00204    data = *spec_adr;
00205    printf("Version  : 0x%x - Serial#   : 0x%x\n", (data >> 12) & 0xf, data & 0xfff);
00206    spec_adr = (WORD *) (A24D16_V488 | base | MAN_MOD);
00207    data = *spec_adr;
00208    printf("Manuf.#  : 0x%x - Mod. type#: 0x%x\n", (data >> 10) & 0x3f, data & 0x3ff);
00209    spec_adr = (WORD *) (A24D16_V488 | base | FIXED_CODE);
00210    data = *spec_adr;
00211    printf("FA code  : 0x%x - F5 code  : 0x%x\n", (data >> 8) & 0xff, data & 0xff);
00212 
00213    /* RR */
00214    spec_adr = (WORD *) (A24D16_V488 | base | RR_REG);
00215    data = *spec_adr;
00216    if (data & 0x1000)
00217       printf("Mode FIFO full      - ");
00218    else
00219       printf("Mode FIFO half full - ");
00220 
00221    /* CTL */
00222    spec_adr = (WORD *) (A24D16_V488 | base | CTL_REG);
00223    data = *spec_adr;
00224    printf("Ch.enable: 0x%x \n", data & 0xff);
00225    if (data & 0x8000)
00226       printf("Common Start  - ");
00227    else
00228       printf("Common Stop   - ");
00229 
00230    if (data & 0x4000)
00231       printf("FIFO empty\n");
00232    else if (data & 0x2000)
00233       printf("FIFO Full\n");
00234    else if (data & 0x1000)
00235       printf("FIFO half full\n");
00236 }
00237 
00238 INLINE void caenv488_status(DWORD base)
00239 {
00240    volatile WORD *spec_adr;
00241    volatile WORD data;
00242 
00243    /* CTL */
00244    spec_adr = (WORD *) (A24D16_V488 | base | CTL_REG);
00245    data = *spec_adr;
00246    printf("CTL status: 0x%x - Ch.enable: 0x%x \n", data, data & 0xff);
00247    if (data & 0x8000)
00248       printf("Common Start       - ");
00249    else
00250       printf("Common Stop        - ");
00251 
00252    if (!(data & 0x4000))
00253       printf("FIFO empty\n");
00254    else if (!(data & 0x2000))
00255       printf("FIFO Full\n");
00256    else if (!(data & 0x1000))
00257       printf("FIFO half full\n");
00258 
00259    /* RR */
00260    spec_adr = (WORD *) (A24D16_V488 | base | RR_REG);
00261    data = *spec_adr;
00262    if (data & 0x1000)
00263       printf("Mode FIFO full     \n");
00264    else
00265       printf("Mode FIFO half full\n");
00266 }
00267 
00268 INLINE void caenv488_cstop_set(DWORD base)
00269 {
00270    WORD ctl;
00271 
00272    caenv488_CTL_read(base, &ctl);
00273    ctl &= 0x70ff;
00274    caenv488_CTL_write(base, ctl);
00275 }
00276 
00277 INLINE void caenv488_cstart_set(DWORD base)
00278 {
00279    caenv488_CTL_write(base, V488_CSTART);
00280 }
00281 
00282 INLINE void caenv488_all_enable(DWORD base)
00283 {
00284    caenv488_CTL_write(base, V488_IE18);
00285 }
00286 
00287 INLINE void caenv488_all_disable(DWORD base)
00288 {
00289    caenv488_CTL_write(base, 0x0);
00290 }
00291 
00292 INLINE void caenv488_std_init(DWORD base)
00293 {
00294    caenv488_reset(base);
00295    caenv488_THRH_write(base, 0xc7);
00296    caenv488_THRL_write(base, 0x00);
00297    caenv488_RR_write(base, 0xe0);
00298    caenv488_all_enable(base);
00299 }
00300 
00301 void caenv488_outb_read(DWORD base)
00302 {
00303    volatile WORD *spec_adr;
00304    volatile WORD data, header = 0;
00305 
00306    /* CTL */
00307    spec_adr = (WORD *) (A24D16_V488 | base | OUTB_REG);
00308    data = *spec_adr;
00309    for (;;) {
00310       if (data & 0x8000) {
00311          header = 1;
00312          printf("OutB header: 0x%x - ", data);
00313          printf("OutB multi : %d - event# : %d\n", ((data >> 12) & 0x7) + 1,
00314                 data & 0xfff);
00315          if (((data >> 12) & 0x7) == 0)
00316             break;
00317       } else {
00318          if (header) {
00319             header = 0;
00320             printf("OutB data  : 0x%x - ", data);
00321             printf("OutB chan. : %d - data# : %d\n", (data >> 12) & 0x7, data & 0xfff);
00322             if (((data >> 12) & 0x7) == 0)
00323                break;
00324          } else {
00325             printf("OutB data  : 0x%x - No header\n", data);
00326             break;
00327          }
00328       }
00329    }
00330 }

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Contributions: Pierre-Andre Amaudruz - Sergio Ballestrero - Suzannah Daviel - Doxygen - Peter Green - Qing Gu - Greg Hackman - Gertjan Hofman - Paul Knowles - Exaos Lee - Rudi Meier - Glenn Moloney - Dave Morris - John M O'Donnell - Konstantin Olchanski - Renee Poutissou - Tamsen Schurman - Andreas Suter - Jan M.Wouters - Piotr Adam Zolnierczuk