vf48.c

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00001 /*********************************************************************
00002   Name:         vf48.c
00003   Created by:   Pierre-Andre Amaudruz / Jean-Pierre Martin
00004 
00005   Contents:     48 ch Flash ADC / 20..64 Msps from J.-P. Martin
00006                 
00007   $Id: vf48.c 4721 2010-05-04 01:59:01Z svn $
00008 
00009 *********************************************************************/
00010 #include <stdio.h>
00011 #include <string.h>
00012 #include <stdlib.h>
00013 #include <assert.h>
00014 
00015 #include "vf48.h"
00016 
00017 /********************************************************************/
00018 /** vf48_EventRead64
00019     Read one Event through the local buffer. MBLT64 is used for aquiring
00020     a buffer, the event is then extracted from this buffer until event
00021     incomplete which in this case a DMA is requested again.
00022     @param mvme vme structure
00023     @param base  VF48 base address
00024     @param pdest Pointer to destination
00025     @param nentry Number of DWORD to transfer
00026     @return status VF48_ERROR, SUCCESS
00027 */
00028 static int   idx = 0, inbuf;
00029 int vf48_EventRead64(MVME_INTERFACE *mvme, DWORD base, DWORD *pdest, int *nentry)
00030 {
00031   int   markerfound, j;
00032   DWORD lData[VF48_IDXMAX];
00033   DWORD *phead;
00034   
00035   int timeout;
00036   
00037   mvme_set_am(  mvme, MVME_AM_A24);
00038   mvme_set_dmode(mvme, MVME_DMODE_D32);
00039   
00040   if (inbuf > VF48_IDXMAX) idx = 0;
00041   
00042   if (idx == 0) {
00043     inbuf = vf48_NFrameRead(mvme, base);
00044     // max readout buffer (HW dependent)
00045     vf48_DataRead(mvme, base, lData, &inbuf);
00046     //    printf("Data Read Idx=0 %d\n", inbuf);
00047   }
00048   
00049   // Check if available event found in local buffer
00050   timeout = 16;
00051   markerfound = 0;
00052   while (timeout) {
00053     // Scan local buffer from current index to top for Header
00054     while ((idx < inbuf) && ((lData[idx] & 0xF0000000) != VF48_HEADER)) {
00055       idx++;
00056     }
00057     if (idx < inbuf) {
00058       // Header found, save head, flag header, cp header
00059       timeout = 0;              // Reset to force exit on next test
00060       phead = pdest;            // Save top of event for evt length
00061       markerfound = 1;          //
00062       //      printf("Head found  idx %d\n", idx);
00063       *pdest++ = lData[idx];
00064       lData[idx] = 0xffffffff;
00065       idx++;
00066     } else {
00067       // No header found, request VME data (start at idx = 0)
00068       timeout--;               // Safe exit
00069       inbuf = vf48_NFrameRead(mvme, base);
00070       // max readout buffer (HW dependent)
00071       idx = 0;
00072       vf48_DataRead(mvme, base, lData, &inbuf);
00073       //      printf("Data Read Header search %d (timeout %d)\n", inbuf, timeout);
00074     }
00075   }
00076   if ((timeout == 0) && !markerfound) {
00077     //    printf("vf48_EventRead: Header Loop: Timeout Header not found\n");
00078     idx = 0;         // make sure we read VME on next call
00079     *nentry = 0;               // Set returned event length
00080     return VF48_ERROR;
00081   }
00082   
00083   //  printf("Starting data copy\n");
00084   timeout = 64;
00085   while(timeout) {
00086     timeout--;
00087     // copy rest of event until Trailer (nentry: valid# from last vme data)
00088     while ((idx < inbuf) && ((lData[idx] & 0xF0000000) != VF48_TRAILER)) {
00089       *pdest++ = lData[idx++];
00090     }
00091     if ((lData[idx] & 0xF0000000) == VF48_TRAILER) { 
00092       // Event complete return
00093       *pdest++ = lData[idx++];  // copy Trailer
00094       *nentry = pdest - phead;  // Compute event length
00095       //      printf("Event complete idx:%d last inbuf:%d evt len:%d\n", idx, inbuf, *nentry);
00096       return SUCCESS;
00097     } else {
00098       // No Trailer found, request VME data (start at idx = 0)
00099       //      timeout--;                // Safe exit
00100       j = 40000;
00101       while (j) { j--; }
00102       // usleep(1);
00103       inbuf = vf48_NFrameRead(mvme, base);
00104       vf48_DataRead(mvme,  base, lData, &inbuf);
00105       idx = 0;
00106       // printf("Data Read Trailer search %d (timeout:%d)\n", inbuf, timeout);
00107     }
00108     if (timeout == 0) {
00109       printf("vf48_EventRead: Trailer Loop: Timeout Trailer not found\n");
00110       idx = 0;                // make sure we read VME on next call
00111       *nentry = 0;               // Set returned event length
00112       return VF48_ERROR;
00113     }
00114   }
00115   printf(" coming out from here\n");
00116   return VF48_ERROR;
00117 }
00118 
00119 /********************************************************************/
00120 /** vf48_EventRead
00121    Read one Event (in 32bit mode)
00122    @param mvme vme structure
00123    @param base  VF48 base address
00124    @param pdest Pointer to destination
00125    @param nentry Number of DWORD to transfer
00126    @return status VF48_ERROR, SUCCESS
00127 */
00128 int vf48_EventRead(MVME_INTERFACE *mvme, DWORD base, DWORD *pdest, int *nentry)
00129 {
00130   int timeout, nframe;
00131   DWORD hdata;
00132 
00133   mvme_set_am(  mvme, MVME_AM_A24);
00134   mvme_set_dmode(mvme, MVME_DMODE_D32);
00135 
00136   *nentry = 0;
00137   nframe = mvme_read_value(mvme, base+VF48_NFRAME_R);
00138   //  printf("Event Nframe : %d - 0x%x\n", nframe, nframe);
00139 
00140   timeout=25000;  // max number of 32bits per event
00141   if (nframe) {
00142     do {
00143       timeout--;
00144       hdata = mvme_read_value(mvme, base+VF48_DATA_FIFO_R);
00145     } while (!((hdata & 0xF0000000) == VF48_HEADER) && (timeout)); // skip up to the header
00146 
00147     if (timeout == 0) {
00148       *nentry = 0;
00149       //      printf("timeout on header  data:0x%lx\n", hdata);
00150       return VF48_ERR_NODATA;
00151     }
00152     //    channel = (hdata >> 24) & 0xF;
00153     //    printf(">>>>>>>>>>>>>>> Channel : %d \n", channel);
00154     pdest[*nentry] = hdata;
00155     *nentry += 1;
00156     timeout=25000;  // max number of 32bits per event
00157     // Copy until Trailer (max event size == timeout!)
00158     do {
00159       pdest[*nentry] = mvme_read_value(mvme, base+VF48_DATA_FIFO_R);
00160       //      printf("pdest[%d]=0x%x\n", *nentry, pdest[*nentry]);
00161       timeout--;
00162       *nentry += 1;
00163     } while (!((pdest[*nentry-1] & 0xF0000000) == VF48_TRAILER) && timeout); // copy until trailer (included)
00164     if (timeout == 0) {
00165       printf("timeout on Trailer  data:0x%x\n", pdest[*nentry-1]);
00166       printf("nentry:%d data:0x%x base:0x%x \n", *nentry, pdest[*nentry], base+VF48_DATA_FIFO_R);
00167       *nentry = 0;
00168       return VF48_ERROR;
00169     }
00170     nentry--;
00171   }
00172 
00173   return (VF48_SUCCESS);
00174 }
00175 
00176 /********************************************************************/
00177 /** vf48_DataRead
00178 Read N entries (32bit) from the VF48 data FIFO using the MBLT64 mode
00179 @param mvme vme structure
00180 @param base  VF48 base address
00181 @param pdest Destination pointer
00182 @return nentry
00183  */
00184 int vf48_DataRead(MVME_INTERFACE *mvme, DWORD base, DWORD *pdest, int *nentry)
00185 {
00186   int status;
00187 
00188   mvme_set_am(  mvme, MVME_AM_A24);
00189   mvme_set_dmode(  mvme, MVME_DMODE_D32);
00190   mvme_set_blt(  mvme, MVME_BLT_MBLT64);
00191   //mvme_set_blt(  mvme, MVME_BLT_BLT32);
00192   //mvme_set_blt(  mvme, 0);
00193 
00194   // Transfer in MBLT64 (8bytes), nentry is in 32bits(VF48)
00195   // *nentry * 8 / 2
00196   status = mvme_read(mvme, pdest, base+VF48_DATA_FIFO_R, *nentry<<2);
00197   if (status != MVME_SUCCESS)
00198     return 0;
00199 
00200   return (*nentry);
00201 }
00202 
00203 /********************************************************************/
00204 int vf48_ParameterWrite(MVME_INTERFACE *mvme, DWORD base, int grp, int param, int value)
00205 {
00206   int retry;
00207 
00208   if (grp < 0 || grp >= 6) {
00209     printf("vf48_ParameterWrite: Invalid grp %d\n", grp);
00210     return VF48_ERR_PARM;
00211   }
00212 
00213   switch (param) {
00214   case VF48_SEGMENT_SIZE:
00215     if (value > 1023) {
00216       value = 1023;
00217       printf("vf48_ParameterWrite: Segment size troncated to 1023\n");
00218     }
00219     break;
00220   case VF48_PRE_TRIGGER:
00221     if (value > 127) {
00222       value = 100;
00223       printf("vf48_ParameterWrite: Pre trigger troncated to 100\n");
00224     }
00225     break;
00226   case VF48_LATENCY:
00227     if (value > 127) {
00228       value = 127;
00229       printf("vf48_ParameterWrite: Latency troncated to 127\n");
00230     }
00231     break;
00232   };
00233 
00234   mvme_set_am(  mvme, MVME_AM_A24);
00235   mvme_set_dmode(mvme, MVME_DMODE_D32);
00236 
00237   if (0) {
00238     int csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00239     printf("Writing grp %d, param %d, ID_RDY %d, DATA_RDY %d\n", grp, param, csr & VF48_CSR_PARM_ID_RDY, csr & VF48_CSR_PARM_DATA_RDY);
00240   }
00241 
00242   for (retry=20; retry>0; retry--) {
00243     int wr;
00244     int rd;
00245     
00246     wr = param | grp<<VF48_GRP_OFFSET;
00247     mvme_write_value(mvme, base+VF48_PARAM_ID_W, wr);
00248     
00249     // flush posted PCI writes
00250     mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00251     
00252     mvme_write_value(mvme, base+VF48_PARAM_DATA_RW, value);
00253     
00254     // flush posted PCI writes
00255     mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00256 
00257     rd = vf48_ParameterRead(mvme, base, grp, param);
00258 
00259     if (rd == VF48_ERR_PARM) {
00260       printf("vf48_ParameterWrite: Module at 0x%x, Group %d, parameter %d: Error %d during parameter read-back\n", base, grp, param, rd);
00261       return VF48_ERR_PARM;
00262     }
00263 
00264     //printf("Group %d, param %d, write %d, read %d\n", grp, param, value, rd);
00265 
00266     if (rd == value) {
00267       return VF48_SUCCESS;
00268     }
00269 
00270     printf("vf48_ParameterWrite: Module at 0x%x, Group %d, parameter %d: data mismatch error: wrote 0x%08x, read 0x%08x\n", base, grp, param, value, rd);
00271   }
00272 
00273   fprintf(stderr, "vf48_ParameterWrite: Group %d, parameter %d, too many retries writing VF48 parameter!\n", grp, param);
00274   return VF48_ERR_PARM;
00275 }
00276 
00277 /********************************************************************/
00278 /**
00279 Read any Parameter for a given group. Each group (0..5) handles
00280 8 consecutive input channels.
00281 @param mvme vme structure
00282 @param base  VMEIO base address
00283 @param grp   group number (0..5)
00284 @return VF48_SUCCESS, VF48_ERR_PARM
00285 */
00286 int vf48_ParameterRead(MVME_INTERFACE *mvme, DWORD base, int grp, int param)
00287 {
00288   int  to, retry;
00289   int  debug = 0;
00290 
00291   if (vf48_isPresent(mvme, base) != VF48_SUCCESS) {
00292     printf("vf48_ParameterRead: There is no VF48 at VME A24 0x%x\n", base);
00293     return VF48_ERR_PARM;
00294   }
00295 
00296   if (grp < 0 || grp >= 6) {
00297     printf("vf48_ParameterRead: Invalid grp %d\n", grp);
00298     return VF48_ERR_PARM;
00299   }
00300 
00301   mvme_set_am(mvme, MVME_AM_A24);
00302   mvme_set_dmode(mvme, MVME_DMODE_D32);
00303 
00304   for (retry=20; retry>0; retry--) {
00305 
00306     int csr = 0;
00307     int data = 0;
00308     int wr;
00309     
00310     if (debug) {
00311       csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00312       printf("vf48_ParameterRead: CSR 0x%x, Reading grp %d, param %d, ID_RDY %d, DATA_RDY %d\n", csr, grp, param, csr & VF48_CSR_PARM_ID_RDY, csr & VF48_CSR_PARM_DATA_RDY);
00313     }
00314 
00315     wr = VF48_PARMA_BIT_RD | param | grp<<VF48_GRP_OFFSET;
00316 
00317     if (debug)
00318        printf("write id 0x%04x\n", wr);
00319 
00320     mvme_write_value(mvme, base+VF48_PARAM_ID_W, wr);
00321 
00322     // flush posted PCI writes
00323     csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00324 
00325     if (debug) {
00326       printf("vf48_ParameterRead: CSR 0x%x, Reading grp %d, param %d, ID_RDY %d, DATA_RDY %d\n", csr, grp, param, csr & VF48_CSR_PARM_ID_RDY, csr & VF48_CSR_PARM_DATA_RDY);
00327 
00328       //if (!(csr & VF48_CSR_PARM_ID_RDY))
00329       //exit(123);
00330     }
00331 
00332     //mvme_write_value(mvme, base+VF48_PARAM_DATA_RW, 0xFFFFFFFF);
00333     mvme_write_value(mvme, base+VF48_PARAM_DATA_RW, 0xFFFFFFFF);
00334 
00335     // flush posted PCI writes
00336     csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00337 
00338     if (debug) {
00339       printf("vf48_ParameterRead: CSR 0x%x, Reading grp %d, param %d, ID_RDY %d, DATA_RDY %d\n", csr, grp, param, csr & VF48_CSR_PARM_ID_RDY, csr & VF48_CSR_PARM_DATA_RDY);
00340     }
00341 
00342     // wait for VF48_CSR_PARM_DATA_RDY
00343     for (to=10; to>0; to--) {
00344       csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00345       if (debug) {
00346          printf("vf48_ParameterRead: CSR 0x%x, Waiting for 0x%x, TO %d\n", csr, VF48_CSR_PARM_DATA_RDY, to);
00347          data = mvme_read_value(mvme, base+VF48_PARAM_DATA_RW);
00348          printf("data register 0x%x\n", data);
00349       }
00350       if (csr & VF48_CSR_PARM_DATA_RDY)
00351         break;
00352     }
00353 
00354     if (csr & VF48_CSR_CRC_ERROR) {
00355       if (1)
00356         printf("vf48_ParameterRead: CSR 0x%x, CRC error!\n", csr);
00357       //continue;
00358     }
00359 
00360     if (! (csr & VF48_CSR_PARM_DATA_RDY)) {
00361       if (debug)
00362         printf("vf48_ParameterRead: Group %d, parameter %d, timeout waiting for VF48_CSR_PARAM_DATA_RDY, retry %d\n", grp, param, retry);
00363       continue;
00364     }
00365 
00366     data = 0xFFFF & mvme_read_value(mvme, base+VF48_PARAM_DATA_RW);
00367     
00368     csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00369     
00370     if (debug)
00371       printf("vf48_ParameterRead: CSR 0x%x, data 0x%x\n", csr, data);
00372     
00373     return data;
00374   }
00375 
00376   //fprintf(stderr, "vf48_ParameterRead: Group %d, parameter %d, too many retries reading vf48 parameter!\n", grp, param);
00377   return VF48_ERR_PARM;
00378 }
00379 
00380 /********************************************************************/
00381 int vf48_Reset(MVME_INTERFACE *mvme, DWORD base)
00382 {
00383    int i, v, csr, good;
00384 
00385   mvme_set_am(mvme, MVME_AM_A24);
00386   mvme_set_dmode(mvme, MVME_DMODE_D16);
00387 
00388   if (1)
00389     printf("vf48_Reset: CSR 0x%x\n", mvme_read_value(mvme, base+VF48_CSR_REG_RW));
00390   mvme_write_value(mvme, base+VF48_GLOBAL_RESET_W, 0);
00391   csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW); // flush posted PCI writes
00392 
00393   if (1)
00394     printf("vf48_Reset: CSR 0x%x\n", csr);
00395 
00396 #if 0
00397   if (!(csr & VF48_CSR_PARM_ID_RDY) || !(csr & VF48_CSR_PARM_DATA_RDY)) {
00398      /* frontend realtime signals did not reset correctly,
00399       * reset them by toggling the "col_run" realtime signal */
00400 
00401      vf48_AcqStart(mvme, base);
00402   csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW); // flush posted PCI writes
00403   csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW); // flush posted PCI writes
00404   csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW); // flush posted PCI writes
00405   csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW); // flush posted PCI writes
00406   csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW); // flush posted PCI writes
00407   csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW); // flush posted PCI writes
00408      vf48_AcqStop(mvme, base);
00409 
00410      csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW); // flush posted PCI writes
00411 
00412      if (1)
00413         printf("vf48_Reset: CSR 0x%x\n", csr);
00414   }
00415 #endif
00416 
00417   mvme_write_value(mvme, base+VF48_TEST_REG_RW, 0x00000000);
00418   v = mvme_read_value(mvme, base+VF48_TEST_REG_RW);
00419   if (v != 0)
00420     printf("vf48_Reset: Test register data mismatch: read 0x%08x, expected 0\n", v);
00421 
00422   mvme_write_value(mvme, base+VF48_TEST_REG_RW, 0x0000FFFF);
00423   v = mvme_read_value(mvme, base+VF48_TEST_REG_RW);
00424   if (v != 0x0000FFFF)
00425     printf("vf48_Reset: Test register data mismatch: read 0x%08x, expected 0x0000FFFF\n", v);
00426 
00427   if (vf48_isPresent(mvme, base) != VF48_SUCCESS) {
00428     printf("There is no VF48 at VME A24 0x%x\n", base);
00429     return VF48_ERR_HW;
00430   }
00431 
00432   printf("vf48_Reset: Module 0x%06x: Firmware revision: collector: 0x%x, frontend:", base, mvme_read_value(mvme, base+VF48_FIRMWARE_R));
00433   
00434   good = 1;
00435   for (i=0; i<6; i++) {
00436      v = vf48_ParameterRead(mvme, base, i, VF48_FIRMWARE_ID);
00437      printf(" 0x%x", v);
00438      if (v < 0)
00439         good = 0;
00440   }
00441   printf("\n");
00442 
00443   return VF48_SUCCESS;
00444 }
00445 
00446 /********************************************************************/
00447 int vf48_ResetCollector(MVME_INTERFACE *mvme, DWORD base)
00448 {
00449   mvme_set_am(mvme, MVME_AM_A24);
00450   mvme_set_dmode(mvme, MVME_DMODE_D16);
00451   mvme_write_value(mvme, base+VF48_SOFTWARE_RESET_W, 0);
00452   mvme_read_value(mvme, base+VF48_CSR_REG_RW); // flush posted PCI writes
00453   return VF48_SUCCESS;
00454 }
00455 
00456 /********************************************************************/
00457 int vf48_ResetFrontends(MVME_INTERFACE *mvme, DWORD base, int groupMask)
00458 {
00459   mvme_set_am(mvme, MVME_AM_A24);
00460   mvme_set_dmode(mvme, MVME_DMODE_D16);
00461   mvme_write_value(mvme, base+VF48_LVDSSR_W, groupMask);
00462   mvme_read_value(mvme, base+VF48_CSR_REG_RW); // flush posted PCI writes
00463   return VF48_SUCCESS;
00464 }
00465 
00466 /********************************************************************/
00467 int vf48_AcqStart(MVME_INTERFACE *mvme, DWORD base)
00468 {
00469   int  csr;
00470 
00471   mvme_set_am(mvme, MVME_AM_A24);
00472   mvme_set_dmode(mvme, MVME_DMODE_D32);
00473   csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00474   csr |= VF48_CSR_START_ACQ;  // start ACQ
00475   mvme_write_value(mvme, base+VF48_CSR_REG_RW, csr);
00476   mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00477   return VF48_SUCCESS;
00478 
00479 #if 0
00480   status = mvme_read_value(mvme, base+VF48_NFRAME_R);
00481   if (status <= 0xFF) {
00482     mvme_write_value(mvme, base+VF48_SELECTIVE_SET_W, VF48_CSR_ACTIVE_ACQ);
00483   }
00484   return (status > 0xFF ? VF48_ERR_HW : VF48_SUCCESS);
00485 #endif
00486 }
00487 
00488 /********************************************************************/
00489 int vf48_AcqStop(MVME_INTERFACE *mvme, DWORD base)
00490 {
00491   int  csr;
00492 
00493   mvme_set_am(mvme, MVME_AM_A24);
00494   mvme_set_dmode(mvme, MVME_DMODE_D32);
00495   csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00496   csr &= ~(VF48_CSR_START_ACQ);  // stop ACQ
00497   mvme_write_value(mvme, base+VF48_CSR_REG_RW, csr);
00498   mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00499   return VF48_SUCCESS;
00500 
00501 #if 0
00502   status = mvme_read_value(mvme, base+VF48_NFRAME_R);
00503   if (status <= 0xFF) {
00504     mvme_write_value(mvme, base+VF48_SELECTIVE_CLR_W, VF48_CSR_ACTIVE_ACQ);
00505   }
00506   return (status > 0xFF ? VF48_ERR_HW : VF48_SUCCESS);
00507 #endif
00508 }
00509 
00510 /********************************************************************/
00511 /**
00512 Set External Trigger enable
00513 @param mvme vme structure
00514 @param base  VF48 base address
00515 @return VF48_SUCCESS
00516 */
00517 int vf48_ExtTrgSet(MVME_INTERFACE *mvme, DWORD base)
00518 {
00519   int csr;
00520   mvme_set_am(mvme, MVME_AM_A24);
00521   mvme_set_dmode(mvme, MVME_DMODE_D32);
00522   csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00523   csr |= VF48_CSR_EXT_TRIGGER;  // Set
00524   mvme_write_value(mvme, base+VF48_CSR_REG_RW, csr);
00525   return VF48_SUCCESS;
00526 }
00527 
00528 /********************************************************************/
00529 /**
00530 Clear External Trigger enable
00531 @param mvme vme structure
00532 @param base  VMEIO base address
00533 @return vf48_SUCCESS
00534 */
00535 int vf48_ExtTrgClr(MVME_INTERFACE *mvme, DWORD base)
00536 {
00537   int csr;
00538 
00539   mvme_set_am(mvme, MVME_AM_A24);
00540   mvme_set_dmode(mvme, MVME_DMODE_D32);
00541   csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00542   csr &= ~(VF48_CSR_EXT_TRIGGER);  // clr
00543   mvme_write_value(mvme, base+VF48_CSR_REG_RW, csr);
00544   return VF48_SUCCESS;
00545 }
00546 
00547 /********************************************************************/
00548 int vf48_NFrameRead(MVME_INTERFACE *mvme, DWORD base)
00549 {
00550   int nframe;
00551 
00552   mvme_set_am(mvme, MVME_AM_A24);
00553   mvme_set_dmode(mvme, MVME_DMODE_D32);
00554   nframe =  mvme_read_value(mvme, base+VF48_NFRAME_R);
00555   return nframe;
00556 }
00557 
00558 /********************************************************************/
00559 int vf48_CsrRead(MVME_INTERFACE *mvme, DWORD base)
00560 {
00561   int csr;
00562 
00563   mvme_set_am(mvme, MVME_AM_A24);
00564   mvme_set_dmode(mvme, MVME_DMODE_D16);
00565   csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00566   return csr;
00567 }
00568 
00569 /********************************************************************/
00570 int vf48_FeFull(MVME_INTERFACE *mvme, DWORD base)
00571 {
00572   int fefull;
00573 
00574   mvme_set_am(mvme, MVME_AM_A24);
00575   mvme_set_dmode(mvme, MVME_DMODE_D32);
00576   fefull = mvme_read_value(mvme, base+VF48_CSR_REG_RW) & VF48_CSR_FE_FULL;
00577   return fefull;
00578 }
00579 
00580 /********************************************************************/
00581 int vf48_FeNotEmpty(MVME_INTERFACE *mvme, DWORD base)
00582 {
00583   int fenotempty;
00584 
00585   mvme_set_am(mvme, MVME_AM_A24);
00586   mvme_set_dmode(mvme, MVME_DMODE_D32);
00587   fenotempty = mvme_read_value(mvme, base+VF48_CSR_REG_RW) & VF48_CSR_FE_NOTEMPTY;
00588   return fenotempty;
00589 }
00590 
00591 /********************************************************************/
00592 int  vf48_GrpEnable(MVME_INTERFACE *mvme, DWORD base, int grpbit)
00593 {
00594 
00595   mvme_set_am(mvme, MVME_AM_A24);
00596   mvme_set_dmode(mvme, MVME_DMODE_D16);
00597   grpbit &= 0x3F;
00598   mvme_write_value(mvme, base+VF48_GRP_REG_RW, grpbit);
00599   return VF48_SUCCESS;
00600 }
00601 
00602 /********************************************************************/
00603 int vf48_GrpRead(MVME_INTERFACE *mvme, DWORD base)
00604 {
00605   int grp;
00606 
00607   mvme_set_am(mvme, MVME_AM_A24);
00608   mvme_set_dmode(mvme, MVME_DMODE_D16);
00609   grp = mvme_read_value(mvme, base+VF48_GRP_REG_RW);
00610   return grp;
00611 }
00612 
00613 /********************************************************************/
00614 /**
00615 Set the segment size for all 6 groups
00616  */
00617 int vf48_SegmentSizeSet(MVME_INTERFACE *mvme, DWORD base, DWORD size)
00618 {
00619   int i;
00620 
00621   assert(size>0);
00622   assert(size<=1000);
00623 
00624   mvme_set_am(mvme, MVME_AM_A24);
00625   mvme_set_dmode(mvme, MVME_DMODE_D16);
00626   for (i=0;i<6;i++)
00627     vf48_ParameterWrite(mvme, base, i, VF48_SEGMENT_SIZE, size);
00628   return 1;
00629 }
00630 
00631 /********************************************************************/
00632 /**
00633 Read the segment size from a given group. This value should be the
00634 same for all the groups.
00635  */
00636 int vf48_SegmentSizeRead(MVME_INTERFACE *mvme, DWORD base, int grp)
00637 {
00638   int val;
00639 
00640   mvme_set_am(mvme, MVME_AM_A24);
00641   mvme_set_dmode(mvme, MVME_DMODE_D16);
00642   val =  vf48_ParameterRead(mvme, base, grp, VF48_SEGMENT_SIZE);
00643   return val;
00644 }
00645 
00646 /********************************************************************/
00647 /**
00648 Set the trigger threshold for the given group. the threshold value
00649 correspond to the difference of 2 sampling values separated by 2
00650 points (s6-s3). It is compared to a  positive value. If the slope
00651 of the signal is negative, the signal should be inverted.
00652  */
00653 int vf48_TrgThresholdSet(MVME_INTERFACE *mvme, DWORD base, int grp, DWORD size)
00654 {
00655 
00656   mvme_set_am(mvme, MVME_AM_A24);
00657   mvme_set_dmode(mvme, MVME_DMODE_D16);
00658   vf48_ParameterWrite(mvme, base, grp, VF48_TRIG_THRESHOLD, size);
00659   return grp;
00660 }
00661 
00662 /********************************************************************/
00663 /**
00664 Read the trigger threshold for a given group.
00665 */
00666 int vf48_TrgThresholdRead(MVME_INTERFACE *mvme, DWORD base, int grp)
00667 {
00668   int val;
00669 
00670   mvme_set_am(mvme, MVME_AM_A24); 
00671   mvme_set_dmode(mvme, MVME_DMODE_D16);
00672   val =  vf48_ParameterRead(mvme, base, grp, VF48_TRIG_THRESHOLD);
00673   return val;
00674 }
00675 
00676 /********************************************************************/
00677 /**
00678 Set the hit threshold for the given group. the threshold value
00679 correspond to the difference of 2 sampling values separated by 2
00680 points (s6-s3). It is compared to a  positive value. If the slope
00681 of the signal is negative, the signal should be inverted.
00682 The hit threshold is used for channel suppression in case none
00683 of the described condition is satisfied.
00684  */
00685 int vf48_HitThresholdSet(MVME_INTERFACE *mvme, DWORD base, int grp, DWORD size)
00686 {
00687 
00688   mvme_set_am(mvme, MVME_AM_A24);
00689   mvme_set_dmode(mvme, MVME_DMODE_D16);
00690   vf48_ParameterWrite(mvme, base, grp, VF48_HIT_THRESHOLD, size);
00691   return grp;
00692 }
00693 
00694 /********************************************************************/
00695 /**
00696 Read the hit threshold for a given group.
00697 */
00698 int vf48_HitThresholdRead(MVME_INTERFACE *mvme, DWORD base, int grp)
00699 {
00700   int val;
00701 
00702   mvme_set_am(mvme, MVME_AM_A24);
00703   mvme_set_dmode(mvme, MVME_DMODE_D16);
00704   val =  vf48_ParameterRead(mvme, base, grp, VF48_HIT_THRESHOLD);
00705   return val;
00706 }
00707 
00708 /********************************************************************/
00709 /**
00710 Enable the channel within the given group. By default all 8 channels
00711 are enabled.
00712 */
00713 int vf48_ActiveChMaskSet(MVME_INTERFACE *mvme, DWORD base, int grp, DWORD size)
00714 {
00715 
00716   mvme_set_am(mvme, MVME_AM_A24);
00717   mvme_set_dmode(mvme, MVME_DMODE_D16);
00718   vf48_ParameterWrite(mvme, base, grp, VF48_ACTIVE_CH_MASK, size);
00719   return grp;
00720 }
00721 
00722 /********************************************************************/
00723 /**
00724 Read the channel enable mask for a given group.
00725  */
00726 int vf48_ActiveChMaskRead(MVME_INTERFACE *mvme, DWORD base, int grp)
00727 {
00728   int val;
00729 
00730   mvme_set_am(mvme, MVME_AM_A24);
00731   mvme_set_dmode(mvme, MVME_DMODE_D16);
00732   val =  vf48_ParameterRead(mvme, base, grp, VF48_ACTIVE_CH_MASK);
00733   return val;
00734 }
00735 
00736 /********************************************************************/
00737 /**
00738 Suppress the transmission of the raw data (wave form) of all the channels
00739 of a given group. Feature Q,T are always present expect if channel masked.
00740  */
00741 int vf48_RawDataSuppSet(MVME_INTERFACE *mvme, DWORD base, int grp, DWORD size)
00742 {
00743 
00744   mvme_set_am(mvme, MVME_AM_A24);
00745   mvme_set_dmode(mvme, MVME_DMODE_D16);
00746   vf48_ParameterWrite(mvme, base, grp, VF48_MBIT1, size);
00747   return grp;
00748 }
00749 
00750 /********************************************************************/
00751 /**
00752 Read the flag of the raw data suppression of a given channel.
00753  */
00754 int vf48_RawDataSuppRead(MVME_INTERFACE *mvme, DWORD base, int grp)
00755 {
00756   int val;
00757 
00758   mvme_set_am(mvme, MVME_AM_A24);
00759   mvme_set_dmode(mvme, MVME_DMODE_D16);
00760   val =  vf48_ParameterRead(mvme, base, grp, VF48_MBIT1);
00761   return val;
00762 }
00763 
00764 /********************************************************************/
00765 /**
00766 Enable the suppression of channel based on the hit threshold for a
00767 given group.
00768 Currently the MBIT2 contains the divisor parameter too.
00769 This function will overwrite this parameter. Apply this
00770 function prior the divisor.
00771  */
00772 int vf48_ChSuppSet(MVME_INTERFACE *mvme, DWORD base, int grp, DWORD value)
00773 {
00774   int  mbit2;
00775 
00776   mvme_set_am(mvme, MVME_AM_A24);
00777   mvme_set_dmode(mvme, MVME_DMODE_D16);
00778   mbit2 =  vf48_ParameterRead(mvme, base, grp, VF48_MBIT2);
00779   mbit2 &= ~1;
00780   mbit2 |= value&0x1;
00781   vf48_ParameterWrite(mvme, base, grp, VF48_MBIT2, mbit2);
00782   return grp;
00783 }
00784 
00785 /********************************************************************/
00786 /**
00787 Read the channel suppression flag for a given group.
00788  */
00789 int vf48_ChSuppRead(MVME_INTERFACE *mvme, DWORD base, int grp)
00790 {
00791   int val;
00792 
00793   mvme_set_am(mvme, MVME_AM_A24);
00794   mvme_set_dmode(mvme, MVME_DMODE_D16);
00795   val =  0x1 & vf48_ParameterRead(mvme, base, grp, VF48_MBIT2);
00796   return val;
00797 }
00798 
00799 /********************************************************************/
00800 /**
00801 write the sub-sampling divisor factor to all 6 groups.
00802 Value of 0   : base sampling
00803 Value of x>0 : base sampling / x
00804  */
00805 int vf48_DivisorWrite(MVME_INTERFACE *mvme, DWORD base, DWORD value)
00806 {
00807    int i, mbit2, grp;
00808 
00809   assert(value > 0);
00810   assert(value < 256);
00811 
00812   mvme_set_am(mvme, MVME_AM_A24);
00813   mvme_set_dmode(mvme, MVME_DMODE_D16);
00814   grp = vf48_GrpRead(mvme, base);
00815   for (i=0;i<6;i++)
00816     if (grp&(1<<i)) {
00817       mbit2 =  vf48_ParameterRead(mvme, base, i, VF48_MBIT2);
00818       mbit2 &= ~0xFF00;
00819       mbit2 |= (value << 8);
00820       vf48_ParameterWrite(mvme, base, i, VF48_MBIT2, mbit2);
00821     }
00822   for (i=0;i<6;i++)
00823     if (grp&(1<<i)) {
00824       int rd = vf48_DivisorRead(mvme, base, i);
00825       if (rd != value) {
00826         printf("vf48_DivisorWrite: Divisor read back mismatch: module at 0x%x, group %d, wrote %d, read back %d\n", base, i, value, rd);
00827         abort();
00828       }
00829     }
00830   return value;
00831 }
00832 
00833 /********************************************************************/
00834 /**
00835 Read the divisor parameter of the given group. All the groups
00836 should read the same value.
00837  */
00838 int vf48_DivisorRead(MVME_INTERFACE *mvme, DWORD base, int grp)
00839 {
00840   int val;
00841 
00842   mvme_set_am(mvme, MVME_AM_A24);
00843   mvme_set_dmode(mvme, MVME_DMODE_D16);
00844   val = vf48_ParameterRead(mvme, base, grp, VF48_MBIT2);
00845   val = (val >> 8) & 0xff;
00846   return val;
00847 }
00848 
00849 /********************************************************************/
00850 int  vf48_Trigger(MVME_INTERFACE *mvme, DWORD base)
00851 {
00852   int r;
00853   //printf("Write 0x%x\n", base + VF48_SOFT_TRIG_W);
00854   mvme_set_am(mvme, MVME_AM_A24);
00855   mvme_set_dmode(mvme, MVME_DMODE_D16);
00856   mvme_write_value(mvme, base + VF48_SOFT_TRIG_W, 0);
00857   r = mvme_read_value(mvme, base + VF48_CSR_REG_RW); // flush posted PCI writes
00858   //printf("Readback: CSR 0x%x\n", r);
00859   return VF48_SUCCESS;
00860 }
00861 
00862 /********************************************************************/
00863 int vf48_Setup(MVME_INTERFACE *mvme, DWORD base, int mode)
00864 {
00865   int  i;
00866 
00867   mvme_set_am(mvme, MVME_AM_A24);
00868   mvme_set_dmode(mvme, MVME_DMODE_D16);
00869 
00870   switch (mode) {
00871   case 0x1:
00872     printf("Default setting after power up (mode:%d)\n", mode);
00873     printf("\n");
00874     break;
00875   case 0x2:
00876     printf("External Trigger (mode:%d)\n", mode);
00877     vf48_ExtTrgSet(mvme, base);
00878     break;
00879   case 0x3:
00880     printf("External Trigger, Seg Size=16 (mode:%d)\n", mode);
00881     vf48_ExtTrgSet(mvme, base);
00882     for (i=0;i<6;i++)
00883        vf48_ParameterWrite(mvme, base, i, VF48_SEGMENT_SIZE, 16);
00884     for (i=0;i<6;i++)
00885       printf("SegSize grp %i:%d\n", i, vf48_ParameterRead(mvme, base, i, VF48_SEGMENT_SIZE));
00886     break;
00887   default:
00888     printf("Unknown setup mode\n");
00889     return -1;
00890   }
00891   return 0;
00892 
00893 }
00894 
00895 /********************************************************************/
00896 /** vf48_Status
00897    @param mvme vme structure
00898    @param base  VF48 base address
00899    @return status VF48_ERROR, SUCCESS
00900 */
00901 int vf48_Status(MVME_INTERFACE *mvme, DWORD base)
00902 {
00903   char *parname[] = {
00904     "",
00905     "PED",
00906     "Hit Det Threshold",
00907     "Clip Delay",
00908     "PreTrigger",
00909     "Segment Size",
00910     "K",
00911     "L",
00912     "M",
00913     "Channel enable",
00914     "Mbits1",
00915     "Mbits2",
00916     "Latency",
00917     "Firmware ID",
00918     "Attenuator",
00919     "Trigger Threshold"
00920   };
00921 
00922   int i, j;
00923 
00924   mvme_set_am(mvme, MVME_AM_A24);
00925   mvme_set_dmode(mvme, MVME_DMODE_D32);
00926 
00927   printf("VF48 at VME A24 0x%06x, status:\n", base);
00928   printf("  CSR:          0x%08x\n", mvme_read_value(mvme, base + 0x0));
00929   printf("  Test reg:     0x%08x\n", mvme_read_value(mvme, base + 0x20));
00930   printf("  Firmware:     0x%08x\n", mvme_read_value(mvme, base + 0x30));
00931   printf("  Group enable: 0x%08x\n", mvme_read_value(mvme, base + 0x90));
00932   printf("  NbrFrames:    0x%08x\n", mvme_read_value(mvme, base + 0xA0));
00933 
00934   if (mvme_read_value(mvme, base + 0x0) & 1) {
00935     printf("Module is in running mode: cannot read parameters\n");
00936   } else {
00937     printf("Parameters:\n");
00938     for (i=1; i<16; i++) {
00939       printf("  par%02d (%-20s): ", i, parname[i]);
00940       for (j=0; j<6; j++) {
00941         int v = vf48_ParameterRead(mvme, base, j, i);
00942         printf(" %6d (0x%04x) ", v, v);
00943       }
00944       printf("\n");
00945     }
00946   }
00947 
00948   return VF48_SUCCESS;
00949 }
00950 
00951 /********************************************************************/
00952 /** vf48_isPresent
00953    @param mvme vme structure
00954    @param base  VF48 base address
00955    @return status VF48_ERROR if module is not present, SUCCESS
00956 */
00957 int vf48_isPresent(MVME_INTERFACE *mvme, DWORD base)
00958 {
00959   int missing = 0;
00960 
00961   mvme_set_am(mvme, MVME_AM_A24);
00962   mvme_set_dmode(mvme, MVME_DMODE_D32);
00963 
00964   missing |= (0xFFFFFFFF==mvme_read_value(mvme, base + 0x0));
00965   missing |= (0xFFFFFFFF==mvme_read_value(mvme, base + 0x30));
00966 
00967   if (missing) return VF48_ERROR;
00968 
00969   return VF48_SUCCESS;
00970 }
00971 
00972 /********************************************************************/
00973 #ifdef MAIN_ENABLE
00974 int main (int argc, char* argv[]) {
00975 
00976   MVME_INTERFACE *myvme;
00977 
00978   DWORD VF48_BASE = 0xAF0000;
00979   DWORD buf[200000], buf1[200000], buf2[200000];
00980   DWORD evt=0;
00981   int status, i, nframe, nframe1, nframe2, nentry, pnentry;
00982   int segsize = 10, latency=5, grpmsk = 0x3F, pretrig=0x20;
00983   int tthreshold = 10,hthreshold = 10, evtflag=0;
00984 
00985   // Test under vmic
00986   status = mvme_open(&myvme, 0);
00987 
00988   // Set am to A24 non-privileged Data
00989   mvme_set_am(myvme, MVME_AM_A24_ND);
00990 
00991   // Set dmode to D16
00992   mvme_set_dmode(myvme, MVME_DMODE_D16);
00993 
00994 #if 1
00995 
00996   if (argc > 1) {
00997 
00998     for (i=1;i<argc; i+=2) {
00999       if (argv[i][1] == 's') {
01000         segsize = atoi(argv[i+1]);
01001       }
01002       else if (argv[i][1] == 'l') {
01003         latency = atoi(argv[i+1]);
01004       }
01005       else if (argv[i][1] == 'p') {
01006         pretrig = atoi(argv[i+1]);
01007       }
01008       else if (argv[i][1] == 't') {
01009         tthreshold = atoi(argv[i+1]);
01010       }
01011       else if (argv[i][1] == 'u') {
01012         hthreshold = atoi(argv[i+1]);
01013       }
01014       else if (argv[i][1] == 'r') {
01015         i--;
01016         vf48_Reset(myvme, VF48_BASE);
01017       }
01018       else if (argv[i][1] == 'e') {
01019         evtflag = atoi(argv[i+1]);
01020       }
01021       else if (argv[i][1] == 'g') {
01022         grpmsk = strtol(argv[i+1], (char **)NULL, 16);
01023       }
01024       else if (argv[i][1] == 'h') {
01025         printf("\nvf48         : Run read only (no setup)\n");
01026         printf("vf48 -h      : This help\n");
01027         printf("vf48 -r      : Reset now\n");
01028         printf("vf48 -e val  : Event flag for event display, 0, x, 64\n");
01029         printf("vf48 -s val  : Setup Segment size value & Run [def:10]\n");
01030         printf("vf48 -l val  : Setup Latency value & Run [def:5]\n");
01031         printf("vf48 -g 0xval: Setup Group Enable pattern & Run [def:0x3F]\n");
01032         printf("vf48 -p val  : Setup PreTrigger & Run [def:0x20]\n");
01033         printf("vf48 -t val  : Setup Trig Threshold & Run [def:0x0A]\n");
01034         printf("vf48 -u val  : Setup Hit Threshold & Run [def:0x0A]\n");
01035         printf("Comments     : Setup requires Run stopped\n\n");
01036         return 0;
01037       }
01038     }
01039 
01040   // Stop DAQ for seting up the parameters
01041   vf48_AcqStop(myvme, VF48_BASE);
01042 
01043   // Segment Size
01044   printf("Set Segment size to all grp to %d\n", segsize);
01045   for (i=0;i<6;i++) {
01046     vf48_ParameterWrite(myvme, VF48_BASE, i, VF48_SEGMENT_SIZE, segsize);
01047     printf("SegSize grp %i:%d\n", i, vf48_ParameterRead(myvme, VF48_BASE, i, VF48_SEGMENT_SIZE));
01048   }
01049 
01050   // Latency
01051   printf("Set Latency to all grp to %d\n", latency);
01052   for (i=0;i<6;i++) {
01053     vf48_ParameterWrite(myvme, VF48_BASE, i, VF48_LATENCY, latency);
01054     printf("Latency grp %i:%d\n", i, vf48_ParameterRead(myvme, VF48_BASE, i, VF48_LATENCY));
01055   }
01056 
01057   // PreTrigger
01058   printf("Set PreTrigger to all grp to %d\n", pretrig);
01059   for (i=0;i<6;i++) {
01060     vf48_ParameterWrite(myvme, VF48_BASE, i, VF48_PRE_TRIGGER, pretrig);
01061     printf("Pre Trigger grp %i:%d\n", i, vf48_ParameterRead(myvme, VF48_BASE, i, VF48_PRE_TRIGGER));
01062   }
01063 
01064   // Trigger Threshold
01065   printf("Set Trigger Threshold to all grp to %d\n", tthreshold);
01066   for (i=0;i<6;i++) {
01067     vf48_ParameterWrite(myvme, VF48_BASE, i, VF48_TRIG_THRESHOLD, tthreshold);
01068     printf("Trigger Threshold grp %i:%d\n", i, vf48_ParameterRead(myvme, VF48_BASE, i, VF48_TRIG_THRESHOLD));
01069   }
01070 
01071   // Hit Threshold
01072   printf("Set Hit Threshold to all grp to %d\n", hthreshold);
01073   for (i=0;i<6;i++) {
01074     vf48_ParameterWrite(myvme, VF48_BASE, i, VF48_HIT_THRESHOLD, hthreshold);
01075     printf("Hit Threshold grp %i:%d\n", i, vf48_ParameterRead(myvme, VF48_BASE, i, VF48_HIT_THRESHOLD));
01076   }
01077 
01078   // Active Channel Mask
01079   for (i=0;i<6;i++)
01080     vf48_ParameterWrite(myvme, VF48_BASE, i, VF48_ACTIVE_CH_MASK, VF48_ALL_CHANNELS_ACTIVE);
01081 
01082   // Raw Data Suppress (Mbit 1)
01083   for (i=0;i<6;i++)
01084     vf48_ParameterWrite(myvme, VF48_BASE, i, VF48_MBIT1, VF48_RAW_DISABLE);
01085 
01086   // Inverse Signal (Mbit 1)
01087   for (i=0;i<6;i++)
01088     vf48_ParameterWrite(myvme, VF48_BASE, i, VF48_MBIT1, VF48_INVERSE_SIGNAL);
01089 
01090   // Channel Suppress (Mbit 2)
01091   for (i=0;i<6;i++)
01092     vf48_ParameterWrite(myvme, VF48_BASE, i, VF48_MBIT2, VF48_CH_SUPPRESS_ENABLE);
01093 
01094   // External trigger
01095   printf("External Trigger\n");
01096   vf48_ExtTrgSet(myvme, VF48_BASE);
01097 
01098   // Group Enable
01099   vf48_GrpEnable(myvme, VF48_BASE, grpmsk);
01100   printf("Group Enable :0x%x\n", vf48_GrpRead(myvme, VF48_BASE));
01101 
01102   // Start DAQ
01103   vf48_AcqStart(myvme, VF48_BASE);
01104 
01105   printf("Run Started : CSR Buffer: 0x%x\n", vf48_CsrRead(myvme, VF48_BASE));
01106 
01107   printf("Access mode:%d\n", evtflag);
01108 
01109   // Wait for a few data in buffer first
01110   do {
01111     // Read Frame counter
01112     nentry = vf48_NFrameRead(myvme, VF48_BASE);
01113   } while (nentry <= 0);
01114   printf("1 NFrame: 0x%x\n", nentry);
01115   }
01116 
01117 #endif  // if 0/1
01118 
01119   if (evtflag == 0) {
01120     printf(" DataRead transfer\n");
01121     while (1) // (vf48_NFrameRead(myvme, VF48_BASE))
01122       {
01123         usleep(100000);
01124         nframe = vf48_NFrameRead(myvme, VF48_BASE);
01125         if (nframe) {
01126           //  printf("Doing DMA read now\n");
01127         nframe = vf48_NFrameRead(myvme, VF48_BASE);
01128         vf48_DataRead(myvme, VF48_BASE, (DWORD *)&buf, &nframe);
01129 
01130         usleep(1000);
01131 
01132         nframe1 = vf48_NFrameRead(myvme, VF48_BASE);
01133         vf48_DataRead(myvme, VF48_BASE, (DWORD *)&buf1, &nframe1);
01134         usleep(1000);
01135         
01136         nframe2 = vf48_NFrameRead(myvme, VF48_BASE);
01137         vf48_DataRead(myvme, VF48_BASE, (DWORD *)&buf2, &nframe2);
01138         
01139         /*
01140         printf("CSR Buffer: 0x%x\n", vf48_CsrRead(myvme, VF48_BASE));
01141         printf("NFrame: buf %d  buf1 %d  buf2 %d\n", nframe, nframe1, nframe2);
01142         for (i=0;i<nframe+2;i++) {
01143           printf("Buf   data[%d]: 0x%x\n", i, buf[i]);
01144         }
01145         for (i=0;i<nframe1+2;i++) {
01146           printf("Buf1  data[%d]: 0x%x\n", i, buf1[i]);
01147         }
01148         for (i=0;i<nframe2+2;i++) {
01149           printf("Buf2  data[%d]: 0x%x\n", i, buf2[i]);
01150         }
01151         */
01152         printf("End of Data for %d %d %d\n", nframe, nframe1, nframe2);
01153       }
01154     }
01155   }
01156 
01157   if (evtflag == 64) {
01158     printf(" 64 bit transfer\n");
01159     while (1) {
01160       usleep(100000);
01161       nentry = 0;
01162       vf48_EventRead64(myvme, VF48_BASE, (DWORD *)&buf, &nentry);
01163       if (nentry != 0) {
01164         if (evt+1 != (buf[0] & 0xFFFFFF))
01165           printf(">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>--------------- Event# mismatch %x %x\n", evt, (buf[0] & 0xFFFFFF));
01166 
01167         evt = (buf[0] & 0xFFFFFF);
01168 
01169         for (i=0;i<nentry;i++) {
01170           //    printf("buf[%d]:0x%x\n", i, buf[i]);
01171           if ((buf[i] & 0xe0000000) == 0xe0000000 ||
01172               (buf[i] & 0x10000BAD) == 0x10000BAD)
01173           printf("\t\t\t\t\t\t\t\t %d buf[%d]:0x%x\n", nentry, i, buf[i]);
01174         }
01175         
01176         if (pnentry != nentry)
01177           printf("End of Event previous(%d) (%d)\n", pnentry, nentry);
01178       else
01179         printf("End of Event              (%d) T(0x%x)\n", nentry, buf[nentry]);
01180         pnentry = nentry;
01181       }
01182     }
01183   }
01184   else {   // 32bit
01185     printf(" 32 bit transfer\n");
01186     while (1) {
01187       usleep(100000);
01188       nentry = 0;
01189       vf48_EventRead(myvme, VF48_BASE, (DWORD *)&buf, &nentry);
01190       if (nentry != 0) {
01191         if (evt+1 != (buf[0] & 0xFFFFFF))
01192           printf("--------------- Event# mismatch %x %x\n", evt, (buf[0] & 0xFFFFFF));
01193         
01194         evt = (buf[0] & 0xFFFFFF);
01195         
01196         for (i=0;i<nentry;i++) {
01197           if ((buf[i] & 0xe0000000) == 0xe0000000)
01198           printf("\t\t\t\t\t\t\t\t  %d buf[%d]:0x%x\n", nentry, i, buf[i]);
01199         }
01200         
01201         if (pnentry != nentry)
01202           printf("End of Event previous(%d) (%d)\n", pnentry, nentry);
01203         else
01204           printf("End of Event              (%d) T(0x%x)\n", nentry, buf[nentry]);
01205         pnentry = nentry;
01206       }
01207     }
01208   }
01209 
01210   // Close VME
01211   status = mvme_close(myvme);
01212   return 1;
01213 }
01214 #endif

Midas DOC Version 3.0.0 ---- PSI Stefan Ritt ----
Contributions: Pierre-Andre Amaudruz - Sergio Ballestrero - Suzannah Daviel - Doxygen - Peter Green - Qing Gu - Greg Hackman - Gertjan Hofman - Paul Knowles - Exaos Lee - Rudi Meier - Glenn Moloney - Dave Morris - John M O'Donnell - Konstantin Olchanski - Renee Poutissou - Tamsen Schurman - Andreas Suter - Jan M.Wouters - Piotr Adam Zolnierczuk