VME Functions (mvme_xxx)
[Midas VME standard]


Functions

int EXPRT mvme_open (MVME_INTERFACE **vme, int idx)
int EXPRT mvme_close (MVME_INTERFACE *vme)
int EXPRT mvme_sysreset (MVME_INTERFACE *vme)
int EXPRT mvme_read (MVME_INTERFACE *vme, void *dst, mvme_addr_t vme_addr, mvme_size_t n_bytes)
unsigned int EXPRT mvme_read_value (MVME_INTERFACE *vme, mvme_addr_t vme_addr)
int EXPRT mvme_write (MVME_INTERFACE *vme, mvme_addr_t vme_addr, void *src, mvme_size_t n_bytes)
int EXPRT mvme_write_value (MVME_INTERFACE *vme, mvme_addr_t vme_addr, unsigned int value)
int EXPRT mvme_set_am (MVME_INTERFACE *vme, int am)
int EXPRT mvme_get_am (MVME_INTERFACE *vme, int *am)
int EXPRT mvme_set_dmode (MVME_INTERFACE *vme, int dmode)
int EXPRT mvme_get_dmode (MVME_INTERFACE *vme, int *dmode)
int EXPRT mvme_set_blt (MVME_INTERFACE *vme, int mode)
int EXPRT mvme_get_blt (MVME_INTERFACE *vme, int *mode)
int EXPRT mvme_interrupt_generate (MVME_INTERFACE *mvme, int level, int vector, void *info)
int EXPRT mvme_interrupt_attach (MVME_INTERFACE *mvme, int level, int vector, void(*isr)(int, void *, void *), void *info)
int EXPRT mvme_interrupt_detach (MVME_INTERFACE *mvme, int level, int vector, void *info)
int EXPRT mvme_interrupt_enable (MVME_INTERFACE *mvme, int level, int vector, void *info)
int EXPRT mvme_interrupt_disable (MVME_INTERFACE *mvme, int level, int vector, void *info)


Function Documentation

int EXPRT mvme_close ( MVME_INTERFACE mvme  ) 

Close and release ALL the opened VME channel.

Parameters:
*mvme VME structure.
Returns:
MVME_SUCCESS, ERROR

Definition at line 525 of file gefvme.c.

00526 {
00527   int j;
00528   VME_TABLE *table;
00529   //DMA_INFO  *info;
00530   
00531   table = ((VME_TABLE *)mvme->table);
00532   
00533   /*------------------------------------------------------------*/
00534   /* Close all the window handles */
00535   for (j=0; j< MAX_VME_SLOTS; j++) {
00536     if (table[j].valid) {
00537       close(table[j].handle);
00538     }
00539   } // scan
00540   
00541   /* Free table pointer */
00542   free (mvme->table);
00543   mvme->table = NULL;
00544   
00545   /* Free mvme block */
00546   free (mvme);
00547   
00548   return MVME_SUCCESS;
00549 }

int EXPRT mvme_get_am ( MVME_INTERFACE vme,
int *  am 
)

Get Address Modifier.

Parameters:
*vme VME structure
*am returned address modifier
Returns:
MVME_SUCCESS

Definition at line 965 of file gefvme.c.

Referenced by sis3820_FifoRead(), VPPGRegRead(), and VPPGRegWrite().

00966 {
00967   *am = mvme->am;
00968   return MVME_SUCCESS;
00969 }

int EXPRT mvme_get_blt ( MVME_INTERFACE vme,
int *  mode 
)

Get current Data mode.

Parameters:
*vme VME structure
*mode returned BLT mode
Returns:
MVME_SUCCESS

Definition at line 993 of file gefvme.c.

00994 {
00995   *mode = mvme->blt_mode;
00996   return MVME_SUCCESS;
00997 }

int EXPRT mvme_get_dmode ( MVME_INTERFACE vme,
int *  dmode 
)

Get current Data mode.

Parameters:
*vme VME structure
*dmode returned address modifier
Returns:
MVME_SUCCESS

Definition at line 979 of file gefvme.c.

Referenced by lrs1151_Clear(), lrs1151_Read(), lrs1190_CountRead(), lrs1190_Disable(), lrs1190_Enable(), lrs1190_H2Read(), lrs1190_I4Read(), lrs1190_L2Read(), lrs1190_Reset(), sis3801_channel_enable(), sis3801_CSR_read(), sis3801_CSR_write(), sis3801_dwell_time(), sis3801_FIFO_clear(), sis3801_FIFO_flush(), sis3801_HFIFO_read(), sis3801_input_mode(), sis3801_int_attach(), sis3801_int_source(), sis3801_int_source_disable(), sis3801_int_source_enable(), sis3801_IRQ_REG_read(), sis3801_IRQ_REG_write(), sis3801_module_ID(), sis3801_module_reset(), sis3801_next_logic(), sis3801_ref1(), sis3801_Setup(), v1190_AcqModeRead(), v1190_ContinuousSet(), v1190_DataRead(), v1190_DataReady(), v1190_EventRead(), v1190_EvtCounter(), v1190_EvtStored(), v1190_GeoWrite(), v1190_LEResolutionSet(), v1190_MicroFlush(), v1190_MicroRead(), v1190_MicroWrite(), v1190_OffsetSet(), v1190_ResolutionRead(), v1190_SetEdgeDetection(), v1190_Setup(), v1190_SoftClear(), v1190_SoftReset(), v1190_SoftTrigger(), v1190_Status(), v1190_TdcIdList(), v1190_TriggerMatchingSet(), v1190_WidthSet(), v1729_AcqStart(), v1729_ChannelSelect(), v1729_DataRead(), v1729_FrqSamplingSet(), v1729_isTrigger(), v1729_NColsGet(), v1729_NColsSet(), v1729_OrderData(), v1729_PedestalRun(), v1729_PostTrigSet(), v1729_PreTrigSet(), v1729_Reset(), v1729_Setup(), v1729_SoftTrigger(), v1729_Status(), v1729_TimeCalibrationRun(), v1729_TriggerTypeSet(), v792_BitSet2Clear(), v792_BitSet2Read(), v792_BitSet2Set(), v792_ControlRegister1Read(), v792_ControlRegister1Write(), v792_CSR1Read(), v792_CSR2Read(), v792_DataClear(), v792_DataRead(), v792_DataReady(), v792_EmptyEnable(), v792_EventRead(), v792_EvtCntRead(), v792_EvtCntReset(), v792_EvtTriggerSet(), v792_IntDisable(), v792_IntEnable(), v792_IntSet(), v792_isBusy(), v792_isPresent(), v792_LowThDisable(), v792_LowThEnable(), v792_OnlineSet(), v792_Setup(), v792_SingleShotReset(), v792_SoftReset(), v792_Status(), v792_ThresholdRead(), v792_ThresholdWrite(), v792_Trigger(), vpc6_ASDHysteresisSet(), vpc6_ASDModeSet(), vpc6_ASDRegSet(), vpc6_ASDThresholdSet(), vpc6_CfgRetrieve(), vpc6_isPortBusy(), vpc6_PATypeRead(), vpc6_PATypeWrite(), vpc6_PortCfgLoad(), vpc6_PortRegRBRead(), vpc6_PortRegRead(), vpc6_PortTypeRead(), vpc6_Setup(), vpc6_Status(), VPPGRegRead(), VPPGRegWrite(), vt2_CSRRead(), vt2_CycleNumberRead(), vt2_CycleReset(), vt2_FifoLevelRead(), vt2_FifoRead(), vt2_IntEnable(), vt2_KeepAlive(), vt2_ManReset(), vt48_EventRead(), vt48_RegPrint(), vt48_RegRead(), vt48_RegWrite(), vt48_Setup(), vt48_Status(), vt48_WindowOffsetSet(), and vt48_WindowSet().

00980 {
00981   *dmode = mvme->dmode;
00982   return MVME_SUCCESS;
00983 }

int EXPRT mvme_interrupt_attach ( MVME_INTERFACE mvme,
int  level,
int  vector,
void(*)(int, void *, void *)  isr,
void *  info 
)

static void handler(int sig, siginfo_t * siginfo, void *extra) { print_intr_msg(level, siginfo->si_value.sival_int); done = 0; } </endcode>

Definition at line 1018 of file gefvme.c.

Referenced by sis3801_int_attach().

01020 {
01021   assert(!"Not implemented");
01022   return MVME_SUCCESS;
01023 }

int EXPRT mvme_interrupt_detach ( MVME_INTERFACE mvme,
int  level,
int  vector,
void *  info 
)

Definition at line 1026 of file gefvme.c.

01027 {
01028   assert(!"Not implemented");
01029   return MVME_SUCCESS;
01030 }

int EXPRT mvme_interrupt_disable ( MVME_INTERFACE mvme,
int  level,
int  vector,
void *  info 
)

Definition at line 1040 of file gefvme.c.

01041 {
01042   assert(!"Not implemented");
01043   return MVME_SUCCESS;
01044 }

int EXPRT mvme_interrupt_enable ( MVME_INTERFACE mvme,
int  level,
int  vector,
void *  info 
)

Definition at line 1033 of file gefvme.c.

01034 {
01035   assert(!"Not implemented");
01036   return MVME_SUCCESS;
01037 }

int EXPRT mvme_interrupt_generate ( MVME_INTERFACE mvme,
int  level,
int  vector,
void *  info 
)

Definition at line 1000 of file gefvme.c.

01001 {
01002   assert(!"Not implemented");
01003   return MVME_SUCCESS;
01004 }

int EXPRT mvme_open ( MVME_INTERFACE **  mvme,
int  index 
)

Open a VME channel One bus handle per crate.

Parameters:
*mvme VME structure.
index VME interface index
Returns:
MVME_SUCCESS, ERROR

Definition at line 455 of file gefvme.c.

00456 {
00457   /* index can be only 0 for VMIC */
00458   if (index != 0) {
00459     fprintf(stderr,"mvme_open: invalid index value %d, only 0 is permitted\n", index);
00460     return MVME_INVALID_PARAM;
00461   }
00462   
00463   /* Allocate MVME_INTERFACE */
00464   *mvme = (MVME_INTERFACE *) calloc(1, sizeof(MVME_INTERFACE));
00465 
00466   (*mvme)->handle = -1;
00467   
00468   /* Allocte VME_TABLE */
00469   (*mvme)->table = (char *) calloc(MAX_VME_SLOTS, sizeof(VME_TABLE));
00470   
00471   /* Set default parameters */
00472   (*mvme)->am = MVME_AM_DEFAULT;
00473 
00474   /* Set default block transfer mode */
00475   (*mvme)->blt_mode = 0; // 0 == disabled
00476 
00477 #if 0
00478   /* create a default master window */
00479   if (vmic_mmap(*mvme, DEFAULT_SRC_ADD, FullWsze((*mvme)->am)) != MVME_SUCCESS) {
00480     printf("mvme_open: cannot create vme map window");
00481     return(MVME_ACCESS_ERROR);
00482   }
00483 #endif
00484 
00485   /* set controls */
00486 
00487   if (1) {
00488      char devname[256];
00489      int fd;
00490      int status;
00491      struct vmeRequesterCfg cfg;
00492 
00493      cfg.requestLevel = 0;      /*  Requester Bus Request Level */
00494      cfg.fairMode = 0;  /*  Requester Fairness Mode Indicator */
00495      cfg.releaseMode = 0;       /*  Requester Bus Release Mode */
00496      cfg.timeonTimeoutTimer = 7;        /*  Master Time-on Time-out Timer */
00497      cfg.timeoffTimeoutTimer = 0;       /*  Master Time-off Time-out Timer */
00498 
00499      sprintf(devname, "%s", "/dev/vme_ctl");
00500      fd = open(devname, O_RDWR);
00501      if (fd < 0) {
00502         fprintf(stderr,"mvme_open: GEFVME VME driver not present? Cannot open VME device \'%s\', errno %d (%s)\n", devname, errno, strerror(errno));
00503         exit(1);
00504      }
00505 
00506      status = ioctl(fd, VME_IOCTL_SET_REQUESTOR, &cfg);
00507      if (status != 0) {
00508         fprintf(stderr,"mvme_open: Cannot set GEFVME VME_IOCTL_SET_REQUESTOR, errno %d (%s)\n", errno, strerror(errno));
00509         exit(1);
00510      }
00511 
00512      close(fd);
00513   }
00514   
00515   return MVME_SUCCESS;
00516 }

int EXPRT mvme_read ( MVME_INTERFACE mvme,
void *  dst,
mvme_addr_t  vme_addr,
mvme_size_t  n_bytes 
)

Read from VME bus. Uses MVME_BLT_BLT32 for enabling the DMA or size to transfer larger the 128 bytes (32 DWORD) VME access measurement on a VMIC 7805 is : Single read access : 1us DMA read access : 300ns / DMA latency 28us

Parameters:
*mvme VME structure
*dst destination pointer
vme_addr source address (VME location).
n_bytes requested transfer size.
Returns:
MVME_SUCCESS, ERROR

Definition at line 655 of file gefvme.c.

Referenced by sis3820_FifoRead(), v1190_DataRead(), v1720_DataBlockRead(), v1740_DataBlockRead(), v792_DataRead(), and vf48_DataRead().

00656 {
00657   int i, fd;
00658   int offset;
00659   int status;
00660   char* addr;
00661 
00662   /* Perform read */
00663   /*--------------- DMA --------------*/
00664   switch (mvme->blt_mode) {
00665   default:
00666     fprintf(stderr,"mvme_read: Unknown VME block transfer mode %d\n", mvme->blt_mode);
00667     return MVME_ACCESS_ERROR;
00668 
00669   case MVME_AM_A24_SMBLT:
00670   case MVME_AM_A24_NMBLT:
00671   case MVME_AM_A32_SMBLT:
00672   case MVME_AM_A32_NMBLT:
00673   case MVME_BLT_BLT32:
00674   case MVME_BLT_MBLT64:
00675     return gefvme_read_dma(mvme, dst, vme_addr, n_bytes);
00676 
00677   case 0: // no block transfers
00678   
00679     status = gefvme_mapcheck(mvme, vme_addr, n_bytes, &fd, &offset, &addr);
00680     if (status != MVME_SUCCESS)
00681       return status;
00682 
00683     addr += offset;
00684 
00685     if (mvme->dmode == MVME_DMODE_D8) {
00686       char* cdst = (char*)dst;
00687       char* csrc = (char*)addr;
00688       for (i=0; i<n_bytes; i+=sizeof(char))
00689         *cdst++  = *csrc++;
00690     } else if (mvme->dmode == MVME_DMODE_D16) {
00691       WORD* sdst = (WORD*)dst;
00692       WORD* ssrc = (WORD*)addr;
00693       for (i=0; i<n_bytes; i+=sizeof(WORD))
00694         *sdst++  = *ssrc++;
00695     } else if (mvme->dmode == MVME_DMODE_D32) {
00696       DWORD* ddst = (DWORD*)dst;
00697       DWORD* dsrc = (DWORD*)addr;
00698       for (i=0; i<n_bytes; i+=sizeof(DWORD))
00699         *ddst++  = *dsrc++;
00700     } else {
00701       fprintf(stderr,"mvme_read_pio: Invalid dmode %d\n",mvme->dmode);
00702       return MVME_ACCESS_ERROR;
00703     }
00704 
00705 #if 0
00706       for (i=0; i<n_bytes; i+=4) {
00707         char tmp;
00708         tmp = ptr[i+0];
00709         ptr[i+0] = ptr[i+3];
00710         ptr[i+3] = tmp;
00711         tmp = ptr[i+1];
00712         ptr[i+1] = ptr[i+2];
00713         ptr[i+2] = tmp;
00714       }
00715 #endif
00716 
00717 #if 0
00718     status = pread(fd, dst, n_bytes, offset);
00719     if (status != n_bytes)
00720       return MVME_ACCESS_ERROR;
00721 
00722     // NOTE: gefvme PIO block read uses D32 data accesses, so D8 and D16 would not work.
00723     // If gefvme ever implements mmap(), then we can do D8/D16/D32 PIO
00724     // block reads...
00725 
00726     if (mvme->dmode == MVME_DMODE_D8) {
00727       assert(!"mvme_read: VME D8 PIO block read not implemented");
00728     } else if (mvme->dmode == MVME_DMODE_D16) {
00729       assert(!"mvme_read: VME D16 PIO block read not implemented");
00730     } else if (mvme->dmode == MVME_DMODE_D32) {
00731       int i;
00732       char *ptr = (char*)dst;
00733       
00734       for (i=0; i<n_bytes; i+=4) {
00735         char tmp;
00736         tmp = ptr[i+0];
00737         ptr[i+0] = ptr[i+3];
00738         ptr[i+3] = tmp;
00739         tmp = ptr[i+1];
00740         ptr[i+1] = ptr[i+2];
00741         ptr[i+2] = tmp;
00742       }
00743 
00744     } else
00745       assert(!"mvme_read: Unknown value of mvme->dmode. Only MVME_DMODE_D32 and MVME_DMODE_D64 permitted");
00746 #endif
00747 
00748     return MVME_SUCCESS;
00749   }
00750 
00751   assert(!"Cannot be reached!");
00752   return MVME_ACCESS_ERROR;
00753 }

unsigned int EXPRT mvme_read_value ( MVME_INTERFACE mvme,
mvme_addr_t  vme_addr 
)

Read single data from VME bus.

Parameters:
*mvme VME structure
vme_addr source address (VME location).
Returns:
value return VME data

Definition at line 762 of file gefvme.c.

Referenced by lrs1151_Read(), lrs1190_CountRead(), lrs1190_H2Read(), lrs1190_I4Read(), lrs1190_L2Read(), lrs1190_Reset(), regRead(), regReadFloat(), sis3801_CSR_read(), sis3801_dwell_time(), sis3801_FIFO_flush(), sis3801_HFIFO_read(), sis3801_input_mode(), sis3801_IRQ_REG_read(), sis3801_IRQ_REG_write(), sis3801_module_ID(), sis3801_next_logic(), sis3801_ref1(), v1190_DataReady(), v1190_EventRead(), v1190_EvtCounter(), v1190_EvtStored(), v1190_GeoWrite(), v1190_MicroRead(), v1190_MicroWrite(), v1190_Read16(), v1190_Read32(), v1729_DataRead(), v1729_isTrigger(), v1729_NColsGet(), v1729_OrderData(), v1729_PedestalRun(), v1729_Status(), v1729_TimeCalibrationRun(), v560_Read(), v792_BitSet2Read(), v792_ControlRegister1Read(), v792_CSR1Read(), v792_CSR2Read(), v792_DataReady(), v792_EventRead(), v792_EvtCntRead(), v792_isBusy(), v792_isPresent(), v792_Read16(), v792_Status(), v792_ThresholdRead(), v792_ThresholdWrite(), v895_readReg16(), v895_readReg8(), vf48_AcqStart(), vf48_AcqStop(), vf48_CsrRead(), vf48_EventRead(), vf48_ExtTrgClr(), vf48_ExtTrgSet(), vf48_FeFull(), vf48_FeNotEmpty(), vf48_GrpRead(), vf48_isPresent(), vf48_NFrameRead(), vf48_ParameterRead(), vf48_ParameterWrite(), vf48_Reset(), vf48_ResetCollector(), vf48_ResetFrontends(), vf48_Status(), vf48_Trigger(), vmeio_AsyncRead(), vmeio_CsrRead(), vmeio_SyncRead(), vpc6_ASDHysteresisSet(), vpc6_ASDModeSet(), vpc6_ASDThresholdSet(), vpc6_isPortBusy(), vpc6_PATypeRead(), vpc6_PortRegRBRead(), vpc6_PortRegRead(), vpc6_PortTypeRead(), VPPGRegRead(), VPPGRegWrite(), vt2_CSRRead(), vt2_CycleNumberRead(), vt2_FifoLevelRead(), vt2_FifoRead(), vt48_EventRead(), and vt48_RegRead().

00763 {
00764   int status, fd, offset;
00765   char *addr;
00766   DWORD dst = 0;
00767   unsigned char tmp[4];
00768   
00769   status = gefvme_mapcheck(mvme, vme_addr, 4, &fd, &offset, &addr);
00770   if (status != MVME_SUCCESS)
00771     return 0xFFFFFFFF;
00772   
00773   //printf("mvme_read_value: fd %d, vmeaddr 0x%08x, offset %d, addr %p\n", fd, vme_addr, offset, addr);
00774 
00775   addr += offset;
00776   
00777   /* Perform read */
00778   if (mvme->dmode == MVME_DMODE_D8)
00779     dst  = *((char *)addr);
00780   else if (mvme->dmode == MVME_DMODE_D16) {
00781     *((WORD*)tmp) = *((WORD*)addr);
00782     dst = tmp[0]<<8 | tmp[1];
00783   }
00784   else if (mvme->dmode == MVME_DMODE_D32) {
00785     *((DWORD*)tmp) = *((DWORD*)addr);
00786     dst = tmp[0]<<24 | tmp[1]<<16 | tmp[2]<<8 | tmp[3];
00787   }
00788 
00789 #if 0  
00790   /* Perform read */
00791   if (mvme->dmode == MVME_DMODE_D8) {
00792     status = pread(fd, &dst, 1, offset);
00793     if (status != 1) {
00794       //fprintf(stderr,"mvme_read_value: read() returned %d, errno %d (%s)\n", status, errno, strerror(errno));
00795       return 0xFF;
00796     }
00797   } else if (mvme->dmode == MVME_DMODE_D16) {
00798     char buf16[2];
00799     uint16_t dst16;
00800     status = pread(fd, buf16, 2, offset);
00801     dst16 = (buf16[1]&0xFF) | (buf16[0]<<8);
00802     //printf("read16: addr 0x%x, value 0x%02x 0x02x 0x%04x, status %d\n", vme_addr, buf16[0], buf16[1], dst16, status);
00803     if (status == 2)
00804       return dst16;
00805 
00806     //fprintf(stderr,"mvme_read_value: read() returned %d, errno %d (%s)\n", status, errno, strerror(errno));
00807     return 0xFFFF;
00808   } else if (mvme->dmode == MVME_DMODE_D32) {
00809     char buf32[4];
00810     uint32_t dst32;
00811     status = pread(fd, buf32, 4, offset);
00812     dst32 = (buf32[3]&0xFF) | (0xFF00&buf32[2]<<8)| (0xFF0000&buf32[1]<<16) | (0xFF000000&buf32[0]<<24);
00813     //printf("read32: fd %d, addr 0x%x, offset 0x%x, value 0x%02x 0x%02x 0x%02x 0x%02x 0x%08x, status %d\n", fd, vme_addr, offset, buf32[0], buf32[1], buf32[2], buf32[3], dst32, status);
00814     //exit(1);
00815     if (status == 4)
00816       return dst32;
00817 
00818     //fprintf(stderr,"mvme_read_value: read() returned %d, errno %d (%s)\n", status, errno, strerror(errno));
00819     return 0xFFFFFFFF;
00820   }
00821 #endif
00822 
00823   return dst;
00824 }

int EXPRT mvme_set_am ( MVME_INTERFACE vme,
int  am 
)

Set Address Modifier.

Parameters:
*vme VME structure
am address modifier
Returns:
MVME_SUCCESS

Definition at line 958 of file gefvme.c.

Referenced by regRead(), regReadFloat(), regWrite(), regWriteFloat(), sis3820_FifoRead(), v1190_Read16(), v1190_Read32(), v1190_Write16(), v1720_DataBlockRead(), v1740_DataBlockRead(), v1740_DataRead(), v560_Read(), v895_readReg16(), v895_readReg8(), v895_writeReg16(), v895_writeReg8(), vf48_AcqStart(), vf48_AcqStop(), vf48_ActiveChMaskRead(), vf48_ActiveChMaskSet(), vf48_ChSuppRead(), vf48_ChSuppSet(), vf48_CsrRead(), vf48_DataRead(), vf48_DivisorRead(), vf48_DivisorWrite(), vf48_EventRead(), vf48_EventRead64(), vf48_ExtTrgClr(), vf48_ExtTrgSet(), vf48_FeFull(), vf48_FeNotEmpty(), vf48_GrpEnable(), vf48_GrpRead(), vf48_HitThresholdRead(), vf48_HitThresholdSet(), vf48_isPresent(), vf48_NFrameRead(), vf48_ParameterRead(), vf48_ParameterWrite(), vf48_RawDataSuppRead(), vf48_RawDataSuppSet(), vf48_Reset(), vf48_ResetCollector(), vf48_ResetFrontends(), vf48_SegmentSizeRead(), vf48_SegmentSizeSet(), vf48_Setup(), vf48_Status(), vf48_TrgThresholdRead(), vf48_TrgThresholdSet(), vf48_Trigger(), vmeio_AsyncRead(), vmeio_AsyncWrite(), vmeio_CsrRead(), vmeio_IntEnable(), vmeio_IntRearm(), vmeio_OutputSet(), vmeio_StrobeClear(), vmeio_SyncRead(), vmeio_SyncWrite(), VPPGRegRead(), and VPPGRegWrite().

00959 {
00960   mvme->am = am;
00961   return MVME_SUCCESS;
00962 }

int EXPRT mvme_set_blt ( MVME_INTERFACE vme,
int  mode 
)

Set Block Transfer mode.

Parameters:
*vme VME structure
mode BLT mode
Returns:
MVME_SUCCESS

Definition at line 986 of file gefvme.c.

Referenced by sis3820_FifoRead(), v1190_DataRead(), v1720_DataBlockRead(), v1740_DataBlockRead(), and vf48_DataRead().

00987 {
00988   mvme->blt_mode = mode;
00989   return MVME_SUCCESS;
00990 }

int EXPRT mvme_set_dmode ( MVME_INTERFACE vme,
int  dmode 
)

Set Data mode.

Parameters:
*vme VME structure
dmode Data mode
Returns:
MVME_SUCCESS

Definition at line 972 of file gefvme.c.

Referenced by lrs1151_Clear(), lrs1151_Read(), lrs1190_CountRead(), lrs1190_Disable(), lrs1190_Enable(), lrs1190_H2Read(), lrs1190_I4Read(), lrs1190_L2Read(), lrs1190_Reset(), regRead(), regReadFloat(), regWrite(), regWriteFloat(), sis3801_channel_enable(), sis3801_CSR_read(), sis3801_CSR_write(), sis3801_dwell_time(), sis3801_FIFO_clear(), sis3801_FIFO_flush(), sis3801_HFIFO_read(), sis3801_input_mode(), sis3801_int_attach(), sis3801_int_source(), sis3801_int_source_disable(), sis3801_int_source_enable(), sis3801_IRQ_REG_read(), sis3801_IRQ_REG_write(), sis3801_module_ID(), sis3801_module_reset(), sis3801_next_logic(), sis3801_ref1(), sis3801_Setup(), v1190_AcqModeRead(), v1190_ContinuousSet(), v1190_DataRead(), v1190_DataReady(), v1190_EventRead(), v1190_EvtCounter(), v1190_EvtStored(), v1190_GeoWrite(), v1190_LEResolutionSet(), v1190_MicroFlush(), v1190_MicroRead(), v1190_MicroWrite(), v1190_OffsetSet(), v1190_Read16(), v1190_Read32(), v1190_ResolutionRead(), v1190_SetEdgeDetection(), v1190_Setup(), v1190_SoftClear(), v1190_SoftReset(), v1190_SoftTrigger(), v1190_Status(), v1190_TdcIdList(), v1190_TriggerMatchingSet(), v1190_WidthSet(), v1190_Write16(), v1720_DataBlockRead(), v1729_AcqStart(), v1729_ChannelSelect(), v1729_DataRead(), v1729_FrqSamplingSet(), v1729_isTrigger(), v1729_NColsGet(), v1729_NColsSet(), v1729_OrderData(), v1729_PedestalRun(), v1729_PostTrigSet(), v1729_PreTrigSet(), v1729_Reset(), v1729_Setup(), v1729_SoftTrigger(), v1729_Status(), v1729_TimeCalibrationRun(), v1729_TriggerTypeSet(), v1740_DataBlockRead(), v1740_DataRead(), v560_Read(), v792_BitSet2Clear(), v792_BitSet2Read(), v792_BitSet2Set(), v792_ControlRegister1Read(), v792_ControlRegister1Write(), v792_CSR1Read(), v792_CSR2Read(), v792_DataClear(), v792_DataRead(), v792_DataReady(), v792_EmptyEnable(), v792_EventRead(), v792_EvtCntRead(), v792_EvtCntReset(), v792_EvtTriggerSet(), v792_IntDisable(), v792_IntEnable(), v792_IntSet(), v792_isBusy(), v792_isPresent(), v792_LowThDisable(), v792_LowThEnable(), v792_OnlineSet(), v792_Read16(), v792_Setup(), v792_SingleShotReset(), v792_SoftReset(), v792_Status(), v792_ThresholdRead(), v792_ThresholdWrite(), v792_Trigger(), v792_Write16(), v895_readReg16(), v895_readReg8(), v895_writeReg16(), v895_writeReg8(), vf48_AcqStart(), vf48_AcqStop(), vf48_ActiveChMaskRead(), vf48_ActiveChMaskSet(), vf48_ChSuppRead(), vf48_ChSuppSet(), vf48_CsrRead(), vf48_DataRead(), vf48_DivisorRead(), vf48_DivisorWrite(), vf48_EventRead(), vf48_EventRead64(), vf48_ExtTrgClr(), vf48_ExtTrgSet(), vf48_FeFull(), vf48_FeNotEmpty(), vf48_GrpEnable(), vf48_GrpRead(), vf48_HitThresholdRead(), vf48_HitThresholdSet(), vf48_isPresent(), vf48_NFrameRead(), vf48_ParameterRead(), vf48_ParameterWrite(), vf48_RawDataSuppRead(), vf48_RawDataSuppSet(), vf48_Reset(), vf48_ResetCollector(), vf48_ResetFrontends(), vf48_SegmentSizeRead(), vf48_SegmentSizeSet(), vf48_Setup(), vf48_Status(), vf48_TrgThresholdRead(), vf48_TrgThresholdSet(), vf48_Trigger(), vmeio_AsyncRead(), vmeio_AsyncWrite(), vmeio_CsrRead(), vmeio_IntEnable(), vmeio_IntRearm(), vmeio_OutputSet(), vmeio_StrobeClear(), vmeio_SyncRead(), vmeio_SyncWrite(), vpc6_ASDHysteresisSet(), vpc6_ASDModeSet(), vpc6_ASDRegSet(), vpc6_ASDThresholdSet(), vpc6_CfgRetrieve(), vpc6_isPortBusy(), vpc6_PATypeRead(), vpc6_PATypeWrite(), vpc6_PortCfgLoad(), vpc6_PortRegRBRead(), vpc6_PortRegRead(), vpc6_PortTypeRead(), vpc6_Setup(), vpc6_Status(), VPPGRegRead(), VPPGRegWrite(), vt2_CSRRead(), vt2_CycleNumberRead(), vt2_CycleReset(), vt2_FifoLevelRead(), vt2_FifoRead(), vt2_IntEnable(), vt2_KeepAlive(), vt2_ManReset(), vt48_EventRead(), vt48_RegPrint(), vt48_RegRead(), vt48_RegWrite(), vt48_Setup(), vt48_Status(), vt48_WindowOffsetSet(), and vt48_WindowSet().

00973 {
00974   mvme->dmode = dmode;
00975   return MVME_SUCCESS;
00976 }

int EXPRT mvme_sysreset ( MVME_INTERFACE mvme  ) 

VME bus reset. For the VMIC system this will reboot the CPU!

Parameters:
*mvme VME structure.
Returns:
MVME_SUCCESS, ERROR

Definition at line 558 of file gefvme.c.

00559 {
00560   assert(!"Not implemented");
00561   return MVME_SUCCESS;
00562 }

int EXPRT mvme_write ( MVME_INTERFACE mvme,
mvme_addr_t  vme_addr,
void *  src,
mvme_size_t  n_bytes 
)

Write data to VME bus. Uses MVME_BLT_BLT32 for enabling the DMA or size to transfer larger the 128 bytes (32 DWORD)

Parameters:
*mvme VME structure
vme_addr source address (VME location).
*src source array
n_bytes size of the array in bytes
Returns:
MVME_SUCCESS, MVME_ACCESS_ERROR

Definition at line 836 of file gefvme.c.

00837 {
00838   assert(!"Not implemented");
00839 #if 0
00840   /* Perform write */
00841   /*--------------- DMA --------------*/
00842   if ((mvme->blt_mode == MVME_BLT_BLT32) ||
00843       (mvme->blt_mode == MVME_BLT_MBLT64) ||
00844       (n_bytes > 127)) {
00845 
00846     DMA_INFO  *info = ((DMA_INFO  *)mvme->info);
00847 
00848     if (n_bytes >= DEFAULT_DMA_NBYTES)
00849       {
00850         fprintf(stderr,"mvme_write: Attempt to DMA %d bytes more than DEFAULT_DMA_NBYTES=%d\n", (int)n_bytes, DEFAULT_DMA_NBYTES);
00851         return(ERROR);
00852       }
00853 
00854     memcpy(info->dma_ptr, src, n_bytes);
00855     
00856     if(0 > vme_dma_write((vme_bus_handle_t )mvme->handle
00857        , info->dma_handle
00858        , 0
00859        , vme_addr
00860        , mvme->am
00861        , n_bytes
00862        , 0)) {
00863       perror("Error writing data");
00864       return(MVME_ACCESS_ERROR);
00865     }
00866   } else {
00867     int i;
00868     mvme_addr_t addr;
00869   
00870     /*--------------- Single Access -------------*/
00871     addr = vmic_mapcheck(mvme, vme_addr, n_bytes);
00872     
00873     /* Perform write */
00874     if (mvme->dmode == MVME_DMODE_D8) {
00875       char*dst = (char*)addr;
00876       char*sss = (char*)src;
00877       for (i=0; i<n_bytes; i+=sizeof(char))
00878         *dst++ = *sss++;
00879     } else if (mvme->dmode == MVME_DMODE_D16) {
00880       WORD*dst = (WORD*)addr;
00881       WORD*sss = (WORD*)src;
00882       for (i=0; i<n_bytes; i+=sizeof(WORD))
00883         *dst++ = *sss++;
00884     } else if (mvme->dmode == MVME_DMODE_D32) {
00885       DWORD*dst = (DWORD*)addr;
00886       DWORD*sss = (DWORD*)src;
00887       for (i=0; i<n_bytes; i+=sizeof(DWORD))
00888         *dst++ = *sss++;
00889     } else {
00890       fprintf(stderr,"mvme_write: Invalid dmode %d\n",mvme->dmode);
00891       return(ERROR);
00892     }
00893   }
00894   return MVME_SUCCESS;
00895 #endif
00896 }

int EXPRT mvme_write_value ( MVME_INTERFACE vme,
mvme_addr_t  vme_addr,
unsigned int  value 
)

Write single data to VME bus. Useful for register access. See example in mvme_open()

Parameters:
*vme VME structure
vme_addr source address (VME location).
value Value to be written to the VME bus
Returns:
MVME_SUCCESS

Referenced by lrs1151_Clear(), lrs1190_Disable(), lrs1190_Enable(), lrs1190_I4Read(), regWrite(), regWriteFloat(), sis3801_channel_enable(), sis3801_CSR_write(), sis3801_dwell_time(), sis3801_FIFO_clear(), sis3801_input_mode(), sis3801_int_attach(), sis3801_int_clear(), sis3801_int_source(), sis3801_int_source_disable(), sis3801_int_source_enable(), sis3801_IRQ_REG_write(), sis3801_module_reset(), sis3801_next_logic(), sis3801_ref1(), v1190_GeoWrite(), v1190_MicroWrite(), v1190_SoftClear(), v1190_SoftReset(), v1190_SoftTrigger(), v1190_Write16(), v1729_AcqStart(), v1729_ChannelSelect(), v1729_FrqSamplingSet(), v1729_NColsSet(), v1729_PostTrigSet(), v1729_PreTrigSet(), v1729_Reset(), v1729_Setup(), v1729_SoftTrigger(), v1729_TriggerTypeSet(), v792_BitSet2Clear(), v792_BitSet2Set(), v792_ControlRegister1Write(), v792_DataClear(), v792_EmptyEnable(), v792_EvtCntReset(), v792_EvtTriggerSet(), v792_IntDisable(), v792_IntEnable(), v792_IntSet(), v792_LowThDisable(), v792_LowThEnable(), v792_OnlineSet(), v792_SingleShotReset(), v792_SoftReset(), v792_ThresholdWrite(), v792_Trigger(), v792_Write16(), v895_writeReg16(), v895_writeReg8(), vf48_AcqStart(), vf48_AcqStop(), vf48_ExtTrgClr(), vf48_ExtTrgSet(), vf48_GrpEnable(), vf48_ParameterRead(), vf48_ParameterWrite(), vf48_Reset(), vf48_ResetCollector(), vf48_ResetFrontends(), vf48_Trigger(), vmeio_AsyncWrite(), vmeio_IntEnable(), vmeio_IntRearm(), vmeio_OutputSet(), vmeio_StrobeClear(), vmeio_SyncWrite(), vpc6_ASDRegSet(), vpc6_CfgRetrieve(), vpc6_PATypeWrite(), vpc6_PortCfgLoad(), VPPGRegWrite(), vt2_CycleReset(), vt2_IntEnable(), vt2_KeepAlive(), vt2_ManReset(), and vt48_RegWrite().


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