VME-PPG32

VME-PPG32 - pulse pattern generator VME FPGA board

References

• [1] VME-PPG32 (REA 198) project page on edev.triumf.ca
• [2] Rev0 board schematics
• [3] Svn repository for initial test firmware
• [4] Current PPG firmware Source/binary

General characteristics

Available hardware

• Altera cyclone 3 FPGA: EP3C40Q240C8
• Serial flash for FPGA configuration: Altera EPCS16
• VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
• 32 NIM outputs
• 4 NIM inputs
• 32 "NIM output" LEDs
• 4 "NIM input" LEDs
• 1 "VME access" LED
• 2 output serial DAC: AD5439YRUZ

PPG characteristics

  4k words (128bit words) of program memory.
  256 entry stack.
  Halt/Continue/Loop/Subroutine/Branch instructions
  100Mhz clock (derived from either 50Mhz internal crystal or external 20Mhz clock input)
  fixed 3 clk per instruction plus 32bit delay individualy programmable for each instruction

VME interface

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address. VME registers are listed in the table below.

Registers

Number	Address	Name	Access	Description
0	0x00000	Test	RW	Test Register
1	0x00004	CSR	RW	Control/Status Register
2	0x00008	Addr	RW	Program Address Register
3	0x0000C	Inst_Lo	RW	Instruction Register Part 1/4
4	0x00010	Inst_Med	RW	Instruction Register Part 2/4
5	0x00014	Inst_Hi	RW	Instruction Register Part 3/4
6	0x00018	Inst_Top	RW	Instruction Register Part 4/4
7	0x0001C	Version	R	Firmware Version Register
8	0x00020	Flash	RW	Serial Flash Control Register
9	0x00024	Serial	R	Serial Number Register
10	0x00028	Hardware	R	hardware Identification Register

Test Register (0x00000)

Simple Test Register - Value Written is preserved and can be read back.

CSR Register (0x00004)

The first 5 bits control the ppg, the remaining 26 bits provide read-only status information. (writes to the 26 bits of status information are ignored, and overwritten on the next status update)

CSR Description

Bit	Name	Access	description
0	Run	R/W	Run Control/Status
1	Ext-Clk	R/W	The PPG logic uses the external Clk
2	Ext-Start	R/W
3	Slow-Clk	R/W
4	Test-Mode	R/W
5-31	Status	R	Readback of PC,SP,Current Delay Counter

RUN bit: Writing 1 here instructs the ppg to begin executing its program, reading this bit returns 1 if the program is still running, or 0 if halted.

Ext_Clk bit: Writing 1 here switches the ppg logic to use the external CLK (Nim_Input[0]) (The VME interface always uses the internal clock)

Ext_Start bit: Writing 1 here disables the CSR-Run-bit-start (Reading this bit still returns the correct status), and switches control to the External Start input (NIM_INPUT[1])

Slow-Clk bit: Writing 1 here Switches the ppg clock to a much slower one (2kHz) for low speed/long delay operation. NOTE - this is currently ignored.

Test-mode bit: Writing 1 here Changes the outputs (LED/NIM) to simple follow the state of the Address register.

Address Register (0x00008)

Sets PPG Program Memory Address - next instruction will be written to this location. Also when program is started, execution begins from this address

Instruction Registers (0x0000C - 0x00018)

Registers to hold the 128bit Program Instructions. Writing the Upper register triggers the storing of the entire 128bit instruction to the address currently in the address register.

The instructions format is as follows ...

Instruction Format

Bits 0-31	Bits 32-63	Bits 64-95	Bits 96-115	Bits 116-117	Bits 118-127
32 Output Set Bits	32 Output Clear Bits	32bit Delay Count	20bit Data	4bit instruction type	Ignored

The 32bit delay count at 100Mhz gives maximum delay of 10 seconds per instruction.

  The instruction types are ...
  0 - Halt
  1 - Continue
  2 - new Loop        ( 20 bit data used for count - i.e. maximum 1 million )
  3 - End Loop
  4 - Call Subroutine ( 20 bit data used for address )
  5 - Return from subroutine
  6 - Branch          ( 20 bit data used for address )

Firmware Version (0x0001C)

Returns the 32bit unix timestamp corresponding to the date this firmware was compiled.

Serial Flash Control (0x00020)

Used for reading/Writing to the Configuration Flash device (Reading/Updating firmware)

Serial Number (0x00024)

Returns the module serial number, and Board revision (if set) or -1

hardware Type (0x00028)

Returns a 32 bit description of this hardware - which should confirm the identity of this module as a vme-ppg32