ALPHA: Difference between revisions

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* VF48 readout is set to "scope mode", 20 Ms/s (divider 3, see ttc_test3)
* VF48 readout is set to "scope mode", 20 Ms/s (divider 3, see ttc_test3)
* from the VME bus, calibration pulse is triggered, at the same time VF48 is triggered, records 1000 samples at 20 Ms/s (divider 3), this captures the complete calibration pulse waveform
* from the VME bus, calibration pulse is triggered, at the same time VF48 is triggered, records 1000 samples at 20 Ms/s (divider 3), this captures the complete calibration pulse waveform
* alternatively, the HOLD delay is trigged at the same time and the HOLD signal is operated half-way-through the waveform, at the moment of HOLD it becomes flat. this is used to demonstrate the operationof the HOLD signal and to confirm that HOLD works on all VA1TA ASICs.
* alternatively, the HOLD delay is trigged at the same time and the HOLD signal is operated half-way-through the waveform, at the moment of HOLD the waveform becomes flat. this is used to demonstrate the operation of the HOLD signal and to confirm that HOLD works on all VA1TA ASICs.


In addition, the TA signals are tested:
In addition, the TA signals are tested:

Revision as of 17:45, 24 June 2026

ALPHA AD-5 at CERN

Links

ALPHA-2

Rebuild midas:

  • cd ~/packages/midas; make clean; make cmake -j
  • restart mlogger, mserver, mhttpd, lazylogger

Rebuild frontends:

  • fevme: ssh alphavme04, cd online/vme, make clean, make, restart fevme
  • SVD bias P.S. fecaenr14xxet.exe: cd packages/frontends/fecaen14xxet, make clean, make, restart fecaen_hvps01
  • felabview: no update
  • super_felabiew, feXSequencer: cd online/src, make clean, make, not sure how to install to ../bin and restart.
  • feGEM: cd online/feGEM, make clean, make,

ALPHA-2 SVD

clock distribution

  • IO32 internal osc (IO32 has no external trigger input) -> 2x LEMO NIM output 20 MHz -> TTC1, TTC2
  • -> TTC1
  • -> VETO_IN LEMO1A
  • -> FPGA pin FP_Ext_TrigInput1 -> 20 MHz PLL -> PLL1_20MHz -> mux -> mux_clk -> pll_20MHz
  • -> FPGA pin PLL_20MHz -> FP_ADC_CLK -> LVDS_ADC_CLK -> ADC clock LEMO5A
  • -> VF48 20 MHz clock daisy chain, 4 VF48 modules
  • -> VF48 clock input -> PLL 20MHz-to-60MHz -> 60 MHz ADC sampling clock

same thing repeats for the 2nd TTC

  • -> TTC2

TTC functions

Downloading VA1TA configurations (BOOT control)

VA1TA configuration is done via J2 daisychain cable to the FRCs:

  • LVDS_BOOT_CLKIN and LVDS_BOOT_REGIN - shift serial data to VA1TA ASIC shift register
  • LVDS_BOOT_REGOUT - serial data shifted out from VA1TA ASIC shift register
  • LVDS_BOOT_LOAD - load serial data from VA1TA shift register into internal registers
  • LVDS_BOOT_READ - read VA1TA internal registers to the serial data shift register
  • CMOS_FEC_ADD[0..5] - select which FRC port is connected to the LVDS_BOOT_xxx signals

Loading VA1TA configuration is done by bit-banging an FPGA register that maps VME data bits to LVDS_BOOT_xxx signals (see alphaTTC.txt).

Typical write sequence:

  • set FRC port address via CMOS_FEC_ADD (4 bits select the FRC, 2 bits select one of four FRC ports)
  • toggle CLKIN and REGIN to shift 4x??? bits of VA1TA configuration data (all four VA1TA ASICs are loaded at the same time)
  • (not useful to observe REGOUT, it is shifting out whatever random data happens to be in the VA1TA shift register)
  • toggle LOAD to transfer configuration data from shift register to internal registers

Typical read sequence:

  • set FRC port address via CMOS_FEC_ADD
  • toggle READ to transfer data from internal registers to the shift register
  • toggle CLKIN, record value of REGOUT from each clock

Typical load cycle will do 1 write and 1 read, compare the shifted-out bits against shifted-in bits, flag an error if there is a mismatch.

To operate the VA1TA, CLKIN, REGIN and LOAD signals must work.

If READ and REGOUT signals do not work or are unreliable, one can confirm correctly loaded configuration by doing a threshold scan or some other indirect method (i.e. change VA gain and observe change of calibration pulse).

ALPHA-3

on the new FRC, CMOC_FEC_ADD should be removed, BOOT_CLKIN, LVDS_BOOT_REGIN, LVDS_BOOT_REGOUT, LVDS_BOOT_LOAD, LVDS_BOOT_READ from all 4 Si module ports should be connected directly to the FPGA, 4*5=20 signals.

loading VA1TA configuration will be done by local FPGA control from MIDAS via ethernet on each new FRC separately.

loading of TA thresholds during the TA threshold scan will be controlled by MIDAS via ethernet.

Sequencing the readout of the VA1TA analog multiplexor and VF48 trigger

VA1TA analog mux is operated using the J2 daisychain connector signals:

  • LVDS_READOUT_CKB, LVDS_READOUT_SHIN - shift 1 bit across the analog mux
  • LVDS_READOUT_RESET - zero out the analog mux shift register
  • LVDS_READOUT_HOLD - latch Si detector analog voltages (1-time-bin-deep storage capacitor array, SCA)
  • LVDS_READOUT_SHOUT exists on the VA1TA, but does it come out to the FRC? (TBC)

The HOLD signal is asserted by the delayed event trigger. This delay is adjusted to latch the Si detector signals at their maximum peaking time. This is done by a HOLD delay scan on cosmic data.

Readout should start soon after HOLD time, analog signals stored in capacitor array degrade over time.

Typical read sequence (see ALPHA_TTC.pdf for exact sequence):

  • TA signals fire, arrive to TTC trigger FPGA, generate a trigger
  • trigger arrives to TTC
  • HOLD delay runs
  • HOLD signal is operated
  • readout delay runs
  • readout starts
  • adc delay runs, triggers the VF48 ADC
  • at the same time
  • 1 bit is shifted into SHIN
  • every 3 clocks of 10 MHz clock, CKB is operated, next strip capacitor is connected to the mux
  • not sure when RESET is operated (TBC)

VF48 ADC is set to divider 18 (60MHz/6/3) to register 1 ADC sample per 1 analog max step.

VF48 trigger delay and TTC adc delay are adjusted to record all 128 strips at the analog mux output max peaking time.

This is done using the ADC delay scan on cosmic data: ADC delay is adjusted to observe maximum signal amplitude and to ensure there is data from the first and last strip. Decreasing the ADC delay will reduce ADC amplitude (analog mux signal rise time), after next decrease we start seeing data from the previous strip (data from last strip is lost, or data from the first strip is lost).

(TBC), current sequencer stretches the first strip and the last strip, ideally VF48 ADC should match this and record the extra samples (3+126+3 samples).

Readout of all VA1TA ASICs on all Si modules is done in parallel, the same CKB, SHIN, HOLD and RESET is connected to all VA1TA ASICs. (so there will be 4 SHOUT coming back from the Si module, TBC). This is different from LVDS_BOOT_REGIN which is daisychained across all 4 VA1TA ASICs.

ALPHA-3

  • on the new FRC, it is best if all of them run on the same clock
  • but 100 ns resolution of the 10 MHz clock is not good enough to reproduce the existing system
  • 10 ns resolution of the 100 MHz clock should be good enough
  • analog mux readout will run on each new FRC from the local FPGA, no need to distribute the READOUT_xxx signals from the TTC
  • HOLD signal on each new FRC should be asserted at it's own ideal time, this means separate HOLD delay scan and ADC delay scan on each new FRC (I expect they will all want to use the same values, I expect no per-FRC variations)
  • trigger signal must be distributed from the TTC to all the new FRCs at the same time (no daisychain). Old TTC HOLD signal cannot be reused for this, it may come too late (because of HOLD delay).

Control of calibration pulser

The calibration pulser is used to confirm correct operation of the VA1TA ASICs:

  • analog pulse is injected into the inputs of the VA1TA ASIC
  • VA analog mux is configured to connect VA analog output to a specific strip (pass through, or scope mode)
  • VF48 readout is set to "scope mode", 20 Ms/s (divider 3, see ttc_test3)
  • from the VME bus, calibration pulse is triggered, at the same time VF48 is triggered, records 1000 samples at 20 Ms/s (divider 3), this captures the complete calibration pulse waveform
  • alternatively, the HOLD delay is trigged at the same time and the HOLD signal is operated half-way-through the waveform, at the moment of HOLD the waveform becomes flat. this is used to demonstrate the operation of the HOLD signal and to confirm that HOLD works on all VA1TA ASICs.

In addition, the TA signals are tested:

  • calibration pulse fires the VA1TA TA signal
  • it travels all the way through the FRC (4 TA per Si module)
  • to the TTC (16 TA per FRC)
  • through the TA signal conditioner
  • to a TA counter
  • when running test_ttc3, operator confirms that each TA signal fires once (1) per calibration pulse. 0 fires means TA is dead, double pulsing is normal for some channels, ringing and oscillations mean TA threshold is not loaded into the VA1TA registers.

ALPHA-3

  • proposed new digitizer is 10 Ms/s, slower than existing 20 Ms/s used by ttc_test3 & co. we can test if reduced samplign rate is good enough by changing ttc_test3 divider from 3 to 6. (TBC)
  • central calibration pulse must be generated by the TTC and distributed to all FRCs
  • the trigger signal from TTC to all new FRCs (described above) should be sufficient to implement all the ttc_testNNN functions
  • perhaps local calibration pulser on each new FRC can be used, in this case, ttc_testNNN will run on each new FRC separately, there will be no central ttc_test script. TA counters will be on the new FRC, transmission of TA from new FRC to TTC will be tested by some other means. (TBC)
  • new calibration pulse should be done some as existing: i2c DAC output gated by a square wave pulse from an FPGA output pin.

Processing VA1TA TA outputs and generation of NIM trigger outputs

AAA

ALPHA-3 SVD Upgrade

Changes and improvements vs ALPHA-2

  • connect LVDS_READOUT_SHOUT if it comes back from the Si module at all
  • record the stretched first and last strips (3+126+3 samples)

End

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