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== clock distribution == | == clock distribution == | ||
* IO32 internal osc (IO32 has no external trigger input) -> 2x LEMO NIM output 20 MHz -> | |||
IO32 internal osc (IO32 has no external trigger input) -> 2x LEMO NIM output 20 MHz -> | * -> TTC1 | ||
-> TTC1 | * -> TTC FP_Ext_TrigInput1 (VETO_IN LEMO1A) -> 20 MHz PLL -> PLL1_20MHz -> mux -> mux_clk -> pll_20MHz -> (ADC clock LEMO5A) | ||
-> TTC FP_Ext_TrigInput1 (VETO_IN LEMO1A) -> 20 MHz PLL -> PLL1_20MHz -> mux -> mux_clk -> pll_20MHz -> (ADC clock LEMO5A) | * -> VF48 20 MHz clock daisy chain, 4 VF48 modules | ||
-> VF48 20 MHz clock daisy chain, 4 VF48 modules | * -> VF48 clock input -> PLL 20MHz-to-60MHz -> 60 MHz ADC sampling clock | ||
-> VF48 clock input -> PLL 20MHz-to-60MHz -> 60 MHz ADC sampling clock | |||
same thing repeats for the 2nd TTC | same thing repeats for the 2nd TTC | ||
-> TTC2 | * -> TTC2 | ||
== TTC functions == | == TTC functions == | ||
Revision as of 23:34, 23 June 2026
ALPHA AD-5 at CERN
Links
- ALPHA-2 MIDAS: https://alphacpc05.cern.ch
- ALPHA-g MIDAS: https://alphacpc05.cern.ch/agdaq/
- nodeinfo: https://alphacpc05.cern.ch/gonodeinfo/gonodereport.html
- zfs quota report: https://alphacpc05.cern.ch/zfsquotareport/zfsquota.html
- ganglia: https://alphacpc05.cern.ch/ganglia/
- elog: https://alphacpc05.cern.ch/elog/alpha/
- AgWiki: https://daq00.triumf.ca/AgWiki/
- old alpha-g elog: https://daq00.triumf.ca/elog-alphag-old/alphag/
ALPHA-2
Rebuild midas:
- cd ~/packages/midas; make clean; make cmake -j
- restart mlogger, mserver, mhttpd, lazylogger
Rebuild frontends:
- fevme: ssh alphavme04, cd online/vme, make clean, make, restart fevme
- SVD bias P.S. fecaenr14xxet.exe: cd packages/frontends/fecaen14xxet, make clean, make, restart fecaen_hvps01
- felabview: no update
- super_felabiew, feXSequencer: cd online/src, make clean, make, not sure how to install to ../bin and restart.
- feGEM: cd online/feGEM, make clean, make,
ALPHA-2 SVD
- VME-ALPHA-TTC
- VME-NIMIO32#ALPHA_trigger_control
- VME-TTC board schematics File:ALPHA TTC 20091105.pdf
- VME-TTC firmware schematics, main FPGA File:ALPHA TTC 20091105.pdf
- VME-TTC firmware schematics, trigger FPGA File:ALPHA TTC Trigger2.pdf
- VME-TTC firmware schematics, TA singal conditioner File:ALPHA TTC SignalConditioner.pdf
- VME-TTC manual https://bitbucket.org/expalpha/ttc_firmware/src/master/alphaTTC.txt
clock distribution
- IO32 internal osc (IO32 has no external trigger input) -> 2x LEMO NIM output 20 MHz ->
- -> TTC1
- -> TTC FP_Ext_TrigInput1 (VETO_IN LEMO1A) -> 20 MHz PLL -> PLL1_20MHz -> mux -> mux_clk -> pll_20MHz -> (ADC clock LEMO5A)
- -> VF48 20 MHz clock daisy chain, 4 VF48 modules
- -> VF48 clock input -> PLL 20MHz-to-60MHz -> 60 MHz ADC sampling clock
same thing repeats for the 2nd TTC
- -> TTC2
TTC functions
- Downloading VA1TA configurations (BOOT control)
- Control of calibration pulser DACs
- Sequencing the readout of the VA1TA analog multiplexor and VF48 trigger
- Processing VA1TA TA outputs and generation of NIM trigger outputs
ALPHA-3 SVD Upgrade
AAA