ALPHA: Difference between revisions

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== TTC functions ==
== TTC functions ==


* Downloading VA1TA configurations (BOOT control)
=== Downloading VA1TA configurations (BOOT control) ===
* Control of calibration pulser DACs
 
* Sequencing the readout of the VA1TA analog multiplexor and VF48 trigger
AAA
* Processing VA1TA TA outputs and generation of NIM trigger outputs
 
=== Control of calibration pulser DACs ===
 
AAA
 
=== Sequencing the readout of the VA1TA analog multiplexor and VF48 trigger ===
 
AAA
 
=== Processing VA1TA TA outputs and generation of NIM trigger outputs ===
 
AAA


= ALPHA-3 SVD Upgrade =
= ALPHA-3 SVD Upgrade =

Revision as of 23:40, 23 June 2026

ALPHA AD-5 at CERN

Links

ALPHA-2

Rebuild midas:

  • cd ~/packages/midas; make clean; make cmake -j
  • restart mlogger, mserver, mhttpd, lazylogger

Rebuild frontends:

  • fevme: ssh alphavme04, cd online/vme, make clean, make, restart fevme
  • SVD bias P.S. fecaenr14xxet.exe: cd packages/frontends/fecaen14xxet, make clean, make, restart fecaen_hvps01
  • felabview: no update
  • super_felabiew, feXSequencer: cd online/src, make clean, make, not sure how to install to ../bin and restart.
  • feGEM: cd online/feGEM, make clean, make,

ALPHA-2 SVD

clock distribution

  • IO32 internal osc (IO32 has no external trigger input) -> 2x LEMO NIM output 20 MHz -> TTC1, TTC2
  • -> TTC1
  • -> VETO_IN LEMO1A
  • -> FPGA pin FP_Ext_TrigInput1 -> 20 MHz PLL -> PLL1_20MHz -> mux -> mux_clk -> pll_20MHz
  • -> FPGA pin PLL_20MHz -> FP_ADC_CLK -> LVDS_ADC_CLK -> ADC clock LEMO5A
  • -> VF48 20 MHz clock daisy chain, 4 VF48 modules
  • -> VF48 clock input -> PLL 20MHz-to-60MHz -> 60 MHz ADC sampling clock

same thing repeats for the 2nd TTC

  • -> TTC2

TTC functions

Downloading VA1TA configurations (BOOT control)

AAA

Control of calibration pulser DACs

AAA

Sequencing the readout of the VA1TA analog multiplexor and VF48 trigger

AAA

Processing VA1TA TA outputs and generation of NIM trigger outputs

AAA

ALPHA-3 SVD Upgrade

AAA

End