VT4 info
VME-VT4 - 4-channel timestamp module using the VME-IO32 board
VME interface
VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address. VME registers are listed in the table below.
Registers
| Number | Address | Name | Access | Description |
|---|---|---|---|---|
| 0 | 0x0003C | CSR | RW | Control/Status Register |
| 1 | 0x00040 | Test | RW | Test Register |
| 2 | 0x00044 | Tstamp | R | Firmware Timestamp |
| 3 | 0x00048 | Nwords | R | Data Words available |
| 4 | 0x0004C | Data_Loq | R | Data lower half [bits 31:0] |
| 5 | 0x00050 | Data_Hi | R | Data upper half [bits 63:32] |
CSR Register (0x00000)
The first 8 bits auto-clear after a few clocks, bits 8, 9 indicate databuffer empty/full the other bits are currently unused and retain whatever is written to them
| Bit | Name | Access | description |
|---|---|---|---|
| 0 | Reset | W | autocleared to zero |
| 1-7 | unused | W | autocleared to zero |
| 8 | Empty | R | Data Buffer Empty |
| 9 | Full | R | Data Buffer Full |
| 10-31 | unused | R/W | unused |
reset bit: Writing 1 here resets the module to powerup state.
Operation
inputs 1 to 6 are used
inputs 1-4 are tdc inputs input 6 is tdc-gate input 5 is "new-cycle"
at start of run, the module should be reset
cycles are counted, timestamps reset on first tdc-gate of each cycle tdc inputs are only counted during tdc-gates (tdc-gates are not counted)
data words are written to buffer on each: cycle, tdc-gate-rise, tdc-gate-fall, tdc-input[if gate high]
data words are all 64bits with same format (from msb to lsb) ...
[6bit id, 10bit cycle-count, 48bit timestamp]
6 id bits are cycle,gaterise,ch1-4 [tdc-gate-fall words will have no id bits set]
as the module is set up currently, if inputs/cycle/tdc-gate occur simultaneously, only one data word will be produced, but it will have all relevant id bits set.