ALPHA

ALPHA AD-5 at CERN

Links

• ALPHA-2 MIDAS: https://alphacpc05.cern.ch
• ALPHA-g MIDAS: https://alphacpc05.cern.ch/agdaq/
• nodeinfo: https://alphacpc05.cern.ch/gonodeinfo/gonodereport.html
• zfs quota report: https://alphacpc05.cern.ch/zfsquotareport/zfsquota.html
• ganglia: https://alphacpc05.cern.ch/ganglia/
• elog: https://alphacpc05.cern.ch/elog/alpha/
• AgWiki: https://daq00.triumf.ca/AgWiki/
• old alpha-g elog: https://daq00.triumf.ca/elog-alphag-old/alphag/

ALPHA-2

Rebuild midas:

• cd ~/packages/midas; make clean; make cmake -j
• restart mlogger, mserver, mhttpd, lazylogger

Rebuild frontends:

• fevme: ssh alphavme04, cd online/vme, make clean, make, restart fevme
• SVD bias P.S. fecaenr14xxet.exe: cd packages/frontends/fecaen14xxet, make clean, make, restart fecaen_hvps01
• felabview: no update
• super_felabiew, feXSequencer: cd online/src, make clean, make, not sure how to install to ../bin and restart.
• feGEM: cd online/feGEM, make clean, make,

ALPHA-2 SVD

• VME-ALPHA-TTC
• VME-NIMIO32#ALPHA_trigger_control
• VME-TTC board schematics File:ALPHA TTC 20091105.pdf
• VME-TTC firmware schematics, main FPGA File:ALPHA TTC 20091105.pdf
• VME-TTC firmware schematics, trigger FPGA File:ALPHA TTC Trigger2.pdf
• VME-TTC firmware schematics, TA singal conditioner File:ALPHA TTC SignalConditioner.pdf
• VME-TTC manual https://bitbucket.org/expalpha/ttc_firmware/src/master/alphaTTC.txt

clock distribution

• IO32 internal osc (IO32 has no external trigger input) -> 2x LEMO NIM output 20 MHz -> TTC1, TTC2
• -> TTC1
• -> VETO_IN LEMO1A
• -> FPGA pin FP_Ext_TrigInput1 -> 20 MHz PLL -> PLL1_20MHz -> mux -> mux_clk -> pll_20MHz
• -> FPGA pin PLL_20MHz -> FP_ADC_CLK -> LVDS_ADC_CLK -> ADC clock LEMO5A
• -> VF48 20 MHz clock daisy chain, 4 VF48 modules
• -> VF48 clock input -> PLL 20MHz-to-60MHz -> 60 MHz ADC sampling clock

same thing repeats for the 2nd TTC

• -> TTC2

TTC functions

Downloading VA1TA configurations (BOOT control)

VA1TA configuration is done via J2 daisychain cable to the FRCs:

• LVDS_BOOT_CLKIN and LVDS_BOOT_REGIN - shift serial data to VA1TA ASIC shift register
• LVDS_BOOT_REGOUT - serial data shifted out from VA1TA ASIC shift register
• LVDS_BOOT_LOAD - load serial data from VA1TA shift register into internal registers
• LVDS_BOOT_READ - read VA1TA internal registers to the serial data shift register
• CMOS_FEC_ADD[0..5] - select which FRC port is connected to the LVDS_BOOT_xxx signals

Loading VA1TA configuration is done by bit-banging an FPGA register that maps VME data bits to LVDS_BOOT_xxx signals (see alphaTTC.txt).

Typical write sequence:

• set FRC port address via CMOS_FEC_ADD (4 bits select the FRC, 2 bits select one of four FRC ports)
• toggle CLKIN and REGIN to shift 4x??? bits of VA1TA configuration data (all four VA1TA ASICs are loaded at the same time)
• (not useful to observe REGOUT, it is shifting out whatever random data happens to be in the VA1TA shift register)
• toggle LOAD to transfer configuration data from shift register to internal registers

Typical read sequence:

• set FRC port address via CMOS_FEC_ADD
• toggle READ to transfer data from internal registers to the shift register
• toggle CLKIN, record value of REGOUT from each clock

Typical load cycle will do 1 write and 1 read, compare the shifted-out bits against shifted-in bits, flag an error if there is a mismatch.

To operate the VA1TA, CLKIN, REGIN and LOAD signals must work.

If READ and REGOUT signals do not work or are unreliable, one can confirm correctly loaded configuration by doing a threshold scan or some other indirect method (i.e. change VA gain and observe change of calibration pulse).

Control of calibration pulser DACs

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Sequencing the readout of the VA1TA analog multiplexor and VF48 trigger

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Processing VA1TA TA outputs and generation of NIM trigger outputs

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ALPHA-3 SVD Upgrade

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