POL: Data format and analysis

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Introduction

This document describes the MIDAS format data banks that are output by the POL frontend pol_fevme.exe. This frontend controls the hardware for the experiment, and programs the contents of the data banks. The analyzer reads the data from the data banks.

MIDAS Data

The data are sent out as MIDAS events which contain various banks as shown in Table 1 below:

Table 1 : POL data banks
Equipment name INFO HISTO VME
Event ID 3 5 11*
Sent out at end of SuperCycle at end of SuperCycle at end of SuperCycle
Banknames DBUG CYCL ** SUMS HISI HIS0 HIS1 HIS2 HIS3 HSUM CYCL ** MCS0
Contents Debug and other useful information Histograms and sums of the time-bins over each supercycle, ADC readout etc. Raw cycle scaler data (debugging)
Data sent to ODB YES NO NO
NOTES
  • For definitions of Cycle, Supercycle, Scan etc. see Nomenclature
  • In this version, threshold checks are not supported.
  • ** The CYCL banks in Event ID 3 and 5 are no longer identical
  • * Event 11 is for debugging and is normally disabled.
  • Event 11 can be enabled by setting the edit-on-start parameter send raw data bank to TRUE. This parameter points to the ODB key /Equipment/POL_ACQ/Settings/input/send raw data bank.

The examples of data banks in this document have been generated by the utility mdump e.g. 

mdump -l 20      (dumps the data from the running experiment)
or
mdump -x /isdaq/data1/pol/data/2014_vmic/run00100.mid | more      (dumps the data from a saved data file)



Event ID 3 INFO Event Banks sent out once per cycle

The INFO event contains the following MIDAS Banks: DBUG CYCL SUMS

Bank Contents
Readout of debug and other useful information (e.g. counters, DAC set/readback values/histo sums).
NOTE

The INFO event (event ID 3) is sent to the ODB for display when running, and is also sent out to the data buffer.


DBUG bank

The DBUG bank is for debugging and need not concern the user too much. It may be disabled in later versions.

The contents of the DBUG bank are shown in Table 2 below.

Table 2 : DBUG: Debug bank Type: FLOAT
Word Contents Explanation
1 Data to read Number of 32-bit words of data still buffered in the SIS3820
2 LNE per cycle Number of values in the SIS3820 buffer for one cycle (i.e. number of LNE)
3 LNE per SC LNE count from SIS3802 Acquisition Count Register i.e. Number of LNE pulses received from PPG
4 LNE preset Number of LNE set in SIS3820 Preset register. Once this number of LNE are received, SC is complete.
5 Num bins Number of bins sent out.
6 Data bytes 2 for 16-bit data. [1 (8-bit data) and 2 (32-bit data) are not yet supported/tested in SC version.]
7 Num Chan Number of input channels of the SIS3820 enabled. Always 4 for Pol experiment.
8 Discard 1st Bin True if first bin is discarded each cycle
9 Discard 1st Cycle True if first cycle is discarded each SC
KEY to Table 2
  • LNE Load Next Event On receipt of LNE signal from PPG, SIS3820 moves to the next bin
  • SC SuperCycle. The user selects how many PPG cycles taken at the same DAC value make up the SuperCycle
Note
  • Counters in this bank include
    • one extra cycle if Discard first cycle is set or
    • one extra time bin if Discard first time bin is set.
  • Discard first cycle and Discard first time bin are parameters available on the mhttpd Pol expt PPG CYCLE custom web page.


CYCL Bank (EVID 3)

The contents of the CYCL bank are shown in Table 3 below.

Table 3 : CYCL: Cycle counter bank Type: FLOAT EventId: 3
Word Contents Explanation
1 Scan type code Always 1 - indicates a DAC scan
2 Cycle counter Increments, counting cycles. Cycle Counter will count by N
3 SuperCycle counter Increments, counting supercycles. If there are N cycles in a supercycle, the Cycle Counter will count N times as fast as the Supercycle Counter.
4 Cycles/SC counter Counts cycles within each supercycle. If there are N cycles per supercycle, this counter should always show N.
5 Sweep counter Increments, counting the number of complete DAC sweeps (or scans).
6 Skipped-cycle counter Counts number of cycles skipped. If first cycle is discarded each SC, this number will be same as SuperCycle Counter.
7 Num cycles histogrammed Should be the same as Cycle counter.
8 DAC Increment counter Counts DAC increments within a sweep. If the number of DAC increments selected per sweep is M, counter will vary from 0 to M.
9 DAC Set Value DAC Set value in Volts (DAC Output 0)
10 DAC Readback DAC Readback value in Volts (i.e. direct readback via Input 0 of Galil ADC connected to DAC Output 0 )
11 ADC0 Average Average value of ADC Input 0 ( DAC Readback in Volts)
12 ADC1 Average Average value of ADC Input 1 (Volts)
13 ADC2 Average Average value of ADC Input 2 (Volts)
14 ADC3 Average Average value of ADC Input 3 (Volts)
15 spare not used
Notes
  • Counters in this bank include
    • one extra cycle if Discard first cycle is set or
    • one extra time bin if Discard first time bin is set.
  • Discard first cycle and Discard first time bin are parameters available on the mhttpd Pol expt PPG CYCLE custom web page.
  • "N" in the table below is the calculated number of cycles per supercycle, i.e.
    • N = number of requested cycles per supercycle if Discard first cycle is false.
    • N = (number of requested cycles + 1) if Discard first cycle is true.
  • "DAC Readback" reads back the DAC Set Value from ADC Input 0. There is a second user-defined readback on ADC Input 1 which can be found in bank #HISI.
  • Contents of this CYCL bank (Event 3) is now different from the CYCL bank in Event 5


SUMS Bank

The SUMS bank is a copy of #HSUM bank.


Example of Event ID 3

Since Event ID 3 is sent to the ODB, you can see the contents of the INFO Event by clicking on "Info" on the MIDAS status page, e.g. Figure 1

image

In this case, the input parameters were:

  • 100 bins per cycle
  • 100 cycles per supercycle
  • Discard first cycle per SC and first bin per cycle
  • DAC Sweep 0-0.1V 10 increments of 0.01V step

This data can also be found in the data buffer, e.g.: 

------------------------- Event# 2 ------------------------
Evid:0003- Mask:0008- Serial:4- Time:0x53dc4735- Dsize:180/0xb4
#banks:3 - Bank list:-DBUGCYCLSUMS-

Bank:DBUG Length: 36(I*1)/9(I*4)/9(Type) Type:Real*4 (FMT machine dependent)
   1-> 0.000e+00 1.010e+02 2.030e+04 2.030e+04 1.010e+02 2.000e+00 4.000e+00 1.000e+00
   9-> 1.000e+00

Bank:CYCL Length: 60(I*1)/15(I*4)/15(Type) Type:Real*4 (FMT machine dependent)
   1-> 1.000e+00 1.000e+03 5.000e+00 2.000e+02 1.000e+00 5.000e+00 1.000e+03 4.000e+00
   9-> 4.000e-02 4.300e-02 4.150e-02 3.913e-01 0.000e+00 9.263e+00 0.000e+00

Bank:SUMS Length: 32(I*1)/8(I*4)/4(Type) Type:double*8
   1->     0.00000e+00        9.99990e+04        0.00000e+00        0.00000e+00

Event ID 5: Histograms sent out once per Supercycle

The INFO event contains the following MIDAS Banks: HISI HIS0 HIS1 HIS2 HIS3 HSUM CYCL Bank Names : HISI HIS0 HIS1 HIS2 HIS3 HSUM CYCL Bank Contents: Example

HISI Bank

Table 4 : HISI Histo counter bank Type: FLOAT EventId: 5
Word Contents Explanation
1 Cycle counter Increments, counting cycles. This will count by N where N is the requested number of cycles per supercycle.
2 SuperCycle counter Increments, counting supercycles.
3 Set Value DAC Set Value in Volts for this event
4 Set Value Readback Users' Readback (ADC Channel 1 Average value - see also CYCL bank ). See DAC Set value Readback **.
5 DAC Increment counter Counts from 0 to Num Dac Increments
6 NumCycles Summed Number of cycles summed in these histograms. Should be equal to the number of cycles per supercycle
7 Scaler buffer 1st word DAC Set Value in Volts for this event stored in Scaler data buffer as the first word for checking.

Should always be equal to word 3 (but may have rounding errors due to conversion to integer mV and back).


Notes:

  • Cycle counter contains the user-requested number of cycles, so if parameter Discard first cycle is set, the first cycle will already have been discarded. Compare with #CYCL bank, where the actual number of cycles is recorded.
  • ** The DAC is used to drive a high voltage power supply. The Set Value Readback is read from ADC Channel 1, which is connected by the users to their own voltage readback. The actual readback of the DAC itself is found in #CYCL bank, read from ADC Channel 0.


HIS0,HIS1,HIS2,HIS3 Banks

The banks HIS0...HIS3 are the histogram banks for Scaler Input channels 0-3. These contain the cumulative sums of each time bin summed over the number of cycles/supercycle at a particular DAC increment value. Summing all the bins together for each channel should give the same value as in the HSUM bank. The histograms are cleared after each supercycle.

Table 5 : HIS0..3 Histogram Sums for Scaler Inputs 0..3 Type: Unsigned Integer EventId: 5
Word Contents
1 Time bin 0 summed for one SuperCycle
2 Time bin 1 summed for one SuperCycle
... ............
... ............
N Last time bin summed for one SuperCycle

HSUM Bank

The HSUM bank contains the sums of all the time-bins (output as histograms in Event 5) for each Scaler Channel. The sums are cleared after each SuperCycle.


Table 6 : HSUM Histogram Sums for Scaler Inputs 0..3 Type: FLOAT EventId: 5
Word Contents
1 Sum of all the time bins of Scaler input 0 for one SuperCycle
2 Sum of all the time bins of Scaler input 1 for one SuperCycle
3 Sum of all the time bins of Scaler input 2 for one SuperCycle
4 Sum of all the time bins of Scaler input 3 for one SuperCycle


CYCL Bank (EVID 5)

Note that this bank (EVID 5) is now DIFFERENT from the CYCL Bank in Event ID 3. Words 1-10 inclusive are identical in both cases, but this bank also contains the readback of the first 4 ADC Inputs (two of which were formerly in ADCR bank, now removed).

Table 7 : CYCL Cycle counter/ADC Readback bank Type: FLOAT EventId: 5
Word Contents Explanation
1 Scan type code Always 1 - indicates a DAC scan
2 Cycle counter Increments, counting cycles. Cycle Counter will count by N
3 SuperCycle counter Increments, counting supercycles. If there are N cycles in a supercycle, the Cycle Counter will count N times as fast as the Supercycle Counter.
4 Cycles/SC counter Counts cycles within each supercycle. If there are N cycles per supercycle, this counter should always show N.
5 Sweep counter Increments, counting the number of complete DAC sweeps (or scans).
6 Skipped-cycle counter Counts number of cycles skipped. If first cycle is discarded each SC, this number will be same as SuperCycle Counter.
7 Num cycles histogrammed Should be the same as Cycle counter.
8 DAC Increment counter Counts DAC increments within a sweep. If the number of DAC increments selected per sweep is M, counter will vary from 0 to M.
9 DAC Set Value DAC Set value in Volts (DAC Output 0)
10 ADC0 Galil ADC0 Input (connected to DAC Output 0 ) i.e. DAC Readback in Volts
11 ADC1 Galil ADC1 Input (Volts)
12 ADC2 Galil ADC2 Input (Volts)
13 ADC3 Galil ADC3 Input (Volts)
14 ADC0 Average Average value of ADC Input 0 (DAC Readback in Volts)
15 ADC1 Average Average value of ADC Input 1 (Volts)
16 ADC2 Average Average value of ADC Input 2 (Volts)
17 ADC3 Average Average value of ADC Input 3(Volts)


NOTES

ADC Channel 1 (user-defined DAC readback) is also output in the #HISI Bank. Since the HISI bank is assembled at a slightly different time to the CYCL bank, the values in the two banks may differ because of jitter on the ADC readback. The average values are generated to average out this jitter.



Example of EventID 5

In this example, only Scaler Input 1 has been connected to a clock, so only the HIS1 bank has counts. 

------------------------ Event# 7 ------------------------
Evid:0005- Mask:0020- Serial:1- Time:0x5339eea8- Dsize:352/0x160
#banks:8 - Bank list:-CYCLHISIHIS0HIS1HIS2HIS3HSUM-

Bank:CYCL Length: 68(I*1)/17(I*4)/17(Type) Type:Real*4 (FMT machine dependent)
   1-> 1.000e+00 1.000e+03 5.000e+00 2.000e+02 1.000e+00 5.000e+00 1.000e+03 4.000e+00
   9-> 4.000e-02 4.150e-02 3.943e-01 9.000e-04 9.263e+00 4.150e-02 3.913e-01 0.000e+00
  17-> 9.263e+00

Bank:HISI Length: 28(I*1)/7(I*4)/7(Type) Type:Real*4 (FMT machine dependent)
   1-> 1.000e+03 5.000e+00 4.000e-02 3.958e-01 4.000e+00 1.000e+00 4.000e-02

Bank:HIS0 Length: 400(I*1)/100(I*4)/100(Type) Type:Unsigned Integer*4
   1-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
   9-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  17-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  25-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  33-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  41-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  49-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  57-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  65-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  73-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  81-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  89-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  97-> 0x00000000 0x00000000 0x00000000 0x00000000

Bank:HIS1 Length: 400(I*1)/100(I*4)/100(Type) Type:Unsigned Integer*4
   1-> 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8
   9-> 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8
  17-> 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8
  25-> 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8
  33-> 0x000003e7 0x000003e9 0x000003e7 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8
  41-> 0x000003e8 0x000003e9 0x000003e7 0x000003e8 0x000003e9 0x000003e8 0x000003e7 0x000003e9
  49-> 0x000003e8 0x000003e8 0x000003e7 0x000003e9 0x000003e8 0x000003e8 0x000003e8 0x000003e8
  57-> 0x000003e8 0x000003e8 0x000003e9 0x000003e7 0x000003e9 0x000003e8 0x000003e8 0x000003e7
  65-> 0x000003e9 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e7
  73-> 0x000003e8 0x000003e8 0x000003e9 0x000003e8 0x000003e7 0x000003e9 0x000003e7 0x000003e8
  81-> 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e7
  89-> 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8 0x000003e8
  97-> 0x000003e8 0x000003e8 0x000003e8 0x000003e8

Bank:HIS2 Length: 400(I*1)/100(I*4)/100(Type) Type:Unsigned Integer*4
   1-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
   9-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  17-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  25-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  33-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  41-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  49-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  57-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  65-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  73-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  81-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  89-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  97-> 0x00000000 0x00000000 0x00000000 0x00000000

Bank:HIS3 Length: 400(I*1)/100(I*4)/100(Type) Type:Unsigned Integer*4
   1-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
   9-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  17-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  25-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  33-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  41-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  49-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  57-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  65-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  73-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  81-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  89-> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  97-> 0x00000000 0x00000000 0x00000000 0x00000000

Bank:HSUM Length: 32(I*1)/8(I*4)/4(Type) Type:double*8
   1->     0.00000e+00        9.99990e+04        0.00000e+00        0.00000e+00



Event ID 11: Raw data sent out each cycle

Event ID 11 contains the bank MCS0.

MSC0 Bank (EVID 11)

Bank Contents: Example

Presently the MCS0 Bank IS sent out for debugging purposes. It may later be disabled by default, in which case it can be enabled by setting the ODB Key 

     /Equipment/POL_ACQ/Settings/input/send debug banks/send raw data bank to "y".

The MCS0Bank is always in 32-bit format. However, the data packing depends on the SIS3820 data format selected. This can be 8-bit, 16-bit**, 32-bit (see SIS3820 manual). With 4 channels enabled, the MCS0 bank format is shown in Table 8 for the three supported cases of SIS3820 data format.

Note
Only the 16-bit format is implemented/tested for the SuperCycle mode POL is currently using.
Table 8 : MCS0 Raw Data bank Type: Unsigned Integer (32-bit) EventId: 11
Table 8a : 8-BIT FORMAT DATA Table 8b : 16-BIT FORMAT DATA Table 8c : 32-BIT FORMAT DATA
Word Byte Time Bin Input
1 0 0 0
1 0 1
2 0 2
3 0 3
2 0 1 0
1 1 1
2 1 2
3 1 3
......... .......... ....... .........
Nbins 0 Nbins 0
1 Nbins 1
2 Nbins 2
3 Nbins 3





Word Byte Time Bin Input
1 0 0 0
1
2 0 2
3
2 0 0 2
1
2 0 3
3
......... .......... ....... .........
2*Nbins-1 0 Nbins 0
1
2 Nbins 2
3
2*Nbins 0 Nbins 2
1
2 Nbins 3
3
Word Byte Time Bin Input
1 0-3 Time bin 0 0
2 0-3 Time bin 0 1
3 0-3 Time bin 0 2
4 0-3 Time bin 0 3
5 0-3 Time bin 1 0
6 0-3 Time bin 1 1
7 0-3 Time bin 1 2
8 0-3 Time bin 1 3
.... .... .... ....
4*Nbins-3 0-3 Last Time bin 0
4*Nbins-2 0-3 Last Time bin 1
4*Nbins-1 0-3 Last Time bin 2
4*Nbins 0-3 Last Time bin 3





Notes
  • The data are buffered in the SIS3820 scaler. The data are read out periodically into a data buffer.
  • At the end of a SuperCycle, the data buffer is decoded. The data from each cycle are summed to form the data for a SuperCycle. The histograms are sent out, the DAC incremented, and the next SuperCycle is started.


Examples of Event ID 11

The pol experiment uses the 16-bit SIS3820 data format. The following data in 16-bit SIS3820 format are for 4 inputs with 10 bins selected. Discard First Bin and Discard First Cycle are selected.

The first word of the MCS0 bin is always the DAC Voltage * 1000 i.e. the DAC Voltage in mV. This is to convert the DAC Voltage (type float) to integer for the (integer) data bank.

The Time Bin number for the first few data words has been added in yellow, and the data for

  • Input 0 is coloured blue
  • Input 1 is coloured green
  • Input 2 is coloured red
  • Input 3 is coloured purple


Input 3 is connected to a clock. The counts are constant during the cycle, but at the end of each cycle the counts increase as the scaler remains on the same bin for a longer period (waiting for next TOF). This longer time is discarded when the first bin/cycle is discarded.

Programming Note

Currently the scaler is ENABLEd rather than ARMed. In the future, ENABLE may be changed to ARM, in which case an extra bin must be added and the first bin need no longer be discarded.

Table 9 : Example of MCS0 data in 16-bit format
------------------------ Event# 5 ------------------------

Evid:000b- Mask:0800- Serial:2- Time:0x5339eea7- Dsize:556/0x22c #banks:1 - Bank list:-MCS0-

Bank:MCS0 Length: 536(I*1)/134(I*4)/134(Type) Type:Unsigned Integer*4
DAC(mv) 0 0 1 1 2 2 3 Time bin
1-> 0x000001f4 0x00000000 0x00570000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
3 4 4 5 5 6 6 7 First Cycle
9-> 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
7 8 8 9 9 10 0 Next Cycle
17-> 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
0 1 1 2 2 3 3 4
25-> 0x8a7c0000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
33-> 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
41-> 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x85470000 0x00000000
49-> 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
57-> 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
65-> 0x00050000 0x00000000 0x00050000 0x00000000 0x84ca0000 0x00000000 0x00050000 0x00000000
73-> 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
81-> 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
89-> 0x00050000 0x00000000 0x84960000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
97-> 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
105-> 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
113-> 0x84770000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
121-> 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
129-> 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000


Event# 5 ------------------------

Evid:000b- Mask:0800- Serial:2- Time:0x5339eea7- Dsize:556/0x22c

  1. banks:1 - Bank list:-MCS0-

Bank:MCS0 Length: 536(I*1)/134(I*4)/134(Type) Type:Unsigned Integer*4 

       DAC(mv)            0                 0                1                 1             2               2               3           Time bin 
  1->  0x000001f4 0x00000000 0x00570000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
               3                4                 4                5                 5             6              6               7                   First Cycle
  9->  0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
               7                8                 8                9                 9            10             10             0                   Next Cycle
 17-> 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
               0                1                 1                2                 2              3              3              4          
 25-> 0x8a7c0000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
 33-> 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
 41-> 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x85470000 0x00000000
 49-> 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
 57-> 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
 65-> 0x00050000 0x00000000 0x00050000 0x00000000 0x84ca0000 0x00000000 0x00050000 0x00000000
 73-> 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
 81-> 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
 89-> 0x00050000 0x00000000 0x84960000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
 97-> 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
105-> 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
113-> 0x84770000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
121-> 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000
129-> 0x00050000 0x00000000 0x00050000 0x00000000 0x00050000 0x00000000


Updates

19Aug2019 document moved to wiki Original document: dasdevpc2:/home/suz/www/pol/vmicbanks.html Version 4 scaler read out at end of supercycle rather than each cycle. Galil Rio DAC incremented after histograms are sent Version 5 Galil Rio averaging program for 4 ADC channels is loaded (pgm and RIO loaded by Donald). Averages of ADC0-3 are added to CYCL banks which are now different in Events 3 and 5.

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