VME-PPG32: Difference between revisions

From DaqWiki
Jump to navigation Jump to search
Line 22: Line 22:
* 2 output serial DAC: AD5439YRUZ
* 2 output serial DAC: AD5439YRUZ


==== Firmware functions ====
TBW
=== Firmware revisions ===
To find out the current firmware revision, read VME register 0, i.e. run "test_VMENIMIO32_gef.exe --addr 0xN00000 --read 0".
To write Cyclone 1 FPGA firmware into the flash memory, use a JTAG programmer or a VME programmer:
"srunner_vme_gef.exe -program -64 ~/daq/VME-NIMIO32/VME-NIMIO32/VME-NIMIO32/VME-NIMIO32.pof 0xN00020", where "N" is the A24 VME base address.
To reboot the Cyclone 1 FPGA into the new firmware, run "test_VMENIMIO32_gef.exe --addr 0xN00000 --read 0 --write 1 2 --read 0 --sleep 1 --read 0", where "N" is the A24 VME base address. This requires firmware 0x01100810 or newer and the "fpga-reset" hardware modification.
Firmware for the main FPGA:
* firmware sources [[http://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-PPG32]]
* 0x4bcf5aef - [[http://ladd00.triumf.ca/viewcvs/daqsvn/trunk/VME-PPG32/VME-PPG32.pof?revision=73&view=co]]
Firmware for the VME address decoder (same as VME-NIMIO32):
* firmware sources [[http://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode]]
* board Rev0 [[http://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode/VME_Addr_decode.pof?revision=37&view=co]]
* board Rev1 [[http://ladd00.triumf.ca/viewvc/daqsvn/trunk/VME-NIMIO32/MAX3000A_Addr_decode/VME_Addr_decode.pof?revision=87&view=co]]
=== Manual ===


==== VME interface ====
==== VME interface ====


Firmware 0x01100810 implements VME A24/D32 access only. A24 addresses 0x00N0xxxx are decoded, where "N" is the A24 base address set by rotary switch SW3 "ADDRESS 20-23". Rotary switches SW1 and SW2 should be set to "0".
VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address.
 
VME registers are listed in the table below.
VME accessible registers are listed in the table below. VME address offsets are register numbers multiplied by 4, i.e. CSR register 1 is at address 0x00N00004. Flash programmer register 8 is at 0x00N00020 (use this address with srunner_vme flash programmer).


==== Registers ====
==== Registers ====
{| cellpadding="10" cellspacing="0" border="1"
{| cellpadding="10" cellspacing="0" border="1"
! Number || Name || Access || FwRev || Description
! Number || Address || Name || Access || Description
|-
|  0 || 0x00000 || Test || RW || Test Register
|-
|  1 || 0x00004 || CSR || RW || Control/Status Register
|-
|  2 || 0x00008 || Addr || RW || Program Address Register
|-
|  3 || 0x0000C || Inst_Lo || RW || Instruction Register Part 1/4
|-
|  4 || 0x00010 || Inst_Med || RW || Instruction Register Part 2/4
|-
|  5 || 0x00014 || Inst_Hi || RW || Instruction Register Part 3/4
|-
| 6 || 0x00018 || Inst_Top || RW || Instruction Register Part 4/4
|-
|-
| 0 || FwRev || RO || || Firmware revision
| 7 || 0x0001C || Version || R || Firmware Version Register
|-
|-
| 1 || CSR || RW || TBW || TBW
| 8 || 0x00020 || Flash || RW || Serial Flash Control Register
|-
|  9 || 0x00024 || Serial || R || Serial Number Register
|-
| 10 || 0x00028 || Hardware || R || hardware Identification Register
|}
|}
==== SOFTWARE ====
===== test_VMENIMIO32.exe =====
Command line switches:
* --addr 0x00N00000 - module A24 base address, N is the setting of rotary switch SW3 "ADDRESS 20-23"
* --read MMM - read register MMM, i.e. "--read 0" reads the firmware revision
* --write MMM VVV - write value VVV into register MMM, i.e. "--write 1 0" writes 0 to the CSR
* --readscalers - read the 32 input scalers, print scaler value, counting rate using the 20 MHz timestamp clock and counting rate using the computer clock.
* --pulsenim - pulse all NIM outputs
* --sleep SSS - sleep SSS seconds, i.e. "--sleep 1" sleeps for 1 second.
* --readtsc - example reading TSC register
* --readtsc4 - example reading and decoding the TSC4 data, programming TSC4 routing
=== Board modifications ===
==== Rev0 modifications ====
* multiple mistakes on PCB
K.O.

Revision as of 22:49, 8 November 2010

VME-PPG32 - pulse pattern generator VME FPGA board

References

  • [1] VME-PPG32 (REA 198) project page on edev.triumf.ca
  • [2] Rev0 board schematics
  • [3] Svn repository for initial test firmware
  • [4] Current PPG firmware Source/binary

General characteristics

Available hardware

  • Altera cyclone 3 FPGA: EP3C40Q240C8
  • Serial flash for FPGA configuration: Altera EPCS16
  • VME interface: VME-D[31..0] bidirectional, VME-A[23..0] input only, DTACK output, no BERR, no RETRY/RESP. VME-A[31..20] input only connected only to address decoder FPGA (Altera MAX-something CPLD). This permits all single-word transfer modes, 32-bit DMA (BLT32) and 2eVME DMA (only drives D-lines, but still faster than BLT32). 64-bit DMA (MBLT64) and 2eSST are impossible.
  • 32 NIM outputs
  • 4 NIM inputs
  • 32 "NIM output" LEDs
  • 4 "NIM input" LEDs
  • 1 "VME access" LED
  • 2 output serial DAC: AD5439YRUZ


VME interface

VME A32/D32 access only. Rotary switches SW1, SW2 and SW3 set the upper 12 bits of the address. VME registers are listed in the table below.

Registers

Number Address Name Access Description
0 0x00000 Test RW Test Register
1 0x00004 CSR RW Control/Status Register
2 0x00008 Addr RW Program Address Register
3 0x0000C Inst_Lo RW Instruction Register Part 1/4
4 0x00010 Inst_Med RW Instruction Register Part 2/4
5 0x00014 Inst_Hi RW Instruction Register Part 3/4
6 0x00018 Inst_Top RW Instruction Register Part 4/4
7 0x0001C Version R Firmware Version Register
8 0x00020 Flash RW Serial Flash Control Register
9 0x00024 Serial R Serial Number Register
10 0x00028 Hardware R hardware Identification Register
Retrieved from "https://daq00.triumf.ca/DaqWiki/index.php?title=VME-PPG32&oldid=4075"