/home/daqweb/fgddaq/c8051/Devices/ExtEEPROM.h File Reference


Defines

#define CLEAR_EEPROM   0x00
#define WRITE_EEPROM   0x01
#define EEP_WRENcmd   0x06
#define EEP_WRDIcmd   0x04
#define EEP_RDSRcmd   0x05
#define EEP_WRSRcmd   0x01
#define EEP_READcmd   0x03
#define EEP_WRITEcmd   0x02
#define WP_START_ADDR   0x0600
#define WP_FINAL_ADDR   0x07FF
#define EEP_MAX_BYTE   32
#define EEP_PROTECTION   0x84
#define EEP_ERROR   0
#define EEP_SUCCESS   1
#define EEP_READY   1
#define EEP_PROTECTED   2
#define EEP_BUSY   3
#define EEP_delay   25
#define W_INTERNAL   0x71

Functions

void ExtEEPROM_Init (void)
unsigned char ExtEEPROM_Read (unsigned int ReadPage, unsigned char xdata *destination, unsigned int page_size)
unsigned char ExtEEPROM_Write_Clear (unsigned int WritePage, unsigned char xdata **source, unsigned int page_size, unsigned char WC_flag, unsigned char *flag)
unsigned char ExtEEPROM_WriteEnable (void)
unsigned char ExtEEPROM_WriteStatusReg (unsigned char status)
unsigned char ExtEEPROM_Status (void)
unsigned char ExtEEPROM_Wait (void)

Variables

sbit RAM_CSn = RAM_CHIP_SELECT
sbit RAM_HLDn = RAM_HOLD_DOWN
sbit RAM_WPn = RAM_WRITE_PROTECT

Define Documentation

#define CLEAR_EEPROM   0x00

#define EEP_BUSY   3

#define EEP_delay   25

#define EEP_ERROR   0

#define EEP_MAX_BYTE   32

#define EEP_PROTECTED   2

#define EEP_PROTECTION   0x84

#define EEP_RDSRcmd   0x05

#define EEP_READcmd   0x03

#define EEP_READY   1

#define EEP_SUCCESS   1

#define EEP_WRDIcmd   0x04

#define EEP_WRENcmd   0x06

#define EEP_WRITEcmd   0x02

#define EEP_WRSRcmd   0x01

#define W_INTERNAL   0x71

#define WP_FINAL_ADDR   0x07FF

#define WP_START_ADDR   0x0600

#define WRITE_EEPROM   0x01

Function Documentation

void ExtEEPROM_Init ( void   ) 

unsigned char ExtEEPROM_Read ( unsigned int  ReadPage,
unsigned char xdata *  destination,
unsigned int  page_size 
)

unsigned char ExtEEPROM_Status ( void   )  

00184 {
00185   unsigned char status;
00186 
00187   RAM_CSn = 0;
00188   SPI_WriteByte(AT2516_RDSR);
00189   status=SPI_ReadByteRising();
00190   delay_us(25);
00191   RAM_CSn = 1;
00192   delay_us(25);
00193 
00194   return status;
00195 }

unsigned char ExtEEPROM_Wait ( void   )  

00198                           {
00199   unsigned char status;
00200   do {
00201     status = ExtEEPROM_Status();
00202   } while((status & 0x71) != 0);
00203 }

unsigned char ExtEEPROM_Write_Clear ( unsigned int  WritePage,
unsigned char xdata **  source,
unsigned int  page_size,
unsigned char  WC_flag,
unsigned char *  flag 
)

unsigned char ExtEEPROM_WriteEnable ( void   )  

00159 {
00160   //Enabling the write operation
00161   RAM_CSn = 0;
00162   delay_us(10);
00163   SPI_WriteByte(AT2516_WREN);
00164   delay_us(25);
00165   RAM_CSn = 1;
00166   delay_us(25);
00167   ExtEEPROM_Wait();
00168 }

unsigned char ExtEEPROM_WriteStatusReg ( unsigned char  status  )  

00171                                                     {
00172   ExtEEPROM_WriteEnable();
00173   RAM_CSn = 0;
00174   SPI_WriteByte(AT2516_WRSR);
00175   SPI_WriteByte(status);
00176   delay_us(25);
00177   RAM_CSn = 1;
00178   delay_us(25);
00179   ExtEEPROM_Wait();
00180 }

Variable Documentation

sbit RAM_CSn = RAM_CHIP_SELECT

sbit RAM_HLDn = RAM_HOLD_DOWN

sbit RAM_WPn = RAM_WRITE_PROTECT

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