POL: Data format and analysis

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Introduction

This document describes the MIDAS format data banks that are output by the POL frontend fepol_32bit.exe. This frontend controls the hardware for the experiment, and programs the contents of the data banks. The analyzer reads the data from the data banks.

MIDAS Data

The data are sent out as MIDAS events which contain various banks: HISI HIS0 HIS1 HIS2 HIS3 HSUM CYCL. Some of these banks contain duplicated information (e.g. HISI vs CYCL), but they are all kept for backwards compatibility.

HISI Bank

Table 4 : HISI Histo counter bank Type: FLOAT EventId: 5

Word	Contents	Explanation
1	Cycle counter	Increments, counting cycles. This will count by N where N is the requested number of cycles per supercycle.
2	SuperCycle counter	Increments, counting supercycles.
3	Set Value	DAC Set Value in Volts for this event
4	Set Value Readback	Users' Readback (ADC Channel 1 Average value - see also CYCL bank ). See DAC Set value Readback **.
5	DAC Increment counter	Counts from 0 to Num Dac Increments
6	NumCycles Summed	Number of iterations summed in these histograms.
7	Scaler buffer 1st word	DAC Set Value in Volts for this event stored in Scaler data buffer as the first word for checking. Should always be equal to word 3 (but may have rounding errors due to conversion to integer mV and back).

Notes:

• Cycle counter contains the user-requested number of cycles, so if parameter Discard first cycle is set, the first cycle will already have been discarded. Compare with #CYCL bank, where the actual number of cycles is recorded.

• ** The DAC is used to drive a high voltage power supply. The Set Value Readback is read from ADC Channel 1, which is connected by the users to their own voltage readback. The actual readback of the DAC itself is found in #CYCL bank, read from ADC Channel 0.

HIS0,HIS1,HIS2,HIS3 Banks

The banks HIS0...HIS3 are the histogram banks for Scaler Input channels 0-3. These contain the cumulative sums of each time bin summed over the number of cycles/supercycle at a particular DAC increment value. Summing all the bins together for each channel should give the same value as in the HSUM bank. The histograms are cleared after each supercycle.

Table 5 : HIS0..3 Histogram Sums for Scaler Inputs 0..3 Type: Unsigned Integer EventId: 5

Word	Contents
1	Time bin 0 summed for one SuperCycle
2	Time bin 1 summed for one SuperCycle
...	............
...	............
N	Last time bin summed for one SuperCycle

HSUM Bank

The HSUM bank contains the sums of all the time-bins (output as histograms in Event 5) for each Scaler Channel. The sums are cleared after each SuperCycle.

Table 6 : HSUM Histogram Sums for Scaler Inputs 0..3 Type: FLOAT EventId: 5

Word	Contents
1	Sum of all the time bins of Scaler input 0 for one SuperCycle
2	Sum of all the time bins of Scaler input 1 for one SuperCycle
3	Sum of all the time bins of Scaler input 2 for one SuperCycle
4	Sum of all the time bins of Scaler input 3 for one SuperCycle

CYCL bank

Table 7 : CYCL Cycle counter/ADC Readback bank Type: FLOAT EventId: 5

Word	Contents	Explanation
1	Scan type code	Always 1 - indicates a DAC scan
2	Iteration counter	Increments, counting PPG iterations.
3	Cycle counter	Increments, counting cycles. If there are N iterations in a cycle, the Cycle Counter will count N times as fast as the Iteration Counter.
4	Iterations/Cycle counter	Counts PPG iterations within each cycle. If there are N iterations per cycle, this counter should always show N.
5	Sweep counter	Increments, counting the number of complete DAC sweeps (or scans).
6	Skipped-iteration counter	Counts number of iterations skipped. If first iteration is discarded each cycle, this number will be same as Cycle Counter.
7	Num iterations histogrammed	Should be the same as Iteration counter.
8	DAC Increment counter	Counts DAC increments within a sweep. If the number of DAC increments selected per sweep is M, counter will vary from 0 to M.
9	DAC Set Value	DAC Set value in Volts (DAC Output 0)
10	ADC0	Galil ADC0 Input (connected to DAC Output 0 ) i.e. DAC Readback in Volts
11	ADC1	Galil ADC1 Input (Volts)
12	ADC2	Galil ADC2 Input (Volts)
13	ADC3	Galil ADC3 Input (Volts)
14	ADC0 Average	Average value of ADC Input 0 (DAC Readback in Volts)
15	ADC1 Average	Average value of ADC Input 1 (Volts)
16	ADC2 Average	Average value of ADC Input 2 (Volts)
17	ADC3 Average	Average value of ADC Input 3(Volts)

NOTES

ADC Channel 1 (user-defined DAC readback) is also output in the #HISI Bank. Since the HISI bank is assembled at a slightly different time to the CYCL bank, the values in the two banks may differ because of jitter on the ADC readback. The average values are generated to average out this jitter.