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13 Feb 2020, Marius Koeppel, Forum, Writting Midas Events via FPGAs
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13 Feb 2020, Stefan Ritt, Forum, Writting Midas Events via FPGAs
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14 Feb 2020, Konrad Briggl, Forum, Writting Midas Events via FPGAs
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14 Feb 2020, Stefan Ritt, Forum, Writting Midas Events via FPGAs
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20 Feb 2020, Konstantin Olchanski, Forum, Writting Midas Events via FPGAs
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20 Feb 2020, Marius Koeppel, Forum, Writting Midas Events via FPGAs
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20 Feb 2020, Stefan Ritt, Forum, Writting Midas Events via FPGAs
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21 Feb 2020, Konstantin Olchanski, Forum, Writting Midas Events via FPGAs
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21 Feb 2020, Stefan Ritt, Forum, Writting Midas Events via FPGAs
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21 Feb 2020, Konstantin Olchanski, Forum, Writting Midas Events via FPGAs
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> > We also agree and found the problem now.
>
> Good. what was wrong?
>
> > - Own DMA engine since we are doing burst writing DMA with PCIe 3.0.
> > - Own device driver
>
> Scary stuff.
>
> > - no interrupts
>
> Right. Best I can tell, interrupts no longer useful in Linux - interrupt handler cannot do any real work, has to hand off to a kernel thread, resulting
> in so much latency and overhead that one might as well poll for the data... And for DMA data transfers, the data rate is well known,
> so easy to predict how long the DMA will run for and sleep for that amount of time instead of waiting for an interrupt.
>
> K.O.
So the problem was that we assumed that the bank (with the header) needs to be 64bit aligned. Even more we aligned the hole Midas event to 256bit in the fpga since we have a 250mhz x 256 Bit interface for PCIe. But then we saw that you align the bank data to 64bit -> crash of mdump etc. For now we generate the data on the FPGA in the „old“ Midas format. So having a flag for changing to a different alignment would be actually really nice.
Cheers,
Marius |